intel/fs: Teach the lower_regioning pass how to split instructions of unsuported exec type.

This adds some generic infrastructure that allows splitting any
instruction into a number of instructions of a smaller legal execution
type.  This is meant to replace several instances of handcrafted 64bit
type lowering done manually in the code generator, which is rather
error-prone, prevents scheduling of the lowered instructions, and
makes them invisible to the SWSB pass on Gfx12+ platforms, which will
become especially problematic on Gfx12.5+ since the EUs introduce
multiple asynchronous execution pipelines which the SWSB pass needs to
be able to synchronize to one another, so it's critical for the real
execution type of the instruction to be visible to the SWSB pass.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>

intel/fs: Move legal exec type calculation into helper function in lower_regioning pass.

Right now the execution type lowering functionality of this pass
assumes that an integer type of the original bit size is always
acceptable, however we'll want more complex behavior than that in
order to leverage this pass to automate the lowering of unsupported
64-bit operations into multiple 32-bit operations.

In order to do that calculate the closest legal execution type from a
new helper function, and take advantage of that function from the
has_invalid_exec_type() helper, along the lines of other
lower_regioning() helpers structured as a pair of has_invalid_foo() +
required_foo() functions.

This shouldn't have any functional changes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>

intel/fs/xehp: Merge repeated in-order read dependencies instead of replacement.

Previously the software scoreboard structure would drop previous
dependencies for a given register and replace them with the most
recent one for the same register when a new instruction (or set of
instructions) is processed.  This worked correctly on the Gfx12LP
platforms this code was originally designed for, because a repeated
dependency on the same register would either require the second
instruction to synchronize against the first (so the first dependency
could be disregarded from that point on) *or* require the dependency
to be RaR and in-order, which allows the synchronization to be
optimized out (the first dependency could still be disregarded as
well, since the pipeline is in-order).  However the latter assumption
will break on upcoming Gfx12HP platforms, because they have multiple
asynchronous FPU pipelines, so whenever we hit a RaR dependency we
need to propagate forward both dependencies, since the order in which
both reads will complete is not guaranteed by the hardware in cases
where they occur from different asynchronous pipelines.

Note that this dependency propagation change requires us to change the
definition of dependency::done as well, since that constant is defined
to discard any previous dependency information when used as argument
for shadow().

This has been reported to fix the following conformance failures on DG2:

   KHR-GL46.shaders.uniform_block.random.all_per_block_buffers.19
   dEQP-GLES3.functional.shaders.derivate.fwidth.*

Reported-by: Tapani Pälli <tapani.palli@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5670
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>

vc4/nir_lower_blend: update write mask when we update num components

As explained at the header of the lowering:

  "Once this pass is done, the color write will either have one
   component (for single sample) with packed argb8888, or 4 components
   with the per-sample argb8888 result."

So in several cases the lowering was updating the number of
components, so we need to update the writemask too.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14708>

radv/amdgpu: Use aligned sizing for IB buffers.

Otherwise aligning might run over buffer size ...

Fixes: 1f36f6b83f2 ("radv/winsys: use same IBs padding as the kernel")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14644>

radv/amdgpu: Fix handling of IB alignment > 4 words.

We reserved space for chaining by subtracting 4 words from max_dw, but
then the new alignment code in radv_amdgpu_cs_finalize ended up running
all over that. That resulted in going over buffer size when chaining.
When lucky you'd get a crash, and when unlucky other stuff might happen.

This always adds the 4 words at the end, but initializes with NOP by
default. That way we still adhere to the alignment rules.

Fixes: 1f36f6b83f2 ("radv/winsys: use same IBs padding as the kernel")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14644>

mesa: consolidate setting no error state and checking suid.

This makes MESA_NO_ERROR and mesa_no_error via drirc do the same thing.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14701>

radv/ci: mark dEQP-VK.api.version_check.version as expected failure on Stoney

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>

radv: advertise Vulkan 1.3

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>

radv: bump conformance version to 1.3.0.0 for RDNA2

We can't report conformance for an older major API version and this is
required to pass dEQP-VK.api.driver_properties.conformance_version.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>

radv: switch a bunch of struct/enum to 1.3 versions

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>

radv: add a no-op version of vkGetPhysicalDeviceToolPropertiesEXT()

It seems the vulkan common runtime code exposes VK_EXT_tooling but
doesn't (yet) have a fallback if the backend doesn't enable this
extension. Implement it as a no-op for a temporary workaround.

This fixes crashes with dEQP-VK.api.tooling_info.*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>

radv: report textureCompressionASTC_HDR as not supported

To fix a mismatch with
dEQP-VK.api.info.get_physical_device_properties2.features.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>

radv: implement 1.3 features/properties

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>

vulkan/runtime: Implement 1.3 features/properties

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>

vulkan: Update the XML and headers to 1.3.204

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>

Revert "wsi/x11: Avoid a class of deadlocks in the WSI queue thread"

This reverts commit 272fba8e7540f09163169a6e95bc108919ca24ff.

Multiple regressions have been reported against this. Let's revert and
maybe try again.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5910
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5913
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14710>

intel/dev: Add device info for RPL

Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=52407c220c44c8dcc6aa8aa35ffc8a2db3c849a9
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14664>

tu: add reference counting for descriptor set layouts

The spec states that descriptor set layouts can be destroyed almost
at any time:

   "VkDescriptorSetLayout objects may be accessed by commands that operate
    on descriptor sets allocated using that layout, and those descriptor
    sets must not be updated with vkUpdateDescriptorSets after the descriptor
    set layout has been destroyed. Otherwise, a VkDescriptorSetLayout object
    passed as a parameter to create another object is not further accessed
    by that object after the duration of the command it is passed into."

Copied mostly from ANV.

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5893

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14622>

anv: verify that the format supports multisampling

We tightened the requirements for multisampling on Gfx7 but didn't
format that at the Vulkan level.

This will break more conformance tests on Gfx7, but we weren't
conformant anyway.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 531b1b7511af ("intel/isl: Strengthen MCS SINT format restriction")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14679>

intel/dev: Add device ids for ADL-N

Ref: https://cgit.freedesktop.org/drm/drm-tip/commit/?id=7e28d0b26759846485978ada860ef4a427e06c8f
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14666>

intel/dev: Add DG1 PCI id 0x4909

Ref: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=5f0d4214938db66969a50d4b1262307e39f4f2b2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14665>

v3dv: support VK_KHR_8bit_storage

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: update comment on load_uniform fast-path

The comment for 16-bit applies to 8-bit uniforms as well.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: allow vectorization to larger scalar type

Allow to vectorize operations from a smaller bit-size into
scalar operations of a larger bit-size. This allows us to
turn 2x8-bit into a equivalent scalar 16-bit load/store.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: support 8-bit loads via ldunifa

This generalizes the support we added for 16-bit to also handle
8-bit loads via ldunifa. The story is the same: we align the address
to 32-bit downwards and we skip any bytes that are not of interest.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: handle to/from 8-bit integer conversions

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: support 8-bit general store access

Just like with 16-bit, this mode only supports scalar access, but
we are already lowering all non 32-bit accesses to scalar.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

v3dv: expose storagePushConstant16 feature from VK_KHR_16bit_storage

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: support 16-bit uniforms

Since ldunif is a 32-bit instruction we need to demote these to
UBO loads, like we do for indirect indexing, with the exception
of scalar 16bit uniforms with an offset that is 32-bit aligned.

For the exception where we can use lfdunif we read a 32-bit slot
from memory where the uniform data is in the lower 16-bit and we
will read garbage in the upper 16-bit which we won't use anyway.

It should be noted that by using ldunif, we are consuming
32-bit from the uniform stream, but this is fine because
if there is valid uniform data in the upper 16-bit (i.e.
we had a ivec2 uniform aligned to a 32-bit address), since
we scalarize 16-bit loads, we would see another load uniform
with an unaligned offset for the second component, which we
will demote to UBO.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

v3dv: support VK_KHR_16_bit_storage

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: support f32 to f16 RTZ and RTE rounding modes

These are required by VK_KHR_16bit_storage. Our hardware, however,
doesn't provide any mechanism to decide on the rounding mode of
the conversion and it seems to be using RTE, so we implement
RTZ in software.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: implement 32-bit/16-bit conversion opcodes

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: use ldunifa with unaligned constant offset

If we know we have a load with a constant offset, then even if it
is not aligned to 32-bit we can still produce an aligned offset
and then skip over the bytes we don't need.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: support ldunifa with some 16-bit loads

Even though ldunifa is strictly 32-bit we may be able to use it
to load 16-bit values that sit at 32-bit aligned addresses.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: lower packing after vectorization

The vectorization pass can inject 32_2x16 (un)packing opcodes
upon successful vectorization of 16-bit operations into 32-bit
counterparts, so make sure we lower these to something our
backend can handle.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: implement TMU general 16-bit load/store

This allows us to implement 16-bit access on uniform and
storage buffers.

Notice that V3D hardware can only do general access on scalar
16-bit elements, which we currently enforce by running a lowering
pass during shader compile.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: better document vectorization implications

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

broadcom/compiler: add lowering pass to scalarize non 32-bit general load/store

V3D hardware doesn't support vector access for general TMU load/store
operations like the ones we use for UBO and SSBO, so we need to split
these to scalar operations.

It should be noted that we also have a vectorization pass (which runs
later, during optimization), that may reconstruct some of these into
32-bit operations when possible (i.e. when the resulting operation
is 32-bit aligned).

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>

mesa: change GetProgramiv name length queries to use program resources

Program resource queries provide equivalent code, gl_resource_name
introduced by commit dea558cbd29 takes care of ARB_gl_spirv special
case where name information is not available.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14636>

mesa: move GetProgramInterfaceiv as a shader_query function

This matches how _mesa_get_program_resourceiv was done and this
makes it possible to skip some validation and shader program lookup
when calling it from glGetProgramiv.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14636>

nir/lower_locals_to_regs: Do an ad-hoc copy propagate on our generated MOV.

I noticed the inefficiency in NIR-to-TGSI output while trying to debug a
failure handling some arrays in r600.  While this makes reading CTS
shaders easier, the effect in the real world is pretty limited.  From
softpipe shader-db:

total instructions in shared programs: 2929840 -> 2929836 (<.01%)
instructions in affected programs: 118 -> 114 (-3.39%)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14321>

freedreno/drm, turnip: set DRM_RDWR for exported dma-bufs

This allows the exported fds to be mapped for writing.  My use case is
for virtio-gpu blob resources where the fds are mapped rw and mappings
are added to the guests using KVM_SET_USER_MEMORY_REGION.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14699>

svga: enable PIPE_CAP_IMAGE_STORE_FORMATTED on gl43 capable device

With upstream mesa PIPE_CAP_IMAGE_STORE_FORMATTED needs to be set to enable
ARB_shader_image_load_store extension. This will reenable GL43 support for svga GL43 capable
device

Fixes: 3b81d2d30dab ('mesa/st: do not expose ARB_shader_image_load_store if not fully implemented')

Tested with glretrace

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14688>

ci: debian-android: drop -Wno-error=extern-initializer

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14654>

vulkan/vk_extensions_gen: fix -Wextern-initializer warning

vk_android_allowed_device_extensions is already declared as
extern in vk_extensions.h

Fixes a warning with clang

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14654>

iris: Fix and refactor check for clear color being fully zero

I missed updating this code to check res->aux.clear_color_unknown when
I added it a while back.  While we're here, also refactor this code into
a helper function - I'll want to use it in another place shortly.

Fixes: e83da2d8e3b ("iris: Don't try to CPU read imported clear color BOs")

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>

iris: Implement iris_blorp_exec() for the blitter engine

This splits iris_blorp_exec() into separate functions for executing on
the render command streamer and the blitter command streamer.  A future
patch could add a separate iris_blorp_exec_compute() path that skips a
bunch of render-specific work.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>

iris: Set BLORP_BATCH_USE_{COMPUTE,BLITTER} flags for the target batch

This makes blits, copies, and (non-fast) clears set the appropriate
BLORP_BATCH_USE_{COMPUTE,BLITTER} flag if their batch is either
IRIS_BATCH_COMPUTE or IRIS_BATCH_BLITTER.  We ignore the other
operations for now as those don't support compute or blit yet.

Of course, there is no code to attempt to launch BLORP operations on
either the compute or blitter batches yet, but that will come in time.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>

iris: Only have one blorp_batch_init/finish in iris_copy_region()

This is a little simpler, and gives us one place to change flags.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>

iris: Create an IRIS_BATCH_BLITTER for using the BLT command streamer

We removed all the hardware blitter support from i965 years ago because
the blitter was not worth using (limited functionality, bad performance,
extra synchronization, and worse).  However, on Tigerlake there are new
blitter commands that are actually fast and allow us to do proper
asynchronous copies while 3D is busy doing other work.

So, reintroduce the blitter.  We'll want to use it.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>

blorp: Add support for blorp_copy via XY_BLOCK_COPY_BLT

This introduces a new blorp_copy() path using the new XY_BLOCK_COPY_BLT
blitter command introduced on Tigerlake.  Unlike the blitter commands of
old, this one is actually fast and worth using.  Although it doesn't use
shaders like the rest of BLORP, we still can use some surface-munging
code from there, and BLORP also provides a nice place to put this which
is shared among the drivers.

To use the new path, set BLORP_BATCH_USE_BLITTER (much like Jordan's
recent BLORP_BATCH_USE_COMPUTE bit) and target the batch at the copy
engine.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>

isl: Add isl_dev->mocs.blitter_{src,dst} fields

These will be used for XY_BLOCK_COPY_BLT on XeHP.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>

blorp: Add a blorp_address::local_hint flag

This will be used as a performance hint for XY_BLOCK_COPY_BLT to
indicate whether the source/destination surfaces are (likely) in
device-local memory or system memory.  We don't need to be precise
here - it's okay to set the fields to LOCAL even if a buffer has
been evicted out to system memory.

We should set this from Vulkan too, but I haven't yet.  There isn't
a convenient anv_bo field like there is in iris...

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>

intel/dev: Add a has_flat_ccs flag

This should only be set on XeHP.  It implies that CCS works via based on
the virtual addresses involved and a flat memory carve-out, rather than
treating CCS like a surface, or using auxiliary maps.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>

intel/genxml: Add XY_BLOCK_COPY_BLT Color Depth enum values

Requested by Jason.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>

intel: Allow copy engine class in intel_gem_create_context_engines()

I want to use I915_ENGINE_CLASS_COPY in iris.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14687>

lavapipe: remove unused struct member

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14695>

ci: debian-android: drop -Wno-error=unused-label

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14639>

anv: drop unused label

Added in 053d4c328fa48838572857bd53d07d7680070d52
Last usage removed in 0967584549fa12c754e594dfaf5ac9d7671e7b18

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14639>

vulkan/wsi: add VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT for swapchain image caps

I need this, and drivers can do it, so add it

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14641>

mesa/st: move st_fb_orientation into a mesa function

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: move invalidate_on_gl_viewport to ctx

This is cleaner in the gl context now.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: move manager colorbuffer interface to gl_context.

This just avoids some st_context in main.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: move renderbuffer format choosing wrapper into mesa.

This moves this and cleans up the results.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: move last of renderbuffer functionality into mesa

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: migrate blit code into mesa

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: fixup viewport drawable invalidation

This moves the code into more appropriate places

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: move some fbo helpers around.

This inlines one, and moves the other to a more appropriate place

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: move st_new_renderbuffer_fb to manager

This is st_manager code really.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: move map/unmap renderbuffer code into mesa

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: move st renderbuffer code into mesa renderbuffer

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: move DrawBufferAllocate into mesa.

Little bit of refactoring here.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: move st_ReadBuffer functionality into mesa

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: move validate/discard framebuffer into mesa

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: move render/finish_render texture in to mesa.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: merge framebuffer objects from st to mesa

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: move some renderbuffer code into mesa

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: merge st_renderbuffer into gl_renderbuffer.

This touches lots of places

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14675>

mesa/st: Lower user clip planes for tess eval too

The logic in st_atom_shader.c leads me to believe this was supposed
to work, but was incomplete to actually finish it. This fixes
compatibility tess tests on d3d12.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14662>

pan/decode: Fix missing newlines in error messages

Otherwise these error message lines end up truncated, which is a bit
annoying.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14575>

pan/bi: Pull BLEND precolouring out of per-dest loop

Indentation fail. This should happen once per instruction, not once per
destination. In theory, this is a minor performance win; in practice,
it's simply less wrong.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14575>

panfrost: Only cull polygons

The spec says only polygons, not points/lines, should be culled when
culling is enabled. The hardware does not make this distinction, so we
have to.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Icecream95 <ixn@disroot.org>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14575>

panfrost: Use u_reduced_prim for primitive checks

Use a Gallium helper that papers over the differences between primitive
types, as required by hardware operation.

[Cc'd to mesa-stable for use in the next commit.]

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14575>

freedreno/a5xx: Fix clip_mask

The clip_mask needs to also take into account rast->clip_plane_enable

Fixes: 99838513aee ("freedreno/a5xx: Add support for clip distances and use them for userclip.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14643>

freedreno/a6xx: Fix clip_mask

The clip_mask needs to also take into account rast->clip_plane_enable

Fixes: f2ae8d116ab ("freedreno/a6xx: Implement user clip/cull distances")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14643>

freedreno: Add FD_DIRTY_RASTERIZER_CLIP_PLANE_ENABLE

Add a dirty bit for clip_plane_enable changes.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14643>

freedreno: Pass shader cache key instead of shader key

We are going to need to extend the cache key to add state that effects
the program stateobj, but not necessarily the shader itself (ie. so
ir3_shader_key wouldn't be the correct place to add it).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14643>

mesa/st: Lowered ucp should still mark rast state dirty

Lowered clip planes should respect the enabled/disabled GL_CLIP_PLANEn
(aka GL_CLIP_DISTANCEn), which means updating the rast state as well.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14643>

agx: Lower UBO loads to use per-element indexing

This lets us support indirect access to UBOs easily. The existing
constant special case disappears too, since the peephole optimizer can
inline the constant later. (note: this is too conservative since we can
go up to 16-bit immediates...)

Unfortunately, nir_opt_algebraic can't seem to optimize expressions like
"((a << 3) + 4) >> 2" to "(a << 1) + 1" which would be necessary for
reasonable perf out of this...

Fixes:

dEQP-GLES2.functional.shaders.indexing.uniform_array.float_dynamic_loop_read_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14581>

docs: Update features and new_features for anv

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14681>

v3dv: implement VK_KHR_driver_properties

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14680>

radv: Remove VK_EXT_display_control support in favor of common impl.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14365>

anv: Remove VK_EXT_display_control support in favor of common impl.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14365>

vulkan/wsi/display: Add common implementation of VK_EXT_display_control.

Based on the new vk_sync functions.

Copied the version from anv as that seemed more thorough by using the
temporary sync payload. However that does mean we have do use the vk_sync
functions instead of being able to layer it on top of the dispatch table.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14365>

anv: Enable VK_VALVE_mutable_descriptor_type

This change introduces the anv_descriptor_size_for_mutable_type and
anv_descriptor_data_for_mutable_type helpers to compute the size and
data flags respectively for mutable descriptor types.

In order to make handling these types easier we now store a precomputed
descriptor stride for all types and use in the in appropriate places.

We also need to adjust the compiler to take into account this descriptor
stride. To that extent, we now pack the stride into the upper 16 bits
alongside the index and the dynamic offset index and use it later to
compute the correct offset.

Closes: #4250
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14633>

anv: refactor queue chain

Simplify the buffer chaining process with a single loop and
a helper function from Lionel Landwerlin's input.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14578>

broadcom/simulator: handle DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT

Without this the simulator wrapper will abort upon seeing this
query, rendering the driver unusable in that context.

Also, it seems the simulator environment doesn't quite work with
multisync at present, so do not enable it until we figure out what
the issue is.

Reviewed-by: Melissa Wen <mwen@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14678>

radv: stop checking if pipelines are NULL during draws/dispatches

This can't happen.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14617>

iris: Directly access BOs rather than using iris_resource_bo(...)

iris_resource_bo() is convenient when we only have a pipe_resource *
variable, and don't need to do a lot with it other than get at the BO.

When we need to do more with a resource, we usually cast it to
iris_resource *, at which point we can just use res->bo instead.

This patch updates iris_copy_region to use src_res->bo, dst_res->bo,
rather than iris_resource_bo(src) and iris_resource_bo(dst), since we
already have those cast versions on hand.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14667>