Alyssa Rosenzweig [Fri, 10 Jun 2022 15:28:09 +0000 (11:28 -0400)]
panfrost: Disable CRC at <16x16 tile sizes
The hardware writes one CRC per (effective) tile, the tile size of the CRC
buffer is the same as the configured effective tile size. However, all our CRC
infrastructure assumes 16x16 tiles. In case CRC is used with smaller tiles,
buffer overflows and incorrect rendering are all possible. Don't use CRC at
smaller tile sizes. Note disabling CRC correctly invalidates any bound CRC
buffers.
Fixes:
2e97d7c8350 ("panfrost: Transaction elimination support")
Closes: #6332
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16983>
Alyssa Rosenzweig [Fri, 10 Jun 2022 15:43:53 +0000 (11:43 -0400)]
panfrost: Inline pan_fbd_has_zs_crc_ext
It has a single user -- in a section of code that only runs for MFBD GPUs and
that has already decided whether to use CRCs -- so inlining it simplifies its
definition greatly and may avoid redeciding the CRC setting.
[Note for mesa-stable maintainers: This is not a bug fix but is marked for
backport so the next patch applies cleanly.]
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16983>
Samuel Pitoiset [Fri, 10 Jun 2022 15:07:32 +0000 (17:07 +0200)]
zink/ci: update list of expected failures with RADV
See https://gitlab.freedesktop.org/mesa/mesa/-/issues/6597
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16974>
Connor Abbott [Thu, 9 Jun 2022 19:37:09 +0000 (21:37 +0200)]
tu: Enable VK_KHR_swapchain_mutable_format
This is already implemented entirely in common code.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16976>
Denis Pauk [Fri, 10 Jun 2022 20:04:10 +0000 (23:04 +0300)]
panvk: Return VK_ERROR_INCOMPATIBLE_DRIVER for Midgard
Midgard is unsupported after merge of !16915
Signed-off-by: Denis Pauk <pauk.denis@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16991>
Alyssa Rosenzweig [Fri, 10 Jun 2022 16:09:13 +0000 (12:09 -0400)]
panfrost: Allow pixels using discard to be killed
info.fs.sidefx considers discard() to be a side effect. That definition is...
dubious at best. It certainly isn't the definition needed for forward pixel
kill. The only reason pixels couldn't be killed by FPK is if the shader has side
effects in the sense of writing to memory. Use that more precise condition so
FPK works more often.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Closes: #5607
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16984>
Francisco Jerez [Wed, 27 Apr 2022 06:20:21 +0000 (09:20 +0300)]
intel/fs/xehp+: Emit scheduling fence for all NIR barriers on platforms with LSC.
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15743>
Tapani Pälli [Tue, 5 Apr 2022 04:59:51 +0000 (07:59 +0300)]
intel/fs: setup SEND message descriptor from nir scope
This fixes many tests in following groups on DG2:
dEQP-VK.memory_model.*
dEQP-VK.fragment_shader_interlock.*
v2: use memory scope and setup descriptor also
for barriers without defined scope (Curro),
use local scope and flush type none with
NIR_SCOPE_NONE scope, cleanups (Lionel)
v3: use LSC_FENCE_THREADGROUP for NIR_SCOPE_WORKGROUP,
remove default case (Curro), use eviction if scope
was not defined, use LSC_FENCE_GPU scope for vertex
stage
v4: use LSC_FENCE_TILE independent of stage for device
scope (Curro)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15743>
Mike Blumenkrantz [Sat, 11 Jun 2022 21:02:48 +0000 (17:02 -0400)]
zink: more lavapipe glcts fails
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16994>
Mike Blumenkrantz [Fri, 10 Jun 2022 20:47:26 +0000 (16:47 -0400)]
zink: warn on missing customBorderColorWithoutFormat
this is required
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16982>
Eric Engestrom [Thu, 9 Jun 2022 09:47:00 +0000 (10:47 +0100)]
docs: show and link to the new macOS CI
Show the badge with the status of the new macOS CI introduced in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16875,
and make it a link to the build details.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Yurii Kolesnykov <root@yurikoles.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16941>
Marek Olšák [Thu, 9 Jun 2022 18:06:12 +0000 (14:06 -0400)]
ac/gpu_info: clamp gart_size_kb and vram_size_kb to fix buggy kernel driver
amdgpu returns 12 TB of GTT on Kaveri, which resulted in 0 KB of GTT
after the conversion to uint32_t, which caused us to report 0 as the UBO
size, which disabled UBOs and downgraded the driver to OpenGL 3.0.
Fixes:
aee8ee17a50 - radeonsi: change max TBO/SSBO sizes again and rework max alloc size
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6642
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Sun, 15 May 2022 06:17:20 +0000 (02:17 -0400)]
ac,radeonsi: don't export null from PS if it has no effect on gfx10+
We just need to pass the uses_discard flag to the epilog.
The hw skips the export anyway. This will hang if SPI registers declare
an output format or KILL_ENABLE is set because those cases require
an export with done=1.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Thu, 9 Jun 2022 13:43:12 +0000 (09:43 -0400)]
radeonsi: allocate only 1 GDS OA counter for gfx10 NGG streamout
It works with just one.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Wed, 8 Jun 2022 17:42:33 +0000 (13:42 -0400)]
radeonsi: allocate GDS only once per process
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Mon, 6 Jun 2022 11:26:34 +0000 (07:26 -0400)]
winsys/amdgpu: add a kernel GDS management workaround retrying on -ENOMEM
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Mon, 6 Jun 2022 09:27:14 +0000 (05:27 -0400)]
radeonsi: remove streamout code from shaders if no streamout buffers are bound
This is an optimization using asynchronous shader compilation.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Mon, 6 Jun 2022 09:11:56 +0000 (05:11 -0400)]
radeonsi: fix NGG streamout hang by allocating GDS in the right place
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Fri, 3 Jun 2022 23:45:31 +0000 (19:45 -0400)]
radeonsi: inline gfx10_emit_streamout_begin/end
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Sat, 4 Jun 2022 00:16:05 +0000 (20:16 -0400)]
radeonsi: unconditionally enable the streamout overflow query with NGG
It fails some tests, but we need it for gfx11.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Fri, 3 Jun 2022 21:38:09 +0000 (17:38 -0400)]
radeonsi: fix a crash in gfx10_sh_query_get_result_resource
If tmp_buffer (in ssbo[1]) is NULL, setting the writable bit causes
the called function to access the NULL buffer.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Sun, 5 Jun 2022 10:00:22 +0000 (06:00 -0400)]
radeonsi: fix an NGG streamout hang with monolithic shaders
ac_llvm_add_target_dep_function_attr has no effect if the function is
inlined.
amdgpu-gds-size determines m0 for ds_sub_u32 gds, which hangs if it's 0.
This helps both gfx10 and gfx11, though it will only be used by gfx11
after we enable streamout.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Thu, 9 Jun 2022 13:41:52 +0000 (09:41 -0400)]
radeonsi: rework how vs_state_bits is set and unpacked
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Mon, 6 Jun 2022 08:47:56 +0000 (04:47 -0400)]
radeonsi: move GS_STATE bits to the end to make space at the beginning
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Mon, 6 Jun 2022 08:35:40 +0000 (04:35 -0400)]
radeonsi: rename and regroup VS_STATE definitions
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Mon, 6 Jun 2022 08:12:48 +0000 (04:12 -0400)]
radeonsi: rework how VS_STATE_BITS are set for VS, TES, and GS
We need more GS/NGG bits, so we need to add current_gs_state for that.
This simplifies the logic in the draw code.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Thu, 2 Jun 2022 21:14:40 +0000 (17:14 -0400)]
radeonsi: simplify how pipeline statistic offsets are computed
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Thu, 2 Jun 2022 21:18:43 +0000 (17:18 -0400)]
radeonsi: add BREAK_BATCH at the beginning of IBs
to fix possible issues if the previous IB comes from a different app
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Tue, 24 May 2022 15:07:04 +0000 (11:07 -0400)]
radeonsi: set INTERPOLATE_COMP_Z to 0 to work around an EQAA bug
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Thu, 9 Jun 2022 14:21:11 +0000 (10:21 -0400)]
radeonsi: determine DB_SHADER_CONTROL in si_shader_ps
This is cleaner and more flexible.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Mon, 16 May 2022 13:49:27 +0000 (09:49 -0400)]
radeonsi: restructure PS no-export fixups
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Sun, 15 May 2022 06:12:18 +0000 (02:12 -0400)]
radeonsi: fix polygon stippling without color and Z outputs (v2)
We need to handle the fact that it kills pixels.
v2: also update si_update_ps_inputs_read_or_disabled
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Sun, 5 Jun 2022 10:13:52 +0000 (06:13 -0400)]
radeonsi: remove unused dword from wait_mem_scratch
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Sun, 5 Jun 2022 10:15:53 +0000 (06:15 -0400)]
radeonsi: fix uninitialized wait_mem_scratch_tmz
The initialization was dead code because it's allocated later.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Sun, 5 Jun 2022 10:57:43 +0000 (06:57 -0400)]
radeonsi: don't use info.gs.invocations if it's not GS
It's a union, which makes gs.invocations undefined for VS and TES.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Mon, 6 Jun 2022 06:46:54 +0000 (02:46 -0400)]
radeonsi: print LDS size in bytes
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Marek Olšák [Sun, 15 May 2022 02:16:16 +0000 (22:16 -0400)]
winsys/amdgpu: use AMDGPU_IB_FLAG_PREAMBLE for the CS preamble on gfx10+
This skips the preamble for following IBs if the queue receives IBs from
the same context back-to-back. This eliminates VGT_FLUSH (for tess and
legacy GS) and PS_PARTIAL_FLUSH (for gfx11) in those cases if the preamble
contains them.
v2: only use this on gfx10+ due to stability issues on Stoney and limited
testing
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
Konstantin Seurer [Mon, 6 Jun 2022 15:58:29 +0000 (17:58 +0200)]
radv: Move some rt intrinsics to the top
We need to move tr intrinsics to the top of the
shader that might be overwritten by
nir_intrinsic_rt_trace_ray.
Fixes the Khronos reflection sample.
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16889>
Erik Faye-Lund [Fri, 3 Jun 2022 12:29:30 +0000 (14:29 +0200)]
dzn: enable binding_model tests
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16904>
Erik Faye-Lund [Fri, 10 Jun 2022 06:35:40 +0000 (08:35 +0200)]
microsoft/spirv_to_dxil: lower cube-images to 2d arrays
textureLoad() doesn't work on cube images. We need to lower cube
images to 2D arrays.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16904>
Erik Faye-Lund [Wed, 8 Jun 2022 14:03:37 +0000 (16:03 +0200)]
microsoft/compiler: make sampler-lowering optional
We don't want this in DZN, so let's make it optional.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16904>
Erik Faye-Lund [Wed, 8 Jun 2022 13:45:57 +0000 (15:45 +0200)]
microsoft/compiler: mark image-functions as such
These functions only deal with images, so let's make that clear.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16904>
Erik Faye-Lund [Wed, 8 Jun 2022 13:53:44 +0000 (15:53 +0200)]
d3d12: move cubemap-lowering to common-code
We're going to want to do part of this in DZN as well.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16904>
Mike Blumenkrantz [Thu, 19 May 2022 19:38:10 +0000 (15:38 -0400)]
zink: run copy_prop_vars during optimization
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16973>
Mike Blumenkrantz [Fri, 10 Jun 2022 15:32:13 +0000 (11:32 -0400)]
zink: rewrite atomic ssbo intrinsics as atomic derefs
todo--
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16973>
Mike Blumenkrantz [Fri, 10 Jun 2022 20:45:23 +0000 (16:45 -0400)]
zink: more requirement docs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16981>
Mike Blumenkrantz [Fri, 10 Jun 2022 20:42:40 +0000 (16:42 -0400)]
zink: add feature req for border colors
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16981>
Mike Blumenkrantz [Fri, 10 Jun 2022 20:40:57 +0000 (16:40 -0400)]
zink: fix feature requirement
this is ARB_texture_buffer_object_rgb32, and both bits are needed
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16981>
Georg Lehmann [Sun, 29 Aug 2021 17:58:36 +0000 (19:58 +0200)]
anv: Implement VK_EXT_non_seamless_cube_map.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12730>
Pierre-Eric Pelloux-Prayer [Fri, 10 Jun 2022 09:57:20 +0000 (11:57 +0200)]
radeonsi: prevent recursion in si_decompress_dcc
This avoids u_blitter recursion:
#0 util_blitter_set_running_flag
#1 util_blitter_custom_color
#2 si_blit_decompress_color
#3 si_decompress_dcc
#4 si_texture_disable_dcc
#5 si_update_ps_colorbuf0_slot
#6 si_bind_ps_shader
#7 util_blitter_restore_fragment_states
#8 util_blitter_custom_color
#9 si_blit_decompress_color
#10 si_decompress_dcc
#11 si_sdma_copy_image
#12 si_blit
cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16962>
Pierre-Eric Pelloux-Prayer [Fri, 10 Jun 2022 08:44:39 +0000 (10:44 +0200)]
tradeonsi: fix preamble state producing incorrect packets
If the first time the preamble is written, one of the rings
isn't allocated, we wouldn't write the RING_SIZE to the preamble.
Later, when the preamble gets updated after the ring allocation,
the new RING_SIZE packet would overwrite other packets.
To prevent this, always write the RING_SIZE (the alternative would
be to write NOP packets).
This fix "*ERROR* Illegal register access in command stream" hangs
I observed on GFX8.
Fixes:
32c7805ccca ("radeonsi: merge all preamble states into one")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16962>
Georg Lehmann [Fri, 10 Jun 2022 12:52:49 +0000 (14:52 +0200)]
aco: Remove r128_a16 MIMG builder option.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16969>
Georg Lehmann [Fri, 10 Jun 2022 12:44:58 +0000 (14:44 +0200)]
aco: Print r128/a16 MIMG bits separately.
These both exist since Navi and we can have instructions which are one but
not the other.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16969>
Samuel Pitoiset [Fri, 10 Jun 2022 14:28:55 +0000 (16:28 +0200)]
zink/ci: skip two KHR-GL46 tests that timeout most of the time with RADV
Also timeout in vk-cts-image.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16972>
Samuel Pitoiset [Thu, 9 Jun 2022 12:09:44 +0000 (14:09 +0200)]
radv/ci: rename deqp-XXX jobs to vkcts-XXX
This looks clearer and will avoid confusion with future Zink CI testing.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16943>
Danylo Piliaiev [Fri, 10 Jun 2022 10:06:19 +0000 (13:06 +0300)]
tu/autotune: Prevent division by zero
src/freedreno/vulkan/tu_autotune.c:509:48: runtime error: division by zero
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16967>
Danylo Piliaiev [Fri, 10 Jun 2022 09:31:08 +0000 (12:31 +0300)]
turnip: Fix out-of-bounds builder->shader_iova access
src/freedreno/vulkan/tu_pipeline.c:1722:72: runtime error: index 5 out of bounds for type 'uint64_t [5]'
Fixes:
05329d7f9acabbc9306c9538a30b502d4c580d38
("tu: Implement pipeline caching with shared Vulkan cache")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16967>
Erik Faye-Lund [Wed, 8 Jun 2022 16:07:43 +0000 (18:07 +0200)]
ci/windows: add back build-error detection
This was accidentally broken while refactoring the script.
Fixes:
bf3c772e5e5 ("ci: Improve vs2019 mesa_build.ps1 for remove the need of cmd.exe")
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16965>
Chia-I Wu [Tue, 24 May 2022 22:26:42 +0000 (15:26 -0700)]
turnip: force sample interpolations for sample shading
Sample shading has similiar definitions in Vulkan and OpenGL, and they
both require unique associated data. While the definition for Vulkan
might change, we should stick to the current definition until the change
takes place and until apps (i.e., ANGLE) are updated.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16700>
Boris Brezillon [Wed, 16 Feb 2022 15:55:36 +0000 (16:55 +0100)]
nir: Fix flat new_var assignment in create_new_io_vars()
If the type is not an array, glsl_get_length() returns 0 and we don't
update the new_vars[]/flat_vars[] entries.
Fixes:
bcd14756eec ("nir/lower_io_to_vector: add flat mode")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16960>
Boris Brezillon [Mon, 14 Feb 2022 14:58:02 +0000 (06:58 -0800)]
microsoft/compiler: Lower fquantize2f16
As far as I can't tell, there's no native operation doing this
equivalent of fquantize2f16. Let's lower this operation to
if (val < MIN_FLOAT16)
return -INFINITY;
else if (val > MAX_FLOAT16)
return -INFINITY;
else if (fabs(val) < SMALLER_NORMALIZED_FLOAT16)
return 0;
else
return val;
which matches the definition of OpQuantizeToF16:
"
If Value is an infinity, the result is the same infinity.
If Value is a NaN, the result is a NaN, but not necessarily the same NaN.
If Value is positive with a magnitude too large to represent as a 16-bit
floating-point value, the result is positive infinity. If Value is negative
with a magnitude too large to represent as a 16-bit floating-point value,
the result is negative infinity. If the magnitude of Value is too small to
represent as a normalized 16-bit floating-point value, the result may be
either +0 or -0.
"
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16959>
Kristian H. Kristensen [Thu, 9 Jun 2022 18:11:44 +0000 (14:11 -0400)]
util/u_debug: Use 'initialized' instead of 'first'
Using 'initialized' to guard the one-time init, means it can be set to
false as part of .bss instead setting 'first' to true in .data. This
is more efficient and works at .ctor time.
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16952>
Mike Blumenkrantz [Fri, 10 Jun 2022 03:57:43 +0000 (23:57 -0400)]
zink: add new flakes
these take a while to run and I don't want anyone failing ci
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16957>
Emma Anholt [Tue, 26 Apr 2022 20:47:25 +0000 (13:47 -0700)]
crocus: Enable PIPE_CAP_LEGACY_MATH_RULES.
Now that TTN hooks this up to use_legacy_math_rules, we can flip the
switch and gallium nine can get the desired behavior from the hardware
instead of emitting math workarounds.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16176>
Emma Anholt [Tue, 26 Apr 2022 20:45:47 +0000 (13:45 -0700)]
iris: Enable PIPE_CAP_LEGACY_MATH_RULES.
Now that TTN hooks this up to use_legacy_math_rules, we can flip the
switch and gallium nine can get the desired behavior from the hardware
instead of emitting math workarounds.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16176>
Emma Anholt [Tue, 26 Apr 2022 20:55:24 +0000 (13:55 -0700)]
Revert "nine: Disable optional use of TTN when MUL_ZERO_WINS is available."
This reverts commit
7f01299c40ef5d301bbbb99fc6a6420aa27a65dc.
Now that I've got it hooked up to use_legacy_math_rules on the NIR side
and made sure that NIR frontends on drivers with
PIPE_CAP_LEGACY_MATH_RULES handle it, we should be able to enable this
again.
Fixes: #5678
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16176>
Emma Anholt [Tue, 26 Apr 2022 20:48:41 +0000 (13:48 -0700)]
gallium: Rename PIPE_CAP_TGSI_LEGACY_MATH_RULES to drop "TGSI"
Now NIR drivers can implement it as well.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16176>
Emma Anholt [Tue, 26 Apr 2022 20:44:46 +0000 (13:44 -0700)]
tgsi_to_nir: Set use_legacy_math_rules for TGSI_PROPERTY_LEGACY_MATH_RULES.
These control the same behavior, now that we've clarified what the flags
do.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16176>
Emma Anholt [Tue, 26 Apr 2022 20:39:28 +0000 (13:39 -0700)]
nouveau/nir: Implement mul_zero_wins behavior for use_legacy_math_rules.
This is the same flag TGSI sets for LEGACY_MATH_RULES.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Tested-by: Mobin Aydinfar <mobin@mobintestserver.ir>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16176>
Emma Anholt [Tue, 26 Apr 2022 20:23:03 +0000 (13:23 -0700)]
r600/sfn: Implement 0*x=0 behavior for use_legacy_math_rules.
The TGSI backend chooses these opcodes for LEGACY_MATH_RULES, so do the
same thing here for ARB programs which want the same behavior.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16176>
Emma Anholt [Tue, 26 Apr 2022 19:01:01 +0000 (12:01 -0700)]
nir_to_tgsi: Set LEGACY_MATH_RULES cap for use_legacy_math_rules shaders.
This should help get correct math for ARB_fp/vp after the NTT transition,
and will be used for wine nine shortly.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16176>
Emma Anholt [Thu, 2 Jun 2022 18:59:37 +0000 (11:59 -0700)]
gallium: Rename MUL_ZERO_WINS to LEGACY_MATH_RULES.
This is a clearer name for what it does than MUL_ZERO_WINS, and matches up
to the new name in shader_info.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16176>
Emma Anholt [Tue, 26 Apr 2022 18:58:14 +0000 (11:58 -0700)]
nir: Rename is_arb_asm to use_legacy_math_rules and document its meaning.
On iris and crocus, this flag is used to set "alt mode" math on the shader
as a whole. Some other drivers have a similar mode for DX9/ARB-program
behavior, so document what it does so we can start using it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16176>
Mike Blumenkrantz [Fri, 10 Jun 2022 03:09:16 +0000 (23:09 -0400)]
zink: update tu a630 baseline
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16956>
Mike Blumenkrantz [Fri, 20 May 2022 15:04:11 +0000 (11:04 -0400)]
zink: fix 32bit bo rewriting
this was correct for 64bit loads and manually converted 32bit loads (e.g., bindless),
but it was broken for the case where 64bit was not supported, as the offset wasn't
being correctly adjusted
break out the offset division to hopefully make this a little clearer
Fixes:
150d6ee97e3 ("zink: move all 64-32bit shader load rewriting to nir pass")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Fri, 27 May 2022 01:20:18 +0000 (21:20 -0400)]
zink: avoid adding more 64bit alus during bo rewriting
nir_unpack_64_2x32 isn't supported, but split is, so use that
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Thu, 26 May 2022 21:27:39 +0000 (17:27 -0400)]
zink: scalarize when rewriting explicit 64bit io
all of ntv requires scalarized io since the offsets are now array indices
instead of byte offsets, so enforce scalarization here to avoid breaking
the universe
Fixes:
150d6ee97e3 ("zink: move all 64-32bit shader load rewriting to nir pass")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Wed, 18 May 2022 14:11:41 +0000 (10:11 -0400)]
zink: rewrite 64bit shader i/o as 32bit
zink can't use lower_io, so this all has to be done manually and in
excruciating depth and detail
fixes (tu):
KHR-Single-GL46.arrays_of_arrays_gl.InteractionFunctionCalls2
KHR-GL46.gpu_shader_fp64.fp64.named_uniform_blocks
KHR-GL46.gpu_shader_fp64.fp64.varyings
KHR-GL46.vertex_attrib_binding.advanced-bindingUpdate
KHR-Single-GL46.enhanced_layouts.varying_array_components
KHR-Single-GL46.enhanced_layouts.varying_array_locations
KHR-Single-GL46.enhanced_layouts.varying_components
KHR-Single-GL46.enhanced_layouts.varying_locations
KHR-Single-GL46.enhanced_layouts.xfb_explicit_location
dEQP-GLES3.functional.transform_feedback.basic_types.interleaved.lines.highp_mat3x4
dEQP-GLES3.functional.transform_feedback.basic_types.interleaved.lines.mediump_vec3
dEQP-GLES3.functional.transform_feedback.basic_types.interleaved.points.mediump_vec4
dEQP-GLES3.functional.transform_feedback.basic_types.separate.points.highp_vec3
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Fri, 27 May 2022 01:24:40 +0000 (21:24 -0400)]
zink: implement nir_op_unpack_64_2x32 in ntv
it's really annoying to not have the full suite of these, so just do it
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Sat, 21 May 2022 00:12:57 +0000 (20:12 -0400)]
zink: improve/expand manual xfb emission
I left this semi-unfinished back when I discovered that I could blast
out xfb values inline with variable declarations, but this is not viable
for all scenarios, so it has to work and it has to be able to pass cts
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Sat, 21 May 2022 00:03:01 +0000 (20:03 -0400)]
zink: if a variable is flagged as being xfb, treat it as manual xfb output
this allows passes to flag variables as "needs manual action" for further
handling later on
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Sat, 21 May 2022 22:53:59 +0000 (18:53 -0400)]
zink: fix variable locations in manual xfb emission
the last output isn't always only consuming 1 slot, so ensure that the
xfb outputs begin at the appropriate place
cc: mesa-stable
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Sat, 21 May 2022 22:52:38 +0000 (18:52 -0400)]
zink: flag all shader i/o variables as !is_xfb
reclaiming this flag for internal use
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Fri, 20 May 2022 17:23:05 +0000 (13:23 -0400)]
zink: fix ntv partial stores
the previous conditional here was stupid and wrong: it should be comparing
to see whether the writemask is the full mask of the type's size
cc: mesa-stable
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Thu, 19 May 2022 19:38:26 +0000 (15:38 -0400)]
zink: run more int64 passes during optimization loop if int64 isn't available
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Wed, 18 May 2022 16:34:57 +0000 (12:34 -0400)]
zink: don't lower pack/unpack intrinsics
this just ends up propagating the bitsize that we don't want, making it
harder to remove them later
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Sat, 21 May 2022 18:48:26 +0000 (14:48 -0400)]
zink: always scalarize pack/unpack alu ops
these are tricky
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Thu, 19 May 2022 22:46:36 +0000 (18:46 -0400)]
zink: run nir_lower_alu_to_scalar in optimizer loop for 64bit lowering
ensure that pack/unpack ops aren't passing swizzles since those are hard
to implement
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Wed, 18 May 2022 16:34:43 +0000 (12:34 -0400)]
zink: break out nir alu typing in ntv
this is reusable
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Mike Blumenkrantz [Wed, 18 May 2022 14:08:26 +0000 (10:08 -0400)]
zink: flag optimization pass after inlining uniforms
this probably generated some pretty gnarly code
cc: mesa-stable
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16669>
Kenneth Graunke [Wed, 8 Jun 2022 22:25:35 +0000 (15:25 -0700)]
intel/compiler: Fix A64 header construction with a uniform address
fs_visitor::assign_curb_setup() maps UNIFORM registers to HW regs,
and contains the following assert:
assert(inst->src[i].stride == 0);
emit_a64_oword_block_header's striding tricks run afoul of this
restriction, by producing stride 1 values on a 64-bit UNIFORM source.
Work around this by copying the UNIFORM value to a VGRF first.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16938>
Jason Ekstrand [Mon, 15 Mar 2021 17:06:53 +0000 (12:06 -0500)]
vulkan/wsi: Signal semaphores and fences from the dma-buf
Instead of attempting to signal based on the memory object, use the new
DMA_BUF_IOCTL_EXPORT_SYNC_FILE to get a sync_file for the dma-buf and
use that to signal the semaphore or fence. Because this happens before
we transfer ownership back to the driver, the resulting sync_file should
only contain dma_fences from the compositor and/or display and shouldn't
be mixed up with the driver in any way. This gives us a real semaphore
and fence (as opposed to the dummy objects we've used int the past)
without over-synchronization.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4037>
Jason Ekstrand [Mon, 15 Mar 2021 17:19:54 +0000 (12:19 -0500)]
vulkan/wsi: Set memory ownership after signaling fences and semaphores
This isn't a functional change today because the set of drivers which
use set_ownership and those that use signal_fence/semaphore_for_memory
are mutually exclusive. It's important for the next commit, though.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4037>
Jason Ekstrand [Fri, 20 May 2022 01:23:30 +0000 (20:23 -0500)]
vulkan/wsi: Re-arrange QueueSubmit code in wsi_common_queue_present
Instead of treating the blit submit specially in the buffer_blit_queue
case, treat the dummy submit as special. This lets us keep all the
handling of special-queue blits together. It also means that the
wsi_memory_signal_submit_info gets chained into the final submit which
is what we want if we're to rely on it for implicit sync. If we chain
it into the dummy submit, we'll implicit sync on all work previous to
the blit but not the blit. This won't work if X11 or a Wayland
compositor is depending on that to synchronize the linear copy.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4037>
Jason Ekstrand [Fri, 20 May 2022 01:05:21 +0000 (20:05 -0500)]
vulkan/wsi: Reset fences earlier in wsi_common_queue_present
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4037>
Jason Ekstrand [Fri, 20 May 2022 01:09:52 +0000 (20:09 -0500)]
vulkan/wsi: Use a STACK_ARRAY for stage_flags
This avoids the heap allocation in the common case.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4037>
Jesse Natalie [Wed, 8 Jun 2022 23:47:55 +0000 (16:47 -0700)]
dzn: Init sync types before wsi
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4037>
Jason Ekstrand [Wed, 8 Jun 2022 23:50:01 +0000 (18:50 -0500)]
turnip: Set supported_sync_types before wsi_init
The WSI code is about to start querying for available semaphore handle
types via GetPhysicalDeviceExternalSemaphoreProperties in wsi_init().
For drivers that use vk_sync, supported_sync_types needs to be
initialized before GetPhysicalDeviceExternalSemaphoreProperties is
called. Really, wsi_init() should be the very last step of physical
device setup.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4037>
Jason Ekstrand [Wed, 8 Jun 2022 23:31:01 +0000 (18:31 -0500)]
turnip: Use the common QueuePresent implementation
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4037>
Jason Ekstrand [Wed, 8 Jun 2022 23:29:09 +0000 (18:29 -0500)]
turnip: Use the common AcquireNextImage implementation
The only reason for the wrapper was so that we could dummy signal the
semaphore and fence. Now that the WSI code always dos this for us, we
can drop our wrapper.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4037>
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