platform/kernel/u-boot.git
3 years agoarm64: dts: zynqmp: Add psgtr and phy entry for USB and SATA node
Piyush Mehta [Mon, 21 Jun 2021 04:41:27 +0000 (10:11 +0530)]
arm64: dts: zynqmp: Add psgtr and phy entry for USB and SATA node

This patch adds psgtr clocks and phy entry for USB0, USB1 and SATA node for
zc1751-xm017-dc3 board.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agonet: xilinx: axi_emac: Add support for 10G/25G AXI ethernet
Ashok Reddy Soma [Thu, 24 Jun 2021 06:34:41 +0000 (00:34 -0600)]
net: xilinx: axi_emac: Add support for 10G/25G AXI ethernet

Add support for 10G/25G (XXV) high speed ethernet. This Makes use of
the exiting AXI DMA, similar to 1G.

Signed-off-by: Alessandro Temil <atemil@waymo.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agonet: xilinx: axi_emac: Cleanup of of_to_plat()
Ashok Reddy Soma [Thu, 24 Jun 2021 06:34:40 +0000 (00:34 -0600)]
net: xilinx: axi_emac: Cleanup of of_to_plat()

There are lot of accesses to priv data in of_to_plat(), which is incorrect.
Create a platform data structure and use it in of_to_plat(), then copy all
platform data to priv data in probe.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoserial: zynq: Add support for serial parameters
Kunihiko Hayashi [Fri, 25 Jun 2021 11:19:11 +0000 (20:19 +0900)]
serial: zynq: Add support for serial parameters

This adds serial parameters that include stop bit mode, parity mode,
and character length. Mark parity and space parity modes are not
supported.

At the moment, the only path to call setconfig directly is DM testing,
however, this affects the size of SPL for DM testing, so it doesn't
apply to SPL.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoserial: Add additional depencies for PL010 and PL011 drivers
Michal Simek [Thu, 24 Jun 2021 11:36:23 +0000 (13:36 +0200)]
serial: Add additional depencies for PL010 and PL011 drivers

Both of these drivers are implemented with and without DM that's why more
symbols should be handled.
The most problematic one is enabling DEBUG_UART_PL011 based on
PL01X_SERIAL(DM based) because debug console has type selection based on
it.
enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
TYPE_PL011 : TYPE_PL010;

Without it pl01x_generic_setbrg() is configuring different registers.

Fixes: 4cc24aeaf420 ("serial: Add missing Kconfig dependencies for debug consoles")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agospl: fit: Also record architecture in /fit-images
Michal Simek [Thu, 27 May 2021 09:40:09 +0000 (11:40 +0200)]
spl: fit: Also record architecture in /fit-images

On ARM64 secure OS can run as 64bit or 32bit that's why it is necessary to
record information about architecture that other code can read it and
properly pass it to TF-A and start in 64bit or 32bit mode.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoarm64: zynqmp: Add missing year in Kria dts files
Michal Simek [Mon, 14 Jun 2021 13:07:07 +0000 (15:07 +0200)]
arm64: zynqmp: Add missing year in Kria dts files

DT files have been added this year but forgot to update it that's why do it
in separate patch now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Add psgtr description to zc1751 dc1 board
Michal Simek [Mon, 14 Jun 2021 12:58:35 +0000 (14:58 +0200)]
arm64: zynqmp: Add psgtr description to zc1751 dc1 board

Wire psgtr for zc1751 dc1 board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Remove gpio from aliases list
Michal Simek [Thu, 3 Jun 2021 08:47:04 +0000 (10:47 +0200)]
arm64: zynqmp: Remove gpio from aliases list

It is not recommended to have aliases for gpio. In past it was used in
Linux for assigning numbers via sysfs which is deprecated and libgpiod
should be used instead.
In U-Boot this number is used for seq number but gpio offset are not
counted from this number. That's why having these aliases only for seq
number is not needed. As is done in Linux it is the best to use full gpio
name instead of sequence number which depends on sequence in binding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Enable USB3.0 for dc2/dc3
Michal Simek [Fri, 11 Jun 2021 06:52:25 +0000 (08:52 +0200)]
arm64: zynqmp: Enable USB3.0 for dc2/dc3

Both boards are usb3.0 capable. dc3 was also missing enabling dwc3* nodes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Update usb dwc3 DT description
Michal Simek [Fri, 11 Jun 2021 06:51:19 +0000 (08:51 +0200)]
arm64: zynqmp: Update usb dwc3 DT description

Align USB nodes with the latest dt-bindings. It is adding resets, new
interrupt and also some quirks.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Use overlay sugar syntax for Kria SOM
Michal Simek [Thu, 10 Jun 2021 15:59:46 +0000 (17:59 +0200)]
arm64: zynqmp: Use overlay sugar syntax for Kria SOM

dtc supports new sugar syntax which is easier compare to previous one
that's why also covert overlays for SOM to it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Remove revA compatibility string from kv260 revB/1
Michal Simek [Thu, 10 Jun 2021 16:52:14 +0000 (18:52 +0200)]
arm64: zynqmp: Remove revA compatibility string from kv260 revB/1

kv260-revB is different compare to revA (usbhub is wired via i2c) that's
why remove revA compatible string.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoclk: zynq: Add clock wizard driver
Zhengxun [Fri, 11 Jun 2021 15:10:48 +0000 (15:10 +0000)]
clk: zynq: Add clock wizard driver

The Clocking Wizard IP supports clock circuits customized
to your clocking requirements. The wizard support for
dynamically reconfiguring the clocking primitives for
Multiply, Divide, Phase Shift/Offset, or Duty Cycle.

Limited by U-Boot clk uclass without set_phase API, this
patch only provides set_rate to modify the frequency.

Signed-off-by: Zhengxun <zhengxunli.mxic@gmail.com>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Add support for 64bit addresses in its
Michal Simek [Mon, 7 Jun 2021 10:37:32 +0000 (12:37 +0200)]
arm64: zynqmp: Add support for 64bit addresses in its

Xilinx ZynqMP supports also addresses above 4GB (32bit) that's why also
generate u-boot.its with 64bit load/entry addresses to also support
different configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Sync psgtr location on zcu104/zcu111/zc1751-dc1
Michal Simek [Thu, 3 Jun 2021 13:18:04 +0000 (15:18 +0200)]
arm64: zynqmp: Sync psgtr location on zcu104/zcu111/zc1751-dc1

psgtr node should be below pinctrl for easier comparion among dts files.
That's why move that nodes to different location.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Remove information about dma clock on zcu106
Michal Simek [Thu, 3 Jun 2021 12:12:05 +0000 (14:12 +0200)]
arm64: zynqmp: Remove information about dma clock on zcu106

Clock setting is not static anymore that's why it depends on firmware setup
that's why remove this comment.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Remove unused property from SD/USB
Michal Simek [Thu, 3 Jun 2021 11:46:27 +0000 (13:46 +0200)]
arm64: zynqmp: Remove unused property from SD/USB

Linux kernel is not using these properties that's why they can be removed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Remove can aliases from zc1751
Michal Simek [Thu, 3 Jun 2021 10:32:18 +0000 (12:32 +0200)]
arm64: zynqmp: Remove can aliases from zc1751

Networking subsystem is not using aliases that's why remove them for CAN
devices. There is also no any other Xilinx ZynqMP DT file with them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Remove si5328 and si5382 nodes
Michal Simek [Thu, 3 Jun 2021 09:58:08 +0000 (11:58 +0200)]
arm64: zynqmp: Remove si5328 and si5382 nodes

There are no drivers for these devices that's why remove that nodes
completely. This change is done based on Linux kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210308115437.2232847-1-quanyang.wang@windriver.com
3 years agoxilinx: Convert xlnx,eeprom property to nvmem alias
Michal Simek [Thu, 3 Jun 2021 09:46:50 +0000 (11:46 +0200)]
xilinx: Convert xlnx,eeprom property to nvmem alias

Convert all boards to use nvmem alias instead of xlnx,eeprom. The change is
done based on discussion in the link below.

Link: https://lore.kernel.org/r/CAL_JsqLMDqpkyg-Q7mUfw-XH67-v068Q6e9wTq2UOoN=0-_coQ@mail.gmail.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: rtc: Update rtc calibration value
Srinivas Neeli [Mon, 8 Mar 2021 08:35:19 +0000 (14:05 +0530)]
arm64: zynqmp: rtc: Update rtc calibration value

As per the design specification
"The 16-bit Seconds Calibration Value represents the number of
 Oscillator Ticks that are required to measure the largest time
 period that is less than or equal to 1 second.
 For an oscillator that is 32.768 KHz, this value will be 0x7FFF."

Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Sync psgtr location on zcu100/zcu106
Michal Simek [Tue, 1 Jun 2021 14:42:50 +0000 (16:42 +0200)]
arm64: zynqmp: Sync psgtr location on zcu100/zcu106

psgtr node should be below pinctrl for easier comparion among dts files.
That's why move that nodes to different location.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Sync dp port location on zc1751 dc4
Michal Simek [Tue, 1 Jun 2021 14:42:02 +0000 (16:42 +0200)]
arm64: zynqmp: Sync dp port location on zc1751 dc4

Historically dpdma and dpsub are placed at the end of files. Move nodes
there for easier comparison among dts files.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Remove unused dp_aclk clock
Michal Simek [Tue, 1 Jun 2021 14:40:43 +0000 (16:40 +0200)]
arm64: zynqmp: Remove unused dp_aclk clock

dp_aclk is not used anywhere that's why remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Remove addition newline from zc1751 dc1
Michal Simek [Tue, 1 Jun 2021 14:37:32 +0000 (16:37 +0200)]
arm64: zynqmp: Remove addition newline from zc1751 dc1

Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Add maximum-speed property for dwc3 nodes
Michal Simek [Mon, 31 May 2021 15:51:58 +0000 (17:51 +0200)]
arm64: zynqmp: Add maximum-speed property for dwc3 nodes

dwc3 can be used only for higher speeds than super-speed that's why
explicitly set it up.
This is also aligned with other ZynqMP dts files.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Remove additional header from zc1232 DT
Michal Simek [Mon, 31 May 2021 15:44:51 +0000 (17:44 +0200)]
arm64: zynqmp: Remove additional header from zc1232 DT

Remove unused phy.h from zc1232 DTS.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agozynqmp: Remove u-boot,dm-pre-reloc for uart instances
Michal Simek [Mon, 31 May 2021 12:41:23 +0000 (14:41 +0200)]
zynqmp: Remove u-boot,dm-pre-reloc for uart instances

Uarts already have u-boot,dm-pre-reloc via zynqmp.dtsi that's why there is
no need to have them in platform DT files too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agozynqmp: Pass bl32 entry to TF-A via xilinx handoff structure
Michal Simek [Mon, 31 May 2021 09:06:59 +0000 (11:06 +0200)]
zynqmp: Pass bl32 entry to TF-A via xilinx handoff structure

There is need to pass entry about secure OS when bl32_entry is defined.
Currently only 64bit support is added but /fit-images node have been
extended to also record if this is 32bit or 64bit secure OS. When this is
tested the code will be update to support this configuration too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agozynqmp: Generate u-boot.its also with TEE dynamically
Michal Simek [Mon, 31 May 2021 09:13:45 +0000 (11:13 +0200)]
zynqmp: Generate u-boot.its also with TEE dynamically

The first change is to trying to find out TF-A load address based on
reading elf file. Expectation is that bl31.bin is in the same folder as
bl31.elf. It brings new flexibility to place TF-A to any address (DDR
included).

And also enable TEE generation also with TEE configuration.
Expecation is the same as above that tee.bin and tee.elf are in the same
folder.

User has to just define link to BL31/BL32 binary files and the rest should
be handled by the script.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agozynqmp: Do not place u-boot to reserved memory location
Michal Simek [Mon, 31 May 2021 09:03:19 +0000 (11:03 +0200)]
zynqmp: Do not place u-boot to reserved memory location

TF-A and SecureOS can allocate the part of DDR for self but U-Boot is not
handling this configuration that the part of memory is reserved and
shouldn't be used by U-Boot. That's why read all reserved memory locations
and don't use it.
The code was taken from commit 4a1b975dac02 ("board: stm32mp1: reserve
memory for OP-TEE in device tree") and commit 1419e5b5167e ("stm32mp:
update MMU config before the relocation") which is used by stm32 and does
the job properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agozynqmp: Enable regulators
Michal Simek [Mon, 31 May 2021 08:38:30 +0000 (10:38 +0200)]
zynqmp: Enable regulators

Enable command and fixed regulators. XDP platform is using them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Update Copyright years to 2021
Michal Simek [Mon, 31 May 2021 07:50:01 +0000 (09:50 +0200)]
arm64: zynqmp: Update Copyright years to 2021

Trivial change for all files I have touched recently.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Add label for zynqmp_ipi
Michal Simek [Mon, 31 May 2021 07:42:08 +0000 (09:42 +0200)]
arm64: zynqmp: Add label for zynqmp_ipi

Add label which is used by bootloader for adding bootloader specific flag.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/3dc8416abdd3498e61edcd83830a12af295c5c6d.1611224800.git.michal.simek@xilinx.com
3 years agoarm64: zynqmp: Move DP nodes to the end of file (zcu106)
Michal Simek [Thu, 27 May 2021 11:44:35 +0000 (13:44 +0200)]
arm64: zynqmp: Move DP nodes to the end of file (zcu106)

Just sync it with others for easier comparison.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Add reset description for sata
Michal Simek [Thu, 27 May 2021 11:49:05 +0000 (13:49 +0200)]
arm64: zynqmp: Add reset description for sata

Sata needs to get reset before configuration that's why add property for it
there.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi
Stefano Stabellini [Wed, 5 May 2021 21:18:21 +0000 (14:18 -0700)]
arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi

The SMMU is disabled in device tree so this change has no impact.
The benefit is that this way it is in sync with xen.dtsi. Xen enables
the SMMU and makes use of it.

Signed-off-by: Stefano Stabellini <stefano.stabellini@xilinx.com>
3 years agoarm64: zynqmp: Disable CCI by default
Michal Simek [Mon, 11 May 2020 08:14:34 +0000 (10:14 +0200)]
arm64: zynqmp: Disable CCI by default

There is no reason to have CCI no enabled by default. Enable it when your
system configuration requires it. In Xilinx configuration flow this is
work for Device Tree Generator which reads information from HW Design
configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Update psgtr clocks index for boards
Michal Simek [Mon, 31 May 2021 07:56:58 +0000 (09:56 +0200)]
arm64: zynqmp: Update psgtr clocks index for boards

Update the psgtr clock indexing for couple of zynqmp boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Handle MMC seq number based on boot device
Michal Simek [Wed, 19 May 2021 13:16:19 +0000 (15:16 +0200)]
arm64: zynqmp: Handle MMC seq number based on boot device

K26 has EMMC and SD and default 0 is not working when system is booting out
of SD which is controller 1. Add controller autodetection via
mmc_get_env_dev(). The same code is used for distro_boot selection done in
board_late_init(). bootseq variable can't be reused because this is called
so late.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Add psu_init_gpl for k26 boards
Michal Simek [Wed, 19 May 2021 11:02:20 +0000 (13:02 +0200)]
arm64: zynqmp: Add psu_init_gpl for k26 boards

Add psu_init_gpl file for getting SPL to work directly from the tree.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoARM: zynq: Rename bus to be align with simple-bus yaml
Michal Simek [Thu, 26 Nov 2020 13:25:01 +0000 (14:25 +0100)]
ARM: zynq: Rename bus to be align with simple-bus yaml

Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI
point-to-point channels for communicating addresses, data, and response
transactions between master and slave clients. This ARM AMBA 3.0..."

Issues are reported as:
.. amba: $nodename:0: 'amba' does not match
'^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
>From schema:
../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml

Similar change has been done for Xilinx ZynqMP SoC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/8a4bc80debfbb79c296e76fc1e4c173e62657286.1606397101.git.michal.simek@xilinx.com
3 years agoarm64: zynqmp: Enable gpio driver for zcu1275/zcu1285
Michal Simek [Tue, 11 May 2021 11:59:01 +0000 (13:59 +0200)]
arm64: zynqmp: Enable gpio driver for zcu1275/zcu1285

Enable gpio driver on these boards. GPIOs can be used on any board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Add support for SVD devices
Michal Simek [Mon, 5 Oct 2020 07:35:40 +0000 (09:35 +0200)]
arm64: zynqmp: Add support for SVD devices

SVDs  are using different name which can't be handled via zynqmp_devices
structure. That's why introduce zynqmp_detect_svd_name() which checks ID
code for these devices and show proper name for them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Enable EFI secure boot
Michal Simek [Thu, 13 May 2021 11:58:58 +0000 (13:58 +0200)]
arm64: zynqmp: Enable EFI secure boot

Enabling EFI secure boot which is required for EBBR specification.
Enabling this will fix
"RT.SetVariable - Create one Time Base Auth Variable, the expect return
status should be EFI_SUCCESS"

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: xilinx: Set CONFIG_ZYNQMP_FIRMWARE config for mini emmc
T Karthik Reddy [Thu, 29 Apr 2021 14:02:30 +0000 (08:02 -0600)]
arm64: xilinx: Set CONFIG_ZYNQMP_FIRMWARE config for mini emmc

CONFIG_ZYNQMP_FIRMWARE enables zynqmp firmware driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
3 years agoarm64: zynqmp: Fix application loading on R5 core1
Ashok Reddy Soma [Thu, 15 Apr 2021 11:12:15 +0000 (05:12 -0600)]
arm64: zynqmp: Fix application loading on R5 core1

From U-Boot, loading application on RPU core 0 is fine but loading on
core 1 is not handled properly. Lock-step mode needs both the R5 cores
to be initialized and it is working fine. Whereas in SPLIT mode individual
R5 cores needs to be initialized as they need to execute differenet
applications. Handle both these lock-step and split modes by propagating
mode and RPU core number(4 for RPU0 and 5 for RPU1) for various functions
and by adding conditions in those functions.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoARM: zynq: Fix OCM mapping to be aligned with binding on zc702
Michal Simek [Thu, 26 Nov 2020 13:25:03 +0000 (14:25 +0100)]
ARM: zynq: Fix OCM mapping to be aligned with binding on zc702

The Linux commit f69629919942 ("dt-bindings: sram: Convert SRAM bindings to
json-schema") converted binding to yaml and some missing required
properties started to be reported. Align binding based on it.

The patch is fixing these warnings:
.../zynq-zc702.dt.yaml: sram@fffc0000: '#address-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc0000: '#size-cells' is a required property
.../zynq-zc702.dt.yaml: sram@fffc0000: 'ranges' is a required property
>From schema: .../Documentation/devicetree/bindings/sram/sram.yaml

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/87c02786ccd8d7827827a9d95a8737bb300caeb0.1606397101.git.michal.simek@xilinx.com
3 years agoARM: zynq: Convert at25 binding to new description on zc770-xm013
Michal Simek [Thu, 26 Nov 2020 13:25:04 +0000 (14:25 +0100)]
ARM: zynq: Convert at25 binding to new description on zc770-xm013

The Linux commit f8f79fa6bb25 ("dt-bindings: at25: convert the binding
document to yaml") converted binding to yaml and 3 deprecated properties
pop up.

The patch is fixing these warnings:
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'pagesize' is a required property
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'size' is a required property
.../zynq-zc770-xm013.dt.yaml: eeprom@2: 'address-width' is a required property
>From schema: .../Documentation/devicetree/bindings/eeprom/at25.yaml

by converting them to new binding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/be2c1125d98386033e182012eb08986924707a76.1606397101.git.michal.simek@xilinx.com
3 years agozynqmp: spl: support DRAM ECC initialization
Jorge Ramirez-Ortiz [Sun, 13 Jun 2021 18:55:53 +0000 (20:55 +0200)]
zynqmp: spl: support DRAM ECC initialization

Use the ZDMA channel 0 to initialize the DRAM banks. This avoid
spurious ECC errors that can occur when accessing unitialized memory.

The feature is enabled by setting the option
CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT and providing the following data:

 SPL_ZYNQMP_DRAM_BANK1_BASE: start of memory to initialize
 SPL_ZYNQMP_DRAM_BANK1_LEN : len of memory to initialize (hex)
 SPL_ZYNQMP_DRAM_BANK2_BASE: start of memory to initialize
 SPL_ZYNQMP_DRAM_BANK2_LEN : len of memory to initialize (hex)

Setting SPL_ZYNQMP_DRAM_BANK_LEN to 0 takes no action.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agogpio: pca953x: Add missing i2c dependency
Michal Simek [Wed, 2 Jun 2021 10:40:45 +0000 (12:40 +0200)]
gpio: pca953x: Add missing i2c dependency

pca953x also depends on i2c that's why add dependency to Kconfig.
Where GPIO is enabled but I2C compilation error pops up.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
3 years agoazure: Use msys2 20210604 installer for Windows build
Bin Meng [Mon, 21 Jun 2021 23:33:21 +0000 (07:33 +0800)]
azure: Use msys2 20210604 installer for Windows build

MSYS2 Windows build started to fail since yesterday (Jun 21):

  checking keyring...
  checking package integrity...
  error: gcc-libs: signature from "David Macek <david.macek.0@gmail.com>" is unknown trust
  :: File /var/cache/pacman/pkg/gcc-libs-10.2.0-1-x86_64.pkg.tar.zst is corrupted (invalid or corrupted package (PGP signature)).
  error: gcc: signature from "David Macek <david.macek.0@gmail.com>" is unknown trust
  :: File /var/cache/pacman/pkg/gcc-10.2.0-1-x86_64.pkg.tar.zst is corrupted (invalid or corrupted package (PGP signature)).
  error: failed to commit transaction (invalid or corrupted package)
  Errors occurred, no packages were upgraded.

Switching to the latest installer (version 20210604) seems to fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Tom Rini <trini@konsulko.com>
3 years agoMerge branch 'network_master' of https://source.denx.de/u-boot/custodians/u-boot-net
Tom Rini [Fri, 18 Jun 2021 15:18:56 +0000 (11:18 -0400)]
Merge branch 'network_master' of https://source.denx.de/u-boot/custodians/u-boot-net

3 years agonet: octeontx: smi: use dt live tree API
Tim Harvey [Thu, 17 Jun 2021 23:08:54 +0000 (16:08 -0700)]
net: octeontx: smi: use dt live tree API

clean up octeontx_smi_probe by using the live-tree API.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
3 years agocmd: pxe_utils: sysboot: fix crash if either board or soc are not set.
Dimitri John Ledkov [Wed, 21 Apr 2021 11:42:01 +0000 (12:42 +0100)]
cmd: pxe_utils: sysboot: fix crash if either board or soc are not set.

If the environment does not have "soc" or "board" set, and fdtdir
option is specified in extlinux.conf, the bootloader will crash whilst
dereferencing a null pointer. Add a guard against null soc or
board. Fixes a crash of qemu-riscv64_smode configuration, which does
not have CONFIG_SYS_SOC defined.

Signed-off-by: Dimitri John Ledkov <xnox@ubuntu.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
3 years agonet: use the same alias stem for ethernet as linux
Michael Walle [Thu, 25 Feb 2021 15:51:11 +0000 (16:51 +0100)]
net: use the same alias stem for ethernet as linux

Linux uses the prefix "ethernet" whereas u-boot uses "eth". This is from
the linux tree:

$ grep "eth[0-9].*=.*&" arch/**/*dts{,i}|wc -l
0
$ grep "ethernet[0-9].*=.*&" arch/**/*dts{,i}|wc -l
633

In u-boot device trees both prefixes are used. Until recently the only
user of the ethernet alias was the sandbox test device tree. This
changed with commit fc054d563bfb ("net: Introduce DSA class for Ethernet
switches"). There, the MAC addresses are inherited based on the devices
sequence IDs which is in turn given by the device tree.

Before there are more users in u-boot and both worlds will differ even
more, rename the alias prefix to "ethernet" to match the linux ones.
Also adapt the test cases and rename any old aliases in the u-boot
device trees.

Cc: David Wu <david.wu@rock-chips.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agonet: use a more deterministic approach to get the active ethernet device
Michael Walle [Wed, 24 Feb 2021 16:30:44 +0000 (17:30 +0100)]
net: use a more deterministic approach to get the active ethernet device

If the environment variable "ethact" is not set, the first device in the
uclass is returned. This depends on the probing order of the ethernet
devices. Moreover it is not not configurable at all.

Try to return the ethernet device with sequence id 0 first which then
can be configured by the aliases in a device tree. Fall back to the old
mechanism in case of an error.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
3 years agonet: sun8i-emac: fix MDIO frequency
Heinrich Schuchardt [Thu, 3 Jun 2021 07:52:41 +0000 (07:52 +0000)]
net: sun8i-emac: fix MDIO frequency

Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to
network failure on the OrangePi PC.

    => dhcp
    sun8i_emac_eth_start: Timeout

According to the commit message the change of the MDIO frequency is only
required for external PHYs.

Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agonet: synquacer: Add netsec driver
Jassi Brar [Fri, 4 Jun 2021 09:44:38 +0000 (18:44 +0900)]
net: synquacer: Add netsec driver

Add SynQuacer's NETSEC GbE controller driver.
Since this driver will load the firmware from SPI NOR flash,
this depends on CONFIG_SYNQUACER_SPI=y.

Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
3 years agonet: dwc_eth_qos: Revert some changes of commit 3a97da12ee7b
Daniil Stas [Sun, 30 May 2021 13:34:09 +0000 (13:34 +0000)]
net: dwc_eth_qos: Revert some changes of commit 3a97da12ee7b

Revert some changes of commit 3a97da12ee7b ("net: dwc_eth_qos: add dwc
eqos for imx support") that were probably added by mistake.

One of these changes can lead to received data corruption (enabling
FUP and FEP bits). Another causes invalid register rxq_ctrl0 settings
for some platforms. And another makes some writes at unknown memory
location.

Fixes: 3a97da12ee7b ("net: dwc_eth_qos: add dwc eqos for imx support")
Signed-off-by: Daniil Stas <daniil.stas@posteo.net>
Cc: Ye Li <ye.li@nxp.com>
Cc: Fugang Duan <fugang.duan@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
3 years agonet: dwc_eth_qos: Fix needless phy auto-negotiation restarts
Daniil Stas [Sun, 23 May 2021 22:24:48 +0000 (22:24 +0000)]
net: dwc_eth_qos: Fix needless phy auto-negotiation restarts

Disabling clk_ck clock leads to link up status loss in phy, which
leads to auto-negotiation restart before each network command
execution.

This issue is especially big for PXE boot protocol because of
auto-negotiation restarts before each configuration filename trial.

To avoid this issue don't disable clk_ck clock after it was enabled.

Signed-off-by: Daniil Stas <daniil.stas@posteo.net>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
3 years agonet: e1000: do not attempt to set hwaddr for i210 without FLASH
Tim Harvey [Fri, 16 Apr 2021 20:25:09 +0000 (13:25 -0700)]
net: e1000: do not attempt to set hwaddr for i210 without FLASH

commit f1bcad22dd19 ("net: e1000: add support for writing to EEPROM")
adds support for storing hwaddr in EEPROM however i210 devices do not
support this and thus results in errors such as:
Warning: e1000#0 failed to set MAC address'

Check if a flash device is present and if not return -ENOSYS indicating
this is not supported.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
3 years agoFix a memory leak issue in the RX port initialization.
Hou Zhiqiang [Sat, 12 Jun 2021 18:15:41 +0000 (21:15 +0300)]
Fix a memory leak issue in the RX port initialization.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
3 years agoMerge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Tom Rini [Thu, 17 Jun 2021 12:44:56 +0000 (08:44 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

- fsl-qoriq: Bug fixes related pfe, eth, thermal node, vid.c, cpu release,
  mmc, usb, env, etc for Layerscape boards
- powerpc: Update Maintainers for some boards.

3 years agoMerge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
Tom Rini [Thu, 17 Jun 2021 12:44:23 +0000 (08:44 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv

- ae350 related dts fixes.

3 years agoboard: freescale: t1028xrdb: Add MAINTAINER for revD
Priyanka Jain [Thu, 17 Jun 2021 07:22:46 +0000 (12:52 +0530)]
board: freescale: t1028xrdb: Add MAINTAINER for revD

Add Priyanka Jain as MAINTAINER for
 T2080RDB_revD_defconfig,
 T2080RDB_revD_NAND_defconfig,
 T2080RDB_revD_SDCARD_defconfig and
 T2080RDB_revD_SPIFLASH_defconfig

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoarmv8: Update erratum number to align with doc
Ran Wang [Wed, 16 Jun 2021 12:23:19 +0000 (17:53 +0530)]
armv8: Update erratum number to align with doc

Change the USB erratum number A-050106 to A-050204 as A-050106 is
a duplicate and never be published.

Fixes 0cfa00cdb94 (“armv8: Add workaround for USB erratum A-050106”)
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: freescale: t208xrdb: add a config option for rev D dts fixups
Camelia Groza [Fri, 11 Jun 2021 12:28:08 +0000 (15:28 +0300)]
board: freescale: t208xrdb: add a config option for rev D dts fixups

Under DM, we rely on u-boot's device tree to provide the correct PHY
addresses. The board_fix_fdt callback is intended to be used for
device tree fixups before relocation. Unfortunately, this isn't an
option when booting from flash since the device tree isn't writable
before relocation.

This patch introduces the CONFIG_T2080RDB_REV_D option to signal that a
board revision D or up is the target. The config option is used to set
the correct Aquantia PHY address in the board's u-boot device tree.

Defconfig files with the option enable explicitly are added for
convenience.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: freescale: t208xrdb: add Linux fdt fix-ups for rev D
Camelia Groza [Wed, 16 Jun 2021 12:17:31 +0000 (17:47 +0530)]
board: freescale: t208xrdb: add Linux fdt fix-ups for rev D

The T2080RDB boards revisions D and up have updated 10G Aquantia PHYs
connected to MAC1 and MAC2. The second Aquantia PHY is located at a
different address on the MDIO bus compared to rev C (0x8 instead of 0x1).

Fix-up the Linux device tree to update the PHY address for the second
Aquantia PHY on boards revisions D and up. Also rename the PHY node to
reflect the changes.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: freescale: t208xrdb: detect the board revision version
Camelia Groza [Fri, 11 Jun 2021 12:28:06 +0000 (15:28 +0300)]
board: freescale: t208xrdb: detect the board revision version

Detect and print the board revision version based on the CPLD registers.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: freescale: t208xrdb: remove the legacy non-DM_ETH code
Camelia Groza [Fri, 11 Jun 2021 12:28:05 +0000 (15:28 +0300)]
board: freescale: t208xrdb: remove the legacy non-DM_ETH code

Both DM_ETH and DM_PCI are enabled for the T2080RDB board. Remove the
board_eth_init() callback and the non-DM_ETH code paths since they are not
needed anymore.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agopg-wcom-ls102xa: fix sys counter frequency
Aleksandar Gerasimovski [Tue, 8 Jun 2021 14:25:21 +0000 (14:25 +0000)]
pg-wcom-ls102xa: fix sys counter frequency

A system clock of 66MHz was chosen for the pg-wcom-ls102xa.
Compared to the Evalboard, this corresponds to a reduction of 1/3.
The system counter clock should have been reduced accordingly,
but that was not the case, so we had a system time that was
1/3 behind the real time.

This patch corrects the system counter clock to
8.333MHz = 66.667MHz / 8.

Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com>
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agopg-wcom-ls102x: initialize front led and app buf
Aleksandar Gerasimovski [Tue, 8 Jun 2021 14:24:32 +0000 (14:24 +0000)]
pg-wcom-ls102x: initialize front led and app buf

This patch adds the front led initialization and the application
buffer enable to the eraly board inititlaization.

Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com>
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agokm: ls102x: update device disable configuration acc hw design desc
Aleksandar Gerasimovski [Tue, 8 Jun 2021 14:23:34 +0000 (14:23 +0000)]
km: ls102x: update device disable configuration acc hw design desc

In order to improve power consumption ls102x allows to disable peripherals
that are not in use.
This patch follows SELI8 HW design description and disables peripherals
that are not in use in our designs, the same configuration is applicable
and for EXPU1.

This patch uses available hwconfig option for updating ls102x device
disable configuration.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agokm: ls102x: set ethrotate envvar to no
Aleksandar Gerasimovski [Tue, 8 Jun 2021 14:21:15 +0000 (14:21 +0000)]
km: ls102x: set ethrotate envvar to no

The default behavior in the latest u-boot revisions is to rotate the
active net device to the next available if the requested link is not
established.

For our ls102x based devices this would mean that if active debug net
device is not available, u-boot will rotate and set the next net device
that is one of the estar adapters.
To return from this situation manual action to set correct ethact
adapter will be needed and this can be annoying when working in
debug mode.

Setting ethrotate=no will disable net adapter rotation and will make sure
that the primary adapter is always used.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agokm/scripts: fix saveenv command syntax
Aleksandar Gerasimovski [Tue, 8 Jun 2021 14:20:13 +0000 (14:20 +0000)]
km/scripts: fix saveenv command syntax

This is most probably a typo, and in older u-uboot versions is same as
'saveenv', in the newer uboot versions there is a separate 'save' command
that is different from 'saveenv'.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agokm: ls102xa: add missing define for PRAM regions
Aleksandar Gerasimovski [Tue, 8 Jun 2021 14:19:08 +0000 (14:19 +0000)]
km: ls102xa: add missing define for PRAM regions

In our designs we reserve PRAM area at the end of the RAM, and in order
this area to be visible and taken into account by the u-boot memory mgmt
CONFIG_PRAM has to be defined.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agokm/ls102xa: add support for u-boot POST memory test
Aleksandar Gerasimovski [Tue, 8 Jun 2021 14:17:34 +0000 (14:17 +0000)]
km/ls102xa: add support for u-boot POST memory test

From production view this is standard test executed during production on
all linux based foxmc cards.
On CENT2 HW defined memory region is zero means that some DDR accesses are
done by memory_post_dataline and memory_post_addrline but pattern tests
are skipped that's why mem_regions is fast there.

On ls102x for the complete DDR region of 1GiB memory_regions_post_test
takes approx. 4min and this is too much for production, so this patch
defines only 1MiB region as compromise.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard/km: add support for expu1 design based on nxp
Aleksandar Gerasimovski [Tue, 8 Jun 2021 14:16:28 +0000 (14:16 +0000)]
board/km: add support for expu1 design based on nxp

The EXPU1 design is a new 40G capable ethernet service unit card for
Hitachi-Powergrids wired-com product lines.

The base SoC is same as for already added SELI8 card, consequently the
already added u-boot support for SELI8 is reused.

Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com>
Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
[Fixed new line error at EOF]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: freescale: t102xrdb: Add MAINTAINER
Priyanka Jain [Tue, 8 Jun 2021 08:07:01 +0000 (13:37 +0530)]
board: freescale: t102xrdb: Add MAINTAINER

Add "Priyanka Jain <priyanka.jain@nxp.com>" as
MAINTAINER for t102xrdb board.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: freescale: p2041rdb: Add MAINTAINER
Priyanka Jain [Tue, 8 Jun 2021 08:07:00 +0000 (13:37 +0530)]
board: freescale: p2041rdb: Add MAINTAINER

Add "Priyanka Jain <priyanka.jain@nxp.com>" as
MAINTAINER for p2041rdb board.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: freescale: p1_p2_rdb_pc: Add MAINTAINER
Priyanka Jain [Tue, 8 Jun 2021 08:06:59 +0000 (13:36 +0530)]
board: freescale: p1_p2_rdb_pc: Add MAINTAINER

Add "Priyanka Jain <priyanka.jain@nxp.com>" as
MAINTAINER for p1_p2_rdb_pc board.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: freescale: t4rdb: Add MAINTAINER
Priyanka Jain [Tue, 8 Jun 2021 08:06:58 +0000 (13:36 +0530)]
board: freescale: t4rdb: Add MAINTAINER

Add "Priyanka Jain <priyanka.jain@nxp.com>" as
MAINTAINER for t4rdb board.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoarm: dts: ls1021a.dtsi: Fix invalid reg on gpio nodes
Lasse Klok Mikkelsen [Tue, 8 Jun 2021 06:39:12 +0000 (08:39 +0200)]
arm: dts: ls1021a.dtsi: Fix invalid reg on gpio nodes

Address and size cells on SOC are set to 1. But gpio nodes are specified
with 2 cells. This fixes the gpio nodes to correct cells.

Signed-off-by: Lasse Klok Mikkelsen <lkmi@prevas.dk>
Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agonet: tsec: add option to set device max-speed via dts
Aleksandar Gerasimovski [Fri, 4 Jun 2021 13:40:58 +0000 (13:40 +0000)]
net: tsec: add option to set device max-speed via dts

Current tsec adapter sets adapter gigabit capabilities by default, and in
reality this must not always be the case.
It is possible that tsec adapter is used for 100Mbps connection, and in
this case setting 1000Mbps capabilities can lead to some side effects such
longer autoneg process.

In our ls102x designs this problem leads to long autoneg times (> 4 sec)
in case board rgmii link is 100Mbps capable only.
Limiting the rgmii link capabilities provides faster and smoother
link establishment.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agokeymile: common: fix hexadecimal env variable format
Aleksandar Gerasimovski [Fri, 4 Jun 2021 09:25:00 +0000 (09:25 +0000)]
keymile: common: fix hexadecimal env variable format

Commit df86d32 breaks linux kernel and product application boot.

Linux kernel and our product application scripts are expecting 0x prefix
for hexadecimal values, while env_set_hex writes them without a prefix.

This patch partially revert env_set_hex usage for affected env variables.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoconfigs: seli8: set envsize to 0x4000
Aleksandar Gerasimovski [Fri, 4 Jun 2021 09:17:56 +0000 (09:17 +0000)]
configs: seli8: set envsize to 0x4000

During the mainlining of the board this was by mistake set to sector size.
Our user space env scripts are expecting envsize of 0x4000, and setting
this differently will break our cross-platform compatibility.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoarmv8: layerscape: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Yangbo Lu [Thu, 3 Jun 2021 02:51:19 +0000 (10:51 +0800)]
armv8: layerscape: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33

Drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
is used instead.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Acked-by: Michael Walle <michael@walle.cc> [for kontron-sl28]
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agommc: fsl_esdhc_imx: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Yangbo Lu [Thu, 3 Jun 2021 02:51:18 +0000 (10:51 +0800)]
mmc: fsl_esdhc_imx: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33

There is no i.MX board using such option. Drop it.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agommc: fsl_esdhc: convert to CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
Yangbo Lu [Thu, 3 Jun 2021 02:51:17 +0000 (10:51 +0800)]
mmc: fsl_esdhc: convert to CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT

For eSDHC, power supply is through peripheral circuit.
Some eSDHC versions have value 0 of the bit but that
does not reflect the truth. 3.3V is common for SD/MMC,
and is supported for all boards with eSDHC in current
u-boot. So, make 3.3V is supported in default in code.
CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT can be enabled if
future board does not support 3.3V.

This is also a fix-up for one previous patch, which converted
to use IS_ENABLED() for CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
that is not a Kconfig option.

Fixes: 52faec31827e ("mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()")
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: freescale: p2041rdb: use correct EEPROM address length
Matt Merhar [Sun, 30 May 2021 00:16:17 +0000 (00:16 +0000)]
board: freescale: p2041rdb: use correct EEPROM address length

These boards, according to the schematic and per the board I own, use an
M24256-BWDW6TP I2C EEPROM which requires two address bytes.

This fixes the 'mac' command which is used to program, among other
things, the MAC addresses for the ethernet interfaces on the board.

Signed-off-by: Matt Merhar <mattmerhar@protonmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoconfigs: ls2088aqds: fix synchronous exception
Biwen Li [Fri, 21 May 2021 07:15:06 +0000 (15:15 +0800)]
configs: ls2088aqds: fix synchronous exception

IFC NOR flash base address of ls2088a is 0x580000000,
and offset of env crc is 0x500000, so fix the macro
CONFIG_ENV_ADDR to fix synchronous exception(access illegal address)

Fixes: 59071804c1 ("configs: ls2080a: Correct ENV_ADDR value")
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoconfigs: ls1088a: Enable CONFIG_SYS_RELOC_ENV_ADDR
Kuldeep Singh [Wed, 19 May 2021 11:10:12 +0000 (16:40 +0530)]
configs: ls1088a: Enable CONFIG_SYS_RELOC_ENV_ADDR

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoarm: dts: lx2162aqds: support eMMC HS400 mode on esdhc1
Yangbo Lu [Fri, 14 May 2021 02:33:57 +0000 (10:33 +0800)]
arm: dts: lx2162aqds: support eMMC HS400 mode on esdhc1

Add properties related to eMMC HS400 mode for esdhc1.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agopci: layerscape-ep: Add check of the PCIe controller enablement
Hou Zhiqiang [Thu, 13 May 2021 06:54:32 +0000 (14:54 +0800)]
pci: layerscape-ep: Add check of the PCIe controller enablement

Stop to initialize the PCIe controller if it's disabled by RCW.

Fixes: 118e58e26eba ("pci: layerscape: Split the EP and RC driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoarmv8: ls1012a: Pass PPFE firmware to Linux through FDT
Chaitanya Sakinam [Fri, 7 May 2021 04:22:05 +0000 (12:22 +0800)]
armv8: ls1012a: Pass PPFE firmware to Linux through FDT

Read Linux PPFE firmware from flash partition and pass it to Linux through
FDT entry. So that we can avoid placing PPFE firmware in Linux rootfs.
(FDT may increase at max by 64KB)

Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoarmv8: layerscape: enable eMMC HS400 workarounds for LX2160A/LX2162A
Yangbo Lu [Tue, 27 Apr 2021 08:42:11 +0000 (16:42 +0800)]
armv8: layerscape: enable eMMC HS400 workarounds for LX2160A/LX2162A

Enable eMMC HS400 workarounds for LX2160A/LX2162A.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoarmv8: layerscape: add PSCI support for cpu release
Jiafei Pan [Wed, 21 Apr 2021 04:12:49 +0000 (12:12 +0800)]
armv8: layerscape: add PSCI support for cpu release

For cpu release command, check whether PSCI is supported firstly,
if supported, use PSCI to kick off secondary cores, otherwise still
use spin table.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
[Fixed checkpatch alignment CHECKs]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
3 years agoboard: freescale: vid.c: Add check for return value of adjust_vdd()
Priyanka Singh [Mon, 19 Apr 2021 05:45:04 +0000 (11:15 +0530)]
board: freescale: vid.c: Add check for return value of adjust_vdd()

Add check for return value of adjust_vdd()

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>