Sean Anderson [Tue, 27 Oct 2020 23:55:22 +0000 (19:55 -0400)]
log: Add additional const qualifier to arrays
Both these arrays and their members are const. Fixes checkpatch complaint.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Tue, 27 Oct 2020 23:55:21 +0000 (19:55 -0400)]
log: Fix incorrect documentation of log_filter.cat_list
Logging category lists are terminated by LOGC_END, not LOGC_NONE.
Fixes:
e9c8d49d54 ("log: Add an implementation of logging")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Sean Anderson [Tue, 27 Oct 2020 23:55:20 +0000 (19:55 -0400)]
log: Fix missing negation of ENOMEM
Errors returned should be negative.
Fixes:
45fac9fc18 ("log: Correct missing free() on error in log_add_filter()")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heiko Schocher [Sat, 10 Oct 2020 08:28:06 +0000 (10:28 +0200)]
imx6: enable early spi environment access on aristainetos boards
On aristianetos boards the display type is detected
through "panel" environment variable. Dependend on the
display type we detect the board type and this decides which
DTB we have to use for the board.
So we need early spi environment access.
Signed-off-by: Heiko Schocher <hs@denx.de>
Heiko Schocher [Sat, 10 Oct 2020 08:28:05 +0000 (10:28 +0200)]
env: Access Environment in SPI flashes before relocation
Enable the new Kconfig option ENV_SPI_EARLY if you want
to use Environment in SPI flash before relocation.
Call env_init() and than you can use env_get_f() for
accessing Environment variables.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heiko Schocher [Sat, 10 Oct 2020 08:28:04 +0000 (10:28 +0200)]
env: split env_import_redund() into 2 functions
split from env_import_redund() the part which checks
which Environment is valid into a separate function
called env_check_redund() and call it from env_import_redund().
So env_check_redund() can be used from places which also
need to do this checks.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 29 Oct 2020 15:30:29 +0000 (11:30 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch)
- Armada 8k: Use ATF serdes init instead of the "old" U-Boot version
(Baruch)
- Minor update to Octeon TX/TX2 defconfig (Stefan)
Tom Rini [Thu, 29 Oct 2020 15:30:15 +0000 (11:30 -0400)]
Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.01-v2
common:
- Add support for 64bit loadables from SPL
xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format
microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot
zynq:
- Add support for Zturn V5
zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling
versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power
zynq-sdhci:
- Add support for tap delay programming
zynq-spi/zynq-qspi:
- Use clock framework for getting clocks
xilinx-spi:
- Fix some code issues (unused variables)
serial:
- Check return value from clock functions in pl01x
Tom Rini [Thu, 29 Oct 2020 14:48:01 +0000 (10:48 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Andre Przywara [Wed, 28 Oct 2020 23:37:43 +0000 (23:37 +0000)]
MAINTAINERS, git-mailrc: Update sunxi maintainers
Maxime mentioned that he feels not having the time to be an Allwinner
maintainer anymore. Take over from him.
Maxime, many thanks for your great work in the past! I hope I can still
relay the occasional technical question to you in the future.
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tom Rini [Thu, 29 Oct 2020 13:10:24 +0000 (09:10 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Bug fixes and updates on vid, ls1088a lx2160a and other layerscape
platforms.
- Add optee_rpmb support for LX2 & Kontron sl28 support
Shmuel Hazan [Thu, 29 Oct 2020 06:52:20 +0000 (08:52 +0200)]
mtd: nand: pxa3xx: enable NAND controller if the SoC needs it
Based on Linux kernel commit
fc256f5789cb ("mtd: nand: pxa3xx: enable
NAND controller if the SoC needs it"). This commit adds support for the
Armada 8040 nand controller.
The kernel commit says this:
Marvell recent SoCs like A7k/A8k do not boot with NAND flash
controller activated by default. Enabling the controller is a matter
of writing in a system controller register that may also be used for
other NAND related choices.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Michal Simek [Tue, 27 Oct 2020 09:04:17 +0000 (10:04 +0100)]
xilinx: Enable SPI driver for Versal
Enable Zynq SPI driver for Versal.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 26 Oct 2020 11:26:13 +0000 (12:26 +0100)]
xilinx: Consolidate board_fit_config_name_match() for Xilinx platforms
Move board_fit_config_name_match() from Zynq/ZynqMP to common location.
This change will open a way to use it also by Microblaze and Versal.
Through this function there is a way to handle images with multiple DTBs.
For now match it with DEVICE_TREE as is done for Zynq.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ashok Reddy Soma [Fri, 23 Oct 2020 10:59:04 +0000 (04:59 -0600)]
mmc: zynq_sdhci: Add common function to set input/output tapdelays
Remove setting tapdelays for different speeds separately. Instead use
the ITAP and OTAP delay values which are read from the device tree.
If the DT does not contain tap delay values, the predefined values
will be used for the same.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ashok Reddy Soma [Fri, 23 Oct 2020 10:59:03 +0000 (04:59 -0600)]
mmc: zynq_sdhci: Extend UHS timings till hs200
Fix the condition to set UHS timings for speeds upto HS200.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Baruch Siach [Thu, 29 Oct 2020 06:52:19 +0000 (08:52 +0200)]
mtd: pxa3xx_nand: remove dead code
The kfree() call is unreachable, and is not needed. Remove this call and
the fail_disable_clk label.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Shmuel Hazan [Thu, 29 Oct 2020 06:52:18 +0000 (08:52 +0200)]
mtd: pxa3xx_nand: port to use driver model
Use the generic DT code to find the device compatible property for us.
This makes the driver look more like other current drivers. It also make
it easier to add support for other variants like Armada 8K in a future
commit.
Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Baruch Siach [Thu, 29 Oct 2020 06:52:17 +0000 (08:52 +0200)]
arm: dts: armada-cp110-master: update nand-controller
Align node properties to kernel dts node.
The change of compatible property does not affect any currently
supported board.
Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Shmuel Hazan [Thu, 29 Oct 2020 06:52:16 +0000 (08:52 +0200)]
arm: dts: armada-cp110-slave: add missing cps_nand
Align node properties to kernel dts node.
Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Stefan Roese [Mon, 19 Oct 2020 06:02:12 +0000 (08:02 +0200)]
arm: octeontx: Enable network support in supported boards
Enable the now included network drivers in the currently supported
Marvell Octeon TX & TX2 boards.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Igal Liberman [Sun, 18 Oct 2020 14:11:13 +0000 (17:11 +0300)]
phy: marvell: cp110: update mode parameter for pcie power on calls
It helps ATF to determine who called power on function (U-boot/Linux).
The corresponding ATF code was added in this commit:
mvebu: cp110: avoid pcie power on/off sequence when called from Linux
https://github.com/ARM-software/arm-trusted-firmware/commit/
55df84f974ea37abbb4f93f000f101f70cda5303
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Grzegorz Jaszczyk [Sun, 18 Oct 2020 14:11:12 +0000 (17:11 +0300)]
phy: marvell: cp110: let the firmware configure comphy for PCIe
Replace the comphy initialization for PCIe with appropriate SMC call, so
the firmware will perform appropriate comphy initialization.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Grzegorz Jaszczyk [Sun, 18 Oct 2020 14:11:11 +0000 (17:11 +0300)]
phy: marvell: cp110: let the firmware configure the comphy
Replace all comphy initialization with appropriate smc calls. It will
result with triggering synchronous exception that is handled by Secure
Monitor code in EL3. Then the Secure Monitor code will dispatch each smc
call (by parsing the smc function identifier) and triggers appropriate
comphy initialization.
This patch reworks serdes handling for: SATA, SGMII, HS-SGMII and SFI
interfaces.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Tom Rini [Wed, 28 Oct 2020 20:30:06 +0000 (16:30 -0400)]
Prepare v2021.01-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 28 Oct 2020 18:50:09 +0000 (14:50 -0400)]
Merge branch '2020-10-28-mux-driver-framework'
- Add a framework for mux drivers
Pratyush Yadav [Fri, 16 Oct 2020 10:46:36 +0000 (16:16 +0530)]
test: mux-cmd: Add tests for the 'mux' command
Tests tests run the three mux subcommands: list, select, and deselect,
and verify that the commands do what we expect.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Pratyush Yadav [Fri, 16 Oct 2020 10:46:35 +0000 (16:16 +0530)]
cmd: Add a mux command
This command lets the user list, select, and deselect mux controllers
introduced with the mux framework on the fly. It has 3 subcommands:
list, select, and deselect.
List: Lists all the mux present on the system. The muxes are listed for
each chip. The chip is identified by its device name. Each chip can have
a number of mux controllers. Each is listed in sequence and is assigned
a sequential ID based on its position in the mux chip. It lists details
like ID, whether the mux is currently selected or not, the current
state, the idle state, and the number of states.
A sample output would look something like:
=> mux list
a-mux-controller:
ID Selected Current State Idle State Num States
0 no unknown as-is 0x4
1 no 0x2 0x2 0x10
2 no 0x73 0x73 0x100
another-mux-controller:
ID Selected Current State Idle State Num States
0 no 0x1 0x1 0x4
1 no 0x2 0x2 0x4
Select: Selects a given mux and puts it in the specified state. This
subcommand takes 3 arguments: mux chip, mux ID, state to set
the mux in. The arguments mux chip and mux ID are used to identify which
mux needs to be selected, and then it is selected to the given state.
The mux needs to be deselected before it can be selected again in
another state. The state should be a hexadecimal number.
For example:
=> mux list
a-mux-controller:
ID Selected Current State Idle State Num States
0 no 0x1 0x1 0x4
1 no 0x1 0x1 0x4
=> mux select a-mux-controller 0 0x3
=> mux list
a-mux-controller:
ID Selected Current State Idle State Num States
0 yes 0x3 0x1 0x4
1 no 0x1 0x1 0x4
Deselect: Deselects a given mux and puts it in its idle state. This
subcommand takes 2 arguments: the mux chip and mux ID to identify which
mux needs to be deselected. So in the above example, we can deselect mux
0 using:
=> mux deselect a-mux-controller 0
=> mux list
a-mux-controller:
ID Selected Current State Idle State Num States
0 no 0x1 0x1 0x4
1 no 0x1 0x1 0x4
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jean-Jacques Hiblot [Fri, 16 Oct 2020 10:46:34 +0000 (16:16 +0530)]
test: Add tests for the multiplexer framework
Provide tests to check the behavior of the multiplexer framework.
Two sets of tests are added. One is using an emulated multiplexer driver
that can be used to test basic functionality like select, deselect, etc.
The other is using the mmio mux which adds tests specific to it.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Pratyush Yadav [Fri, 16 Oct 2020 10:46:33 +0000 (16:16 +0530)]
Kconfig: Increase the pre-relocation memory
The memory is close to full and adding a syscon node in test.dts makes
it go over the limit and makes malloc() fail on startup.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jean-Jacques Hiblot [Fri, 16 Oct 2020 10:46:32 +0000 (16:16 +0530)]
drivers: mux: mmio-based syscon mux controller
This adds a driver for mmio-based syscon multiplexers controlled by
bitfields in a syscon register range.
This is heavily based on the linux mmio-mux driver.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Jean-Jacques Hiblot [Fri, 16 Oct 2020 10:46:31 +0000 (16:16 +0530)]
dm: board: complete the initialization of the muxes in initr_dm()
This will probe the multiplexer devices that have a "u-boot,mux-autoprobe"
property. As a consequence they will be put in their idle state.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Jean-Jacques Hiblot [Fri, 16 Oct 2020 10:46:30 +0000 (16:16 +0530)]
drivers: Add a new framework for multiplexer devices
Add a new subsystem that handles multiplexer controllers. The API is the
same as in Linux.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
[trini: Update some error calls to use different functions or pass
correct arguments]
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 28 Oct 2020 12:35:28 +0000 (08:35 -0400)]
Merge tag 'efi-2021-01-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2021-01-rc2
A software RTC driver is supplied for UEFI SCT testing.
The following UEFI related bugs are fixed:
* correct handling of daylight saving time in GetTime() and SetTime()
* handling of the gd register in function tracing on RISC-V
* disable U-Boot devices in ExitBootServices()
Tom Rini [Wed, 28 Oct 2020 12:34:11 +0000 (08:34 -0400)]
Merge branch '2020-10-27-further-log-enhancements'
- Allow for log message continuation.
- Test fix, build time error checking for new categories
Heinrich Schuchardt [Fri, 23 Oct 2020 11:00:01 +0000 (13:00 +0200)]
log: correct and check array size of log categories
The log command has led to NULL dereferences if an unknown category name
name was used due to missing entries in the list of category names.
Add compile time checks for the array sizes of log_cat_name and
log_lvl_name to avoid future mishaps.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Fri, 23 Oct 2020 03:30:29 +0000 (05:30 +0200)]
efi_loader: daylight saving time
Adjust the SetTime() and GetTime() runtime services to correctly convert
the daylight saving time information when communicating with the RTC.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Ilias Apalodimas [Wed, 21 Oct 2020 22:04:21 +0000 (01:04 +0300)]
efi_loader: Disable devices before handing over control
U-Boot Driver Model is supposed to remove devices with either
DM_REMOVE_ACTIVE_DMA or DM_REMOVE_OS_PREPARE flags set, before exiting.
Our bootm command does that by explicitly calling calling
"dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);" and we also disable any
USB devices.
The EFI equivalent is doing none of those at the moment. As a result
probing an fTPM driver now renders it unusable in Linux. During our
(*probe) callback we open a session with OP-TEE, which is supposed to
close with our (*remove) callback. Since the (*remove) is never called,
once we boot into Linux and try to probe the device again we are getting
a busy error response. Moreover all uclass (*preremove) functions won't
run.
So let's fix this by mimicking what bootm does and disconnect devices
when efi_exit_boot_services() is called.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Ilias Apalodimas [Wed, 21 Oct 2020 22:04:20 +0000 (01:04 +0300)]
efi_loader: Sort header file ordering
Order header files according to https://www.denx.de/wiki/U-Boot/CodingStyle
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Thu, 15 Oct 2020 10:30:09 +0000 (12:30 +0200)]
trace: conserve gd register on RISC-V
An UEFI application may change the value of the register that gd lives in.
But some of our functions like get_ticks() access this register. So we
have to set the gd register to the U-Boot value when entering a trace
point and set it back to the application value when exiting the trace
point.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Thu, 22 Oct 2020 21:52:14 +0000 (23:52 +0200)]
rtc: provide an emulated RTC
On a board without hardware clock this software real time clock can be
used. The build time is used to initialize the RTC. So you will have
to adjust the time either manually using the 'date' command or use
the 'sntp' to update the RTC with the time from a network time server.
See CONFIG_CMD_SNTP and CONFIG_BOOTP_NTPSERVER. The RTC time is
advanced according to CPU ticks.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 25 Oct 2020 06:25:05 +0000 (07:25 +0100)]
Makefile: provide constant with seconds since epoch
Provide a constant U_BOOT_EPOCH with the number of seconds since
1970-01-01. This constant can be used to initialize a software
real time clock until it is updated via the 'sntp' command.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sat, 17 Oct 2020 12:31:59 +0000 (14:31 +0200)]
test: log: test message continuation
Provide a unit test checking that a continuation message will use the same
log level and log category as the previous message.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Sat, 17 Oct 2020 12:31:58 +0000 (14:31 +0200)]
log: allow for message continuation
Some drivers use macro pr_cont() for continuing a message sent via printk.
Hence if we want to convert printk messaging to using the logging system,
we must support continuation of log messages too.
As pr_cont() does not provide a message level we need a means of
remembering the last log level.
With the patch a pseudo log level LOGL_CONT as well as a pseudo log
category LOGC_CONT are introduced. Using these results in the application
of the same log level and category as in the previous log message.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Sat, 17 Oct 2020 12:31:57 +0000 (14:31 +0200)]
log: move processing_msg to global data
Replace the static variable processing_msg by a field in the global data.
Make the field bool at it can only be true or false.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Anatolij Gustschin [Tue, 27 Oct 2020 07:47:17 +0000 (08:47 +0100)]
nokia_rx51: re-enable CONSOLE_MUX and SYS_CONSOLE_IS_IN_ENV
With disabled legacy VIDEO option CONSOLE_MUX is not auto-selected
any more, re-enable it.
Fixes:
9dec5a0ea130 ("nokia_rx51: disable obsolete VIDEO config")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
Ashok Reddy Soma [Fri, 23 Oct 2020 10:59:02 +0000 (04:59 -0600)]
mmc: zynq_sdhci: Add clock phase delays for Versal
Define default values for input and output clock phase delays for
Versal. Also define functions for setting tapdelays based on these
clock phase delays.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Ashok Reddy Soma [Fri, 23 Oct 2020 10:59:01 +0000 (04:59 -0600)]
mmc: zynq_sdhci: Set tapdelays based on clk phase delays
Define and use functions for setting input and output tapdelays
based on clk phase delays.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Michal Simek [Fri, 23 Oct 2020 10:59:00 +0000 (04:59 -0600)]
mmc: zynq_sdhci: Read clock phase delays from dt
Define input and output clock phase delays with pre-defined values.
Define arasan_sdhci_clk_data type structure and add it to priv
structure and store these clock phase delays in it.
Read input and output clock phase delays from dt. If these values are
not passed through dt, use pre-defined values.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Michal Simek [Fri, 23 Oct 2020 10:58:59 +0000 (04:58 -0600)]
mmc: zynq_sdhci: Move macro to the top
Just group macros below headers. Other patches will be using this location
too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Ashok Reddy Soma [Fri, 23 Oct 2020 10:58:58 +0000 (04:58 -0600)]
mmc: Define timing macro's
Define timing macro's for all the available speeds of mmc. This is
done similar to linux. Replace speed macro's used with these new timing
macro's wherever applicable.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ashok Reddy Soma [Fri, 23 Oct 2020 10:58:57 +0000 (04:58 -0600)]
Revert "mmc: zynq: parse dt when probing"
This reverts commit
942b5fc03218d1c94468fc658e7dec65dabcc830.
This is partial revert of the above commit.
mmc_of_parse() is reading no-1-8-v from device tree and if set,
it is clearing the UHS speed capabilities of cfg->host_caps.
cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 |
MMC_MODE_HS400 | MMC_MODE_HS400_ES);
This is still missing to clear UHS speeds like SDHCI_SUPPORT_SDR104,
SDHCI_SUPPORT_SDR50 and SDHCI_SUPPORT_DDR50.
Even if we clear the flags SDHCI_SUPPORT_XXX in mmc_of_parse(),
these speed flags are getting set again in cfg->host_caps in
sdhci_setup_cfg().
The reason for this is, SDHCI_SUPPORT_XXX flags are cleared
only if controller is not capable of supporting MMC_VDD_165_195 volts.
if (caps & SDHCI_CAN_VDD_180)
cfg->voltages |= MMC_VDD_165_195;
if (!(cfg->voltages & MMC_VDD_165_195))
caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
SDHCI_SUPPORT_DDR50);
It means "no-1-8-v", which is read from DT is not coming in to effect.
So it is better we keep the host quirks(SDHCI_QUIRK_NO_1_8_V) to
clear UHS speeds based on no-1-8-v from device tree.
Hence revert the functionality related to no-1-8-v only, rest is fine
in the patch.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ashok Reddy Soma [Tue, 28 Jan 2020 14:39:04 +0000 (07:39 -0700)]
spi: zynq_qspi: Add function description
Add function description for zynq_qspi_init_hw and zynq_qspi_chipselect.
Fix zqspi to priv in function descriptions.
Change the description of priv as pointer to zynq_qspi_priv structure.
Fix other function descriptions to kernel-doc style.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 26 Oct 2020 10:28:27 +0000 (11:28 +0100)]
mtd: spi: Fix incorrect indentation
Use tabs to be aligned with the rest of the code.
Fixes:
658df8bd9464 ("mtd: spi-nor-core: Add octal mode support")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 23 Oct 2020 07:36:36 +0000 (09:36 +0200)]
microblaze: Enable board_late_init()
In board_late_init() several variables are setup to match the current
configuration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 23 Oct 2020 05:54:18 +0000 (07:54 +0200)]
microblaze: Wire generic xilinx board_late_init_xilinx()
Call generic board_late_init_xilinx() to be aligned with the rest of xilinx
platforms. Also getting rid of initrd_high/fdt_high and use
bootm_low/boot_size instead.
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 22 Oct 2020 09:08:58 +0000 (11:08 +0200)]
xilinx: Merge together BOOT_SCRIPT_OFFSET between MB and ARM
There is no reason not to use commong Kconfig by Microblaze too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 22 Oct 2020 08:37:00 +0000 (10:37 +0200)]
xilinx: Remove additional newline in config files
Trivial fix.
Fixes:
e519f03a1846 ("cmd: mem: Remove CONFIG_SYS_MEMTEST_SCRATCH mapping")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 22 Oct 2020 08:34:43 +0000 (10:34 +0200)]
xilinx: Enable SF_TEST command for all ARM based platforms
Enable this command by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 22 Oct 2020 08:34:00 +0000 (10:34 +0200)]
xilinx: zynq: Enable AES command
Enable AES command to be able to use it directly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 22 Oct 2020 08:59:08 +0000 (10:59 +0200)]
xilinx: zynq: Change types from u32 to uint32_t
Change parameter type to avoid compilation error:
In file included from ./tools/../lib/rsa/rsa-verify.c:23:0,
from tools/lib/rsa/rsa-verify.c:1:
include/u-boot/rsa-mod-exp.h:69:18: error: unknown type name ‘u32’; did you mean ‘__u32’?
int zynq_pow_mod(u32 *keyptr, u32 *inout);
^~~
__u32
include/u-boot/rsa-mod-exp.h:69:31: error: unknown type name ‘u32’; did you mean ‘__u32’?
int zynq_pow_mod(u32 *keyptr, u32 *inout);
^~~
__u32
Fixes:
37e3a36a5475 ("xilinx: zynq: Add support to secure images")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 22 Oct 2020 08:33:29 +0000 (10:33 +0200)]
xilinx: Enable FRU command for all ARM based platforms
Enable it by default for board detection.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Wed, 1 Apr 2020 12:01:21 +0000 (06:01 -0600)]
xilinx: Add DDR base address to bootscript address
Add ram base address to scriptaddr env variable to make boot
script address to be a valid address when ddr base address changes.
This works properly if the first memory region is the region where uboot
runs. Also the solution was taken in respect of a lot of jtag script
putting u-boot script to certain address. For standard cases
bd->bi_dram[0].start is 0 all the time. Only for systems with DDR placed
out of this location it does calculation.
This is not the best solution and should be done differently in future but
enough for now till we don't have full solution ready yet.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Wed, 22 Jul 2020 08:27:34 +0000 (02:27 -0600)]
arm64: zynqmp: Fix zynqmp mini qspi max frequency
For zynqmp qspi, frequencies up to 40MHz will work irrespective
of feedback clock enabled or disabled. If we want higher than
40Mhz the feedback clock should be enabled.
With spi-max-frequency 108MHz it is not working when the feedback
clock is disabled. Change it to 40MHz so that it works irrespective
of feedback clock enabled or disabled.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 21 Oct 2020 10:23:17 +0000 (12:23 +0200)]
xilinx: zynqmp: Use tab for macro indentation
Trivial fix.
Fixes:
fa793165daf7 ("xilinx: zynqmp: refactor silicon name function")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 21 Oct 2020 10:17:44 +0000 (12:17 +0200)]
xilinx: zynqmp: Do not check 0 as invalid return from snprintf
U-Boot SPL on ZynqMP is using CONFIG_SPL_USE_TINY_PRINTF which doesn't
return any return value and all the time returns 0. That's why
even correct snprintf was returning in SPL chip ID as "unknown".
Change checking condition and allow snprintf to return 0 which is according
manual patch successful return.
"If an output error is encountered, a negative value is returned."
Fixes:
43a138956f7e ("arm64: zynqmp: Get rid of simple_itoa and replace it by snprintf")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 21 Oct 2020 10:16:50 +0000 (12:16 +0200)]
xilinx: zynqmp: Fix debug message in zynqmp_get_silicon_idcode_name()
Fix hex format from 0x%0X to 0x%0x to show correct numbers.
Fixes:
fa793165daf7 ("xilinx: zynqmp: refactor silicon name function")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 21 Oct 2020 10:16:02 +0000 (12:16 +0200)]
xilinx: zynqmp: Check return value from xilinx_pm_request()
xilinx_pm_request() can failed that's why also check return value.
Fixes:
050f10f103cd ("xilinx: zynqmp: remove chip_id function")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 3 Aug 2020 14:14:23 +0000 (16:14 +0200)]
xilinx: board: Add FRU decoder support
FMC cards are using FRU format for card identification. That's why add
support for this format.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 15 Apr 2019 11:54:09 +0000 (13:54 +0200)]
xilinx: cmd: Add basic fru format generator
Idea is to have something what can be used for board bringup from
generic board perspective.
There is a violation compare to spec that FRU ID is ASCII8 instead of
binary format but this is really for having something to pass boot and
boot to OS which has better generating options.
Also time should be filled properly.
For example:
fru board_gen 1000 XILINX versal-x-prc-01-revA serialX partX
There is also support for revision field which is Xilinx specific field.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Wed, 10 Apr 2019 07:08:10 +0000 (12:38 +0530)]
xilinx: cmd: Add support for FRU commands
This patch adds support for fru commands "fru capture" and "fru display".
The fru capture parses the FRU table present at an address and stores in a
structure for later use. The fru display prints the content of captured
structured in a readable format.
As of now, it supports only common header and board area of FRU. Also, it
supports only English language code and ASCII8/BINARY formats.
fru_data variable is placed to data section because fru parser can be
called very early before bss is initialized. And also information needs to
be shared that's why it is exported via header.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 20 Oct 2020 10:05:14 +0000 (12:05 +0200)]
xilinx: common: Add Makefile to common folder
There is no need to reference files in common folder back. Simply adding
Makefile to this folder does the job because this "common" location is
already wired in main Makefile.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 23 Oct 2020 05:51:04 +0000 (07:51 +0200)]
microblaze: Enable i2c DM by default
Microblaze has been converted fully to DM that's why enabled DM for I2C
too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 22 Oct 2020 09:14:20 +0000 (11:14 +0200)]
xilinx: common: Protect board_late_init_xilinx()
Do not call board_late_init_xilinx() when BOARD_LATE_INIT is not enabled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 14 Oct 2020 15:08:14 +0000 (17:08 +0200)]
xilinx: common: Move ZYNQ_GEM_I2C_MAC_OFFSET to board Kconfig
There is no reason to have ZYNQ specific Kconfig macro in generic location
to be visible for all other SoCs. That's why move it to Xilinx common
location to be visible only for us.
Also introduce new bool entry ZYNQ_MAC_IN_EEPROM to have also an option to
disable it or enable. This has connection to code which is reading the
whole content of i2c and also work with the rest of date not just with MAC
address.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 3 Sep 2020 10:44:51 +0000 (12:44 +0200)]
spl: fdt: Record load/entry fit-images entries in 64bit format
The commit
9f45aeb93727 ("spl: fit: implement fdt_record_loadable") which
introduced fdt_record_loadable() state there spl_fit.c is not 64bit safe.
Based on my tests on Xilinx ZynqMP zcu102 platform there shouldn't be a
problem to record these addresses in 64bit format.
The patch adds support for systems which need to load images above 4GB.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Thu, 3 Sep 2020 09:24:28 +0000 (11:24 +0200)]
spl: Use standard FIT entries
SPL is creating fit-images DT node when loadables are recorded in selected
configuration. Entries which are created are using entry-point and
load-addr property names. But there shouldn't be a need to use non standard
properties because entry/load are standard FIT properties. But using
standard FIT properties enables option to use generic FIT functions to
descrease SPL size. Here is result for ZynqMP virt configuration:
xilinx_zynqmp_virt: spl/u-boot-spl:all -82 spl/u-boot-spl:rodata -22 spl/u-boot-spl:text -60
The patch causes change in run time fit image record.
Before:
fit-images {
uboot {
os = "u-boot";
type = "firmware";
size = <0xfd520>;
entry-point = <0x8000000>;
load-addr = <0x8000000>;
};
};
After:
fit-images {
uboot {
os = "u-boot";
type = "firmware";
size = <0xfd520>;
entry = <0x8000000>;
load = <0x8000000>;
};
};
Replacing calling fdt_getprop_u32() by fit_image_get_entry/load() also
enables support for reading entry/load properties recorded in 64bit format.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
T Karthik Reddy [Tue, 4 Feb 2020 12:47:45 +0000 (05:47 -0700)]
spi: zynq_qspi: Use clk subsystem to get reference qspi clk
Remove fixed reference clk used by plat->frequency and use clk
subsystem to get reference clk. As per spi dt bindings
"spi-max-frequency" property should be used by the slave devices.
This property is read by spi-uclass driver for the slave device.
So avoid reading above property from the platform driver.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 4 Feb 2020 12:47:44 +0000 (05:47 -0700)]
spi: zynq_spi: Use clk subsystem to get reference spi clk
Remove fixed reference clk used by plat->frequency and use clk
subsystem to get reference clk. As per spi dt bindings
"spi-max-frequency" property should be used by the slave devices.
This property is read by spi-uclass driver for the slave device.
So avoid reading above property from the platform driver.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 13 Oct 2020 13:00:24 +0000 (15:00 +0200)]
serial: pl01x: Add error value checking
There also a need to check return values to make sure that clocks were
enabled and setup properly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Mon, 3 Aug 2020 10:57:05 +0000 (12:57 +0200)]
xilinx: board: Add support for additional card detection
The most of Xilinx evaluation boards have FMC connectors which contain
small eeprom for card identification. That's why read content of eeprom and
record it.
Also generate cardX_ variables for easier script handling.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 3 Aug 2020 11:01:45 +0000 (13:01 +0200)]
xilinx: board: Read the whole eeprom not just offset
Starts to use new way how eeproms should be referenced.
Reference is done via nvmem alias nodes. When this new way is specified
code itself read the eeprom and decode xilinx legacy format and fill struct
xilinx_board_description. Then based on information present there board_*
variables are setup.
If variables are saved and content can't be changed information is just
shown on console.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 28 Jul 2020 10:51:08 +0000 (12:51 +0200)]
dm: core: Add support for getting node from aliases
Add support for getting a node/property from aliases.
The similar functionality is provided for chosen node and this
implemenatation is copy of it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
T Karthik Reddy [Thu, 24 Sep 2020 10:32:15 +0000 (04:32 -0600)]
spi: xilinx_spi: remove unused local variable
Remove unused variable 'count' which is causing warning while
compilation.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 8 Apr 2019 11:43:51 +0000 (13:43 +0200)]
dt-bindings: arm64: versal: Add clk and power headers
Add power and reset headers to be sources by Versal dtses.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 20 Oct 2020 06:29:25 +0000 (08:29 +0200)]
arm64: zynqmp: Add support for saving sha3 key to different address
By default 48B sha3 hash value is written to srcaddr which is not the best
solution in case of that you want to use data for other operations. That's
why add key_addr optional parameters which enables to write 48B sha3 hash
value to specified address.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
T Karthik Reddy [Mon, 7 Jan 2019 11:35:11 +0000 (17:05 +0530)]
arm64: zynqmp: Add support for SHA3 command
This patch adds support for SHA3 command. It takes data blob
as input and generates 48 bytes sha3 hash value.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Mon, 7 Jan 2019 11:35:10 +0000 (17:05 +0530)]
arm64: zynqmp: Add support for RSA command
This patch adds support for RSA command, performs RSA encrypt &
RSA decrypt on data blob of key size.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 6 Sep 2018 11:04:44 +0000 (16:34 +0530)]
arm64: zynqmp: Add support for encryption and decryption on data blob
This patch adds support for encryption and decryption on a given data
blob using different key sources such as userkey(KUP), device key and
PUF key. Inorder to support this a new zynqmp command(zynqmp aes) has
been introduced.
Command:
zynqmp aes srcaddr ivaddr len aesop keysrc dstaddr [keyaddr]\n"
Encrypts or decrypts blob of data at src address and puts it\n"
back to dstaddr using key and iv at keyaddr and ivaddr\n"
respectively. keysrc values specifies from which source key\n"
has to be used, it can be User/Device/PUF key. A value of 0\n"
for KUP(user key),1 for DeviceKey and 2 for PUF key. The\n"
aesop value would specify the operationwhich can be 0 for\n"
decrypt and 1 for encrypt(1) operation\n";
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 7 Oct 2020 13:53:39 +0000 (15:53 +0200)]
arm64: zynqmp: Get rid of iommus/power-domains properties for SPL DT
SPL DT contains only nodes which are contain u-boot,dm-pre-reloc property.
iommu node is not this case that's why when DT is read DTC reports some
warnings.
$ dtc -I dtb -O dts dts/dt-spl.dtb >/dev/null
<stdout>: Warning (iommus_property): /amba/spi@
ff0f0000:iommus: Could not get phandle node for (cell 0)
<stdout>: Warning (iommus_property): /amba/mmc@
ff160000:iommus: Could not get phandle node for (cell 0)
<stdout>: Warning (iommus_property): /amba/mmc@
ff170000:iommus: Could not get phandle node for (cell 0)
SPL also has an option to remove some DT properties which are useless for
SPL to make DT even smaller.
Default DT properties are pinctrl-0 pinctrl-names interrupt-parent
interrupts which are already removed.
The patch extends this list with iommus to get rid of above warnings.
Also power-domains unused properties can be removed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 7 Oct 2020 13:41:21 +0000 (15:41 +0200)]
arm64: zynqmp: Enable cache command
Sometimes it is very useful to be able disable/enable cache that's why
enable commands for it by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 5 Oct 2020 13:43:44 +0000 (15:43 +0200)]
arm64: zynqmp: Enable FPGA loading from SPL
fpga bitstream needs to be listed in config node in FIT image. Only tested
option is bitstream in BIN format.
Enabling this feature increase code size by almost 4k.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 7 Oct 2020 13:13:17 +0000 (15:13 +0200)]
arm64: zynqmp: Get rid of simple_itoa and replace it by snprintf
simple_itoa() is implemented only for !CONFIG_USE_TINY_PRINTF. Tiny printf
is normally used by SPL that's code which uses simple_itoa() has missing
reference. That's why refactor code by using on snprintf() instead of
strncpy()/strncat() combination. This change also descrease code size by
saving 24B based on buildman.
aarch64: (for 1/1 boards) all -22.0 rodata +2.0 text -24.0
xilinx_zynqmp_virt: all -22 rodata +2 text -24
u-boot: add: 0/0, grow: 0/-1 bytes: 0/-24 (-24)
function old new delta
board_init 520 496 -24
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 5 Oct 2020 13:23:00 +0000 (15:23 +0200)]
mailbox: zynqmp: Extend timeout for getting observation bit
In case of fpga loading (which can be huge) 100ms is not enough. That's why
extend timeout 10 times to wait maximum 1s to get ACK back.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 5 Oct 2020 13:23:28 +0000 (15:23 +0200)]
firmware: zynqmp: Swap addr_hi/low when PM_FPGA_LOAD is called
Don't know reason but in regular flow addr_hi/low are swapped in ATF. It
means when fpga load is done from EL3 there is a need to swap it for PMUFW
to load bitstream.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Ashok Reddy Soma [Wed, 7 Oct 2020 07:54:18 +0000 (01:54 -0600)]
config: versal: Update mini u-boot timer clock to 100Mhz
Mini u-boot timer clock is not updated when u-boot is migrated from
emulator to silicon. Due to this slower clock of 2.72Mhz, delay() functions
are not working accurately. Update CONFIG_COUNTER_FREQUENCY to 100Mhz.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ashok Reddy Soma [Wed, 7 Oct 2020 06:36:54 +0000 (00:36 -0600)]
arm64: versal: Update mini u-boot eMMC node parameters
Mini u-boot eMMC dt parameters are not in sync with full u-boot dt.
Frequency for eMMC is fixed to 25Mhz. Due to this, mmc multi-block write
commands are failing. Increase frequency to 200Mhz to fix this issue.
Add bus-width = <8>, non-removable and disable-wp properties to the node
as this is eMMC.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 22 Sep 2020 11:18:55 +0000 (05:18 -0600)]
microblaze: Add support for distro boot
Add distro boot support for microblaze and enable jtag, qspi,
dhcp, pxe boot targets for distro boot.
Enable DISTRO_DEFAULTS config in microblaze defconfig and also
enable support for spi xilinx driver & spi vendors to access
spi flash by distro boot.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 22 Sep 2020 11:18:54 +0000 (05:18 -0600)]
microblaze: Setup distro boot env variables at run time
Setup all the distro boot related environment variables at
run time. Add BOOT_SCRIPT_OFFSET config to microblaze board
Kconfig.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Tue, 22 Sep 2020 11:18:53 +0000 (05:18 -0600)]
microblaze: board: Check return value whlie saving env variables
Check and print warning if run time env variables are not saved.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>