platform/kernel/u-boot.git
5 years agoMerge branch 'master' of git://git.denx.de/u-boot-video
Tom Rini [Mon, 26 Nov 2018 20:52:51 +0000 (15:52 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-video

5 years agoMerge branch 'master' of git://git.denx.de/u-boot-sunxi
Tom Rini [Mon, 26 Nov 2018 20:52:47 +0000 (15:52 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-sunxi

5 years agoMerge git://git.denx.de/u-boot-riscv
Tom Rini [Mon, 26 Nov 2018 18:45:29 +0000 (13:45 -0500)]
Merge git://git.denx.de/u-boot-riscv

5 years agoMerge branch '2018-11-25-master-imports'
Tom Rini [Mon, 26 Nov 2018 17:40:22 +0000 (12:40 -0500)]
Merge branch '2018-11-25-master-imports'

- Bring in the series from Simon for SPL logging support and bloblist

5 years agospl: Add support for passing handoff info to U-Boot proper
Simon Glass [Fri, 16 Nov 2018 01:44:09 +0000 (18:44 -0700)]
spl: Add support for passing handoff info to U-Boot proper

There is some basic informaton that SPL normally wants to pass through to
U-Boot, such as the SDRAM size and bank information.

Mkae use of the new bloblist structure for this. Add a new 'handoff' blob
which is set up in SPL and passed to U-Boot proper. Also adda  test for
sandbox_spl that checks that this works correctly and a new 'sb' command
to show the information passed from SPL.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: Boot in U-Boot through the standard call
Simon Glass [Fri, 16 Nov 2018 01:44:08 +0000 (18:44 -0700)]
sandbox: Boot in U-Boot through the standard call

Most architectures use jump_to_image_no_args() to jump from SPL to U-Boot.
At present sandbox is special in that it jumps in its
spl_board_load_image() call. This is not strictly correct, and means that
sandbox misses out some parts of board_init_r(), just as calling
bloblist_finish(), for example.

Change spl_board_load_image() to just identify the filename to boot, and
implement jump_to_image_no_args() to actually jump to it.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: Filter arguments when starting U-Boot
Simon Glass [Fri, 16 Nov 2018 01:44:07 +0000 (18:44 -0700)]
sandbox: Filter arguments when starting U-Boot

The current method of starting U-Boot from U-Boot adds arguments to pass
the memory file through, so that memory is preserved. This is fine for a
single call, but if we call from TPL -> SPL -> U-Boot the arguments build
up and we have several memory files in the argument list.

Adjust the implementation to filter out arguments that we want to replace
with new ones. Also print a useful error if the exec() call fails.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: Use malloc() and free() from os layer
Simon Glass [Fri, 16 Nov 2018 01:44:06 +0000 (18:44 -0700)]
sandbox: Use malloc() and free() from os layer

At present sandbox calls malloc() from various places in the OS layer and
this results in calls to U-Boot's malloc() implementation. It is better to
use the on in the OS layer, since it does not mix allocations with the
main U-Boot code.

Fix this by replacing calls with malloc() to os_malloc(), etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agosandbox: Refactor code to create os_jump_to_file()
Simon Glass [Fri, 16 Nov 2018 01:44:05 +0000 (18:44 -0700)]
sandbox: Refactor code to create os_jump_to_file()

At present os_jump_to_image() jumps to a given image, and this is written
to a file. But it is useful to be able to jump to a file also.

To avoid duplicating code, split out the implementation of
os_jump_to_image() into a new function that jumps to a file.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: Allow puts() output before global_data is set up
Simon Glass [Fri, 16 Nov 2018 01:44:04 +0000 (18:44 -0700)]
sandbox: Allow puts() output before global_data is set up

We support putc() in this case but not puts(), but this is more useful
since it is what printf() uses.

This particularly affects debugging early in SPL, where currently printf()
statements result in no output. Fix this by adding a special case into
puts() for sandbox, just like putc().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
5 years agosandbox: Add a new 'sb' command
Simon Glass [Fri, 16 Nov 2018 01:44:03 +0000 (18:44 -0700)]
sandbox: Add a new 'sb' command

The old 'sb' command was deprecated in 2015 and replaced with 'host'. It
is useful to be able to access some internal sandbox state, particularly
for testing.

Resurrect the old command and provide a way to print some basic state
information (currently just the arguments to sandbox).

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: Drop the deprecated 'sb' command
Simon Glass [Fri, 16 Nov 2018 01:44:02 +0000 (18:44 -0700)]
sandbox: Drop the deprecated 'sb' command

The old 'sb' command was deprecated in 2015 and replaced with 'host'.
Remove the remaining users and the command, so that the name is available
for other purposes.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: Add an option to display of-platdata in SPL
Simon Glass [Fri, 16 Nov 2018 01:44:01 +0000 (18:44 -0700)]
sandbox: Add an option to display of-platdata in SPL

At present we don't have a test that of-platdata can be accessed in SPL.
Add this in as a command-line option to SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agotest/py: Add a way to pass flags to sandbox
Simon Glass [Fri, 16 Nov 2018 01:44:00 +0000 (18:44 -0700)]
test/py: Add a way to pass flags to sandbox

It is sometimes useful to restart sandbox with some particular flags to
test certain functionality. Add a new method to ConsoleSandbox to handle
this, without changing the existing APIs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
5 years agosandbox: Add a memory map to the sandbox README
Simon Glass [Fri, 16 Nov 2018 01:43:59 +0000 (18:43 -0700)]
sandbox: Add a memory map to the sandbox README

We have a few things in the memory map now, so add documentation for this
to avoid confusion. Also note that it is possible to run all tests now.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agospl: Add a comment to spl_set_bd()
Simon Glass [Fri, 16 Nov 2018 01:43:58 +0000 (18:43 -0700)]
spl: Add a comment to spl_set_bd()

There is a strange feature to set global_data to a data-section variable
early in SPL. This only works if SPL actually has access to SRAM which is
not the case on x86, for eaxmple. Add a comment to this effect.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agospl: Make SPL_DISABLE_BANNER_PRINT a positive option
Simon Glass [Fri, 16 Nov 2018 01:43:57 +0000 (18:43 -0700)]
spl: Make SPL_DISABLE_BANNER_PRINT a positive option

Rather than having a negative option, make this a positive option and
enable it by default. This makes it easier to understand.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agospl: Add a define for SPL_TPL_PROMPT
Simon Glass [Fri, 16 Nov 2018 01:43:56 +0000 (18:43 -0700)]
spl: Add a define for SPL_TPL_PROMPT

We should use a macro rather than hard-coding the SPL prompt to 'spl'
since the code can be used by TPL too. Add a macro that works for both
and use it in various places.

This allows TPL to use the same code without printing confusing messages.

Note that the string is lower case ('spl', 'tpl') which is a change from
previously.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agospl: Support hash, input, pch, pci, rtc, tpm in SPL
Simon Glass [Fri, 16 Nov 2018 01:43:55 +0000 (18:43 -0700)]
spl: Support hash, input, pch, pci, rtc, tpm in SPL

At present these subsystems are only supported in U-Boot proper but it is
sometimes necessary to support them in SPL, or even TPL. Update the
Kconfig and Makefile to support this. Also adjust GPIO so that it can be
used in TPL if required.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agoAdd bloblist documentation
Simon Glass [Fri, 16 Nov 2018 01:43:54 +0000 (18:43 -0700)]
Add bloblist documentation

Add a description of the purpose of bloblist and how to use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agotest: Add a simple test for bloblist
Simon Glass [Fri, 16 Nov 2018 01:43:53 +0000 (18:43 -0700)]
test: Add a simple test for bloblist

Add a unit test for the bloblist functionality and enable bloblist for
sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agobloblist: Locate bloblist in U-Boot
Simon Glass [Fri, 16 Nov 2018 01:43:52 +0000 (18:43 -0700)]
bloblist: Locate bloblist in U-Boot

Add support for locating a bloblist in U-Boot that has been set up by SPL.
It is copied into RAM during relocation.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agospl: Set up the bloblist in SPL
Simon Glass [Fri, 16 Nov 2018 01:43:51 +0000 (18:43 -0700)]
spl: Set up the bloblist in SPL

The bloblist is normally set up in SPL ready for use by U-Boot. Add
a simple implementation of this to the common SPL code.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agoAdd core support for a bloblist to convey data from SPL
Simon Glass [Fri, 16 Nov 2018 01:43:50 +0000 (18:43 -0700)]
Add core support for a bloblist to convey data from SPL

At present there is no standard way in U-Boot to pass information from SPL
to U-Boot proper. But sometimes SPL wants to convey information to U-Boot
that U-Boot cannot easily figure out. For example, if SPL sets up SDRAM
then it might want to pass the size of SDRAM, or the location of each
bank, to U-Boot proper.

Add a new 'bloblist' feature which provides this. A bloblist is set up in
the first phase of U-Boot that runs (i.e. TPL or SPL). The location of
this info may be in SRAM or CAR (x86 cache-as-RAM) or somewhere else.

Information placed in this region is preserved (with a checksum) through
TPL and SPL and ends up in U-Boot. At this point it is copied into SDRAM
so it can be used after relocation.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Dannenberg <dannenberg@ti.com>
5 years agospl: Add support for logging in SPL and TPL
Simon Glass [Fri, 16 Nov 2018 01:43:49 +0000 (18:43 -0700)]
spl: Add support for logging in SPL and TPL

It is sometimes useful to log information in SPL and TPL. Add support for
this.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agofs-test.sh: Update to use 'host' not 'sb'
Tom Rini [Mon, 26 Nov 2018 13:24:51 +0000 (08:24 -0500)]
fs-test.sh: Update to use 'host' not 'sb'

For a long time now, 'sb' has been deprecated as a command in favor of
using 'host' for the sandbox hostfs interface, switch.

Signed-off-by: Tom Rini <trini@konsulko.com>
5 years agoriscv: cache: Implement i/dcache [status, enable, disable]
Rick Chen [Wed, 7 Nov 2018 01:34:06 +0000 (09:34 +0800)]
riscv: cache: Implement i/dcache [status, enable, disable]

AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.

This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.

This approach also provide the expansion when the
vender specific features are going to join in.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
5 years agoriscv: dts: Add ae350_32.dts for RV32I
Rick Chen [Tue, 13 Nov 2018 08:33:29 +0000 (16:33 +0800)]
riscv: dts: Add ae350_32.dts for RV32I

Add ae350_32.dts for 32 bit. And also rename
ae350.dts to ae350_64.dts for 64 bit.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
5 years agoconfigs: ax25-ae350: Separate ax25-ae350 for RV32/64I.
Rick Chen [Tue, 13 Nov 2018 08:15:20 +0000 (16:15 +0800)]
configs: ax25-ae350: Separate ax25-ae350 for RV32/64I.

Separate ax25-ae350 from one to two for
32 and 64 bit individually. And also select
different dts for 32 and 64 bit.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
5 years agoriscv: dts: Sync to Linux Kernel ae350 dts.
Rick Chen [Tue, 13 Nov 2018 07:13:34 +0000 (15:13 +0800)]
riscv: dts: Sync to Linux Kernel ae350 dts.

Use same dts to boot U-Boot and Kernel.

Following are the change notes :
1 Remove early printk bootargs.
2 Timer frequency are changed to 60MHz.
3 Add dma, snd, lcd, virtio nodes which are used
  in kernel drivers. They does not been used by U-Boot.
4 Change spi irq from 3 to 4.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
5 years agoriscv: qemu: clear kernel-start/-end in device tree as workaround for BBL
Lukas Auer [Thu, 22 Nov 2018 10:26:37 +0000 (11:26 +0100)]
riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL

QEMU specifies the location of Linux (supplied with the -kernel
argument) in the device tree using the riscv,kernel-start and
riscv,kernel-end properties. We currently rely on the SBI implementation
of BBL to run Linux and therefore embed Linux as payload in BBL. This
causes an issue, because BBL detects the kernel properties in the device
tree and ignores the Linux payload as a result.
Work around this issue by clearing the kernel properties in the device
tree before booting Linux.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: qemu: detect and boot the kernel passed by QEMU
Lukas Auer [Thu, 22 Nov 2018 10:26:36 +0000 (11:26 +0100)]
riscv: qemu: detect and boot the kernel passed by QEMU

QEMU embeds the location of the kernel image in the device tree. Store
this address in the environment as variable kernel_start. It is used in
the board-local distro boot command QEMU to boot the kernel with the
U-Boot device tree. The QEMU boot command is added as the first boot
target device.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
5 years agodm: core: add missing prototype for ofnode_read_u64
Lukas Auer [Thu, 22 Nov 2018 10:26:35 +0000 (11:26 +0100)]
dm: core: add missing prototype for ofnode_read_u64

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agoriscv: qemu: enable distro boot
Lukas Auer [Thu, 22 Nov 2018 10:26:34 +0000 (11:26 +0100)]
riscv: qemu: enable distro boot

Enable distro boot on the qemu-riscv32/64 boards. Supported boot target
devices are VirtIO and DHCP.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
5 years agodistro_bootcmd: add VirtIO distro boot command
Lukas Auer [Thu, 22 Nov 2018 10:26:33 +0000 (11:26 +0100)]
distro_bootcmd: add VirtIO distro boot command

Add a boot command to distro boot to support disks connected over the
VirtIO bus. The boot command uses the shared block environment.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
5 years agoriscv: align bootm implementation with that of other architectures
Lukas Auer [Thu, 22 Nov 2018 10:26:32 +0000 (11:26 +0100)]
riscv: align bootm implementation with that of other architectures

The bootm implementation of RISC-V diverges from that of other
architectures. Update it to match the implementation of other
architectures. The ARM implementation is used as a reference.

This adds the following features and changes to RISC-V.
* Add support for the BOOTM_STATE_OS_FAKE_GO command
* Call the remove function on devices with the removal flag set before
booting Linux
* Force disconnect USB devices from the host before booting Linux
* Print and add bootstage information to the device tree before booting
Linux

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: qemu: support booting Linux
Lukas Auer [Thu, 22 Nov 2018 10:26:31 +0000 (11:26 +0100)]
riscv: qemu: support booting Linux

Support booting Linux (as payload of BBL) from FIT images. For this, the
default CONFIG_SYS_BOOTM_LEN is increased to 16 MB, and the environment
variables fdt_high and initrd_high are set to mark the device tree and
initrd as in-place.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: qemu: use device tree passed by prior boot stage
Lukas Auer [Thu, 22 Nov 2018 10:26:30 +0000 (11:26 +0100)]
riscv: qemu: use device tree passed by prior boot stage

QEMU provides a device tree, which is passed to U-Boot using register
a1. We are now able to directly select the device tree with the
configuration CONFIG_OF_PRIOR_STAGE. Replace the hard-coded address in
qemu-riscv with it.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agoriscv: save hart ID and device tree passed by prior boot stage
Lukas Auer [Thu, 22 Nov 2018 10:26:29 +0000 (11:26 +0100)]
riscv: save hart ID and device tree passed by prior boot stage

Store the hart ID and device tree passed by the prior boot stage (in a0
and a1) in registers s0 and s1. Replace one use of s1 in start.S to
avoid overwriting it.

The device tree is also stored in memory to make it available to U-Boot
with the configuration CONFIG_OF_PRIOR_STAGE.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agoriscv: do not blindly modify the mstatus CSR
Lukas Auer [Thu, 22 Nov 2018 10:26:28 +0000 (11:26 +0100)]
riscv: do not blindly modify the mstatus CSR

The mstatus CSR includes WPRI (writes preserve values, reads ignore
values) fields and must therefore not be set to zero without preserving
these fields. It is not apparent why mstatus is set to zero here since
it is not required for U-Boot to run. Remove it.

This instruction and others encode zero as an immediate.  RISC-V has the
zero register for this purpose. Replace the immediates with the zero
register.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agoriscv: remove unused labels in start.S
Lukas Auer [Thu, 22 Nov 2018 10:26:27 +0000 (11:26 +0100)]
riscv: remove unused labels in start.S

The labels nmi_vector, trap_vector and handle_reset in start.S are not
used for RISC-V. Remove them.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoDrop CONFIG_INIT_CRITICAL
Bin Meng [Thu, 22 Nov 2018 10:26:26 +0000 (11:26 +0100)]
Drop CONFIG_INIT_CRITICAL

This is now deprecated and no board is using it. Drop it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
5 years agoriscv: align mtvec on a 4-byte boundary
Lukas Auer [Thu, 22 Nov 2018 10:26:25 +0000 (11:26 +0100)]
riscv: align mtvec on a 4-byte boundary

The machine trap-vector base address (mtvec) must be aligned on a 4-byte
boundary. Add the necessary align directive to trap_entry.

This patch also removes the global directive for trap_entry, which is
not required.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: fix inconsistent use of spaces and tabs in start.S
Lukas Auer [Thu, 22 Nov 2018 10:26:24 +0000 (11:26 +0100)]
riscv: fix inconsistent use of spaces and tabs in start.S

start.S uses both tabs and spaces after instructions. Fix this by only
using tabs after instructions.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agoriscv: implement the invalidate_icache_* functions
Lukas Auer [Thu, 22 Nov 2018 10:26:23 +0000 (11:26 +0100)]
riscv: implement the invalidate_icache_* functions

Implement the functions invalidate_icache_range() and
invalidate_icache_all().

RISC-V does not have instructions for explicit cache-control. The
functions in this patch are implemented with the memory ordering
instruction for synchronizing the instruction and data streams. This may
be implemented as a cache flush or invalidate on simple processors,
others may only invalidate the relevant cache lines.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agoriscv: hang on unhandled exceptions
Lukas Auer [Thu, 22 Nov 2018 10:26:22 +0000 (11:26 +0100)]
riscv: hang on unhandled exceptions

Hang on unhandled exceptions to prevent execution in a faulty state.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agoriscv: treat undefined exception codes as reserved
Lukas Auer [Thu, 22 Nov 2018 10:26:21 +0000 (11:26 +0100)]
riscv: treat undefined exception codes as reserved

Undefined exception codes currently lead to an out-of-bounds array
access. Prevent this by treating undefined exception codes as
"reserved".

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agoriscv: complete the list of exception codes
Lukas Auer [Thu, 22 Nov 2018 10:26:20 +0000 (11:26 +0100)]
riscv: complete the list of exception codes

Only the first four exception codes are defined. Add the missing
exception codes from the definition in RISC-V Privileged Architecture
Version 1.10.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agoriscv: do not reimplement generic io functions
Lukas Auer [Thu, 22 Nov 2018 10:26:19 +0000 (11:26 +0100)]
riscv: do not reimplement generic io functions

RISC-V U-Boot reimplements the generic io functions from
asm-generic/io.h. Remove the redundant implementation and include the
generic io.h instead.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agoriscv: make use of the barrier functions from Linux
Lukas Auer [Thu, 22 Nov 2018 10:26:18 +0000 (11:26 +0100)]
riscv: make use of the barrier functions from Linux

Replace the barrier functions in arch/riscv/include/asm/io.h with those
defined in barrier.h, which is imported from Linux. This version is
modified to remove the include statement of asm-generic/barrier.h, which
is not available in U-Boot or required.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agoriscv: fix use of incorrectly sized variables
Lukas Auer [Thu, 22 Nov 2018 10:26:17 +0000 (11:26 +0100)]
riscv: fix use of incorrectly sized variables

The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in
several places. Fix this.
In addition, BITS_PER_LONG is set to 64 on RV64I systems.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: enable -fdata-sections
Lukas Auer [Thu, 22 Nov 2018 10:26:16 +0000 (11:26 +0100)]
riscv: enable -fdata-sections

Enable the -fdata-sections compiler option for RISC-V. Buildman reports
the binary size decrease from this as 8365.3 bytes.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agoriscv: set -march and -mabi based on the Kconfig configuration
Lukas Auer [Thu, 22 Nov 2018 10:26:15 +0000 (11:26 +0100)]
riscv: set -march and -mabi based on the Kconfig configuration

Use the new Kconfig entries to construct the ISA string for the -march
compiler flag. The -mabi compiler flag is selected based on the base
integer instruction set.

With this change, the C (compressed instructions) ISA extension is now
enabled for all boards with CONFIG_RISCV_ISA_C set. Buildman reports a
decrease in binary size of 71590 bytes.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: add Kconfig entries for the C and A ISA extensions
Lukas Auer [Thu, 22 Nov 2018 10:26:14 +0000 (11:26 +0100)]
riscv: add Kconfig entries for the C and A ISA extensions

Add Kconfig entries for the C (compressed instructions) and A (atomic
instructions) ISA extensions. Only the C ISA extension is selectable.
This matches the configuration in Linux.

The Kconfig entries are not used yet. A follow-up patch will select the
appropriate compiler flags based on the Kconfig configuration.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoriscv: select CONFIG_PHYS_64BIT on RV64I systems
Lukas Auer [Thu, 22 Nov 2018 10:26:13 +0000 (11:26 +0100)]
riscv: select CONFIG_PHYS_64BIT on RV64I systems

CONFIG_PHYS_64BIT should be enabled on RV64I systems. Select it.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agoriscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
Lukas Auer [Thu, 22 Nov 2018 10:26:12 +0000 (11:26 +0100)]
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I

RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agodts: riscv: update makefile to also clean the RISC-V dts directory
Lukas Auer [Thu, 22 Nov 2018 10:26:11 +0000 (11:26 +0100)]
dts: riscv: update makefile to also clean the RISC-V dts directory

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agotools: .gitignore: add prelink-riscv
Lukas Auer [Thu, 22 Nov 2018 10:26:10 +0000 (11:26 +0100)]
tools: .gitignore: add prelink-riscv

Ignore tools/prelink-riscv.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
5 years agoMerge tag 'pull-tg18' of git://git.denx.de/u-boot-dm
Tom Rini [Fri, 23 Nov 2018 22:25:27 +0000 (17:25 -0500)]
Merge tag 'pull-tg18' of git://git.denx.de/u-boot-dm

Various minor sandbox improvements
Better buildman warning handling
Misc other things

5 years agosun8i_emac: add support for setting EMAC TX/RX delay
Icenowy Zheng [Thu, 22 Nov 2018 23:37:48 +0000 (00:37 +0100)]
sun8i_emac: add support for setting EMAC TX/RX delay

Some boards have the EMAC TX/RX lanes wired with a different length with
the clock lane, which can be workarounded by setting a TX/RX delay in
the EMAC.

This kind of delays are already defined in the newest device tree
binding of dwmac-sun8i, which has already entered linux-next.

Add support for setting these delays.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
5 years agosunxi: Fix memory 2-rank initialization for a33 cpu
Michael Trimarchi [Wed, 31 Oct 2018 19:03:16 +0000 (20:03 +0100)]
sunxi: Fix memory 2-rank initialization for a33 cpu

When we initialize the memory we need to autodetect rank and size
but this can happen only if we send the proper reset to both
memory module including cke signal.
For this reason we need initialize the physical on both channel because
we need to presume that both are connected. This way let the CLKE to be
activated at the right time with the memory reset coming from the cpu

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
5 years agosunxi-mmc: use new mode on both controllers on A64
Vasily Khoruzhick [Sat, 10 Nov 2018 04:41:46 +0000 (20:41 -0800)]
sunxi-mmc: use new mode on both controllers on A64

Using new mode improves stability of eMMC and SD cards. Without
it SPL fails to load u-boot from SD on Pinebook.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
Reviewed-by: Jagan Teki <jagan@openedev.com>
5 years agosunxi-mmc: don't double clock for new mode unconditionally
Vasily Khoruzhick [Sat, 10 Nov 2018 04:41:45 +0000 (20:41 -0800)]
sunxi-mmc: don't double clock for new mode unconditionally

Comment in Linux driver says that clock needs to be doubled only
if we use DDR modes, moreover divider has to be set accordingly.

U-boot driver doesn't declare support for any DDR modes and doesn't
set internal clock divider in CLKCR, so it doubles clock
unconditionally when new mode is used.

Some cards can't handle that and as result SPL fails to load u-boot.

Fixes: de9b1771c3b ("mmc: sunxi: Support new mode")
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
5 years agosunxi-mmc: introduce new MMC_SUNXI_HAS_MODE_SWITCH option
Vasily Khoruzhick [Sat, 10 Nov 2018 04:41:44 +0000 (20:41 -0800)]
sunxi-mmc: introduce new MMC_SUNXI_HAS_MODE_SWITCH option

Allwinner A64 has new mode but doesn't have a mode switch in CCM,
and CCM_MMC_CTRL_MODE_SEL_NEW is not defined, so compilation fails
if MMC_SUNXI_HAS_NEW_MODE is enabled

Introduce new MMC_SUNXI_HAS_MODE_SWITCH option to be able to ifdef usage
of CCM_MMC_CTRL_MODE_SEL_NEW

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[jagan: update commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
5 years agosf: Add a method to obtain the block-protect setting
Simon Glass [Tue, 6 Nov 2018 22:21:41 +0000 (15:21 -0700)]
sf: Add a method to obtain the block-protect setting

It is useful to obtain the block-protect setting of the SPI flash, so we
know whether it is fully open or (perhaps partially) write-protected. Add
a method for this. Update the sandbox driver to process this operation and
add a test.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agotest: sf: Add a simple SPI flash test
Simon Glass [Tue, 6 Nov 2018 22:21:40 +0000 (15:21 -0700)]
test: sf: Add a simple SPI flash test

The current test is a functional test, covering all the way from the
command line to the sandbox SPI driver. This is useful, but it is easier
to diagnose failures with a smaller test.

Add a simple test which reads and writes data and checks that it is stored
and retrieved correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agomisc: Update read() and write() methods to return bytes xfered
Simon Glass [Tue, 6 Nov 2018 22:21:39 +0000 (15:21 -0700)]
misc: Update read() and write() methods to return bytes xfered

At present these functions return 0 on success. For some devices we want
to know how many bytes were transferred. It seems useful to adjust the API
to be more like the POSIX read() and write() functions.

Update these two methods, a test and all users.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
5 years agostring: Include the config header
Simon Glass [Tue, 6 Nov 2018 22:21:38 +0000 (15:21 -0700)]
string: Include the config header

At present the config header is not included in this file, but it does use
a CONFIG option. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agovideo: Update video_set_default_colors() to support invert
Simon Glass [Tue, 6 Nov 2018 22:21:36 +0000 (15:21 -0700)]
video: Update video_set_default_colors() to support invert

It is useful to be able to invert the colours in some cases so that the
text matches the background colour. Add a parameter to the function to
support this.

It is strange that function takes a private data structure from another
driver as an argument. It seems better to pass the device and have the
function internally work out how to find its required information.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agobinman: Set the pathname correctly for ELF files
Simon Glass [Tue, 6 Nov 2018 22:21:33 +0000 (15:21 -0700)]
binman: Set the pathname correctly for ELF files

At present, stripped files don't have the right pathname which means that
blob compression cannot be used. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agobinman: Drop an unnecessary comma in blob handling
Simon Glass [Tue, 6 Nov 2018 22:21:32 +0000 (15:21 -0700)]
binman: Drop an unnecessary comma in blob handling

This comma is not needed. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agobinman: Add a way to enable debugging from the build
Simon Glass [Tue, 6 Nov 2018 22:21:31 +0000 (15:21 -0700)]
binman: Add a way to enable debugging from the build

When the build fails due to something wrong in binman it is sometimes
useful to get a full backtrace showing the location of the failure. Add
a BINMAN_DEBUG environment variable to support this along with some
documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agospl: lz4: Allow use of lz4 compression in SPL
Simon Glass [Tue, 6 Nov 2018 22:21:30 +0000 (15:21 -0700)]
spl: lz4: Allow use of lz4 compression in SPL

In some cases U-Boot is compressed and it is useful to be able to
decompress it in SPL. Add a Kconfig and Makefile change to allow this.
Note that this does not actually implement decompression.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agospl: Support bootstage, log, hash and early malloc in TPL
Simon Glass [Tue, 6 Nov 2018 22:21:28 +0000 (15:21 -0700)]
spl: Support bootstage, log, hash and early malloc in TPL

At present these features are supported in SPL but not TPL. Update the
Kconfig and Makefile to allow this.

Also add a few Makefile comments to make earier to track what is going on.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: Update some drivers to work in SPL/TPL
Simon Glass [Tue, 6 Nov 2018 22:21:27 +0000 (15:21 -0700)]
sandbox: Update some drivers to work in SPL/TPL

At present sandbox drivers are mostly not used before relocation. Some of
these are needed by Chromium OS verified boot, since it uses sandbox TPL,
so update them accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: cros_ec: exynos: Drop use of cros_ec_get_error()
Simon Glass [Tue, 6 Nov 2018 22:21:26 +0000 (15:21 -0700)]
sandbox: cros_ec: exynos: Drop use of cros_ec_get_error()

This function is really just a call to uclass_get_device() and there is no
reason why the caller cannot do it. Update sandbox and snow accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
5 years agosandbox: Add a function to read a host file
Simon Glass [Tue, 6 Nov 2018 22:21:25 +0000 (15:21 -0700)]
sandbox: Add a function to read a host file

Add a way to read a file from the host filesystem. This can be useful for
reading test data, for example. Also fix up the writing function which was
not the right version, and drop the debugging lines.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: log: Add a category for sandbox
Simon Glass [Tue, 6 Nov 2018 22:21:24 +0000 (15:21 -0700)]
sandbox: log: Add a category for sandbox

It seems useful to make sandbox its own log category since it is used for
so much testing. Add this as a new category.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: tpm: Allow debugging of data packages
Simon Glass [Tue, 6 Nov 2018 22:21:23 +0000 (15:21 -0700)]
sandbox: tpm: Allow debugging of data packages

This is not normally useful, so change the code to avoid writing out every
data package. This can be enabled with #define DEBUG.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agocros_ec: Add new features for events and power
Simon Glass [Tue, 6 Nov 2018 22:21:22 +0000 (15:21 -0700)]
cros_ec: Add new features for events and power

This adds new commands to the EC related to setting and clearing events
as well as controlling power-related settings.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agocros_ec: Align uclass data to a cache boundary
Simon Glass [Tue, 6 Nov 2018 22:21:21 +0000 (15:21 -0700)]
cros_ec: Align uclass data to a cache boundary

The LPC driver expects its buffer to be word-aligned. Add the required
flag to the uclass driver to ensure this.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agocros_ec: Fail if we cannot determine the flash burst size
Simon Glass [Tue, 6 Nov 2018 22:21:20 +0000 (15:21 -0700)]
cros_ec: Fail if we cannot determine the flash burst size

This value is required for flashing to work correctly. Add a check for
it.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agocros_ec: Add error logging on a few commands
Simon Glass [Tue, 6 Nov 2018 22:21:19 +0000 (15:21 -0700)]
cros_ec: Add error logging on a few commands

Add some more logging to provide more information on failures.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agocros_ec: Use uint instead of u8 for parameters
Simon Glass [Tue, 6 Nov 2018 22:21:18 +0000 (15:21 -0700)]
cros_ec: Use uint instead of u8 for parameters

There is no advantage to using a u8 for function parameters. It forces
the compiler to mask values and can increase code size. Also the command
enum has been extended to 16 bits. Update the functions to use uint
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agobuildman: Show boards with warning with w+
Simon Glass [Tue, 6 Nov 2018 23:02:13 +0000 (16:02 -0700)]
buildman: Show boards with warning with w+

At present we should boards with warnings in the same way as those with
errors. This is not ideal. Add a new 'warn' state and show these listed
in yellow to match the actual warning lines printing with -e.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agobuildman: Rename the good, better, worse variables
Simon Glass [Tue, 6 Nov 2018 23:02:12 +0000 (16:02 -0700)]
buildman: Rename the good, better, worse variables

At present we don't distinguish between errors and warnings when printing
the architecture summary. Rename the variables to better describe their
purpose.

'Worse' at present means we got an error, so use that as the name.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agobuildman: Detect dtc warnings
Simon Glass [Tue, 6 Nov 2018 23:02:11 +0000 (16:02 -0700)]
buildman: Detect dtc warnings

At present messages from the device-tree compiler like this:

  arch/arm/dts/socfpga_arria10_socdk_sdmmc.dtb: Warning
     (avoid_unnecessary_addr_size): /clocks: unnecessary
     #address-cells/#size-cells without "ranges" or child "reg" property

are detected as errors since they don't match the gcc warning regex. Add a
new one for dtc to fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agobuildman: Only print toolchain probing with -v
Simon Glass [Tue, 6 Nov 2018 23:02:10 +0000 (16:02 -0700)]
buildman: Only print toolchain probing with -v

At present --list-tool-chains prints a lot of information about the
toolchain-probing process. This is generally not very interesting.
Update buildman to print this only if --list-tool-chains is given
with -v.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 years agodm: spi: prevent setting a speed of 0 Hz
Simon Goldschmidt [Tue, 30 Oct 2018 20:09:48 +0000 (21:09 +0100)]
dm: spi: prevent setting a speed of 0 Hz

When the device tree is missing a correct spi slave description below
the bus (compatible "spi-flash" or spi-max-frequency are missing),
the 'set_speed' callback can be called with 'speed' == 0 Hz.
At least with cadence qspi, this leads to a division by zero.

Prevent this by initializing speed to 100 kHz in this case (same
fallback value as is done in 'dm_spi_claim_bus') and issue a warning
to console.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agofdt: restore board_fdt_blob_setup() declaration
Baruch Siach [Sun, 28 Oct 2018 12:41:14 +0000 (14:41 +0200)]
fdt: restore board_fdt_blob_setup() declaration

Commit 90c08fa038451d (fdt: Add device tree memory bindings) removed the
prototype declaration of board_fdt_blob_setup(), most likely by mistake.
This didn't break the build because the only file calling this function
(lib/fdtdec.c) provides a local weak definition. Restore the
declaration.

Cc: Michael Pratt <mpratt@chromium.org>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agocmd: fdt: Fix fdt address information after the movement
Hiroyuki Yokoyama [Thu, 18 Oct 2018 18:43:54 +0000 (20:43 +0200)]
cmd: fdt: Fix fdt address information after the movement

This patch fixes the address information of fdt.

wrong case:
 => fdt addr 0x48000000
 => fdt move 0x48000000 0x41000000 0xa000
 => fdt addr
The address of the fdt is 48000000

Active address in this case is 0x41000000.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agofdt: Fix uncompress_blob() for U-Boot proper
Marek Vasut [Thu, 18 Oct 2018 18:37:05 +0000 (20:37 +0200)]
fdt: Fix uncompress_blob() for U-Boot proper

When U-Boot proper is compiled with CONFIG_MULTI_DTB_FIT and tries
to call uncompress_blob(), it fails with -ENOTSUPP. This is because
the full implementation of this function which includes compression
is available only in SPL. In U-Boot proper or if the compression is
not enabled, the blob is not compressed and thus can be passed to
locate_dtb_in_fit() in fdtdec_setup() without any changes. Pass the
blob without any changes if compression is not enabled instead of
failing.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agodm: core: Widen the dump tree to show more of the driver's name.
Liviu Dudau [Mon, 15 Oct 2018 09:03:06 +0000 (10:03 +0100)]
dm: core: Widen the dump tree to show more of the driver's name.

With drivers that have prefix names that are quite long (like
'versatile_') it is useful to have a wider column for the driver's
name when dumping the device driver tree.

Also update the tests to take into account the wider output format.

Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: README: use setenv ethrotate no
Heinrich Schuchardt [Sun, 14 Oct 2018 20:01:28 +0000 (22:01 +0200)]
sandbox: README: use setenv ethrotate no

If we want to control which network interface is actually used, we have to
issue 'setenv ethrotate no'. If ethrotate is not set any interface may be
used.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: README: setting environment variables
Heinrich Schuchardt [Sun, 14 Oct 2018 19:40:02 +0000 (21:40 +0200)]
sandbox: README: setting environment variables

The command to set environment variables is setenv.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agosandbox: remove stray DEBUG
Heinrich Schuchardt [Sun, 14 Oct 2018 18:45:32 +0000 (20:45 +0200)]
sandbox: remove stray DEBUG

DEBUG should not be defined in production code.
Change printf() to debug() where this writes a debug message.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 years agodm/pci: Change the first CFG read to Vendor ID in enumeration
Hou Zhiqiang [Mon, 8 Oct 2018 08:35:47 +0000 (16:35 +0800)]
dm/pci: Change the first CFG read to Vendor ID in enumeration

As the PCIe specification recommend reading the Vendor ID register
to determine if a Function is present, read the Vendor ID of a
non-existent Function must not result in system error, so we'd better
make the first CFG read to Vendor ID instead of Header Type register
in the PCIe enumeration.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5 years agoMerge git://git.denx.de/u-boot-marvell
Tom Rini [Tue, 20 Nov 2018 17:36:47 +0000 (12:36 -0500)]
Merge git://git.denx.de/u-boot-marvell

- Clearfog GT-8K support added by Baruch / Raheeb
- const and sizes cleanup (also in MIPS) from Baruch
- Minor cleanup to db-88f6820 from Chris

5 years agoMerge branch '2018-11-19-master-imports'
Tom Rini [Tue, 20 Nov 2018 17:36:08 +0000 (12:36 -0500)]
Merge branch '2018-11-19-master-imports'

- adc enhancements
- FAT fix

5 years agofs: fat: assign rootdir sector when accessing root directory
Thomas RIENOESSL [Tue, 13 Nov 2018 13:00:59 +0000 (14:00 +0100)]
fs: fat: assign rootdir sector when accessing root directory

This fixes problems accessing drives formated under
Windows as FAT16.

Signed-off-by: Thomas RIENOESSL <thomas.rienoessl@bachmann.info>
[trini: Rebase on top of f528c140c801]
Signed-off-by: Tom Rini <trini@konsulko.com>