Marcin Ślusarz [Mon, 23 May 2022 15:09:33 +0000 (17:09 +0200)]
intel/compiler: adjust task payload offsets as late as possible
Otherwise passes which expect offsets to be in bytes (like
brw_nir_lower_mem_access_bit_sizes, called from brw_postprocess_nir)
may produce incorrect results.
Fixes 64-bit load/stores in task/mesh shaders.
Fixes:
c36ae42e4cc ("intel/compiler: Use nir_var_mem_task_payload")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16196>
Marcin Ślusarz [Fri, 6 May 2022 14:37:27 +0000 (16:37 +0200)]
intel/common: allocate space for at least one task urb
Fixes:
c93cbc77f78 ("intel/common: Add helper for URB allocation in Mesh pipeline")
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16196>
Emil Velikov [Fri, 24 Jun 2022 12:36:44 +0000 (13:36 +0100)]
c11: reinstate the original license and authorship
The original code that was copied in was Boost licensed, so keep that
in. Since Yonggang Luo has code quite some work, keep their copyright
alongside the original one.
Fixes:
b2ddec4e98f ("c11: Implement c11/time.h with c11/impl/time.c")
Fixes:
e6392fcf3d8 ("c11: Move the implementation of threads.h into c source code")
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17232>
Sviatoslav Peleshko [Fri, 24 Jun 2022 07:43:09 +0000 (10:43 +0300)]
intel/blorp: Dirty depth bounds dynamic state bits after blorp
Blorp emits its own 3DSTATE_DEPTH_BOUNDS, so we'll have to re-emit the
expected state after that.
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Fixes:
56ef501e3aa4 ("blorp: disable depth bounds")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17205>
Sviatoslav Peleshko [Thu, 23 Jun 2022 11:20:24 +0000 (14:20 +0300)]
anv: Dirty all dynamic state bits when creating command buffer state
This makes sure that we'll handle situations when the new state has
the same value as the default one, so we won't dirty some bits, and
consequently will not emit necessary commands (e.g. 3DSTATE_DEPTH_BOUNDS).
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Fixes:
48229d11 ("anv: don't emit 3DSTATE_DEPTH_BOUNDS in pipeline batch")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6722
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17205>
Marcin Ślusarz [Wed, 22 Jun 2022 16:31:08 +0000 (18:31 +0200)]
intel: fix typos found by codespell
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17191>
Boris Brezillon [Fri, 24 Jun 2022 15:42:34 +0000 (08:42 -0700)]
dzn: Enable the depthClamp feature
depthClampEnable is actually the case we support properly.
!depthClampEnable requires extra work to make sure the
depth clamping that's forced by D3D12 is inactive (setting the
viewport depth range to [0,1] and dealing with the actual range
at the shader level), and clamp the depth value read by the
fragment shader in that case. This will be addressed separately.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17231>
Boris Brezillon [Fri, 24 Jun 2022 11:28:09 +0000 (04:28 -0700)]
dzn: Enable shader{Clip,Cull}Distance
DXIL has clip/cull distance builtins too.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17231>
Boris Brezillon [Fri, 24 Jun 2022 11:24:42 +0000 (04:24 -0700)]
dzn: Enable dynamic indexing on all kind of descriptors
nir_to_dxil() supports it.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17231>
Boris Brezillon [Fri, 24 Jun 2022 11:04:46 +0000 (04:04 -0700)]
dzn: Advertise shaderImageGatherExtended support
nir_to_dxil() takes tg4 offsets into account.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17231>
Boris Brezillon [Fri, 24 Jun 2022 10:51:01 +0000 (03:51 -0700)]
dzn: Advertise anisotropic filtering support
We support it already, let's toggle the switch to expose it.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17231>
Boris Brezillon [Thu, 23 Jun 2022 16:53:31 +0000 (18:53 +0200)]
nir/serialize: Put dest last in packed_instr::tex
packed_instr::tex::dest must be last to match the packed_instr::any::dest
position.
Fixes:
35655865cbde ("nir/serialize: pack instructions better")
Cc: stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17212>
Lionel Landwerlin [Sun, 26 Jun 2022 06:36:36 +0000 (09:36 +0300)]
anv: silence border color swizzle debug message
MESA-INTEL: debug: gfx11_CreateSampler: ignored VkStructureType
1000411001
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17245>
Samuel Pitoiset [Wed, 22 Jun 2022 08:34:34 +0000 (10:34 +0200)]
radv: dump UMR waves before UMR rings
Dumping UMR rings might be slow and dumping waves before would make it
more chance to dump them without reporting "No active waves".
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17183>
Samuel Pitoiset [Wed, 22 Jun 2022 08:34:01 +0000 (10:34 +0200)]
radv: fix command line for dumping waves with UMR
GFXOFF must be disabled before dumping waves and re-enabled after.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17183>
Samuel Pitoiset [Wed, 22 Jun 2022 07:38:24 +0000 (09:38 +0200)]
radv: use RADEON_FLAG_VA_UNCACHED for the trace BO
Figured this while debugging a GPU hang with a simple CTS test. This
is to make sure data written by the CP are coherent on the CPU.
This also explains spurious GPU hang reports generated for Hitman 3
that made no sense without it. Now it's clear that this game hangs
after a DRAW_INDEX_INDIRECT packet.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17183>
Samuel Pitoiset [Fri, 24 Jun 2022 08:11:51 +0000 (10:11 +0200)]
radv: disable small primitive culling for user sample locations
The driver can't assume sample positions at (0.5, 0.5) when user
sample locations are used.
This doesn't fix anything in practice because NGGC is only enabled by
default on GFX10.3 and that extension is currently disabled on GFX10+,
but I would like to expose it at some point.
This fixes dEQP-VK.pipeline.*.sample_locations_ext.verify_location.*
(when the extension is enabled locally).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17228>
Ella Stanforth [Tue, 23 Nov 2021 22:29:48 +0000 (22:29 +0000)]
v3dv: Implement VK_KHR_performance_query
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14061>
Erico Nunes [Thu, 23 Jun 2022 15:15:39 +0000 (17:15 +0200)]
ci: Revert "CI: Lima farm is offline"
The lab is up and running again.
This reverts commit
686e20afcd32cb80b96984c8eb4428e777fbce97.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17240>
Qiang Yu [Mon, 30 May 2022 12:09:49 +0000 (20:09 +0800)]
radeonsi: replace llvm gs input handle with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
Qiang Yu [Mon, 30 May 2022 11:49:55 +0000 (19:49 +0800)]
ac/llvm: get back nir_intrinsic_load_gs_vertex_offset_amd
Will be used by radeonsi.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
Qiang Yu [Mon, 30 May 2022 11:46:15 +0000 (19:46 +0800)]
ac/nir: add triangle_strip_adjacency_fix to gs input lower
From radeonsi.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
Qiang Yu [Mon, 30 May 2022 07:03:40 +0000 (15:03 +0800)]
radeonsi: replace llvm es output with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
Qiang Yu [Tue, 31 May 2022 06:18:17 +0000 (14:18 +0800)]
ac/nir: change es output lower param to esgs_itemsize
radeonsi may add extra dword to the stride, so let's pass it
directly.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
Qiang Yu [Mon, 30 May 2022 12:06:03 +0000 (20:06 +0800)]
ac/nir: remove unused param num_reserved_es_outputs from gs input lower
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
Qiang Yu [Tue, 31 May 2022 02:35:28 +0000 (10:35 +0800)]
radeonsi: set lds for gs/es to handle nir shared memory load/store
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
Qiang Yu [Mon, 30 May 2022 06:52:57 +0000 (14:52 +0800)]
ac/nir: skip gl_ViewportIndex and gl_Layer write in ES
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
Qiang Yu [Mon, 30 May 2022 06:41:08 +0000 (14:41 +0800)]
radeonsi: implement two esgs ring nir intrinsic
nir_intrinsic_load_ring_esgs_amd
nir_intrinsic_load_ring_es2gs_offset_amd
Will be used by esgs lowering.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
Qiang Yu [Mon, 30 May 2022 06:28:32 +0000 (14:28 +0800)]
ac/llvm: fix code format alignment in visit_load_local_invocation_index
Used tab instead of space.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
Qiang Yu [Sat, 28 May 2022 14:23:40 +0000 (22:23 +0800)]
radeonsi: replace llvm tes input load with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Sat, 28 May 2022 14:20:08 +0000 (22:20 +0800)]
radeonsi: set uses_vmem_load_other for nir_intrinsic_load_buffer_amd
Before lower TES load input to load buffer, mark this flag for this
intrinsic, otherwise we get corruption with GFX10 after the lowering.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Sat, 28 May 2022 10:09:56 +0000 (18:09 +0800)]
radeonsi: enable PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS
This can remove special handling of tessfactors which also benifit
the nir lower pass which does not handle these as system value.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Sat, 28 May 2022 09:52:35 +0000 (17:52 +0800)]
radeonsi: replace llvm tcs output with nir lower pass
Remove the store_tcs_outputs abi, we can use common output abi
to handle the tessfactor pass as vgpr.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Wed, 1 Jun 2022 09:13:00 +0000 (17:13 +0800)]
ac/nir: add no_input_lds_space param to hs output lower
This is used by radeonsi to save some lds space when all LS output
is passed by register.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Wed, 25 May 2022 11:35:15 +0000 (19:35 +0800)]
ac/llvm: handle write mask for nir_intrinsic_store_buffer_amd
tess lowering may generate buffer store with partial write mask.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Tue, 24 May 2022 07:09:00 +0000 (15:09 +0800)]
radeonsi: implement nir_intrinsic_load_tess_rel_patch_id_amd for both tcs and tes
radv will lower this intrinsic before gets to llvm, so we just need to
implement it in radeonsi.
The tes version will be used in tess lower too.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Tue, 24 May 2022 06:43:36 +0000 (14:43 +0800)]
radeonsi: implement nir_intrinsic_load_ring_tess_offchip(_offset)_amd
Used by tess lower latter.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Tue, 24 May 2022 06:40:05 +0000 (14:40 +0800)]
radeonsi: preload tess offchip ring for tcs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Sigend-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Fri, 27 May 2022 09:39:18 +0000 (17:39 +0800)]
ac/nir: add wave_size parameter to ac_nir_lower_hs_outputs_to_mem
Used by radeonsi and radv to reflect true wave size used, not minimal size.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Mon, 23 May 2022 12:27:55 +0000 (20:27 +0800)]
ac/nir: add pass_tessfactors_by_reg param to hs output lower
radeonsi won't emit tess factor in the lower pass, need to keep
the output for llvm backend to pass it as parameter. This is used
by radeonsi for an optimization to save LDS write.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Mon, 23 May 2022 09:26:00 +0000 (17:26 +0800)]
ac/nir: use nir_intrinsic_load_hs_out_patch_data_offset_amd in tess lower
radeonsi load this from SGPR arg, can't use static value because TCS output
and TES input may not match (TCS output is not a key for TES) and
determined in runtime.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Mon, 23 May 2022 09:23:57 +0000 (17:23 +0800)]
ac/nir: add nir_intrinsic_load_hs_out_patch_data_offset_amd
Also add radv and radeonsi implementation. Will be used in tess lowering.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Mon, 23 May 2022 08:25:15 +0000 (16:25 +0800)]
ac/nir: remove unused parameter in tes input lower
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Mon, 23 May 2022 06:42:06 +0000 (14:42 +0800)]
radeonsi: implement nir_intrinsic_load_tcs_num_patches_amd
Used by ac_nir_lower_tess_io_to_mem.c.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Fri, 20 May 2022 09:27:27 +0000 (17:27 +0800)]
radeonsi: replace llvm based fixed tcs with nir
Create nir passthrough shader with explicit input/output and vertex
output count so that it can be handled by compiler same as user tcs.
The drawback is we create more si_shader_selector with different
input/output and vertex output count which was handled by compiler
backend before.
As fixed function tcs can be handled like user tcs, we don't need
the dedicated fixed_func_tcs_shader state either.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Wed, 18 May 2022 09:12:58 +0000 (17:12 +0800)]
radeonsi: add si_create_passthrough_tcs
For replacing si_create_fixed_func_tcs.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Wed, 18 May 2022 08:57:17 +0000 (16:57 +0800)]
radeonsi: support multi stage shader state creation in nir shaderlib
For creating tcs passthrough shader.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Fri, 27 May 2022 09:32:45 +0000 (17:32 +0800)]
radeonsi: use si_shader as parameter in si_get_nir_shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Fri, 27 May 2022 09:24:41 +0000 (17:24 +0800)]
radeonsi: deserialize nir binary in si_check_blend_dst_sampler_noop
We can do this parse with original nir instead of shader key pass
applied nir in si_get_nir_shader.
This can free si_get_nir_shader to just use si_shader as parameter.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
Qiang Yu [Fri, 17 Jun 2022 07:36:08 +0000 (15:36 +0800)]
radv: no need to do gs_alloc_req for newer chips in ngg vs/tes
Copy from radeonsi.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17130>
Qiang Yu [Wed, 15 Jun 2022 02:34:51 +0000 (10:34 +0800)]
ac/llvm: conditionally check wave id in gs sendmsg
nir lowering already call this with wave id check, no need to
check inside ac_build_sendmsg_gs_alloc_req again.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17130>
Bas Nieuwenhuizen [Mon, 13 Jun 2022 20:17:19 +0000 (22:17 +0200)]
radv: Deal with derefs from opaque types in function parameters.
Needs more copy propagation before nir_opt_derefs picks it up.
Note that the full general problem of opaque types stored in
intermediate variables is still open, but that seems like a whole
can of worms, and no sense to have gfxbench stay broken during the
time it takes to solve that.
Cc: mesa-stable
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5945
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17012>
Alessandro Astone [Sat, 18 Jun 2022 16:28:26 +0000 (18:28 +0200)]
Android.mk: Intermediate output paths may already be absolute
That is the case when OUT_DIR_COMMON_BASE is set.
Only prefix paths with AOSP_ABSOLUTE_PATH if they're relative.
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16674>
Alessandro Astone [Sat, 18 Jun 2022 16:16:09 +0000 (18:16 +0200)]
Android.mk: Generate the dummy source in local-generated-sources-dir
A source file cannot be otherwise referenced by absolute path.
That happens when OUT_DIR_COMMON_BASE is set.
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16674>
Alessandro Astone [Sat, 18 Jun 2022 16:10:34 +0000 (18:10 +0200)]
Android.mk: Make mesa3d-lib work with absolute path meson outputs
LOCAL_PREBUILT_MODULE_FILE is the only variable that allows
specifying the absolute path to a prebuilt.
That happens when OUT_DIR_COMMON_BASE is set.
Since it does not have multilib variants, define two separate
libraries for multilib
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16674>
Alessandro Astone [Sat, 18 Jun 2022 14:20:37 +0000 (16:20 +0200)]
Android.mk: Cleanup mesa3d-lib
Properly cleanup variables before declaring a library.
Explicitly require library dependencies.
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16674>
Kenneth Graunke [Thu, 23 Jun 2022 18:44:18 +0000 (11:44 -0700)]
iris: Update comment about 2GB dynamic state range
We tracked this down with the HW teams back in 2020 and there's now a
documented workaround. Comments from the HW team say this applies all
the way through XeHP but we're not sure beyond that.
This is a bug that we hit but the Windows drivers didn't because Jason
decided to allocate our memory structures from the top end of the VMA
range explicitly to catch bugs like this, while Windows allocates from
zero and up, so they would need to allocate more than 2GB of dynamic
state before running into it.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4880
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17216>
Ryan Neph [Thu, 23 Jun 2022 17:56:28 +0000 (10:56 -0700)]
venus: support VK_KHR_copy_commands2
Signed-off-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17226>
Ryan Neph [Fri, 24 Jun 2022 06:57:24 +0000 (23:57 -0700)]
venus: enable VK_EXT_image_view_min_lod
Signed-off-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17227>
Ryan Neph [Fri, 24 Jun 2022 06:31:29 +0000 (23:31 -0700)]
venus: update venus-protocol with VK_EXT_image_view_min_lod
Copy in auto-generated protocol bindings.
Signed-off-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17227>
Jason Ekstrand [Fri, 6 May 2022 19:53:03 +0000 (14:53 -0500)]
vulkan/render_pass: Support VkAttachmentSampleCountInfoAMD
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16953>
Jason Ekstrand [Wed, 25 May 2022 21:37:32 +0000 (16:37 -0500)]
vulkan/render_pass: Allow for mixed sample counts
RADV supports VK_AMD_mixed_attachment_samples which does exactly what it
sounds like.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16953>
Jason Ekstrand [Fri, 6 May 2022 23:14:26 +0000 (18:14 -0500)]
vulkan/render_pass: Pass sample locations to barriers
This is required for depth/stencil images created with
VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16953>
Jason Ekstrand [Thu, 12 May 2022 21:47:46 +0000 (16:47 -0500)]
vulkan/render_pass: Use a special layout for self-dependencies
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16953>
Jason Ekstrand [Tue, 31 May 2022 21:14:12 +0000 (16:14 -0500)]
anv: Use CmdBeginRendering for resumes in BeginCommandBuffer when possible
This lets us avoid the code duplication between BeginRendering and
BeginCommandBuffer and also lets us stop crawling core render pass
structs directly and instead focus on dynamic rendering concepts.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16953>
Jason Ekstrand [Tue, 31 May 2022 20:53:51 +0000 (15:53 -0500)]
vulkan/render_pass: Add a better helper for render pass inheritance
Instead of making drivers dive into the render pass and framebuffer
themselves, provide a helper that constructs a VkRenderingInfo for a
render pass resume that they can use instead. This should reduce code
duplication between driver implementations of BeginRendering and
BeginCommandBuffer.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16953>
Mike Blumenkrantz [Fri, 24 Jun 2022 16:02:21 +0000 (12:02 -0400)]
zink: add a turnip driver workaround for EXT_depth_clip_enable
this is broken
ref #6732
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17237>
Mike Blumenkrantz [Fri, 24 Jun 2022 16:01:06 +0000 (12:01 -0400)]
zink: fix-ish depth clipping without VK_EXT_depth_clip_enable
if this extension is unsupported, use the previous behavior and hope for the best
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17237>
Jason Ekstrand [Tue, 2 Mar 2021 03:25:11 +0000 (21:25 -0600)]
nir/opt_memcpy: Add another case for function_temp
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> (1.5 years later)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13166>
Jason Ekstrand [Tue, 2 Mar 2021 03:22:06 +0000 (21:22 -0600)]
nir: Add an options parameter to deref_instr_has_complex_use
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> (1.5 years later)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13166>
Jason Ekstrand [Sat, 24 Oct 2020 21:48:16 +0000 (16:48 -0500)]
nir/opt_memcpy: lower copies to/from tightly packed types
v2: Add comment by Jason (Lionel)
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> (1.5 years later)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13166>
Mike Blumenkrantz [Fri, 24 Jun 2022 18:15:06 +0000 (14:15 -0400)]
zink: remove another zink/tu fail
fixed in
f1c1b9687e8d58b62df5bc563c784cffda325611
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17241>
Boris Brezillon [Fri, 24 Jun 2022 12:17:22 +0000 (05:17 -0700)]
ci/dzn: Copy testlog.{css,xsl} to the result dir
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17235>
Boris Brezillon [Fri, 24 Jun 2022 09:38:55 +0000 (02:38 -0700)]
microsoft/compiler: Fix emit_ubo_var()
get_dword_size() is misleading, its name implies it's returning
a size in dwords, but it's actually returning a size in bytes.
This led to a wrong size passed to emit_cbv(). Instead of fixing
get_dword_size(), let's inline the code in emit_ubo_var().
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17230>
Boris Brezillon [Tue, 26 Apr 2022 09:56:15 +0000 (02:56 -0700)]
dzn: Transition resource to RENDER_TARGET/DEPTH_WRITE before clears
When clear_attachment() is called, we must ensure the resource is
in the DEPTH_WRITE or RENDER_TARGET state.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17229>
Boris Brezillon [Fri, 24 Jun 2022 15:12:16 +0000 (08:12 -0700)]
dzn: Clamp depthBiasConstantFactor when doing the float -> int conversion
If we don't do that, we might end up with an integer overflow/underflow.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17236>
Boris Brezillon [Fri, 24 Jun 2022 13:15:03 +0000 (06:15 -0700)]
dzn: Fix CmdPushConstants()
The original offset value is overwritten in our first for(i: num_states)
iteration, messing up the compute push constant update if stageFlags
applies to both compute and graphics.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17233>
Danylo Piliaiev [Tue, 21 Jun 2022 10:08:54 +0000 (13:08 +0300)]
tu: Don't count 3d blits in QUERY_TYPE_PRIMITIVES_GENERATED
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17164>
Danylo Piliaiev [Tue, 21 Jun 2022 09:41:30 +0000 (12:41 +0300)]
tu: Use hw binning or sysmem with QUERY_TYPE_PRIMITIVES_GENERATED
Without hw binning in gmem primitives generated query result could be
multiplied by tile count, which is not expected by OpenGL users for
GL_PRIMITIVES_GENERATED.
See https://gitlab.khronos.org/vulkan/vulkan/-/issues/3131
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17164>
Rhys Perry [Thu, 23 Jun 2022 15:30:17 +0000 (16:30 +0100)]
aco: cleanup force-waitcnt output
If we don't reset ctx.vm_cnt/gpr_map/etc, this will spam a lot of
s_waitcnt instructions.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17207>
Yonggang Luo [Thu, 16 Jun 2022 02:26:58 +0000 (10:26 +0800)]
CODEOWNERS: evelikov renamed to xexaxo
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17072>
Yonggang Luo [Wed, 15 Jun 2022 03:51:45 +0000 (11:51 +0800)]
CODEOWNERS: Update c11 code owners
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17072>
Sviatoslav Peleshko [Mon, 20 Jun 2022 09:47:25 +0000 (12:47 +0300)]
intel/blorp/gen6: Set BLEND_STATEChange only if emitting the blend state
This change is pretty straightforward: if set this field when we don't emit
the blend state, then the garbage at offset=0 will be set as a blend state,
and this will cause artifacts until the proper blend state will be given.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6544
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6232
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17132>
Karmjit Mahil [Thu, 23 Jun 2022 09:30:45 +0000 (10:30 +0100)]
pvr: Rename loop iterator variable.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17206>
Karmjit Mahil [Tue, 17 May 2022 15:27:37 +0000 (16:27 +0100)]
pvr: Fix off by 1 error in buffer_id for ubo pds program.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17206>
Karmjit Mahil [Tue, 17 May 2022 08:52:02 +0000 (09:52 +0100)]
pvr: Handle vdm degen_cull_enable.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17206>
Karmjit Mahil [Thu, 9 Jun 2022 12:03:30 +0000 (13:03 +0100)]
pvr: Fix physical device limits.
This commit changes to the physical device limits which were
missed during the 1.17 transition.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17206>
Lionel Landwerlin [Thu, 23 Jun 2022 12:26:17 +0000 (15:26 +0300)]
anv: make apply_pipeline_layout/compute_push_layout visible to NIR debug
Useful for debug.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17209>
Georg Lehmann [Tue, 21 Jun 2022 14:44:33 +0000 (16:44 +0200)]
radv: Don't check if we need to copy immutable samplers for non push templates.
This should allow the compiler to optimize this out because it knows that
cmd_buffer is NULL.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17166>
Andres Gomez [Wed, 22 Jun 2022 11:27:18 +0000 (14:27 +0300)]
ci: add wrapper script for Valve's traces runner
Contributed by Charlie Turner.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17184>
Andres Gomez [Wed, 22 Jun 2022 12:36:02 +0000 (15:36 +0300)]
ci: move b2c artifacts to its own directory
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17184>
Charlie Turner [Thu, 20 Jan 2022 08:15:25 +0000 (08:15 +0000)]
ci: upgrade to DXVK v1.10.1
Additionally, improve the building scripts.
Contributed by Andres Gomez.
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17184>
Charlie Turner [Wed, 22 Jun 2022 08:05:37 +0000 (11:05 +0300)]
ci: upgrade gfxreconstruct build to v0.9.10
Additionally improve the style of the build script.
- Instead of using platform build tools, use the CMake wrappers
- Instead of build all targets, then manually stripping, use the
CMake helpers.
Contributed by Andres Gomez.
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17184>
Charlie Turner [Wed, 22 Jun 2022 07:35:26 +0000 (10:35 +0300)]
ci: add Linux build of apitrace
This is needed for some of Valve's GL traces to run.
Additionally, make the building commands for apitrace more standard.
Contributed by Andres Gomez.
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17184>
Charlie Turner [Tue, 2 Nov 2021 13:48:23 +0000 (13:48 +0000)]
ci: fix shellcheck violations in the test-vk building script
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17184>
Andres Gomez [Wed, 22 Jun 2022 07:17:45 +0000 (10:17 +0300)]
ci: install gfxinfo-mupuf in the test-vk image
This python module is needed for Valve's tracing jobs.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17184>
Andres Gomez [Wed, 22 Jun 2022 07:01:18 +0000 (10:01 +0300)]
ci: install a more recent version of Wine in the test-vk image
Debian's Wine 5.0 has shown some problems when running Vulkan tests in
the past. Let's install the stable version provided by WineHQ (7.0 at
this time).
v2:
- Remove OBS repository for Wine since it is unused (previously, it
was providing libfaudio0) (Daniel).
v3:
- Add WineHQ's repository GPG key (Michel).
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org> [v2]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17184>
Andres Gomez [Wed, 22 Jun 2022 19:35:46 +0000 (22:35 +0300)]
radv/ci: update vkd3d-proton results for AMD's Kabini
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17184>
Mike Blumenkrantz [Mon, 20 Jun 2022 15:25:43 +0000 (11:25 -0400)]
zink: use tracked barrier info for generated barriers
this should be simpler to read through and maintain while providing
the same results as well as some possible perf and compile time improvements
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17192>
Mike Blumenkrantz [Mon, 20 Jun 2022 15:20:44 +0000 (11:20 -0400)]
zink: track gfx/compute descriptor barrier info
update_barriers has steadily grown more and more complex when the original
idea was for it to be a small function to handle deferred jit barriers and
simplify sync in patterns like bind_ubo -> draw -> buffer_subdata -> draw
instead, track the pending barrier info at bind time so that the stages and
access are already updated by the time draw/compute are reached
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17192>