Alyssa Rosenzweig [Fri, 24 Jun 2022 13:09:06 +0000 (09:09 -0400)]
pan/bi: Handle uhadd, urhadd opcodes
Fixes integer_ops.integer_hadd.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Thu, 23 Jun 2022 22:33:37 +0000 (18:33 -0400)]
pan/va: Fix v4s8 form of R2 opcodes
The XML had a typo which was copypasted (incorrectly) into various instructions.
Fixes a pile of integer_ops subtests.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Thu, 23 Jun 2022 22:21:59 +0000 (18:21 -0400)]
pan/va: Pack IADD.sat bit
Fixes 32-bit portion of integer_ops integer_add_sat.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Fri, 24 Jun 2022 15:44:25 +0000 (11:44 -0400)]
pan/bi: Strip negate when lowering swizzles
When we lower swizzles, we move source modifiers (except for the swizzle) after
the swizzle operation. In particular, we change the order of composition for
negates and abs. However, copying the source will copy the modifiers unless we
specifically strip the extra modifiers. That's harmless in practice on Bifrost,
which doesn't check for extraneous modifiers, but is incorrect IR and trips an
assertion in the Valhall packing code.
Fixes test_relations.relational_bitselect.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Fri, 24 Jun 2022 13:07:42 +0000 (09:07 -0400)]
pan/bi: Lower swizzles for 8-bit shifts
Fixes integers_ops.integer_ctz
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Wed, 22 Jun 2022 20:52:45 +0000 (16:52 -0400)]
pan/bi: Test some 8-bit swizzle lowering
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Wed, 22 Jun 2022 20:52:58 +0000 (16:52 -0400)]
pan/bi: Lower some 8-bit swizzles
Fixes the 8-bit portion of OpenCL's integer_ops.integer_clz test case.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Wed, 22 Jun 2022 20:36:11 +0000 (16:36 -0400)]
pan/bi: Unit test swizzle lowering
We're about to extend this pass to support 8-bit swizzles. That will be a
nontrivial change, so let's get some testing for what's already in the pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Wed, 22 Jun 2022 20:57:43 +0000 (16:57 -0400)]
pan/va: Fix missing swizzle on CLZ.v2u16
Fixes 16-bit portion of integer_clz.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Mon, 19 Sep 2022 01:05:01 +0000 (21:05 -0400)]
panfrost: Assume launch_grid parameters always change
This is only a theoretical bug fix because, for now, we always reemit
everything. But this aligns launch_grid with draw_vbo and makes the intention
explicit, both seem like good things to me.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Mon, 19 Sep 2022 02:08:42 +0000 (22:08 -0400)]
panfrost: Honour flush-to-zero controls on Valhall
Fixes math_bruteforce.atan2 and contractions tests.
For OpenCL, we want to flush fp32 and preserve fp16, applying to both inputs and
outputs so F16_TO_F32 acts as preserve, which implements CL spec text:
> Denormalized numbers for the half data type which may be generated when
converting a float to a half using vstore_half and converting a half to a float
using vload_half cannot be flushed to zero
Note that our libclc builds flush denorms and rusticl does not advertise denorms
so we're expected to flush to zero. rusticl correctly sets the desired float
controls, we just have to match to the hardware requirements.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Thu, 7 Jul 2022 17:48:11 +0000 (13:48 -0400)]
panfrost: Advertise PIPE_CAP_INT64
nir_lower_int64 should be able to chew through everything anyway. Fixes
compilers.feature_macro (with LLVM 15).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Mon, 27 Jun 2022 15:38:59 +0000 (11:38 -0400)]
panfrost: Bump PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
Bump to 2048, the minimum maximum for image support in the full profile of
OpenCL. The relevant hardware limit is 65536 so we have plenty of clearance.
Fixes api.get_image1d_array_info.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Tue, 13 Sep 2022 16:04:32 +0000 (12:04 -0400)]
panfrost: Upload default sampler for txf
In NIR, txf does not take a sampler. However, in the hardware it does take a
sampler. If there is no sampler bound and we use txf, the hardware will read
back all-0's due to bounds checking. As a workaround, bind a trivial sampler and
use that.
As-is this workaround is Valhall specific, making use of an extra resource
table. I'm punting on generalizing back to Bifrost until I can discuss the issue
in more depth with Jason and Karol and figure out the right fix.
Fixes api.image_properties_query.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Wed, 22 Jun 2022 14:32:12 +0000 (10:32 -0400)]
panfrost: Allow compiling MESA_SHADER_KERNEL
Required for Rusticl.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Alyssa Rosenzweig [Tue, 21 Jun 2022 20:55:44 +0000 (16:55 -0400)]
panfrost: Default pipe->clear_texture impl
For rusticl.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18656>
Jason Ekstrand [Thu, 7 Apr 2022 21:45:22 +0000 (16:45 -0500)]
nir/load_libclc: Don't add generic variants that already exist
At some point in the future, adding generic variants to libclc will
hopefully no longer be needed. At that point, we don't want the NIR
code adding duplicates. Check if the generic version already exists
and, if it does, don't re-add it.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18675>
Jason Ekstrand [Thu, 7 Apr 2022 21:44:08 +0000 (16:44 -0500)]
nir: Add a helper for finding a function by name
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18675>
Jason Ekstrand [Thu, 7 Apr 2022 22:04:04 +0000 (17:04 -0500)]
spirv: Don't use libclc for wait_group_events
v2: Drop old code (Karol)
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18675>
Vinson Lee [Sun, 18 Sep 2022 18:02:04 +0000 (11:02 -0700)]
egl/dri2: Fix missing return with dri2_egl_error_unlock.
Fix defect reported by Coverity Scan.
Double unlock (LOCK)
double_unlock: dri2_egl_error_unlock unlocks dri2_dpy->lock while it is unlocked.
Fixes:
f1efe037dfd ("egl/dri2: Add display lock")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18655>
Alyssa Rosenzweig [Sun, 18 Sep 2022 15:38:12 +0000 (11:38 -0400)]
agx: Convert and clamp array indices in NIR
..Rather than at backend IR translation time. This is considerably
simpler because we can use the txs lowering instead of special casing
array sizes. Unfortunately it generates worse code, but that gap should
close once nir_opt_preamble is wired in.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18652>
Alyssa Rosenzweig [Sun, 18 Sep 2022 23:54:44 +0000 (19:54 -0400)]
panfrost: Adapt emit_shared_memory for indirect dispatch
Indirect dispatch does not actually require any dynamic memory allocation, even
with shared memory. We just need to set wls_instances to some (mostly arbitrary)
value, statically allocate memory based on that, and let the hardware throttle
workgroups to fit if needed.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18661>
Alyssa Rosenzweig [Tue, 21 Jun 2022 20:52:01 +0000 (16:52 -0400)]
rusticl: Build Panfrost
We want OpenCL, too!
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18663>
James Park [Thu, 8 Sep 2022 16:15:00 +0000 (09:15 -0700)]
meson,amd: Remove Windows libelf wrap
Functionality isn't worth the maintenance cost.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18478>
Illia Polishchuk [Tue, 13 Sep 2022 09:22:33 +0000 (12:22 +0300)]
driconf/Intel: Add lower_depth_range_rate option workaround for Homerun Clash misrendering issue
Intel has different Z interpolation float point rounding
than other mesa gpus
For example gl_Position.z = 0.0 will be interpolated to
gl_FragCoord.z = 0.5 for all gpus
gl_FragCoord = -0.
00000001 will be interpolated to
gl_FragCoord.z = 0.
4999999702 for Intel
and rounded to gl_FragCoord.z = 0.5 for other gpus
Games with LEQUAL depth func will fail depth test on Intel
and will pass it on other gpus in such case
This workaround lowers translated depth range
and several gl_FragCoord.z coords with extra small difference
will be translated to the same UINT16\UINT24\UINT32
value of an integer depth buffer
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7199
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18412>
Marcin Ślusarz [Thu, 8 Sep 2022 14:18:43 +0000 (16:18 +0200)]
anv: fix emission of primitive replication packet for mesh stage
anv_pipeline_get_last_vue_prog_data (used by emit_3dstate_primitive_replication)
doesn't work for mesh stage.
Fixes:
ae57628dd5c ("anv: Drop anv_pipeline::use_primitive_replication")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18495>
Dave Airlie [Mon, 19 Sep 2022 06:33:59 +0000 (16:33 +1000)]
lavapipe: fix 3d depth stencil image clearing.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18665>
Mike Blumenkrantz [Tue, 30 Aug 2022 15:24:25 +0000 (11:24 -0400)]
zink: use screen interfaces for pipeline barriers
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18628>
Mike Blumenkrantz [Tue, 30 Aug 2022 15:20:04 +0000 (11:20 -0400)]
zink: add screen interfaces for pipeline barriers
this will enable direct calling of the right function without the overhead
of having conditionals in the barrier functions themselves
eventually, the '2' variants will be widely enough deployed that
this can be deleted
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18628>
Mike Blumenkrantz [Tue, 30 Aug 2022 15:19:41 +0000 (11:19 -0400)]
zink: add functions for using '2' variants of pipeline barriers
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18628>
Mike Blumenkrantz [Tue, 30 Aug 2022 14:10:38 +0000 (10:10 -0400)]
zink: add have_vulkan13 to device info
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18628>
Mike Blumenkrantz [Thu, 1 Sep 2022 13:16:01 +0000 (09:16 -0400)]
zink: rewrite clears on fb bind if only the format has changed
in some apps (hl2), there's a weird sequence like:
* bind attachment with srgb view
* clear
* bind attachment with base format
* draw
rewriting the clear color like this avoids unnecessarily triggering
a renderpass
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18627>
Mike Blumenkrantz [Fri, 2 Sep 2022 14:26:25 +0000 (10:26 -0400)]
zink: make void clears more robust
void clears are intended to be the first clear applied to a surface,
so ensure that these don't clobber any scissored clears
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18627>
Mike Blumenkrantz [Fri, 2 Sep 2022 14:25:35 +0000 (10:25 -0400)]
zink: split up get_clear_data()
make the array extension part reusable
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18627>
Mike Blumenkrantz [Fri, 2 Sep 2022 14:10:01 +0000 (10:10 -0400)]
zink: don't add void clears if a full clear already exists
this otherwise may clobber other clears or add unnecessary duplicates
Fixes:
7ea7d0687b8 ("zink: inject a 0,0,0,1 clear for RGBX formats")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18627>
David Heidelberg [Fri, 16 Sep 2022 13:06:53 +0000 (15:06 +0200)]
ci/intel: drop glmark2 terrain trace
See: https://gitlab.freedesktop.org/gfx-ci/tracie/traces-db/-/merge_requests/50
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18633>
David Heidelberg [Fri, 16 Sep 2022 13:06:19 +0000 (15:06 +0200)]
ci/panfrost: drop glmark2 terrain trace
See: https://gitlab.freedesktop.org/gfx-ci/tracie/traces-db/-/merge_requests/50
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18633>
David Heidelberg [Fri, 16 Sep 2022 13:05:34 +0000 (15:05 +0200)]
ci/radeonsi: drop glmark2 terrain trace
See: https://gitlab.freedesktop.org/gfx-ci/tracie/traces-db/-/merge_requests/50
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18633>
Alyssa Rosenzweig [Thu, 7 Jul 2022 16:02:03 +0000 (12:02 -0400)]
panfrost: Evict the BO cache when allocation fails
If memory allocation fails, we look for a suitable sized BO in the BO cache and
wait until we can use its memory. That usually works, but there's a case when it
can fail despite sufficient memory in the system: BOs in the BO cache
contributing to memory pressure but none of them being of sufficient size. This
case is not just theoretical: it's seen in the OpenCL
test_non_uniform_work_group, which puts the system under considerable memory
pressure with an unusual allocation pattern.
To handle this case, try evicting *everything* from the BO cache and stalling
in order to allocate, if the above attempts failed. Fixes the following error:
DRM_IOCTL_PANFROST_CREATE_BO failed: No space left on device
on the aforementioned OpenCL test.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18579>
Pavel Ondračka [Thu, 15 Sep 2022 08:37:12 +0000 (10:37 +0200)]
r300: fix register rewrite when converting rbg instructions to alpha
Example from dEQP-GLES2.functional.shaders.indexing.tmp_array.float_dynamic_write_dynamic_loop_read_fragment
Fragment Program: after 'pair translate'
0: src0.xyz = input[0], src1.xyz = const[5]
MAD temp[0].xyz, src0.xxx, src1.Hyz, src0.000
1: src0.xyz = const[1], src1.xyz = const[6]
MAD temp[1].xyz, src0.xxx, src0.111, -src1.x1z
2: src0.xyz = temp[1]
CMP temp[1].xyz, src0.000, src0.111, src0.xyz
3: src0.xyz = temp[0], src1.xyz = input[0], src2.xyz = temp[1]
CMP temp[2].x, src0.x__, src1.x__, -src2.y__
4: src0.xyz = input[0], src1.xyz = temp[0], src2.xyz = temp[1]
CMP temp[3].x, src0.x__, src1.x__, -src2.z__
5: src0.xyz = temp[1]
MAX temp[4].x, src0.x__, src0.z__
6: src0.xyz = temp[0], src1.xyz = input[0], src2.xyz = temp[4]
CMP temp[4].x, src0.x__, src1.x__, -src2.x__
7: src0.xyz = temp[3], src1.xyz = input[0], src2.xyz = temp[1]
CMP temp[3].x, src0.x__, src1.x__, -src2.x__
8: src0.xyz = input[0], src1.xyz = temp[2], src2.xyz = temp[1]
CMP temp[2].x, src0.x__, src1.x__, -src2.x__
9: src0.xyz = temp[1]
MAD temp[1].x, src0.x__, src0.y__, src0.000
10: src0.xyz = input[0], src1.xyz = temp[0], src2.xyz = temp[1]
CMP temp[1].x, src0.x__, src1.x__, -src2.x__
11: src0.xyz = const[2], src1.xyz = const[6]
MAD temp[5].xyz, src0.xxx, src0.111, -src1.x1z
12: src0.xyz = temp[5]
CMP temp[5].xyz, src0.000, src0.111, src0.xyz
13: src0.xyz = temp[0], src1.xyz = temp[2], src2.xyz = temp[5]
CMP temp[6].x, src0.y__, src1.x__, -src2.y__
14: src0.xyz = temp[3], src1.xyz = temp[0], src2.xyz = temp[5]
CMP temp[7].x, src0.x__, src1.y__, -src2.z__
15: src0.xyz = temp[5]
MAX temp[8].x, src0.x__, src0.z__
16: src0.xyz = temp[0], src1.xyz = temp[4], src2.xyz = temp[8]
CMP temp[4].x, src0.y__, src1.x__, -src2.x__
17: src0.xyz = temp[7], src1.xyz = temp[3], src2.xyz = temp[5]
CMP temp[3].x, src0.x__, src1.x__, -src2.x__
18: src0.xyz = temp[2], src1.xyz = temp[6], src2.xyz = temp[5]
CMP temp[2].x, src0.x__, src1.x__, -src2.x__
....
This will be pair scheduled to:
Fragment Program: after 'pair scheduling'
0: src0.xyz = input[0], src1.xyz = const[5] // original inst 0
MAD temp[0].xyz, src0.xxx, src1.Hyz, src0.000
1: src0.xyz = const[1], src1.xyz = const[6] // original inst 1
MAD temp[1].xyz, src0.xxx, src0.111, -src1.x1z
2: src0.xyz = const[2], src1.xyz = const[6] // original inst 11
MAD temp[5].xyz, src0.xxx, src0.111, -src1.x1
3: src0.xyz = temp[1] // original inst 2
CMP temp[1].xyz, src0.000, src0.111, src0.xyz
4: src0.xyz = temp[1], src1.xyz = temp[0], src2.xyz = input[0]
MAX temp[4].x, src0.x__, src0.z__ // original inst 5
CMP temp[2].w, src1.x, src2.x, -src0.y // original inst 3
5: src0.xyz = input[0], src1.xyz = temp[0], src2.xyz = temp[1]
CMP temp[3].w, src0.x, src1.x, -src2.z // original inst 4
6: src0.xyz = temp[5], src0.w = temp[2], src1.xyz = input[0], src2.xyz = temp[1]
CMP temp[5].xyz, src0.000, src0.111, src0.xyz // original inst 12
CMP temp[5].w, src1.x, src0.w, -src2.x // original inst 8
7: src0.xyz = temp[0], src0.w = temp[5], src1.xyz = temp[2], src2.xyz = temp[5]
CMP temp[6].x, src0.y__, src0.w__, -src2.y__ // original inst 13
8: src0.xyz = temp[5], src0.w = temp[3], src1.xyz = input[0], src2.xyz = temp[1]
MAX temp[8].x, src0.x__, src0.z__ // original inst 15
CMP temp[5].w, src0.w, src1.x, -src2.x // original inst 7
9: src0.xyz = temp[3], src0.w = temp[5], src1.xyz = temp[0], src2.xyz = temp[5]
CMP temp[7].x, src0.w__, src1.y__, -src2.z__ // original inst 14
10: src0.xyz = temp[2], src0.w = temp[5], src1.xyz = temp[6], src2.xyz = temp[5]
CMP temp[2].x, src0.w__, src1.x__, -src2.x__ // original inst 18
11: src0.xyz = temp[7], src0.w = temp[5], src1.xyz = temp[3], src2.xyz = temp[5]
CMP temp[3].x, src0.x__, src0.w__, -src2.x__ // original inst 17
....
The problem is that instruction 11 (which was instruction 17 before the scheduling) now reads
a wrong source for src0. It initially used the result of instruction 8 (now scheduled as 6),
but now it reads from instruction 8 (corresponding to instruction 7 before the scheduling).
The bug is quite subtle and needs few conditions to reproduce:
- there is a loop, therefore we skip the the register rename
pass and hence don't have the ssa-like form,
- there are at least two rgb instructions writing the same register
and both are convertible to alpha instruction,
- there is excess of rgb instructions, so that the conversion actually
happens.
So what happens, while scheduling instructions, the scheduler will
recognize there are no alpha instruction to pair the rgb ones with
and convert some to alpha. It primarily tries to use the same register,
just reuse the alpha channel.
Why it happens? We are tracking the usage of registers in the block
being scheduled and when we rewrite something we move the users tracked
by the reg_value structures to the new register. The problem is that when
we do this, the current code expects that the code is in the ssa-like
form. Here it is not (because of the loop) and when we convert the
original instruction 2, we move the dependency information about the
temp[2].x to temp[2].w. When we later convert instruction 8, which also
writes temp[2].x, the original dependency info is gone, and when we copy
that to the new reg (temp[5].w), we just set it to NULL and it means we
don't mark it as used effectively, and later wrongly use it again when
we look for a next empty register.
Fix this by not deleting the original dependency info. We can't reuse the
reg now, but it doesn't matter, because the regalloc later can sort it out.
There are no changes in the shader-db.
Fixes: dEQP-GLES2.functional.shaders.indexing.tmp_array.float_dynamic_write_dynamic_loop_read_fragment
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6508
Reviewed-by: Filip Gawin <filip@gawin.net>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18621>
Vinson Lee [Sun, 18 Sep 2022 17:15:31 +0000 (10:15 -0700)]
pan/bi: Fix memory leaks.
Fix defects reported by Coverity Scan.
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable used going out of scope leaks the storage it points to.
leaked_storage: Variable multiple_uses going out of scope leaks the storage it points to.
Fixes:
8fb415fee20 ("pan/bi: Reduce some moves when going out-of-SSA")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18653>
Alyssa Rosenzweig [Sat, 17 Sep 2022 21:14:17 +0000 (17:14 -0400)]
asahi: Identify shared memory layouts
Somehow maps to the tile size. Not sure about the details yet.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Sat, 17 Sep 2022 20:53:16 +0000 (16:53 -0400)]
asahi: Identify pixel stride
Number of bytes in a pixel in the tilebuffer, does not depend on the
tile size.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Sat, 17 Sep 2022 15:22:01 +0000 (11:22 -0400)]
asahi: Overhaul USC control packing
Break up the monolithic SET_SHADER_EXTENDED packet into the separate
underlying commands (some only 2-byte sized and aligned), and add a
builder for USC control streams like we did for PPP updates to make that
change manageable.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Sat, 17 Sep 2022 15:19:52 +0000 (11:19 -0400)]
asahi/genxml: Overflow up to words when packing
So we can pack things that aren't 4-byte sized. Note this doesn't help
with alignment.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Thu, 15 Sep 2022 21:15:44 +0000 (17:15 -0400)]
asahi: Consolidate magic numbers for USC controls
Aka "pipeline" states. It's another command/control stream.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Thu, 15 Sep 2022 02:06:56 +0000 (22:06 -0400)]
asahi: Identify shared memory fields
For compute kernels, this encodes how much workgroup-local memory is
used ("shared memory" or "threadgroup memory" or "local memory"). This
memory is partitioned by the hardware.
For fragment shaders, this... encodes exactly the same thing. There is
no traditional tilebuffer in AGX, instead local memory is interpreted as
an imageblock, where each workgroup is a tile. This is a nifty design.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Sat, 3 Sep 2022 18:03:03 +0000 (14:03 -0400)]
asahi: Simplify IOGPU attachment packing
Give bigger ranges, it's simpler and less broken for layered
framebuffers.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Thu, 15 Sep 2022 22:19:25 +0000 (18:19 -0400)]
asahi: Identify spill buffer histogram
Histogram of sizes of the spill buffer, with logarithmic bucket sizes
(relative to the amount spilled from the perspective of a single thread).
Pretty funny.
Also mark a few unknowns that are nonzero when spilling is used.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Fri, 19 Aug 2022 02:48:12 +0000 (22:48 -0400)]
asahi: Use the internal format internally
Confusingly, after creation rsrc->base.format will contain the external
format due to u_transfer_helper quirks. For our internal use, we need to
look at the internal format, rsrc->layout.format. With the new layout
code, the rsrc->internal_format property is redundant, so we delete
that to reduce confusion.
Fixes dEQP-GLES3.functional.texture.format.sized.2d.depth32f_stencil8_*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Sat, 20 Aug 2022 17:34:30 +0000 (13:34 -0400)]
asahi: Assert that u_transfer_helper is well-behaved
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Thu, 15 Sep 2022 00:08:23 +0000 (20:08 -0400)]
asahi: Decode IOGPU compute header
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Thu, 15 Sep 2022 00:07:54 +0000 (20:07 -0400)]
asahi: Identify IOGPU compute header
Much simpler than the graphics one.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Sun, 11 Sep 2022 16:03:01 +0000 (12:03 -0400)]
asahi: Shuffle IOGPU structs
We need the header to be common between gfx and compute, but everything
else seems to be different. Shuffle so we can decode compute without any
terrible hacks.
I don't know the exact layout and don't care: the layout of the fields
here is all software defined in macOS, even though the *values* are
defined by hardware (or firmware in a few cases).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Tue, 13 Sep 2022 02:34:12 +0000 (22:34 -0400)]
asahi: Decode CDM commands separate from VDM
This gets correct handling of CDM stream link/terminate, which are
encoded in a slightly different way from VDM.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Tue, 13 Sep 2022 02:22:56 +0000 (22:22 -0400)]
asahi: Identify CDM block types
Same enum as PowerVR CDM, annoyingly different from the VDM block types.
Split out the stream link / terminate structs (both observed with Metal
for copious amounts of compute), in preparation for decoding "properly".
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Tue, 6 Sep 2022 01:42:20 +0000 (21:42 -0400)]
asahi: Identify ZLS Control word from PowerVR
We're into the cr.xml file now, which is the blob that gets passed
through the kernel.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Alyssa Rosenzweig [Tue, 6 Sep 2022 01:24:56 +0000 (21:24 -0400)]
asahi: Assert cache line alignment on Z/S buffers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
Erik Faye-Lund [Wed, 10 Aug 2022 12:45:42 +0000 (14:45 +0200)]
u_transfer_helper: rip out fake_rgtc code
This is no longer in use, so let's get rid of it!
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
Erik Faye-Lund [Wed, 10 Aug 2022 12:32:05 +0000 (14:32 +0200)]
freedreno: do not fake rgtc-support
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
Erik Faye-Lund [Wed, 10 Aug 2022 06:59:28 +0000 (08:59 +0200)]
mesa/st: enable latc extensions with fallback
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
Erik Faye-Lund [Tue, 23 Aug 2022 12:48:39 +0000 (14:48 +0200)]
mesa/st: do not fall back to uncompressed for latc
This logic doesn't really do what it pretends to; we don't expose the
RGTC features unless we actually have LATC support. This is about to
change, but for that logic to work, we need to be able to tell if we're
using a fallback-format or not, and we can't do that unless we keep the
format as LATC.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
Erik Faye-Lund [Wed, 10 Aug 2022 06:45:16 +0000 (08:45 +0200)]
mesa/st: implement fallback for latc
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
Erik Faye-Lund [Wed, 10 Aug 2022 11:23:08 +0000 (13:23 +0200)]
mesa/main: add support for latc in _mesa_unpack_rgtc
RGTC and LATC unpacks in the same way, just to different formats. So
let's add support for unpacking that in this helper.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
Erik Faye-Lund [Wed, 10 Aug 2022 06:27:19 +0000 (08:27 +0200)]
mesa: add format-helper for latc
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
Erik Faye-Lund [Wed, 10 Aug 2022 06:24:29 +0000 (08:24 +0200)]
mesa/st: add context-flag for latc
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18564>
Erik Faye-Lund [Thu, 15 Sep 2022 16:05:26 +0000 (18:05 +0200)]
lima: do not align width/height for non-shared resources
Otherwise we end up computing the wrong pitch for miplevels on NPOT
textures.
This fixes a bunch of piglit.
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18618>
Erik Faye-Lund [Thu, 15 Sep 2022 14:14:49 +0000 (16:14 +0200)]
lima: don't store width in resource-level
We only write to it, we never read from it. Just drop it.
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18618>
Dmitry Baryshkov [Fri, 16 Sep 2022 06:33:01 +0000 (09:33 +0300)]
freedreno/registers: update hdmi registers to add more 8x74 regs
Define more HDMI PHY/PLL registers used on msm8x74/apq8084 platforms.
Register names are defined in clock-mdss-8974.c (msm-3.10).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18629>
Kai Wasserbäch [Sat, 17 Sep 2022 09:53:26 +0000 (11:53 +0200)]
chore(docs): rusticl: improve list of build dependencies
v2:
- added more requirements for LLVM (thanks Mike Lothian (@FireBurn)).
v3:
- note the optional cases for rustfmt (thanks @LingMan)
- remove the part about the SPIR-V target for LLVM (thanks Karol Herbst
(@karolherbst))
v4:
- added minimum version requirements (thanks Karol Herbst
(@karolherbst))
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18640>
Erik Faye-Lund [Tue, 13 Sep 2022 13:39:49 +0000 (15:39 +0200)]
docs: update staus of mark GL_ARB_texture_compression_bptc
This is now done for all drivers that supports half-float and sRGB
textures. Update features.txt to reflect this.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18574>
Thomas H.P. Andersen [Wed, 14 Sep 2022 22:18:29 +0000 (00:18 +0200)]
panvk: Implement VK_KHR_descriptor_update_template
Based on original patch by Jason Ekstrand
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14780>
Jason Ekstrand [Sat, 17 Sep 2022 02:46:09 +0000 (21:46 -0500)]
panvk: Fix buffer views
Instead of overwriting the BO map pointer, write into the BO map
pointer. Drp... Also, drop an unnecessary & accessing
panvk_buffer_view::tex.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14780>
Jason Ekstrand [Fri, 28 Jan 2022 19:50:16 +0000 (13:50 -0600)]
vulkan/runtime: Compact descriptor update templates
Get rid of any zero-sized entries so drivers never even have to think
about this case when using templates.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14780>
Thomas H.P. Andersen [Wed, 14 Sep 2022 22:06:33 +0000 (00:06 +0200)]
hasvk: Switch to the common descriptor update template struct
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14780>
Jason Ekstrand [Fri, 28 Jan 2022 19:20:05 +0000 (13:20 -0600)]
anv: Switch to the common descriptor update template struct
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14780>
Jason Ekstrand [Fri, 28 Jan 2022 19:02:56 +0000 (13:02 -0600)]
vulkan/runtime: Add a comon vk_descriptor_update_template
We can't actually make the template-based update common efficiently but
we can save everyone a bit of typing by having a common struct. This is
mostly a direct copy+paste from ANV with a type field added and a couple
comments tweaked.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14780>
Adam Jackson [Fri, 5 Aug 2022 22:01:09 +0000 (18:01 -0400)]
glx: Remove some excess work from the GLX_FBCONFIG_ID fallback
The config matched by visual ID will have the right fbconfig ID set, you
don't need to go looking for it, so long as you look in the list of
fbconfigs as opposed to the list of visuals (which do not have
GLX_FBCONFIG_ID filled in).
It's sort of broken that we have two lists here, when the only real
distinction is that glXChooseVisuals needs to filter out non-window-
capable configs from its view. That's a bigger cleanup for another day.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18473>
Adam Jackson [Fri, 5 Aug 2022 21:52:11 +0000 (17:52 -0400)]
glx/dri: Avoid a weird indirection in driFetchDrawable
The gc already has ->psc set, just use it rather than walking all the
way back to the display private to find it.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18473>
Adam Jackson [Tue, 2 Aug 2022 17:19:44 +0000 (13:19 -0400)]
glx/dri*: Unify glx_context subclassing
The AppleGLX way reads a little nicer than the DRI wrapping way, I
think. First time for everything.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18473>
Chia-I Wu [Wed, 14 Sep 2022 22:35:08 +0000 (15:35 -0700)]
turnip: fix kgsl tu_enumerate_devices return code
VK_ERROR_INCOMPATIBLE_DRIVER is not a valid return code in this
function. Return VK_SUCCESS when /dev/kgsl-3d0 does not exist.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18622>
Ella Stanforth [Wed, 14 Sep 2022 11:06:12 +0000 (11:06 +0000)]
util: fix missing fcntl.h on musl
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18617>
Emma Anholt [Thu, 15 Sep 2022 17:48:49 +0000 (10:48 -0700)]
ci/turnip: Move some 15-second-ish test skips to pre-merge skips.
We run with a longer timeout for the full runs, so let's enable the
coverage there.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18620>
Emma Anholt [Thu, 15 Sep 2022 17:46:35 +0000 (10:46 -0700)]
ci/turnip: Drop a couple of spillall skips.
These were fixed in the CTS in
3cc56764adac ("Shrink the framebuffer in 2
graphicsfuzz tests").
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18620>
Emma Anholt [Thu, 15 Sep 2022 17:39:24 +0000 (10:39 -0700)]
ci/turnip: Allow running spirv_ids_abuse in full VK runs.
We have a long enough timeout (5 minutes) during full runs to definitely
run these. Also, they haven't crashed for quite some time.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18620>
Emma Anholt [Thu, 15 Sep 2022 17:32:03 +0000 (10:32 -0700)]
ci/turnip: Re-enable the compressed cubemap tests.
Our CTS now has the linked bug fixed, and it executes quickly locally.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18620>
Emma Anholt [Thu, 15 Sep 2022 19:02:50 +0000 (12:02 -0700)]
ci/turnip: Bump the full-run a618 runner count to 3.
That's 1/3 of the farm locked up per manual full run someone starts. But,
right now, we've bumped the runtime of a full run up to the point that we
were hitting the 2 hour timeout.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18620>
Emma Anholt [Thu, 15 Sep 2022 17:49:44 +0000 (10:49 -0700)]
ci/turnip: Use all 9 a618 runners at once for VK testing.
There are more boards in the collabora lab now, let's use them. We were
spending just over 10 minutes inside of deqp-runner, so a bit more than
our target for the whole job. Plus, we expect to be running more coverage
once VK_EXT_graphics_pipeline_library runs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18620>
Gert Wollny [Fri, 16 Sep 2022 12:55:58 +0000 (14:55 +0200)]
r600/sfn: lower tg4 to backend in NIR
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
Gert Wollny [Fri, 16 Sep 2022 12:55:20 +0000 (14:55 +0200)]
r600/sfn: Make sure texture lowering is done in the right order
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
Gert Wollny [Thu, 15 Sep 2022 16:25:43 +0000 (18:25 +0200)]
r600/sfn: only use 3 channels on Cayman for trans ops
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
Gert Wollny [Thu, 15 Sep 2022 15:50:45 +0000 (17:50 +0200)]
r600/sfn: Handle shifts on Cayman
Fixes:
00599f6e7161065c51812174ca18427b9867f63f
r600/sfn: Schedule shift instruction on R600 in t-slot
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
Gert Wollny [Wed, 14 Sep 2022 17:55:16 +0000 (19:55 +0200)]
r600/sfn: fix some channel pinning
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
Gert Wollny [Mon, 12 Sep 2022 17:00:53 +0000 (19:00 +0200)]
r600/sfn: Add a free-channel mask when testing whether a register can switch channel
This should avoid making 4 slot ops out of 3-slot ops on Cayman
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
Gert Wollny [Fri, 9 Sep 2022 12:00:48 +0000 (14:00 +0200)]
r600/sfn: VS inputs are effectively SSA
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
Gert Wollny [Fri, 9 Sep 2022 12:54:58 +0000 (14:54 +0200)]
r600/sfn: copy propagate register load chains
NIR sometimes produces load chains like
r0 mov value
r1 mov r0
r2 mov r1
Add copy propagation for these cases
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
Gert Wollny [Fri, 9 Sep 2022 12:00:25 +0000 (14:00 +0200)]
r600/sfn: drop some unused code
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
Gert Wollny [Wed, 7 Sep 2022 06:22:04 +0000 (08:22 +0200)]
r600/sfn: Copy propagate into TEX source
This is possible if all register values are actually from the same
register ID.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
Gert Wollny [Wed, 7 Sep 2022 06:21:13 +0000 (08:21 +0200)]
r600/sfn: Don't assert when setting one value
Instead add a method to validate the vec4 registers
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>
Gert Wollny [Wed, 7 Sep 2022 06:19:59 +0000 (08:19 +0200)]
r600/sfn: Add an easy access to get an instruction as ALU
This is used often and makes sense not to be implemented as
a visitor.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18619>