Mike Blumenkrantz [Wed, 4 Aug 2021 15:44:28 +0000 (11:44 -0400)]
zink: sum available memory heaps instead of assigning
this is supposed to accumulate now
Fixes:
73f6bff07f1 ("zink: fix mem info query to be more permissive")
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12199>
Emma Anholt [Wed, 4 Aug 2021 00:27:38 +0000 (17:27 -0700)]
ci/freedreno: Mark border_color as passing on a5xx.
They're marked as flaky, but they're all passing on my board, and maybe in
CI too. Let's see if CI still sees them as flaky once the expectations
are right.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12192>
Emma Anholt [Wed, 4 Aug 2021 00:01:26 +0000 (17:01 -0700)]
freedreno/a5xx: Don't try to emit FS images in binning command streams.
We don't have a compiled FS in that case, so the shader deref fails. We
don't need the state, anyway.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12192>
Emma Anholt [Tue, 3 Aug 2021 19:45:57 +0000 (12:45 -0700)]
freedreno/a5xx: Disable TF when pausing or transitioning to non-TF.
This is not as clean as on a6xx where we just re-emit the SO state, but it
cleans up our dEQP results a ton.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12192>
Emma Anholt [Tue, 3 Aug 2021 21:20:19 +0000 (14:20 -0700)]
ci/freedreno: Clear out TF API errors xfails.
These tests are flaky and sometimes segfault in CI, but usually pass. We
hadn't noticed their change due to the test being marked as flaky.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12192>
Timur Kristóf [Thu, 15 Jul 2021 09:54:33 +0000 (11:54 +0200)]
ac: Remove deprecated use_late_alloc field as nobody uses it anymore.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11905>
Timur Kristóf [Thu, 15 Jul 2021 09:48:25 +0000 (11:48 +0200)]
radv: Use ac_compute_late_alloc in radv_pipeline.
This aligns RADV with RadeonSI in how it handles late alloc,
making it easier for us to deal with deadlocks and such.
Also move setting the RSRC3 registers for VS, GS and NGG
into radv_pipeline.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11905>
Timur Kristóf [Thu, 15 Jul 2021 09:51:32 +0000 (11:51 +0200)]
radv: Don't toggle PC oversubscription for NGG culling.
We are going to add this directly to the pipeline.
If a pipeline has such a shader, NGG culling is turned on
most of the time, so it's not useful to toggle this setting.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11905>
Timur Kristóf [Mon, 2 Aug 2021 14:48:41 +0000 (16:48 +0200)]
aco: Use Navi 10 empty NGG output workaround on NGG culling shaders.
Navi 10 can hang when an NGG workgroup has no output,
so we work around that by always exporting a single zero-area
triangle with a single vertex that has all-NaN coordinates.
Thus far, we only employed this for NGG GS, because on all
other stages, the output can't be empty.
However, with NGG culling, the output can be empty, so let's
apply the same workaround there too.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12169>
Rhys Perry [Tue, 3 Aug 2021 18:04:48 +0000 (19:04 +0100)]
aco: use image_dim and image_array intrinsic indices
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12190>
Rhys Perry [Fri, 30 Jul 2021 12:25:26 +0000 (13:25 +0100)]
radv: set image_dim and image_array intrinsic indices
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12190>
Dave Airlie [Mon, 2 Aug 2021 07:01:56 +0000 (17:01 +1000)]
ci: bump to latest virglrenderer for anisotropic support
Update ci results
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11944>
Dave Airlie [Sun, 18 Jul 2021 20:36:01 +0000 (06:36 +1000)]
virgl: add support for anisotropic texture filtering
This is the guest side for adding correct anisotropic filtering support
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11944>
Dave Airlie [Sun, 18 Jul 2021 19:58:48 +0000 (05:58 +1000)]
virgl: disable anisotropic filtering.
virgl doesn't yet support anisotropic filtering so don't advertise it.
Fixes:
a8987b88ff1d ("virgl: add driver for virtio-gpu 3D (v2)")
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11944>
Sergii Melikhov [Mon, 2 Aug 2021 12:15:34 +0000 (15:15 +0300)]
iris: Fix Null pointer dereferences
Fix the error from Coverity report: CID 1489765
Signed-off-by: Sergii Melikhov <sergii.v.melikhov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12179>
Charmaine Lee [Fri, 30 Jul 2021 23:53:53 +0000 (16:53 -0700)]
aux/draw: Check for preferred IR to take nir-to-tgsi path in draw module
When a vertex program is translated to nir, it uses
nir_to_tgsi_compile_options for drivers with only nir-to-tgsi based
NIR support. But this compile option might not be the same as the NIR
compile option from llvmpipe, hence when the nir shader is bound
to the draw module, it hits an assertion in do_alu_action() when
encounters nir_op_fdot3.
With this patch, draw will take the nir-to-tgsi path if preferred IR
from the driver is TGSI.
Fixes assert running Maya on SVGA device.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12176>
Jason Ekstrand [Tue, 3 Aug 2021 15:16:58 +0000 (10:16 -0500)]
nir: Removing uses of SSA defs destroys SSA liveness
The liveness information will be a superset of real liveness so it's
unlikely something will explode if it tries to use it. However, it is
out-of-date and should be re-run if someone really wants it.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12186>
Ian Romanick [Tue, 3 Aug 2021 00:56:40 +0000 (17:56 -0700)]
isl: Use CLAMP macro instead of MIN of MAX
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12177>
Ian Romanick [Mon, 2 Aug 2021 23:43:52 +0000 (16:43 -0700)]
util: Add and use functions to calculate min and max int for a size
Many places need to know the maximum or minimum possible value for a
given size integer... so everyone just open-codes their favorite
version. There is some potential to hit either undefined or
implementation-defined behavior, so having one version that Just Works
seems beneficial.
v2: Fix copy-and-pasted bug (INT64_MAX instead of INT64_MIN) in
u_intmin. Noticed by CI. Lol. Rename functions
`s/u_(uint|int)(min|max)/u_\1N_\2/g`. Suggested by Jason. Add some
unit tests that would have caught the copy-and-paste bug before wasting
CI time. Change the implementation of u_intN_min to use the same
pattern as stdint.h. This avoids the integer division. Noticed by
Jason.
v3: Add changes to convert_clear_color
(src/gallium/drivers/iris/iris_clear.c). Suggested by Nanley.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12177>
Emma Anholt [Wed, 28 Jul 2021 17:00:12 +0000 (10:00 -0700)]
ci: Update piglit to
4545a28cd8fea03fbab0e5f90bfbd812c32f3be1
Brings in duplicate subtest fixes, gpu_shader4 tests, and more. This
shuffles the radeonsi fractional test run, so we get to catch up with more
failing subtests.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12110>
Emma Anholt [Fri, 23 Jul 2021 18:14:16 +0000 (11:14 -0700)]
ci/zink: Use deqp-runner suite support to reduce the CI job count.
The tests were passing so quickly, and the 1/4th GLES3 subset changed on
the transition to multiple testsuites, so I promoted it to a full run.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12110>
Emma Anholt [Thu, 22 Jul 2021 19:56:23 +0000 (12:56 -0700)]
ci/virgl: Use deqp-runner suite support to reduce CI job count.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12110>
Emma Anholt [Thu, 22 Jul 2021 19:51:41 +0000 (12:51 -0700)]
ci: Save dEQP results on all tests.
Everyone can get artifacts now. Let's make those artifacts useful.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12110>
Emma Anholt [Thu, 22 Jul 2021 17:40:36 +0000 (10:40 -0700)]
ci/i915g: Merge the two dEQP runs together.
Fewer buttons for me to have to click for manual MR testing.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12110>
Emma Anholt [Wed, 21 Jul 2021 23:40:02 +0000 (16:40 -0700)]
ci/llvmpipe: Use the deqp-runner suite support to consolidate jobs.
5 jobs become 2, plus we add KHR-GLES3 and 31 to the test set since
it's cheap.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12110>
Emma Anholt [Wed, 21 Jul 2021 20:12:29 +0000 (13:12 -0700)]
ci: Uprev deqp-runner and use "suite" support to merge softpipe runs.
The deqp-runner "suite" support lets us specify all the deqp variants at
once and shard them across gitlab jobs, so we reduce docker overhead and
get fewer jobs to review the output of.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12110>
Emma Anholt [Wed, 28 Jul 2021 19:08:48 +0000 (12:08 -0700)]
ci/i915: Update deqp expectations for another test passing.
!11411 made this one start passing thanks to reducing instruction counts.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12110>
Lionel Landwerlin [Tue, 3 Aug 2021 12:48:03 +0000 (15:48 +0300)]
intel/disasm: fix missing oword index decoding
Also switch to array of strings to show high/low dwords.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
daba2894ffc300 ("intel/disasm: decode/describe more send messages")
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12183>
Pierre Moreau [Sun, 25 Apr 2021 19:59:27 +0000 (21:59 +0200)]
clover/nir: Set constant buffer pointer size to host
The `argument::size` is supposed to represent the size of a pointer on
the host and not on the device (for which argument::target_size`
exists).
v3: Use `sizeof(buf)` instead of `marg.size`. (Francisco Jerez)
Fixes:
7c6f1d3bf99 ("clover/nir: extract constant buffer into its own section")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10256>
Pierre Moreau [Fri, 14 Aug 2020 07:51:30 +0000 (09:51 +0200)]
clover/api: Interleave details in dispatch table
By adding comments regarding which version or extension introduced the
following dispatched functions, it makes it easier to glance at the
table and see which functions are missing for a particular version, but
more importantly makes it easier to compare against cl_icd.h and see if
anything is missing.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10256>
Pierre Moreau [Tue, 13 Apr 2021 20:14:03 +0000 (22:14 +0200)]
clover/spirv: Properly size 3-component vector args
This resolves clover returning `CL_INVALID_ARG_SIZE` whenever the OpenCL
CTS called `clSetKernelArg()` for 3-component vectors.
Fixes:
21473865050 ("clover/spirv: Add functions for parsing arguments, linking programs, etc.")
v2: Remove “api/clsetkernelarg/set kernel argument for cl_int3” from the
expected fails for llvmpipe
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10256>
Pierre Moreau [Thu, 21 May 2020 16:48:22 +0000 (18:48 +0200)]
clover/spirv: Increase max amount of function args
OpenCL only has an upper limit on the size taken by all arguments to a
kernel (implementation-defined, but at least 1024 bytes), and not on the
count of those arguments.
This fixes OpenCL-CTS’s api.min_max_parameter_size.
v2: Use `numeric_limits<>::max()` instead of hardcoded value.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10256>
Karol Herbst [Sat, 15 Aug 2020 23:51:49 +0000 (01:51 +0200)]
clover: Local memory needs to be aligned.
Fixes a couple of OpenCL CTS tests.
v3:
* Add a comment in module.hpp explaining that target_align means
something different for arguments of type local (Francisco Jerez)
* Squash in the fix for the LLVM backend.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10256>
Pierre Moreau [Sat, 16 Jan 2021 13:55:36 +0000 (14:55 +0100)]
clover: Do not advertise OpenCL x.y when unsupported
Instead of hardcoding a fixed version for all devices, compute the
highest version supported by a device based on the different constraints
mandated by each new version.
For example, besides new functionalities, OpenCL 1.1 also increases the
minimum limits regarding the amount of local memory and the amount of
bytes taken by all arguments to a kernel. Some hardware (such as all
GPUs from NVIDIA’s Tesla micro-architecture) can support the additional
features but do not pass those new minimums.
v3:
* Change `get_highest_supported_version()` to return the version instead
of modifying the version components passed as arguments. (Francisco
Jerez)
* Tweak the line wrapping for `has_extension()`. (Francisco Jerez)
v2:
* Invert the ordering of OpenCL and OpenCL C version, to restrict OpenCL
version based on supported OpenCL C version.
* Rename `get_supported_version()` to `get_highest_supported_version()`;
* Use device methods to query parameters instead of manually executing
them;
* Clarify that the limit checking is only for non-custom devices
supporting the full profile.
* Check for mandatory extensions as well;
* Validate CL_DEVICE_MEM_BASE_ADDR_ALIGN;
* Fix the OpenCL>=1.1 minimum limit for CL_DEVICE_LOCAL_MEM_SIZE, from
32 * 1000 to 32 * 1024;
* Restrict to OpenCL 1.0 if OpenCL C 1.1 is not supported.
* Compute the highest supported version based on constraints (ignoring
2.x versions).
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10256>
Erik Faye-Lund [Tue, 3 Aug 2021 15:08:44 +0000 (17:08 +0200)]
d3d12: split up root parameter update and set
SRV descriptors can require state-transitions before it's legal to set
them on the command-list. We used to just set them right away, and get
away with is, because the validator didn't verify this because we used
to flag the parameters as volatile.
Now that we don't, we trigger validation errors when setting a root
parameter that needs a transition first.
So let's split up the logic a bit, so we can prepare the tables, then do
the transision, and finally set the tables. We do this for all tables
instead of just the SRVs, just because it makes the logic a bit easier to
follow. We leave root constants alone, because they will never require
this, and doing them late would just compilcate things.
Fixes:
12082905582 ("d3d12: Sets all SRV descriptors as data-static")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12187>
Corentin Noël [Thu, 3 Jun 2021 14:32:54 +0000 (16:32 +0200)]
ci: Use crosvm to run dEQP tests for virgl
Allows to use virtio-gpu to actually test the virgl driver.
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11320>
Corentin Noël [Wed, 16 Jun 2021 14:04:28 +0000 (16:04 +0200)]
ci: Increase crosvm version
Also require newer dependencies.
This makes it easier to debug possible crosvm issues as a big refactor occured since the
previous commit included in the CI.
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11320>
Corentin Noël [Fri, 9 Jul 2021 09:40:46 +0000 (11:40 +0200)]
ci: Increase the default Rust toolchain version
We need a newer Rust toolchain to be able to build the latest crosvm.
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11320>
Corentin Noël [Thu, 29 Jul 2021 09:16:21 +0000 (11:16 +0200)]
ci: Disable llvmpipe optimizations when running virgl CI
We are only using the result once so we spend more time optimizing it than
actually using it.
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11320>
Juan A. Suarez Romero [Tue, 3 Aug 2021 11:05:23 +0000 (13:05 +0200)]
gallium/hud: initialize query
Most of the drivers don't set up the maximum value in the query info. So
when later hud_pane_set_max_value() is invoked, we are using a rather
"random" number.
Turns out that in some 32bit cases, this random number is big enough
that `leftmost_digit` is 0 because DIV_ROUND_UP() overflows, aborting
with an assertion.
Fixes:
c91cf7d7d2c ("gallium: implement a heads-up display module")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12181>
Samuel Pitoiset [Mon, 2 Aug 2021 14:43:15 +0000 (16:43 +0200)]
radv: fix missing cache flushes when clearing HTILE levels on GFX10+
The driver should accumulate the cache flush bits because if it uses
CP DMA for clearing the last level, it won't flush.
Found by inspection.
Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12170>
Samuel Pitoiset [Mon, 2 Aug 2021 12:27:11 +0000 (14:27 +0200)]
radv: fix selecting the first active CU when profiling with SQTT
Fixes:
d26bcc0f5cb ("radv: always select the first active CU when profiling with SQTT")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12167>
Erik Faye-Lund [Mon, 2 Aug 2021 12:36:47 +0000 (14:36 +0200)]
gallivm: remove pointless no_filter_hacks flag
This flag now does the same thing as the no_quad_lod flag, so let's get
rid of it to reduce confusion.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12125>
Emma Anholt [Mon, 19 Jul 2021 23:49:02 +0000 (16:49 -0700)]
ci: Stop disabling filter hacks for llvmpipe.
Now that we've disabled brilinear and have per-pixel cube derivatives, we
can use the same rendering paths that end users will see.
In a few cases, we switch to the no_quad_lod option instead, because
otherwise we get a piglit failure.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12125>
Erik Faye-Lund [Mon, 2 Aug 2021 12:34:02 +0000 (14:34 +0200)]
gallivm: make rho-approximation opt-in instead of opt-out
The RHO approximation code has issues passing the OpenGL ES 3.0 CTS, so
let's make correctness the default instead.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12125>
Timothy Arceri [Mon, 26 Jul 2021 13:25:58 +0000 (23:25 +1000)]
nir: add heuristic for instructions in loops with GCM
Moving instructions out of large loops tends to cause excessive
spilling. This appears to be a good limit.
In future it might make sense to make this a NIR options so
other drivers can set their own limits.
Tiger Lake
total instructions in shared programs:
20930180 ->
20926952 (-0.02%)
instructions in affected programs: 280768 -> 277540 (-1.15%)
helped: 734
HURT: 192
helped stats (abs) min: 1 max: 61 x̄: 5.16 x̃: 4
helped stats (rel) min: 0.04% max: 10.64% x̄: 3.23% x̃: 3.14%
HURT stats (abs) min: 1 max: 52 x̄: 2.90 x̃: 1
HURT stats (rel) min: 0.03% max: 9.76% x̄: 1.13% x̃: 0.61%
95% mean confidence interval for instructions value: -3.89 -3.08
95% mean confidence interval for instructions %-change: -2.49% -2.16%
Instructions are helped.
total cycles in shared programs:
841825217 ->
838817552 (-0.36%)
cycles in affected programs:
122088078 ->
119080413 (-2.46%)
helped: 941
HURT: 100
helped stats (abs) min: 1 max: 160080 x̄: 3274.31 x̃: 2660
helped stats (rel) min: <.01% max: 41.64% x̄: 5.50% x̃: 4.80%
HURT stats (abs) min: 1 max: 41856 x̄: 734.62 x̃: 26
HURT stats (rel) min: <.01% max: 7.29% x̄: 0.44% x̃: 0.27%
95% mean confidence interval for cycles value: -3236.56 -2541.85
95% mean confidence interval for cycles %-change: -5.26% -4.60%
Cycles are helped.
total sends in shared programs: 977905 -> 977782 (-0.01%)
sends in affected programs: 2279 -> 2156 (-5.40%)
helped: 119
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 1.03 x̃: 1
helped stats (rel) min: 0.60% max: 14.29% x̄: 6.93% x̃: 6.67%
95% mean confidence interval for sends value: -1.09 -0.98
95% mean confidence interval for sends %-change: -7.42% -6.45%
Sends are helped.
LOST: 2
GAINED: 0
Ice Lake
total instructions in shared programs:
19865361 ->
19861747 (-0.02%)
instructions in affected programs: 185789 -> 182175 (-1.95%)
helped: 593
HURT: 47
helped stats (abs) min: 1 max: 27 x̄: 6.17 x̃: 4
helped stats (rel) min: 0.19% max: 8.65% x̄: 4.53% x̃: 4.60%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.03% max: 0.23% x̄: 0.11% x̃: 0.04%
95% mean confidence interval for instructions value: -5.93 -5.37
95% mean confidence interval for instructions %-change: -4.32% -4.06%
Instructions are helped.
total loops in shared programs: 6120 -> 6117 (-0.05%)
loops in affected programs: 6 -> 3 (-50.00%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
total cycles in shared programs:
961777176 ->
959404350 (-0.25%)
cycles in affected programs:
172224180 ->
169851354 (-1.38%)
helped: 936
HURT: 80
helped stats (abs) min: 1 max: 9566 x̄: 2621.08 x̃: 2550
helped stats (rel) min: <.01% max: 41.77% x̄: 4.22% x̃: 3.84%
HURT stats (abs) min: 1 max: 59146 x̄: 1006.34 x̃: 24
HURT stats (rel) min: <.01% max: 3.78% x̄: 0.44% x̃: 0.25%
95% mean confidence interval for cycles value: -2513.72 -2157.20
95% mean confidence interval for cycles %-change: -4.13% -3.57%
Cycles are helped.
total sends in shared programs: 1019995 -> 1019872 (-0.01%)
sends in affected programs: 2283 -> 2160 (-5.39%)
helped: 119
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 1.03 x̃: 1
helped stats (rel) min: 0.60% max: 14.29% x̄: 6.91% x̃: 6.67%
95% mean confidence interval for sends value: -1.09 -0.98
95% mean confidence interval for sends %-change: -7.39% -6.42%
Sends are helped.
LOST: 4
GAINED: 0
Skylake
total instructions in shared programs:
17994337 ->
17993846 (<.01%)
instructions in affected programs: 146294 -> 145803 (-0.34%)
helped: 190
HURT: 47
helped stats (abs) min: 1 max: 12 x̄: 2.83 x̃: 3
helped stats (rel) min: 0.14% max: 4.29% x̄: 1.08% x̃: 0.90%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.03% max: 0.22% x̄: 0.11% x̃: 0.04%
95% mean confidence interval for instructions value: -2.30 -1.84
95% mean confidence interval for instructions %-change: -0.95% -0.74%
Instructions are helped.
total loops in shared programs: 6029 -> 6023 (-0.10%)
loops in affected programs: 12 -> 6 (-50.00%)
helped: 6
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for loops value: -1.00 -1.00
95% mean confidence interval for loops %-change: -50.00% -50.00%
Loops are helped.
total cycles in shared programs:
939062940 ->
938023548 (-0.11%)
cycles in affected programs:
169671482 ->
168632090 (-0.61%)
helped: 980
HURT: 134
helped stats (abs) min: 1 max: 25000 x̄: 1075.57 x̃: 1052
helped stats (rel) min: <.01% max: 42.75% x̄: 2.51% x̃: 1.32%
HURT stats (abs) min: 1 max: 837 x̄: 109.45 x̃: 20
HURT stats (rel) min: <.01% max: 5.71% x̄: 0.73% x̃: 0.21%
95% mean confidence interval for cycles value: -1005.89 -860.17
95% mean confidence interval for cycles %-change: -2.39% -1.84%
Cycles are helped.
total sends in shared programs: 1026848 -> 1026724 (-0.01%)
sends in affected programs: 2302 -> 2178 (-5.39%)
helped: 120
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 1.03 x̃: 1
helped stats (rel) min: 0.60% max: 14.29% x̄: 6.91% x̃: 6.67%
95% mean confidence interval for sends value: -1.09 -0.98
95% mean confidence interval for sends %-change: -7.40% -6.43%
Sends are helped.
LOST: 1
GAINED: 1
Broadwell
total instructions in shared programs:
17605621 ->
17605154 (<.01%)
instructions in affected programs: 145691 -> 145224 (-0.32%)
helped: 184
HURT: 48
helped stats (abs) min: 1 max: 12 x̄: 2.83 x̃: 3
helped stats (rel) min: 0.13% max: 4.29% x̄: 1.09% x̃: 0.93%
HURT stats (abs) min: 1 max: 7 x̄: 1.12 x̃: 1
HURT stats (rel) min: 0.03% max: 0.48% x̄: 0.12% x̃: 0.04%
95% mean confidence interval for instructions value: -2.26 -1.77
95% mean confidence interval for instructions %-change: -0.95% -0.73%
Instructions are helped.
total loops in shared programs: 5968 -> 5963 (-0.08%)
loops in affected programs: 10 -> 5 (-50.00%)
helped: 5
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for loops value: -1.00 -1.00
95% mean confidence interval for loops %-change: -50.00% -50.00%
Loops are helped.
total cycles in shared programs:
1000679489 ->
998592756 (-0.21%)
cycles in affected programs:
173421234 ->
171334501 (-1.20%)
helped: 993
HURT: 153
helped stats (abs) min: 1 max: 766608 x̄: 2118.49 x̃: 1080
helped stats (rel) min: <.01% max: 54.61% x̄: 2.61% x̃: 1.73%
HURT stats (abs) min: 1 max: 2200 x̄: 110.61 x̃: 11
HURT stats (rel) min: <.01% max: 5.68% x̄: 0.63% x̃: 0.06%
95% mean confidence interval for cycles value: -3191.23 -450.54
95% mean confidence interval for cycles %-change: -2.47% -1.89%
Cycles are helped.
total sends in shared programs: 996341 -> 996222 (-0.01%)
sends in affected programs: 2151 -> 2032 (-5.53%)
helped: 115
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 1.03 x̃: 1
helped stats (rel) min: 0.60% max: 14.29% x̄: 7.07% x̃: 6.67%
95% mean confidence interval for sends value: -1.09 -0.98
95% mean confidence interval for sends %-change: -7.55% -6.58%
Sends are helped.
Haswell
total instructions in shared programs:
16038375 ->
16038121 (<.01%)
instructions in affected programs: 216797 -> 216543 (-0.12%)
helped: 185
HURT: 217
helped stats (abs) min: 1 max: 12 x̄: 2.84 x̃: 3
helped stats (rel) min: 0.13% max: 4.23% x̄: 1.30% x̃: 1.20%
HURT stats (abs) min: 1 max: 6 x̄: 1.25 x̃: 1
HURT stats (rel) min: 0.03% max: 5.66% x̄: 0.61% x̃: 0.40%
95% mean confidence interval for instructions value: -0.85 -0.41
95% mean confidence interval for instructions %-change: -0.40% -0.14%
Instructions are helped.
total loops in shared programs: 5947 -> 5942 (-0.08%)
loops in affected programs: 10 -> 5 (-50.00%)
helped: 5
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for loops value: -1.00 -1.00
95% mean confidence interval for loops %-change: -50.00% -50.00%
Loops are helped.
total cycles in shared programs:
967655093 ->
965746713 (-0.20%)
cycles in affected programs:
197288924 ->
195380544 (-0.97%)
helped: 950
HURT: 195
helped stats (abs) min: 1 max: 782820 x̄: 2274.79 x̃: 1260
helped stats (rel) min: <.01% max: 54.26% x̄: 3.02% x̃: 1.71%
HURT stats (abs) min: 1 max: 15790 x̄: 1295.73 x̃: 21
HURT stats (rel) min: <.01% max: 119.85% x̄: 7.76% x̃: 0.11%
95% mean confidence interval for cycles value: -3014.22 -319.19
95% mean confidence interval for cycles %-change: -1.83% -0.55%
Cycles are helped.
total sends in shared programs: 934894 -> 934765 (-0.01%)
sends in affected programs: 2192 -> 2063 (-5.89%)
helped: 115
HURT: 2
helped stats (abs) min: 1 max: 4 x̄: 1.14 x̃: 1
helped stats (rel) min: 0.60% max: 28.57% x̄: 7.68% x̃: 6.67%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 16.67% max: 16.67% x̄: 16.67% x̃: 16.67%
95% mean confidence interval for sends value: -1.23 -0.98
95% mean confidence interval for sends %-change: -8.28% -6.24%
Sends are helped.
LOST: 1
GAINED: 18
Ivy Bridge
total instructions in shared programs:
15269357 ->
15269398 (<.01%)
instructions in affected programs: 190484 -> 190525 (0.02%)
helped: 77
HURT: 206
helped stats (abs) min: 1 max: 6 x̄: 2.47 x̃: 3
helped stats (rel) min: 0.14% max: 5.31% x̄: 1.46% x̃: 1.65%
HURT stats (abs) min: 1 max: 3 x̄: 1.12 x̃: 1
HURT stats (rel) min: 0.03% max: 2.38% x̄: 0.42% x̃: 0.40%
95% mean confidence interval for instructions value: -0.06 0.35
95% mean confidence interval for instructions %-change: -0.21% 0.03%
Inconclusive result (value mean confidence interval includes 0).
total loops in shared programs: 4001 -> 3996 (-0.12%)
loops in affected programs: 10 -> 5 (-50.00%)
helped: 5
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for loops value: -1.00 -1.00
95% mean confidence interval for loops %-change: -50.00% -50.00%
Loops are helped.
total cycles in shared programs:
562045564 ->
561063543 (-0.17%)
cycles in affected programs:
200924872 ->
199942851 (-0.49%)
helped: 748
HURT: 160
helped stats (abs) min: 2 max: 14926 x̄: 1692.94 x̃: 1620
helped stats (rel) min: <.01% max: 53.29% x̄: 3.17% x̃: 1.87%
HURT stats (abs) min: 2 max: 15726 x̄: 1776.86 x̃: 36
HURT stats (rel) min: <.01% max: 114.43% x̄: 10.66% x̃: 0.21%
95% mean confidence interval for cycles value: -1237.33 -925.71
95% mean confidence interval for cycles %-change: -1.54% 0.08%
Inconclusive result (%-change mean confidence interval includes 0).
total sends in shared programs: 893348 -> 893330 (<.01%)
sends in affected programs: 187 -> 169 (-9.63%)
helped: 14
HURT: 0
helped stats (abs) min: 1 max: 2 x̄: 1.29 x̃: 1
helped stats (rel) min: 4.08% max: 22.22% x̄: 11.70% x̃: 10.10%
95% mean confidence interval for sends value: -1.56 -1.02
95% mean confidence interval for sends %-change: -14.92% -8.48%
Sends are helped.
LOST: 1
GAINED: 19
Sandy Bridge
total instructions in shared programs:
11785227 ->
11785774 (<.01%)
instructions in affected programs: 78403 -> 78950 (0.70%)
helped: 65
HURT: 505
helped stats (abs) min: 1 max: 4 x̄: 2.22 x̃: 3
helped stats (rel) min: 0.14% max: 4.17% x̄: 1.19% x̃: 1.38%
HURT stats (abs) min: 1 max: 5 x̄: 1.37 x̃: 1
HURT stats (rel) min: 0.24% max: 3.33% x̄: 1.57% x̃: 1.72%
95% mean confidence interval for instructions value: 0.85 1.07
95% mean confidence interval for instructions %-change: 1.16% 1.36%
Instructions are HURT.
total loops in shared programs: 2441 -> 2437 (-0.16%)
loops in affected programs: 8 -> 4 (-50.00%)
helped: 4
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for loops value: -1.00 -1.00
95% mean confidence interval for loops %-change: -50.00% -50.00%
Loops are helped.
total cycles in shared programs:
497178796 ->
496669298 (-0.10%)
cycles in affected programs:
51483322 ->
50973824 (-0.99%)
helped: 476
HURT: 137
helped stats (abs) min: 2 max: 7502 x̄: 1079.36 x̃: 1260
helped stats (rel) min: <.01% max: 42.50% x̄: 2.31% x̃: 0.86%
HURT stats (abs) min: 2 max: 754 x̄: 31.23 x̃: 18
HURT stats (rel) min: <.01% max: 3.01% x̄: 0.09% x̃: 0.02%
95% mean confidence interval for cycles value: -901.99 -760.32
95% mean confidence interval for cycles %-change: -2.20% -1.36%
Cycles are helped.
total sends in shared programs: 642919 -> 642915 (<.01%)
sends in affected programs: 32 -> 28 (-12.50%)
helped: 4
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 11.11% max: 14.29% x̄: 12.70% x̃: 12.70%
95% mean confidence interval for sends value: -1.00 -1.00
95% mean confidence interval for sends %-change: -15.61% -9.78%
Sends are helped.
Iron Lake
total instructions in shared programs: 8180061 -> 8180248 (<.01%)
instructions in affected programs: 65004 -> 65191 (0.29%)
helped: 59
HURT: 253
helped stats (abs) min: 1 max: 4 x̄: 2.24 x̃: 3
helped stats (rel) min: 0.16% max: 2.23% x̄: 1.04% x̃: 1.29%
HURT stats (abs) min: 1 max: 5 x̄: 1.26 x̃: 1
HURT stats (rel) min: 0.21% max: 3.85% x̄: 0.93% x̃: 0.60%
95% mean confidence interval for instructions value: 0.43 0.77
95% mean confidence interval for instructions %-change: 0.45% 0.68%
Instructions are HURT.
total loops in shared programs: 863 -> 861 (-0.23%)
loops in affected programs: 4 -> 2 (-50.00%)
helped: 2
HURT: 0
total cycles in shared programs:
239357490 ->
238907668 (-0.19%)
cycles in affected programs:
17314006 ->
16864184 (-2.60%)
helped: 176
HURT: 34
helped stats (abs) min: 4 max: 13400 x̄: 2558.05 x̃: 2920
helped stats (rel) min: 0.01% max: 35.58% x̄: 3.76% x̃: 2.69%
HURT stats (abs) min: 2 max: 14 x̄: 11.59 x̃: 14
HURT stats (rel) min: <.01% max: 0.06% x̄: 0.03% x̃: 0.03%
95% mean confidence interval for cycles value: -2440.68 -1843.34
95% mean confidence interval for cycles %-change: -3.78% -2.51%
Cycles are helped.
GM45
total instructions in shared programs: 4985293 -> 4985401 (<.01%)
instructions in affected programs: 58807 -> 58915 (0.18%)
helped: 57
HURT: 202
helped stats (abs) min: 1 max: 4 x̄: 2.26 x̃: 3
helped stats (rel) min: 0.15% max: 2.23% x̄: 1.06% x̃: 1.29%
HURT stats (abs) min: 1 max: 5 x̄: 1.17 x̃: 1
HURT stats (rel) min: 0.21% max: 3.85% x̄: 0.76% x̃: 0.48%
95% mean confidence interval for instructions value: 0.22 0.61
95% mean confidence interval for instructions %-change: 0.24% 0.48%
Instructions are HURT.
total loops in shared programs: 639 -> 638 (-0.16%)
loops in affected programs: 2 -> 1 (-50.00%)
helped: 1
HURT: 0
total cycles in shared programs:
153794236 ->
153546274 (-0.16%)
cycles in affected programs: 9947778 -> 9699816 (-2.49%)
helped: 110
HURT: 31
helped stats (abs) min: 4 max: 13400 x̄: 2257.51 x̃: 1796
helped stats (rel) min: 0.01% max: 35.58% x̄: 4.33% x̃: 2.45%
HURT stats (abs) min: 2 max: 14 x̄: 11.74 x̃: 14
HURT stats (rel) min: <.01% max: 0.06% x̄: 0.03% x̃: 0.03%
95% mean confidence interval for cycles value: -2113.77 -1403.42
95% mean confidence interval for cycles %-change: -4.27% -2.47%
Cycles are helped.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2899
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12064>
Timothy Arceri [Thu, 29 Jul 2021 05:43:26 +0000 (15:43 +1000)]
nir: move nir_block_ends_in_break() to nir.h
Will be used in a following commit.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12064>
Timothy Arceri [Thu, 29 Jul 2021 09:34:26 +0000 (19:34 +1000)]
nir: add indirect loop unrolling to compiler options
This is where it should be rather than having to pass it into the
optimisation pass every time.
It also allows us to call the loop analysis pass without having to
duplicate these options which we will do later in this series.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12064>
Timothy Arceri [Thu, 29 Jul 2021 02:14:16 +0000 (12:14 +1000)]
intel/compiler: make sure swizzle is applied to if condition
This fixes a hang in the following piglit test when GCM moves a
UBO load outside of the loop.
tests/shaders/ssa/fs-if-def-else-break.shader_test
The end NIR ends up looking like this:
vec2 32 ssa_3 = intrinsic load_ubo (ssa_2, ssa_0) (0,
1073741824, 0, 0, 8)
vec1 32 ssa_4 = mov ssa_3.x
vec1 32 ssa_5 = inot ssa_3.y
/* succs: block_1 */
loop {
...
if ssa_5 { }
}
Fixes:
1edf67fc3f6b ("intel/fs: Generate if instructions with inverted conditions")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12064>
Juan A. Suarez Romero [Tue, 27 Apr 2021 16:11:18 +0000 (18:11 +0200)]
v3d/simulator: implement performance counters
Add support for performance counters when using the simulator.
v2 (Iago):
- Remove brackets from single-line conditionals
- Rename channel to channels
- Ensure perfmon start/stop function is implemented in all versions
- Use an array for perfmons instead of hash table
- Implement performance counters in CSD
v3 (Iago):
- Rename PERFMON_CHUNKS to PERFMONS_ALLOC_SIZE.
- Merge increasing lastid and ensuring space in a single function.
v4 (Iago):
- Assert perfid <= perfmons_size.
v7 (Iago):
- Do not stop perfmon on each submission
v8 (Iago):
- Add comment about stopping the perfmon when retrieving values.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10666>
Juan A. Suarez Romero [Thu, 22 Apr 2021 09:07:22 +0000 (11:07 +0200)]
v3d: implement performance counter queries
These queries are used to retrieve the different hardware counters
values, useful to detect performance issues.
v2 (Iago):
- Fix copyright
- Assert hwperfmon exists
- Print message on error
- Rename hwperfmon structure to make it clear
v4 (Juan):
- Save last_job_fence when perfmon is stopped
v5 (Juan):
- No need to ask for counter values if no job was submitted
v6 (Juan):
- Ensure to flush all jobs before capturing last job fence
v7 (Iago)
- No braces for single-line body conditionals
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10666>
Juan A. Suarez Romero [Thu, 22 Apr 2021 08:10:25 +0000 (10:10 +0200)]
v3d: add fence wait function
Waits for a V3D fence to be signaled.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10666>
Juan A. Suarez Romero [Wed, 21 Apr 2021 12:22:45 +0000 (14:22 +0200)]
v3d: move queries to pipe queries
All the current queries are pipe-related queries; move them to a
different file to add later performance counter queries.
v3 (Iago):
- Fix copyright.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10666>
Juan A. Suarez Romero [Wed, 21 Apr 2021 10:59:21 +0000 (12:59 +0200)]
v3d: attach performance monitor to jobs
When a performance monitor is enabled in the context, all the jobs
submitted to the kernel will have attached this monitor ID, so the
kernel will measuring the performance counters selected in the monitor
when these jobs are executed by the GPU (accumulating the results).
v2 (Iago):
- Update comment
- Assert fence is not NULL
- Assert has_perfmon when using perfmon
- Rewrite conditional
- Implement performance counters in CSD
v4 (Juan):
- Track previous perfmon and sync BCL if required (Juan).
- Track if a job with perfmon was submitted (Juan)
v7 (Iago)
- No braces for single-line body conditionals
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10666>
Juan A. Suarez Romero [Wed, 21 Apr 2021 10:22:33 +0000 (12:22 +0200)]
v3d: check if device supports performance monitors
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10666>
Juan A. Suarez Romero [Wed, 21 Apr 2021 10:14:46 +0000 (12:14 +0200)]
drm-uapi: add v3d performance counters
Extends CL submit to include performance monitor, and add proper ioctl
calls to create, destroy and query performance monitor counters.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10666>
Samuel Pitoiset [Fri, 30 Jul 2021 12:19:26 +0000 (14:19 +0200)]
ac/surface: implement CmaskAddrFromCoord in NIR
It's similar to DCC, only GFX9 is currently supported.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12140>
Samuel Pitoiset [Thu, 29 Jul 2021 07:09:57 +0000 (09:09 +0200)]
ac/surface: copy the CMASK equation to radeon_surf
Only GFX9 is currently supported.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12140>
Samuel Pitoiset [Thu, 29 Jul 2021 07:04:45 +0000 (09:04 +0200)]
ac/surface: store CMASK pitch and height to radeon_surf
Only GFX9+ is currently supported.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12140>
Samuel Pitoiset [Fri, 30 Jul 2021 11:41:53 +0000 (13:41 +0200)]
ac/surface: add tests for CmaskAddrFromCoord prototype outside of addrlib
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12140>
Samuel Pitoiset [Fri, 30 Jul 2021 11:41:30 +0000 (13:41 +0200)]
amd/addrlib: expose CMASK address equations to drivers on GFX9
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12140>
Samuel Pitoiset [Fri, 30 Jul 2021 11:58:25 +0000 (13:58 +0200)]
ac: introduce a structure to store DCC address equations for GFX9
CMASK addr equations will use the same struct.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12140>
Paulo Zanoni [Fri, 30 Jul 2021 00:26:37 +0000 (17:26 -0700)]
iris: mark the workaround_bo as asynchronous
Opt out of implicit synchronization for the workaround bo: we already
never mark it as writable and we only write to it as part of
PIPE_CONTROL synchronization requirements. Setting it as ASYNC should
be enough for i915.ko to pin it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12151>
Rob Clark [Thu, 29 Jul 2021 22:46:10 +0000 (15:46 -0700)]
freedreno: Unleash the dragon!
A number of android games are so far, sadly, unaware of open source
drivers. And when they see an unknown driver they lump it in the lowest
performance tier, artificially limiting framerate and/or gfx settings.
So until the games catch up, use driconf to override vendor/renderer
settings for moar fps and nicer gfx.
Furthermore, some games seem to be limiting *too* conservatively when
we otherwise have plenty of headroom even if we claim to be a bigger
adreno. Possibly a concession to battery life or tighter thermal
constraints in a phone, as compared to something like a chromebook.
Or maybe the flagship gaming phone thing is a scam ;-)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12135>
Rob Clark [Sat, 31 Jul 2021 00:00:32 +0000 (17:00 -0700)]
freedreno: Support per-device driconf overrides
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12135>
Rob Clark [Thu, 29 Jul 2021 01:41:01 +0000 (18:41 -0700)]
driconf: Add force_gl_renderer override
Allow driconf to also override GL_RENDERER string.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12135>
Rob Clark [Thu, 29 Jul 2021 01:17:42 +0000 (18:17 -0700)]
driconfig: Add support for device specific config
Add support for driconf overrides on a per-device level, for cases
where we don't want to override behavior for all devices supported
by a particular driver.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12135>
Emma Anholt [Fri, 30 Jul 2021 21:47:33 +0000 (14:47 -0700)]
gallium/driconf: Allow the driver to parse the driconf options.
This will give the driver a chance to set a device name separate from the
driver name, using info probed during screen creation. All drivers
querying driconf in screen creation now have to call parsing on their own,
but other drivers get fallback parsing after screen creation.
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12135>
Emma Anholt [Fri, 30 Jul 2021 21:35:53 +0000 (14:35 -0700)]
gallium/dri2: Make dri_init_options just init DRI options.
pipe_loader_create_screen() sets up the driconf anyway, so we can just
call this after that.
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12135>
Ella-0 [Wed, 28 Jul 2021 08:53:00 +0000 (08:53 +0000)]
v3dv: Implement VK_EXT_custom_border_color
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12076>
Ella-0 [Wed, 28 Jul 2021 08:52:44 +0000 (08:52 +0000)]
v3dv: Add is_unorm, is_snorm and is_float format functions
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12076>
Chia-I Wu [Fri, 30 Jul 2021 18:17:56 +0000 (11:17 -0700)]
venus: break up vn_device.c
Break it up into vn_{device,instance,physical_device}.c. Suggested by
Ryan Neph.
vn_EnumerateDeviceExtensionProperties and
vn_EnumerateDeviceLayerProperties were previously said to be device
commands. But in this commit, we move them to vn_physical_device.c
instead.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12144>
Chia-I Wu [Fri, 30 Jul 2021 18:07:55 +0000 (11:07 -0700)]
venus: break up vn_device.h
Break it up into vn_{device,instance,physical_device}.h. Suggested by
Ryan Neph.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12144>
Chia-I Wu [Fri, 30 Jul 2021 18:40:29 +0000 (11:40 -0700)]
venus: update venus-protocol headers
Updated to 1.2.182. Added some NULL checks.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12144>
Chia-I Wu [Fri, 30 Jul 2021 21:55:22 +0000 (14:55 -0700)]
iris, crocus: add idep_genxml to per_hw target dependencies
Fixes
In file included from ../src/gallium/drivers/iris/iris_query.c:49:
../src/gallium/drivers/iris/iris_genx_macros.h:81:10: fatal error: genxml/genX_bits.h: No such file or directory
and
In file included from ../src/gallium/drivers/crocus/crocus_query.c:50:
../src/gallium/drivers/crocus/crocus_genx_macros.h:86:10: fatal error: genxml/genX_bits.h: No such file or directory
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12149>
Marek Olšák [Fri, 28 May 2021 05:01:51 +0000 (01:01 -0400)]
st/mesa: remove st_vertex_program::input_to_index
It's the same as a prefix bitcount of inputs_read.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11370>
Marek Olšák [Fri, 28 May 2021 05:01:51 +0000 (01:01 -0400)]
st/mesa: remove st_vertex_program::index_to_input
We just need the mask of used vertex attribs.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11370>
Marek Olšák [Thu, 27 May 2021 03:59:24 +0000 (23:59 -0400)]
st/mesa: remove lowering of 64-bit vertex attribs to 32 bits
pipe_context::create_vertex_elements_state lowers them now.
This removes a bunch of code that is no longer needed.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11370>
Marek Olšák [Thu, 27 May 2021 03:45:45 +0000 (23:45 -0400)]
gallium: lower raw 64-bit vertex formats in cso/vbuf instead of st/mesa
This lower each 64-bit vertex element into 1 or 2 32-bit vertex elements.
The motivation is to simplify st/mesa, which uses a lot more complicated
code to do the same thing, and do the lowering only on a cso_cache miss.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11370>
Marek Olšák [Fri, 28 May 2021 20:11:17 +0000 (16:11 -0400)]
gallium: add pipe_vertex_element::dual_slot to move lowering to CSO creation
This just adds the new field. It will be used to lower 64-bit attribs
in drivers (via a helper).
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11370>
Marek Olšák [Mon, 14 Jun 2021 23:51:11 +0000 (19:51 -0400)]
gallium: add multi-component 64-bit UINT formats for raw double vertex attribs
This is the distinction between formats:
- PIPE_FORMAT_R64_FLOAT is the legacy "convert-to-float" vertex format.
- PIPE_FORMAT_R64_UINT is the raw double format.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11370>
Marek Olšák [Fri, 28 May 2021 19:22:03 +0000 (15:22 -0400)]
gallium: change pipe_vertex_element::src_format to uint8_t
This removes the bitfield packing/unpacking.
pipe_format entries are reordered to have vertex formats first because
vertex formats must be <= 255.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11370>
Marek Olšák [Thu, 27 May 2021 01:14:56 +0000 (21:14 -0400)]
shader_enums,mesa: move VERT_ATTRIB_EDGEFLAG to slot 31 for st/mesa
A future commit will replace st_vertex_program::input_to_index with
a prefix bitcount of inputs_read, but it needs vertex inputs to be
in the same order as vertex attribs.
Some of the FF definitions don't make sense with this ordering and are
removed.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11370>
Dave Airlie [Sun, 1 Aug 2021 23:59:31 +0000 (19:59 -0400)]
crocus: add support for set alpha to one with blt.
This is ported from 965 and fixes
dEQP-GLES2.functional.fbo.render.recreate_colorbuffer.*rebind_tex2d_rgb*
Fixes:
f3630548f1da9 ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12164>
Dave Airlie [Sun, 1 Aug 2021 23:59:10 +0000 (19:59 -0400)]
intel/genxml: fix raster operation field in blt genxml
This field should be a uint, further changes on top of previous
ones in this area
Fixes:
4d80ec8fcfaad ("intel/genxml: fix raster op fields on gen4/5")
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12164>
Dave Airlie [Mon, 2 Aug 2021 06:26:46 +0000 (02:26 -0400)]
crocus/gen45: fix mapping compressed textures
I don't think iris ever hits this path, but probably has the same bug if
it did.
Fixes texsubimage on gfx4 + gfx4.5
Fixes:
5bf6ec31ccf6 ("crocus/gen4: restrict memcpy mapping to gen5")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12164>
xantares [Mon, 2 Aug 2021 10:13:46 +0000 (10:13 +0000)]
lavapipe: Fix 32bits windows build
Fixes:
94a49828
Closes #5161
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12165>
Emma Anholt [Fri, 30 Jul 2021 20:00:52 +0000 (13:00 -0700)]
turnip: Fix assertions on checking mutable combined samplers support.
We would determine that it was unsupported, then ask for the size and
triggered the assertion checking that we never ask for the size of a
combined sampler.
Fixes:
ee3495e46504 ("turnip: Add support for VK_VALVE_mutable_descriptor_type")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12148>
Danylo Piliaiev [Thu, 4 Mar 2021 14:33:54 +0000 (16:33 +0200)]
turnip: reduce maxComputeWorkGroupSize
Blob advertises { 1024, 1024, 64 }, but from tests they all
could be 1024.
Fixes tests:
dEQP-VK.compute.basic.max_local_size_x
dEQP-VK.compute.basic.max_local_size_y
dEQP-VK.compute.basic.max_local_size_z
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9409>
Yiwei Zhang [Mon, 2 Aug 2021 15:49:55 +0000 (15:49 +0000)]
venus: cache ahb backed buffer memory type bits requirement
To properly init buffer memory requirement for AHB, memory type bits
from dma_buf fd properties need to be masked. However, creating a test
AHB at buffer creation is too costy. This patch caches the ahb backed
buffer memory type bits at device creation time if the app is requesting
AHB extension.
Cc: 21.2 mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12171>
Sagar Ghuge [Thu, 29 Jul 2021 21:56:19 +0000 (14:56 -0700)]
genxml/gen125: Update debug register fields according to HW
Updating fields helps to decode the error state correctly.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12133>
Sagar Ghuge [Thu, 29 Jul 2021 21:54:35 +0000 (14:54 -0700)]
genxml/gen12: Update debug register fields according to HW
Updating fields helps to decode the error state correctly.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12133>
Pierre-Eric Pelloux-Prayer [Fri, 12 Mar 2021 14:42:34 +0000 (15:42 +0100)]
radeonsi: add expected tests results for Navi10 GPU
These results will not be enforced by CI, but they'll be helpful to test
a changeset against a baseline.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9561>
Pierre-Eric Pelloux-Prayer [Fri, 12 Mar 2021 14:40:09 +0000 (15:40 +0100)]
radeonsi: add a script to run piglit/glcts/deqp tests
To make it easy to run deqp-runner/piglit-runner.
It's heavily based on Marek' script from:
https://github.com/marekolsak/marek-build/blob/master/run-piglit.sh
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9561>
Timur Kristóf [Thu, 15 Jul 2021 13:28:13 +0000 (15:28 +0200)]
ac/nir: Remove unhelpful nir_opt_cse from ac_nir_lower_ngg_nogs.
This CSE call adds to our compile time without adding any real
benefit to the compiled code.
Fossil DB results on Sienna Cichlid (with NGGC on):
Totals from 1580 (1.23% of 128647) affected shaders:
CodeSize: 4563912 -> 4562312 (-0.04%); split: -0.07%, +0.03%
Instrs: 870722 -> 870338 (-0.04%); split: -0.09%, +0.04%
Latency: 3349863 -> 3351458 (+0.05%); split: -0.10%, +0.14%
InvThroughput: 617796 -> 617971 (+0.03%); split: -0.01%, +0.03%
VClause: 22604 -> 22568 (-0.16%); split: -0.75%, +0.59%
SClause: 16285 -> 16327 (+0.26%); split: -0.07%, +0.33%
Copies: 83472 -> 83599 (+0.15%); split: -0.07%, +0.22%
PreSGPRs: 62340 -> 62334 (-0.01%)
No Fossil DB changes with NGGC off.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11908>
Timur Kristóf [Thu, 15 Jul 2021 12:38:27 +0000 (14:38 +0200)]
nir, aco: Remove vertex and primitive count overwrite intrinsic.
It's no longer needed.
No Fossil DB changes.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11908>
Timur Kristóf [Thu, 15 Jul 2021 12:37:39 +0000 (14:37 +0200)]
ac/nir: Don't count vertices and primitives in wave after culling.
These are not needed anymore, because the EXEC mask doesn't depend on them.
Fossil DB results on Sienna Cichlid (with NGGC on):
Totals from 58239 (45.27% of 128647) affected shaders:
Latency:
138113669 ->
138285372 (+0.12%)
InvThroughput:
22404840 ->
22405245 (+0.00%)
No Fossil DB changes with NGGC off.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11908>
Timur Kristóf [Thu, 15 Jul 2021 12:32:34 +0000 (14:32 +0200)]
ac/nir: Use gs_accepted variable after culling.
This prevents us from recalculating the EXEC mask later
in the shader, and removes the requirement for
counting the number of primitives.
The stats are better than expected because they also
show that some code that is still there is now DCE'd by ACO.
Fossil DB results on Sienna Cichlid (with NGGC on):
Totals from 58239 (45.27% of 128647) affected shaders:
SpillSGPRs: 330 -> 340 (+3.03%)
CodeSize:
166356072 ->
162805724 (-2.13%)
Instrs:
31920041 ->
31089256 (-2.60%)
Latency:
138815742 ->
138113669 (-0.51%); split: -0.54%, +0.03%
InvThroughput:
22459553 ->
22404840 (-0.24%); split: -0.26%, +0.02%
SClause: 753746 -> 753765 (+0.00%); split: -0.00%, +0.01%
Copies: 3226647 -> 3268973 (+1.31%); split: -0.45%, +1.76%
Branches: 1223441 -> 1223440 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 2025339 -> 2091013 (+3.24%)
No Fossil DB changes with NGGC off.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11908>
Timur Kristóf [Thu, 15 Jul 2021 12:20:59 +0000 (14:20 +0200)]
ac/nir: Use es_accepted variable after culling.
This avoids re-calculating the exec mask for ES vertices,
and makes it unnecessary to count the number of vertices left.
Fossil DB results on Sienna Cichlid (with NGGC on):
Totals from 58239 (45.27% of 128647) affected shaders:
CodeSize:
166521108 ->
166356072 (-0.10%); split: -0.10%, +0.00%
Instrs:
31961308 ->
31920041 (-0.13%); split: -0.13%, +0.00%
Latency:
138820463 ->
138815742 (-0.00%); split: -0.04%, +0.04%
InvThroughput:
22460177 ->
22459553 (-0.00%); split: -0.00%, +0.00%
SClause: 753744 -> 753746 (+0.00%)
Copies: 3093140 -> 3226647 (+4.32%); split: -0.03%, +4.34%
No Fossil DB changes with NGGC off.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11908>
Timur Kristóf [Thu, 15 Jul 2021 11:56:18 +0000 (13:56 +0200)]
aco, nir, ac: Simplify sequence of getting initial NGG VS edge flags.
Instead of v_bfe + v_lshl_or for each vertex, get all 3 edge flags
at once of every vertex. This takes fewer VALU instructions than
previously.
Fossil DB results on Sienna Cichlid (with NGGC on):
Totals from 56917 (44.24% of 128647) affected shaders:
CodeSize:
161028288 ->
158751628 (-1.41%)
Instrs:
30917985 ->
30519571 (-1.29%)
Latency:
130617204 ->
129975532 (-0.49%); split: -0.50%, +0.01%
InvThroughput:
21280238 ->
20927401 (-1.66%)
Copies: 3011120 -> 3011125 (+0.00%); split: -0.00%, +0.00%
No Fossil DB changed with NGGC off.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11908>