Stephen Boyd [Tue, 29 Mar 2022 17:19:10 +0000 (10:19 -0700)]
Merge branches 'clk-starfive', 'clk-ti', 'clk-terminate' and 'clk-cleanup' into clk-next
- Audio clks on StarFive JH7100 RISC-V SoC
- Terminate arrays with sentinels and make that clearer
- Cleanup SPDX tags
- Fix typos in comments
* clk-starfive:
clk: starfive: Add JH7100 audio clock driver
clk: starfive: jh7100: Support more clock types
clk: starfive: jh7100: Make hw clock implementation reusable
dt-bindings: clock: Add starfive,jh7100-audclk bindings
dt-bindings: clock: Add JH7100 audio clock definitions
clk: starfive: jh7100: Handle audio_div clock properly
clk: starfive: jh7100: Don't round divisor up twice
* clk-ti:
clk: ti: Drop legacy compatibility clocks for dra7
clk: ti: Drop legacy compatibility clocks for am4
clk: ti: Drop legacy compatibility clocks for am3
clk: ti: Update component clocks to use ti_dt_clk_name()
clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name()
clk: ti: Add ti_dt_clk_name() helper to use clock-output-names
clk: ti: Use clock-output-names for clkctrl
clk: ti: Add ti_find_clock_provider() to use clock-output-names
clk: ti: Optionally parse IO address from parent clock node
clk: ti: Preserve node in ti_dt_clocks_register()
clk: ti: Constify clkctrl_name
* clk-terminate:
clk: actions: Make sentinel elements more obvious
clk: clps711x: Terminate clk_div_table with sentinel element
clk: hisilicon: Terminate clk_div_table with sentinel element
clk: loongson1: Terminate clk_div_table with sentinel element
clk: actions: Terminate clk_div_table with sentinel element
* clk-cleanup:
clk: zynq: Update the parameters to zynq_clk_register_periph_clk
clk: zynq: trivial warning fix
clk: qcom: sm6125-gcc: fix typos in comments
clk: ti: clkctrl: fix typos in comments
clk: COMMON_CLK_LAN966X should depend on SOC_LAN966
clk: Use of_device_get_match_data()
clk: bcm2835: Remove unused variable
clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver
clk: cleanup comments
clk: socfpga: cleanup spdx tags
Stephen Boyd [Tue, 29 Mar 2022 17:18:56 +0000 (10:18 -0700)]
Merge branches 'clk-mvebu', 'clk-const', 'clk-imx' and 'clk-rockchip' into clk-next
- Mark mux table as const in clk-mux
- Make the all_lists array const
* clk-mvebu:
clk: mvebu: use time_is_before_eq_jiffies() instead of open coding it
* clk-const:
clk: Mark clk_core_evict_parent_cache_subtree() 'target' const
clk: Mark 'all_lists' as const
clk: pistachio: Declare mux table as const u32[]
clk: qcom: Declare mux table as const u32[]
clk: mmp: Declare mux tables as const u32[]
clk: hisilicon: Remove unnecessary cast of mux table to u32 *
clk: mux: Declare u32 *table parameter as const
clk: nxp: Declare mux table parameter as const u32 *
clk: nxp: Remove unused variable
* clk-imx: (28 commits)
dt-bindings: clock: drop useless consumer example
clk: imx: Select MXC_CLK for i.MX93 clock driver
clk: imx: remove redundant re-assignment of pll->base
MAINTAINERS: clk: imx: add git tree and dt-bindings files
clk: imx: pll14xx: Support dynamic rates
clk: imx: pll14xx: Add pr_fmt
clk: imx: pll14xx: explicitly return lowest rate
clk: imx: pll14xx: name variables after usage
clk: imx: pll14xx: consolidate rate calculation
clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP
clk: imx: pll14xx: Drop wrong shifting
clk: imx: pll14xx: Use register defines consistently
clk: imx8mp: remove SYS PLL 1/2 clock gates
clk: imx8mn: remove SYS PLL 1/2 clock gates
clk: imx8mm: remove SYS PLL 1/2 clock gates
clk: imx: add i.MX93 clk
clk: imx: support fracn gppll
clk: imx: add i.MX93 composite clk
dt-bindings: clock: add i.MX93 clock definition
dt-bindings: clock: Add imx93 clock support
...
* clk-rockchip:
clk: rockchip: re-add rational best approximation algorithm to the fractional divider
clk/rockchip: Use of_device_get_match_data()
clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568
clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568
clk: rockchip: Add more PLL rates for rk3568
Stephen Boyd [Tue, 29 Mar 2022 17:18:37 +0000 (10:18 -0700)]
Merge branches 'clk-xilinx', 'clk-kunit', 'clk-cs2000' and 'clk-renesas' into clk-next
- Kunit tests for clk-gate implementation
- Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add
support for dynamic mode
* clk-xilinx:
clk: zynqmp: replace warn_once with pr_debug for failed clock ops
* clk-kunit:
clk: gate: Add some kunit test suites
* clk-cs2000:
clk: cs2000-cp: convert driver to regmap
clk: cs2000-cp: freeze config during register fiddling
clk: cs2000-cp: make clock skip setting configurable
clk: cs2000-cp: add support for dynamic mode
clk: cs2000-cp: Make aux output function controllable
dt-bindings: clock: cs2000-cp: document cirrus,dynamic-mode
dt-bindings: clock: cs2000-cp: document cirrus,clock-skip flag
dt-bindings: clock: cs2000-cp: document aux-output-source
dt-bindings: clock: convert cs2000-cp bindings to yaml
* clk-renesas:
dt-bindings: clock: renesas: Make example 'clocks' parsable
clk: rs9: Add Renesas 9-series PCIe clock generator driver
clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index()
dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator
clk: renesas: r8a779f0: Add PFC clock
clk: renesas: r8a779f0: Add I2C clocks
clk: renesas: r8a779f0: Add WDT clock
clk: renesas: r8a779f0: Fix RSW2 clock divider
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
dt-bindings: clock: renesas: Document RZ/V2L SoC
dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
clk: renesas: r8a779a0: Add CANFD module clock
clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3
clk: renesas: r8a7799[05]: Add MLP clocks
clk: renesas: r8a779f0: Add SYS-DMAC clocks
Stephen Boyd [Tue, 29 Mar 2022 17:18:21 +0000 (10:18 -0700)]
Merge branches 'clk-microchip', 'clk-si', 'clk-mtk', 'clk-at91' and 'clk-st' into clk-next
- Clock configuration on Microchip PolarFire SoCs
- Free allocations on probe error in Mediatek clk driver
- Modernize Mediatek clk driver by consolidating code
* clk-microchip:
clk: microchip: Add driver for Microchip PolarFire SoC
dt-bindings: clk: microchip: Add Microchip PolarFire host binding
* clk-si:
clk-si5341: replace snprintf in show functions with sysfs_emit
clk: si5341: fix reported clk_rate when output divider is 2
* clk-mtk: (32 commits)
clk: mediatek: Warn if clk IDs are duplicated
clk: mediatek: mt8195: Implement remove functions
clk: mediatek: mt8195: Implement error handling in probe functions
clk: mediatek: mt8195: Hook up mtk_clk_simple_remove()
clk: mediatek: Unregister clks in mtk_clk_simple_probe() error path
clk: mediatek: mtk: Implement error handling in register APIs
clk: mediatek: pll: Implement error handling in register API
clk: mediatek: mux: Implement error handling in register API
clk: mediatek: mux: Reverse check for existing clk to reduce nesting level
clk: mediatek: gate: Implement error handling in register API
clk: mediatek: cpumux: Implement error handling in register API
clk: mediatek: mtk: Clean up included headers
clk: mediatek: Add mtk_clk_simple_remove()
clk: mediatek: Implement mtk_clk_unregister_composites() API
clk: mediatek: Implement mtk_clk_unregister_divider_clks() API
clk: mediatek: Implement mtk_clk_unregister_factors() API
clk: mediatek: Implement mtk_clk_unregister_fixed_clks() API
clk: mediatek: pll: Clean up included headers
clk: mediatek: pll: Implement unregister API
clk: mediatek: pll: Split definitions into separate header file
...
* clk-at91:
clk: at91: clk-master: remove dead code
clk: at91: sama7g5: fix parents of PDMCs' GCLK
clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DT
clk: at91: allow setting PMC_AUDIOPINCK clock parents via DT
* clk-st:
clk: stm32mp1: Add parent_data to ETHRX clock
clk: stm32mp1: Split ETHCK_K into separate MUX and GATE clock
Shubhrajyoti Datta [Tue, 22 Feb 2022 13:09:03 +0000 (18:39 +0530)]
clk: zynq: Update the parameters to zynq_clk_register_periph_clk
In case there are only one gate or the two_gate is 0 the clk1 clock
passed is not used. We are passing 0 which is arm_pll.
Pass a invalid clock instead.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220222130903.17235-3-shubhrajyoti.datta@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Shubhrajyoti Datta [Tue, 22 Feb 2022 13:09:02 +0000 (18:39 +0530)]
clk: zynq: trivial warning fix
Fix the below warning
WARNING: Missing a blank line after declarations
+ int enable = !!(fclk_enable & BIT(i - fclk0));
+ zynq_clk_register_fclk(i, clk_output_name[i],
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220222130903.17235-2-shubhrajyoti.datta@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Krzysztof Kozlowski [Wed, 16 Mar 2022 13:08:58 +0000 (14:08 +0100)]
dt-bindings: clock: drop useless consumer example
Consumer examples in the bindings of resource providers are trivial,
useless and duplication of code. Remove the example code for consumer
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20220316130858.93455-2-krzysztof.kozlowski@canonical.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Rob Herring [Tue, 1 Mar 2022 19:03:59 +0000 (13:03 -0600)]
dt-bindings: clock: renesas: Make example 'clocks' parsable
'clocks' in the example is not parsable with the 0 phandle value
because the number of #clock-cells is unknown in the previous entry.
Solve this by adding the clock provider node. Only 'cpg_clocks' is
needed as the examples are built with fixups which can be used to
identify phandles.
This is in preparation to support schema validation on .dtb files.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220301190400.1644150-1-robh@kernel.org
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Marek Vasut [Sat, 26 Feb 2022 04:07:23 +0000 (05:07 +0100)]
clk: rs9: Add Renesas 9-series PCIe clock generator driver
Add driver for Renesas 9-series PCIe clock generators. This driver
is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C
PCIe clock generators, currently the only tested and supported chip
is 9FGV0241.
The driver is capable of configuring per-chip spread spectrum mode
and output amplitude, as well as per-output slew rate.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Link: https://lore.kernel.org/r/20220226040723.143705-3-marex@denx.de
[sboyd@kernel.org: Use non-underscore API for fixed factor]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Marek Vasut [Sat, 26 Feb 2022 04:07:22 +0000 (05:07 +0100)]
clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index()
Add an API for a fixed factor clk that uses an index for the parent
instead of a string name. This allows us to move drivers away from the
string based method of describing parents and use the DT/firmware based
method instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Link: https://lore.kernel.org/r/20220226040723.143705-2-marex@denx.de
[sboyd@kernel.org: Expose a new API instead of internal function]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Marek Vasut [Sat, 26 Feb 2022 04:07:21 +0000 (05:07 +0100)]
dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator
Add binding for Renesas 9-series PCIe clock generators. This binding
is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C
PCIe clock generators, currently the only tested and supported chip
is 9FGV0241.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Link: https://lore.kernel.org/r/20220226040723.143705-1-marex@denx.de
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Julia Lawall [Mon, 14 Mar 2022 11:53:39 +0000 (12:53 +0100)]
clk: qcom: sm6125-gcc: fix typos in comments
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/20220314115354.144023-16-Julia.Lawall@inria.fr
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Julia Lawall [Mon, 14 Mar 2022 11:53:38 +0000 (12:53 +0100)]
clk: ti: clkctrl: fix typos in comments
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/20220314115354.144023-15-Julia.Lawall@inria.fr
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Abel Vesa [Tue, 15 Mar 2022 08:24:46 +0000 (10:24 +0200)]
clk: imx: Select MXC_CLK for i.MX93 clock driver
Most of the i.MX clock generic API is built by selecting MXC_CLK.
Without it, the i.MX93 clock driver will fail to build:
aarch64-linux-gnu-ld: drivers/clk/imx/clk-imx93.o:
in function `imx93_clocks_probe': clk-imx93.c:(.text+0xa8):
undefined reference to `imx_obtain_fixed_clk_hw'
So fix this by selecting MXC_CLK for the CLK_IMX93.
Fixes:
24defbe194b6 ("clk: imx: add i.MX93 clk")
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20220315082446.3120850-1-abel.vesa@nxp.com
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tony Lindgren [Thu, 3 Feb 2022 08:56:18 +0000 (10:56 +0200)]
clk: ti: Drop legacy compatibility clocks for dra7
We no longer have users for the compatibility clocks and we can drop them.
These are old duplicate clocks for what we using.
Depends-on:
31aa7056bbec ("ARM: dts: Don't use legacy clock defines for dra7 clkctrl")
Depends-on:
9206a3af4fc0 ("clk: ti: Move dra7 clock devices out of the legacy section")
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220203085618.16043-4-tony@atomide.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tony Lindgren [Thu, 3 Feb 2022 08:56:17 +0000 (10:56 +0200)]
clk: ti: Drop legacy compatibility clocks for am4
We no longer have users for the compatibility clocks and we can drop them.
These are old duplicate clocks for what we using.
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220203085618.16043-3-tony@atomide.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tony Lindgren [Thu, 3 Feb 2022 08:56:16 +0000 (10:56 +0200)]
clk: ti: Drop legacy compatibility clocks for am3
We no longer have users for the compatibility clocks and we can drop them.
These are old duplicate clocks for what we using.
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220203085618.16043-2-tony@atomide.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Tue, 15 Mar 2022 21:06:06 +0000 (14:06 -0700)]
Merge tag 'v5.17-rc4' into clk-ti
We want to get commit
31aa7056bbec ("ARM: dts: Don't use legacy clock
defines for dra7 clkctrl") so merge in the nearest rc.
Daire McNamara [Tue, 22 Feb 2022 12:11:44 +0000 (12:11 +0000)]
clk: microchip: Add driver for Microchip PolarFire SoC
Add support for clock configuration on Microchip PolarFire SoC
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Co-developed-by: Padmarao Begari <padmarao.begari@microchip.com>
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220222121143.3316880-2-conor.dooley@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Geert Uytterhoeven [Thu, 24 Feb 2022 15:29:17 +0000 (16:29 +0100)]
clk: COMMON_CLK_LAN966X should depend on SOC_LAN966
The LAN966x Generic Clock Controller is only present on Microchip
LAN966x SoCs. Hence add a dependency on SOC_LAN966, to prevent asking
the user about this driver when configuring a kernel without LAN966x SoC
support.
Fixes:
54104ee023333e3b ("clk: lan966x: Add lan966x SoC clock driver")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/eb102eae05e5667b9bd342a0c387f7f262d24bda.1645716471.git.geert+renesas@glider.be
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Minghao Chi (CGEL ZTE) [Thu, 3 Mar 2022 01:48:56 +0000 (01:48 +0000)]
clk: Use of_device_get_match_data()
Use of_device_get_match_data() to simplify the code.
Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Minghao Chi (CGEL ZTE) <chi.minghao@zte.com.cn>
Link: https://lore.kernel.org/r/20220303014856.2059307-1-chi.minghao@zte.com.cn
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Maxime Ripard [Tue, 22 Feb 2022 14:07:32 +0000 (15:07 +0100)]
clk: bcm2835: Remove unused variable
Since commit
8ca011ef4af4 ("clk: bcm-2835: Remove rounding up the
dividers"), the rem variable is still set but no longer used. Remove it.
Fixes:
8ca011ef4af4 ("clk: bcm-2835: Remove rounding up the dividers")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20220222140732.253819-1-maxime@cerno.tech
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Miaoqian Lin [Wed, 12 Jan 2022 10:45:01 +0000 (10:45 +0000)]
clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver
The reference taken by 'of_find_device_by_node()' must be released when
not needed anymore.
Add the corresponding 'put_device()' in the error handling path.
Fixes:
2db04f16b589 ("clk: tegra: Add EMC clock driver")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20220112104501.30655-1-linmq006@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tom Rix [Tue, 22 Feb 2022 19:51:53 +0000 (11:51 -0800)]
clk: cleanup comments
For spdx
Space instead of tab before spdx tag
Removed repeated works
the, to, two
Replacements
much much to a much
'to to' to 'to do'
aready to already
Comunications to Communications
freqency to frequency
Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20220222195153.3817625-1-trix@redhat.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tom Rix [Thu, 17 Feb 2022 17:34:53 +0000 (09:34 -0800)]
clk: socfpga: cleanup spdx tags
Replace tabs with spaces in SPDX tag
Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20220217173453.3262672-1-trix@redhat.com
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonathan Neuschäfer [Fri, 18 Feb 2022 00:09:21 +0000 (01:09 +0100)]
clk: actions: Make sentinel elements more obvious
The sentinel elements of various tables in drivers/clk/actions can be a
bit hard to recognize. Make them easier to see by changing the style
from { 0, 0 } to { /* sentinel */ }.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220218000922.134857-6-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonathan Neuschäfer [Fri, 18 Feb 2022 00:09:20 +0000 (01:09 +0100)]
clk: clps711x: Terminate clk_div_table with sentinel element
In order that the end of a clk_div_table can be detected, it must be
terminated with a sentinel element (.div = 0).
Fixes:
631c53478973d ("clk: Add CLPS711X clk driver")
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220218000922.134857-5-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonathan Neuschäfer [Fri, 18 Feb 2022 00:09:19 +0000 (01:09 +0100)]
clk: hisilicon: Terminate clk_div_table with sentinel element
In order that the end of a clk_div_table can be detected, it must be
terminated with a sentinel element (.div = 0).
Fixes:
6c81966107dc0 ("clk: hisilicon: Add clock driver for hi3559A SoC")
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220218000922.134857-4-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonathan Neuschäfer [Fri, 18 Feb 2022 00:09:18 +0000 (01:09 +0100)]
clk: loongson1: Terminate clk_div_table with sentinel element
In order that the end of a clk_div_table can be detected, it must be
terminated with a sentinel element (.div = 0).
Fixes:
b4626a7f4892 ("CLK: Add Loongson1C clock support")
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Link: https://lore.kernel.org/r/20220218000922.134857-3-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonathan Neuschäfer [Fri, 18 Feb 2022 00:09:17 +0000 (01:09 +0100)]
clk: actions: Terminate clk_div_table with sentinel element
In order that the end of a clk_div_table can be detected, it must be
terminated with a sentinel element (.div = 0).
In owl-s900.s, the { 0, 8 } element was probably meant to be just that,
so this patch changes { 0, 8 } to { 0, 0 }.
Fixes:
d47317ca4ade1 ("clk: actions: Add S700 SoC clock support")
Fixes:
d85d20053e195 ("clk: actions: Add S900 SoC clock support")
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://lore.kernel.org/r/20220218000922.134857-2-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tony Lindgren [Fri, 4 Feb 2022 07:14:49 +0000 (09:14 +0200)]
clk: ti: Update component clocks to use ti_dt_clk_name()
Let's update all the TI component clocks to use ti_dt_clk_name() instead
of devicetree node name if available.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220204071449.16762-9-tony@atomide.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tony Lindgren [Fri, 4 Feb 2022 07:14:48 +0000 (09:14 +0200)]
clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name()
Let's update the TI pll and clockdomain clocks to use ti_dt_clk_name()
instead of devicetree node name if available.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220204071449.16762-8-tony@atomide.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tony Lindgren [Fri, 4 Feb 2022 07:14:47 +0000 (09:14 +0200)]
clk: ti: Add ti_dt_clk_name() helper to use clock-output-names
Let's create the clock alias based on the clock-output-names property if
available. Also the component clock drivers can use ti_dt_clk_name() in
the following patches.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220204071449.16762-7-tony@atomide.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tony Lindgren [Fri, 4 Feb 2022 07:14:46 +0000 (09:14 +0200)]
clk: ti: Use clock-output-names for clkctrl
Use clock-output-names devicetree property for clkctrl clocks if
available.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220204071449.16762-6-tony@atomide.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tony Lindgren [Fri, 4 Feb 2022 07:14:45 +0000 (09:14 +0200)]
clk: ti: Add ti_find_clock_provider() to use clock-output-names
Let's add ti_find_clock_provider() so we can use clock-output-names
to name the clock provider instead of relying on non-standard devicetree
node names.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220204071449.16762-5-tony@atomide.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tony Lindgren [Fri, 4 Feb 2022 07:14:44 +0000 (09:14 +0200)]
clk: ti: Optionally parse IO address from parent clock node
If no reg property is specified for a TI clock, let's try to use the
parent clock node IO address. This way we can avoid duplicate devicetree
reg properties that cause warnings for unique_unit_address.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220204071449.16762-4-tony@atomide.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tony Lindgren [Fri, 4 Feb 2022 07:14:43 +0000 (09:14 +0200)]
clk: ti: Preserve node in ti_dt_clocks_register()
In preparation for making use of the clock-output-names, we want to
keep node around in ti_dt_clocks_register().
This change should not needed as a fix currently.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220204071449.16762-3-tony@atomide.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Tony Lindgren [Fri, 4 Feb 2022 07:14:42 +0000 (09:14 +0200)]
clk: ti: Constify clkctrl_name
We can constify clkctrl_name in preparation for making use of the
clock-output-names property.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20220204071449.16762-2-tony@atomide.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Emil Renner Berthing [Wed, 26 Jan 2022 17:39:53 +0000 (18:39 +0100)]
clk: starfive: Add JH7100 audio clock driver
Add a driver for the audio clocks on the Starfive JH7100 RISC-V SoC.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220126173953.1016706-8-kernel@esmil.dk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Emil Renner Berthing [Wed, 26 Jan 2022 17:39:52 +0000 (18:39 +0100)]
clk: starfive: jh7100: Support more clock types
Unlike the system clocks there are audio clocks that combine both
multiplexer/divider and gate/multiplexer/divider, so add support for
that.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220126173953.1016706-7-kernel@esmil.dk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Emil Renner Berthing [Wed, 26 Jan 2022 17:39:51 +0000 (18:39 +0100)]
clk: starfive: jh7100: Make hw clock implementation reusable
The JH7100 has additional audio and video clocks at different memory
ranges, but they use the same register layout. Add a header and export
the starfive_jh7100_clk_ops function so the clock implementation can be
reused by drivers handling these clocks.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220126173953.1016706-6-kernel@esmil.dk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Emil Renner Berthing [Wed, 26 Jan 2022 17:39:50 +0000 (18:39 +0100)]
dt-bindings: clock: Add starfive,jh7100-audclk bindings
Add bindings for the audio clocks on the StarFive JH7100 RISC-V SoC.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220126173953.1016706-5-kernel@esmil.dk
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Emil Renner Berthing [Wed, 26 Jan 2022 17:39:49 +0000 (18:39 +0100)]
dt-bindings: clock: Add JH7100 audio clock definitions
Add all clock outputs for the StarFive JH7100 audio clock generator.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220126173953.1016706-4-kernel@esmil.dk
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Emil Renner Berthing [Wed, 26 Jan 2022 17:39:48 +0000 (18:39 +0100)]
clk: starfive: jh7100: Handle audio_div clock properly
It turns out the audio_div clock is a fractional divider where the
lowest byte of the ctrl register is the integer part of the divider and
the 2nd byte is the number of 100th added to the divider.
The children of this clock is used by the audio peripherals for their
sample rate clock, so round to the closest possible rate rather than
always rounding down like regular dividers.
Fixes:
4210be668a09 ("clk: starfive: Add JH7100 clock generator driver")
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220126173953.1016706-3-kernel@esmil.dk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Emil Renner Berthing [Wed, 26 Jan 2022 17:39:47 +0000 (18:39 +0100)]
clk: starfive: jh7100: Don't round divisor up twice
The problem is best illustrated by an example. Suppose a consumer wants
a 4MHz clock rate from a divider with a 10MHz parent. It would then
call
clk_round_rate(clk, 4000000)
which would call into our determine_rate() callback that correctly
rounds up and finds that a divisor of 3 gives the highest possible
frequency below the requested 4MHz and returns
10000000 / 3 = 3333333Hz.
However the consumer would then call
clk_set_rate(clk, 3333333)
but since 3333333 doesn't divide
10000000 evenly our set_rate() callback
would again round the divisor up and set it to 4 which results in an
unnecessarily low rate of 2.5MHz.
Fix it by using DIV_ROUND_CLOSEST in the set_rate() callback.
Fixes:
4210be668a09 ("clk: starfive: Add JH7100 clock generator driver")
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220126173953.1016706-2-kernel@esmil.dk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Wed, 9 Mar 2022 18:50:09 +0000 (10:50 -0800)]
Merge tag 'renesas-clk-for-v5.18-tag2' of git://git./linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on
R-Car S4-8
- A small fix
* tag 'renesas-clk-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a779f0: Add PFC clock
clk: renesas: r8a779f0: Add I2C clocks
clk: renesas: r8a779f0: Add WDT clock
clk: renesas: r8a779f0: Fix RSW2 clock divider
Stephen Boyd [Wed, 9 Mar 2022 18:47:28 +0000 (10:47 -0800)]
Merge tag 'v5.18-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- Improve the clocks for the rk3568 display outputs (parenting, pll-rates)
- Use of_device_get_match_data() instead of open-coding on rk3568
- Reintroduce the expected fractional-divider behaviour that disappeared
with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS
* tag 'v5.18-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: re-add rational best approximation algorithm to the fractional divider
clk/rockchip: Use of_device_get_match_data()
clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568
clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568
clk: rockchip: Add more PLL rates for rk3568
Colin Ian King [Thu, 3 Mar 2022 09:05:08 +0000 (09:05 +0000)]
clk: imx: remove redundant re-assignment of pll->base
There are two identical assignments of pll->base to the same value,
the second assignment is redundant and can be removed.
Cleans up cppcheck warning:
drivers/clk/imx/clk-sscg-pll.c:528:12: style: Variable 'pll->base' is
reassigned a value before the old one has been used. [redundantAssignment]
Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Link: https://lore.kernel.org/r/20220303090508.1125175-1-colin.i.king@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Abel Vesa [Wed, 16 Feb 2022 13:22:14 +0000 (15:22 +0200)]
MAINTAINERS: clk: imx: add git tree and dt-bindings files
The i.MX clocks dt-bindings are going through the same tree as
the drivers, so add them to the same entry. Also add the git
tree and branch used.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220216132214.258865-1-abel.vesa@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Wed, 9 Mar 2022 18:18:28 +0000 (10:18 -0800)]
Merge tag 'clk-imx-5.18' of git://git./linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa:
- Add i.MXRT1050 clock driver and bindings
- Add i.MX8DXL clock driver and bindings
- Add i.MX93 clock driver and bindings
- Remove SYS PLL 1/2 clock gates for i.MX8M*
- Remove AUDIO MCLK ROOT from i.MX7D
- Add fracn gppll clock type used by i.MX93
- Add new composite clock for i.MX93
- Add missing media mipi phy ref clock for i.MX8MP
- Fix off by one in imx_lpcg_parse_clks_from_dt
- Rework for the pll14xx
* tag 'clk-imx-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: (24 commits)
clk: imx: pll14xx: Support dynamic rates
clk: imx: pll14xx: Add pr_fmt
clk: imx: pll14xx: explicitly return lowest rate
clk: imx: pll14xx: name variables after usage
clk: imx: pll14xx: consolidate rate calculation
clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP
clk: imx: pll14xx: Drop wrong shifting
clk: imx: pll14xx: Use register defines consistently
clk: imx8mp: remove SYS PLL 1/2 clock gates
clk: imx8mn: remove SYS PLL 1/2 clock gates
clk: imx8mm: remove SYS PLL 1/2 clock gates
clk: imx: add i.MX93 clk
clk: imx: support fracn gppll
clk: imx: add i.MX93 composite clk
dt-bindings: clock: add i.MX93 clock definition
dt-bindings: clock: Add imx93 clock support
clk: imx: off by one in imx_lpcg_parse_clks_from_dt()
dt-bindings: fsl: scu: add imx8dxl scu clock support
clk: imx7d: Remove audio_mclk_root_clk
clk: imx8mp: Add missing IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clock
...
Stephen Boyd [Wed, 9 Mar 2022 18:13:45 +0000 (10:13 -0800)]
Merge tag 'clk-at91-5.18' of git://git./linux/kernel/git/at91/linux into clk-at91
Pull AT91 clk driver changes From Nicolas Ferre:
- sama7g5: One low priority fix for GCLK of PDMC
- clk-master: cleanup of dead code
* tag 'clk-at91-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
clk: at91: clk-master: remove dead code
clk: at91: sama7g5: fix parents of PDMCs' GCLK
Claudiu Beznea [Thu, 3 Feb 2022 11:02:02 +0000 (13:02 +0200)]
clk: at91: clk-master: remove dead code
Commit
facb87ad7560 ("clk: at91: sama7g5: remove prescaler part of master
clock") removed the master clock's prescaler from clock tree of SAMA7G5
as it has been discovered that there is a hardware bug when trying to
change it at run-time (bug is described in description of
commit
facb87ad7560 ("clk: at91: sama7g5: remove prescaler part of master
clock")). This was previously changed at CPUFreq driver request. Thus, with
commit
facb87ad7560 ("clk: at91: sama7g5: remove prescaler part of master
clock") there is no need of code that handles run-time changes of master
clock's prescaler, thus remove this code.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220203110202.18329-1-claudiu.beznea@microchip.com
Codrin Ciubotariu [Fri, 4 Mar 2022 18:26:16 +0000 (20:26 +0200)]
clk: at91: sama7g5: fix parents of PDMCs' GCLK
Audio PLL can be used as parent by the GCLKs of PDMCs.
Fixes:
cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5")
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220304182616.1920392-1-codrin.ciubotariu@microchip.com
Sascha Hauer [Fri, 4 Mar 2022 12:52:56 +0000 (13:52 +0100)]
clk: imx: pll14xx: Support dynamic rates
The pll1443x PLL so far only supports rates from a rate table passed
during initialization. Calculating PLL settings dynamically helps audio
applications to get their desired rates, so support for this is added
in this patch.
The strategy to get to the PLL setting for a rate is:
- First try to only adjust kdiv which specifies the fractional part of the PLL.
This setting can be changed without glitches on the output and is therefore
preferred
- When that isn't possible then the rate table is searched for suitable rates,
so for standard rates the same settings are used as without this patch
- As a last resort the best settings are calculated dynamically
The code in this patch is based on patches from Adrian Alonso <adrian.alonso@nxp.com>
and Mads Bligaard Nielsen <bli@bang-olufsen.dk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220304125256.2125023-9-s.hauer@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Sascha Hauer [Fri, 4 Mar 2022 12:52:55 +0000 (13:52 +0100)]
clk: imx: pll14xx: Add pr_fmt
Print all messages from within the pll14xx driver with a common
prefix using pr_fmt. No need to print function names anymore, so
drop them from the messages.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220304125256.2125023-8-s.hauer@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Sascha Hauer [Fri, 4 Mar 2022 12:52:54 +0000 (13:52 +0100)]
clk: imx: pll14xx: explicitly return lowest rate
clk_pll14xx_round_rate() returns the lowest rate by indexing into
the rate table with the variable i. i is actually pll->rate_count
as this is the value we come out of the loop with. Use pll->rate_count
explicitly to make it a bit more clear what is being done. While at
it fix a typo in the comment. No functional change.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220304125256.2125023-7-s.hauer@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Sascha Hauer [Fri, 4 Mar 2022 12:52:53 +0000 (13:52 +0100)]
clk: imx: pll14xx: name variables after usage
In clk_pll1443x_set_rate() 'tmp' is used for the content of different
registers which makes it a bit hard to follow. Use different variables
named after the registers to make it clearer. No functional change
intended.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220304125256.2125023-6-s.hauer@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Sascha Hauer [Fri, 4 Mar 2022 12:52:52 +0000 (13:52 +0100)]
clk: imx: pll14xx: consolidate rate calculation
The PLL driver has support for two different PLLs: The pll1416x and
the pll1443x. The latter has support for an additional kdiv value.
recalc_rate can be the same calculation when kdiv is assumed to be zero
for the PLL which doesn't support that value.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220304125256.2125023-5-s.hauer@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Sascha Hauer [Fri, 4 Mar 2022 12:52:51 +0000 (13:52 +0100)]
clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP
Linux has these marvelous FIELD_GET/FIELD_PREP macros for easy access
to bitfields in registers. Use them and remove the now unused *_SHIFT
defines.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220304125256.2125023-4-s.hauer@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Sascha Hauer [Fri, 4 Mar 2022 12:52:50 +0000 (13:52 +0100)]
clk: imx: pll14xx: Drop wrong shifting
The code tries to mask the bits in SDIV_MASK from 'tmp'. SDIV_MASK
already contains the shifted value, so shifting it again is wrong.
No functional change though as SDIV_SHIFT is zero.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220304125256.2125023-3-s.hauer@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Sascha Hauer [Fri, 4 Mar 2022 12:52:49 +0000 (13:52 +0100)]
clk: imx: pll14xx: Use register defines consistently
The driver has defines for the registers, but they are mostly unused.
Use the defines consistently throughout the driver. While at it rename
DIV_CTL to DIV_CTL0 because that's the name in the reference manual.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220304125256.2125023-2-s.hauer@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Peng Fan [Fri, 25 Feb 2022 08:17:33 +0000 (16:17 +0800)]
clk: imx8mp: remove SYS PLL 1/2 clock gates
Remove the PLL 1/2 gates as it make AMP clock management harder without
obvious benifit.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220225081733.2294166-4-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Peng Fan [Fri, 25 Feb 2022 08:17:32 +0000 (16:17 +0800)]
clk: imx8mn: remove SYS PLL 1/2 clock gates
Remove the PLL 1/2 gates as it make AMP clock management harder without
obvious benifit.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220225081733.2294166-3-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Peng Fan [Fri, 25 Feb 2022 08:17:31 +0000 (16:17 +0800)]
clk: imx8mm: remove SYS PLL 1/2 clock gates
Remove the PLL 1/2 gates as it make AMP clock management harder without
obvious benifit.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220225081733.2294166-2-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Peng Fan [Mon, 28 Feb 2022 02:09:08 +0000 (10:09 +0800)]
clk: imx: add i.MX93 clk
Add i.MX93 clk driver. i.MX93 clk hardware design is different compared
with i.MX8M. It supports 4 sources for each clk root and the sources
are separated into a few groups, low speed/fast io/audio and etc.
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20220228020908.2810346-6-peng.fan@oss.nxp.com
[abel.vesa@nxp.com: Added missing module license and description]
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Peng Fan [Mon, 28 Feb 2022 02:09:07 +0000 (10:09 +0800)]
clk: imx: support fracn gppll
This PLL module is a Fractional-N synthesizer,
supporting 30-bit numerator and denominator. Numerator is a signed
number. It has feature to adjust fractional portion of feedback
divider dynamically. This fracn gppll is used in i.MX93.
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20220228020908.2810346-5-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Peng Fan [Mon, 28 Feb 2022 02:09:06 +0000 (10:09 +0800)]
clk: imx: add i.MX93 composite clk
i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here
is to combine all these into one composite clk and simplify clk tree.
i.MX93 CCM is a new IP compared with i.MX8M, so introduce a new file.
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20220228020908.2810346-4-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Peng Fan [Mon, 28 Feb 2022 02:09:05 +0000 (10:09 +0800)]
dt-bindings: clock: add i.MX93 clock definition
Add i.MX93 clock definition
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20220228020908.2810346-3-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Peng Fan [Mon, 28 Feb 2022 02:09:04 +0000 (10:09 +0800)]
dt-bindings: clock: Add imx93 clock support
Add the clock dt-binding file for i.MX93.
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20220228020908.2810346-2-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Dan Carpenter [Mon, 28 Feb 2022 07:50:14 +0000 (10:50 +0300)]
clk: imx: off by one in imx_lpcg_parse_clks_from_dt()
The > needs to be >= to prevent an off by one access.
Fixes:
d5f1e6a2bb61 ("clk: imx: imx8qxp-lpcg: add parsing clocks from device tree")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220228075014.GD13685@kili
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Abel Vesa [Tue, 22 Feb 2022 08:21:40 +0000 (10:21 +0200)]
dt-bindings: fsl: scu: add imx8dxl scu clock support
Add imx8dxl scu clock support.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220222082140.2073629-1-abel.vesa@nxp.com
Abel Vesa [Thu, 27 Jan 2022 14:10:52 +0000 (16:10 +0200)]
clk: imx7d: Remove audio_mclk_root_clk
The audio_mclk_root_clk was added as a gate with the CCGR121 (0x4790),
but according to the reference manual, there is no such gate. The
CCGR121 belongs to ECSPI2 and it is not shared.
Fixes:
8f6d8094b215b57 ("ARM: imx: add imx7d clk tree support")
Reported-by: David Wolfe <david.wolfe@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20220127141052.1900174-2-abel.vesa@nxp.com
Stephen Boyd [Thu, 17 Feb 2022 22:05:54 +0000 (14:05 -0800)]
clk: Mark clk_core_evict_parent_cache_subtree() 'target' const
Clarify that the 'target' clk isn't being modified, instead it's being
searched for. Mark it const so the function can't modify it.
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220217220554.2711696-3-sboyd@kernel.org
Stephen Boyd [Thu, 17 Feb 2022 22:05:53 +0000 (14:05 -0800)]
clk: Mark 'all_lists' as const
This list array doesn't change at runtime. Mark it const to move to RO
memory.
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220217220554.2711696-2-sboyd@kernel.org
Jonathan Neuschäfer [Sat, 5 Feb 2022 10:36:13 +0000 (11:36 +0100)]
clk: pistachio: Declare mux table as const u32[]
Now that clk_register_mux_table takes a const u32 *, we can declare the
mux table as const u32[].
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220205103613.1216218-8-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonathan Neuschäfer [Sat, 5 Feb 2022 10:36:12 +0000 (11:36 +0100)]
clk: qcom: Declare mux table as const u32[]
Now that clk_register_mux_table takes a const u32 *, we can declare the
mux tables as const u32[].
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220205103613.1216218-7-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonathan Neuschäfer [Sat, 5 Feb 2022 10:36:11 +0000 (11:36 +0100)]
clk: mmp: Declare mux tables as const u32[]
Now that clk_register_mux_table takes a const u32 *, we can declare the
mux tables as const u32[].
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220205103613.1216218-6-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonathan Neuschäfer [Sat, 5 Feb 2022 10:36:10 +0000 (11:36 +0100)]
clk: hisilicon: Remove unnecessary cast of mux table to u32 *
Now that clk_register_mux_table takes a const u32 *, we don't need the
cast anymore.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220205103613.1216218-5-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonathan Neuschäfer [Sat, 5 Feb 2022 10:36:09 +0000 (11:36 +0100)]
clk: mux: Declare u32 *table parameter as const
The elements of the table are never modified in clk-mux.c. To make this
clear to clock drivers, declare the parameter as const u32 *table.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220205103613.1216218-4-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonathan Neuschäfer [Sat, 5 Feb 2022 10:36:08 +0000 (11:36 +0100)]
clk: nxp: Declare mux table parameter as const u32 *
lpc18xx_fill_parent_names's "id" parameter isn't used for writing, so
let's make it const.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220205103613.1216218-3-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonathan Neuschäfer [Sat, 5 Feb 2022 10:36:07 +0000 (11:36 +0100)]
clk: nxp: Remove unused variable
GCC warns:
> ../drivers/clk/nxp/clk-lpc18xx-cgu.c: In function ‘lpc18xx_pll1_recalc_rate’:
> ../drivers/clk/nxp/clk-lpc18xx-cgu.c:460:13: warning: variable ‘stat’ set but not used [-Wunused-but-set-variable]
> 460 | u32 stat, ctrl;
> | ^~~~
Get rid of the (apparently) useless read from the PLL1_STAT register and
the declaration of stat.
Reported-by: kernel test robot <lkp@intel.com>
Fixes:
b04e0b8fd5443 ("clk: add lpc18xx cgu clk driver")
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220205103613.1216218-2-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Quentin Schulz [Mon, 31 Jan 2022 16:32:24 +0000 (17:32 +0100)]
clk: rockchip: re-add rational best approximation algorithm to the fractional divider
In commit
4e7cf74fa3b2 ("clk: fractional-divider: Export approximation
algorithm to the CCF users"), the code handling the rational best
approximation algorithm was replaced by a call to the core
clk_fractional_divider_general_approximation function which did the same
thing back then.
However, in commit
82f53f9ee577 ("clk: fractional-divider: Introduce
POWER_OF_TWO_PS flag"), this common code was made conditional on
CLK_FRAC_DIVIDER_POWER_OF_TWO_PS flag which was not added back to the
rockchip clock driver.
This broke the ltk050h3146w-a2 MIPI DSI display present on a PX30-based
downstream board.
Let's add the flag to the fractional divider flags so that the original
and intended behavior is brought back to the rockchip clock drivers.
Fixes:
82f53f9ee577 ("clk: fractional-divider: Introduce POWER_OF_TWO_PS flag")
Cc: stable@vger.kernel.org
Cc: Quentin Schulz <foss+kernel@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Link: https://lore.kernel.org/r/20220131163224.708002-1-quentin.schulz@theobroma-systems.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Minghao Chi (CGEL ZTE) [Mon, 21 Feb 2022 02:01:03 +0000 (02:01 +0000)]
clk/rockchip: Use of_device_get_match_data()
Use of_device_get_match_data() to simplify the code.
Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Minghao Chi (CGEL ZTE) <chi.minghao@zte.com.cn>
Link: https://lore.kernel.org/r/20220221020103.1925026-1-chi.minghao@zte.com.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Geert Uytterhoeven [Mon, 21 Feb 2022 15:35:56 +0000 (16:35 +0100)]
clk: renesas: r8a779f0: Add PFC clock
Add the module clock used by the Pin Function (PFC/GPIO) controller
on the Renesas R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/4ef3d3dfe714ad75112e4886efea0b66e40a33bc.1645457502.git.geert+renesas@glider.be
Geert Uytterhoeven [Thu, 3 Feb 2022 14:34:28 +0000 (15:34 +0100)]
clk: renesas: r8a779f0: Add I2C clocks
Add the module clocks used by the I2C Bus Interfaces on the Renesas
R-Car S4-8 (R8A779F0) SoC.
Extracted from a larger patch in the BSP by LUU HOAI.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/e4dcee5f6f521dccd7ac7f2fb6c86cfe4a24d032.1643898820.git.geert+renesas@glider.be
Geert Uytterhoeven [Tue, 18 Jan 2022 17:09:01 +0000 (18:09 +0100)]
clk: renesas: r8a779f0: Add WDT clock
Add the module clock used by the RCLK Watchdog Timer (RWDT) on the
Renesas R-Car S4-8 (r8a779f0) SoC. Mark it as a critical clock, to
ensure uninterrupted watchdog operation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/8d9b280065a663f2cf31db7b21a010aa781a0af1.1642525158.git.geert+renesas@glider.be
Geert Uytterhoeven [Fri, 7 Jan 2022 14:34:36 +0000 (15:34 +0100)]
clk: renesas: r8a779f0: Fix RSW2 clock divider
According to Section 8.1.2 Figure 8.1.1 ("Block Diagram of CPG"), Note
22 ("RSW2 divider"), and Table 8.1.4d ("Lists of CPG clocks generated
from CPGMA1"), the RSwitch2 and PCI Express clock is generated from PLL5
by dividing by two, followed by the RSW2 divider. As PLL5 runs at 3200
MHz, and RSW2 is fixed to 320 MHz, the RSW2 divider must be 5.
Correct the parent and the fixed divider.
Fixes:
24aaff6a6ce4c4de ("clk: renesas: cpg-mssr: Add support for R-Car S4-8")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d6a406f31e6f02f892e0253f4e8a9a2f68fd652e.1641566003.git.geert+renesas@glider.be
Laurent Pinchart [Fri, 11 Feb 2022 09:13:11 +0000 (11:13 +0200)]
clk: imx8mp: Add missing IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clock
The IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clock derives from the
media_mipi_phy1_ref clock and is gated by the shared media clock gate.
Its identifier is defined in dt-bindings/clock/imx8mp-clock.h but its
definition is missing from the driver. Add it.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
Link: https://lore.kernel.org/r/20220211091311.28146-1-laurent.pinchart@ideasonboard.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Wang Qing [Tue, 15 Feb 2022 01:55:39 +0000 (17:55 -0800)]
clk: mvebu: use time_is_before_eq_jiffies() instead of open coding it
Use the helper function time_is_{before,after}_jiffies() to improve
code readability.
Signed-off-by: Wang Qing <wangqing@vivo.com>
Link: https://lore.kernel.org/r/1644890154-64915-3-git-send-email-wangqing@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chen-Yu Tsai [Tue, 8 Feb 2022 12:40:34 +0000 (20:40 +0800)]
clk: mediatek: Warn if clk IDs are duplicated
The Mediatek clk driver library handles duplicate clock IDs in two
different ways: either ignoring the duplicate entry, or overwriting
the old clk. Either way may cause unexpected behavior, and the latter
also causes an orphan clk that cannot be cleaned up.
Align the behavior so that later duplicate entries are ignored, and
a warning printed. The warning will also aid in making the issue
noticeable.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220208124034.414635-32-wenst@chromium.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chen-Yu Tsai [Tue, 8 Feb 2022 12:40:33 +0000 (20:40 +0800)]
clk: mediatek: mt8195: Implement remove functions
Until now the mediatek clk driver library did not have any way to
unregister clks, and so none of the drivers implemented remove
functions.
Now that the library does have APIs to unregister clks, use them
to implement remove functions for the mt8195 clk drivers.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220208124034.414635-31-wenst@chromium.org
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chen-Yu Tsai [Tue, 8 Feb 2022 12:40:32 +0000 (20:40 +0800)]
clk: mediatek: mt8195: Implement error handling in probe functions
Until now the mediatek clk driver library did not have any way to
unregister clks, and so all drivers did not do proper cleanup in
their error paths.
Now that the library does have APIs to unregister clks, use them
in the error path of the probe functions for the mt8195 clk drivers
to do proper cleanup.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220208124034.414635-30-wenst@chromium.org
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chen-Yu Tsai [Tue, 8 Feb 2022 12:40:31 +0000 (20:40 +0800)]
clk: mediatek: mt8195: Hook up mtk_clk_simple_remove()
Various small clock controllers only have clock gates, and utilize
mtk_clk_simple_probe() as their driver probe function.
Now that we have a matching remove function, hook it up for the relevant
drivers. This was done with the following command:
sed -i -e '/mtk_clk_simple_probe/a \
.remove = mtk_clk_simple_remove,' drivers/clk/mediatek/clk-mt8195-*.c
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220208124034.414635-29-wenst@chromium.org
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chen-Yu Tsai [Tue, 8 Feb 2022 12:40:30 +0000 (20:40 +0800)]
clk: mediatek: Unregister clks in mtk_clk_simple_probe() error path
Until now the mediatek clk driver library did not have any way to
unregister clks, and so all drivers did not do proper cleanup in
their error paths.
Now that the library does have APIs to unregister clks, use them
in the error path of mtk_clk_simple_probe() to do proper cleanup.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220208124034.414635-28-wenst@chromium.org
Reviewed-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chen-Yu Tsai [Tue, 8 Feb 2022 12:40:29 +0000 (20:40 +0800)]
clk: mediatek: mtk: Implement error handling in register APIs
The remaining clk registration functions do not stop or return errors
if any clk failed to be registered, nor do they implement error
handling paths. This may result in a partially working device if any
step fails.
Make the register functions return proper error codes, and bail out if
errors occur. Proper cleanup, i.e. unregister any clks that were
successfully registered, is done in the new error path.
This also makes the |struct clk_data *| argument mandatory, as it is
used to track the list of clks registered.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220208124034.414635-27-wenst@chromium.org
Reviewed-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chen-Yu Tsai [Tue, 8 Feb 2022 12:40:28 +0000 (20:40 +0800)]
clk: mediatek: pll: Implement error handling in register API
The pll clk type registration function does not stop or return errors
if any clk failed to be registered, nor does it implement an error
handling path. This may result in a partially working device if any
step failed.
Make the register function return proper error codes, and bail out if
errors occur. Proper cleanup, i.e. unregister any clks that were
successfully registered, and unmap the I/O space, is done in the new
error path.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220208124034.414635-26-wenst@chromium.org
Reviewed-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chen-Yu Tsai [Tue, 8 Feb 2022 12:40:27 +0000 (20:40 +0800)]
clk: mediatek: mux: Implement error handling in register API
The mux clk type registration function does not stop or return errors
if any clk failed to be registered, nor does it implement an error
handling path. This may result in a partially working device if any
step failed.
Make the register function return proper error codes, and bail out if
errors occur. Proper cleanup, i.e. unregister any clks that were
successfully registered, is done in the new error path.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220208124034.414635-25-wenst@chromium.org
Reviewed-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chen-Yu Tsai [Tue, 8 Feb 2022 12:40:26 +0000 (20:40 +0800)]
clk: mediatek: mux: Reverse check for existing clk to reduce nesting level
The clk registration code here currently does:
if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) {
... do clk registration ...
}
This extra level of nesting wastes screen real estate.
Reduce the nesting level by reversing the conditional shown above.
Other than that, functionality is not changed.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220208124034.414635-24-wenst@chromium.org
Reviewed-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chen-Yu Tsai [Tue, 8 Feb 2022 12:40:25 +0000 (20:40 +0800)]
clk: mediatek: gate: Implement error handling in register API
The gate clk type registration function does not stop or return errors
if any clk failed to be registered, nor does it implement an error
handling path. This may result in a partially working device if any
step failed.
Make the register function return proper error codes, and bail out if
errors occur. Proper cleanup, i.e. unregister any clks that were
successfully registered, is done in the new error path.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220208124034.414635-23-wenst@chromium.org
Reviewed-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chen-Yu Tsai [Tue, 8 Feb 2022 12:40:24 +0000 (20:40 +0800)]
clk: mediatek: cpumux: Implement error handling in register API
The cpumux clk type registration function does not stop or return errors
if any clk failed to be registered, nor does it implement an error
handling path. This may result in a partially working device if any
step failed.
Make the register function return proper error codes, and bail out if
errors occur. Proper cleanup, i.e. unregister any clks that were
successfully registered, is done in the new error path.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220208124034.414635-22-wenst@chromium.org
Reviewed-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>