Merge branch 'clk-qcom' into clk-next

* clk-qcom: (87 commits)
  clk: qcom: Fix SM_GPUCC_8450 dependencies
  clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC
  clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags
  clk: qcom: gcc-ipq5018: change some variable static
  clk: qcom: gcc-ipq4019: add missing networking resets
  dt-bindings: clock: qcom: ipq4019: add missing networking resets
  clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC
  dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC
  clk: qcom: gcc-qdu1000: Update the RCGs ops
  clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops
  clk: qcom: gcc-qdu1000: Add support for GDSCs
  clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support
  clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock
  clk: qcom: gcc-qdu1000: Fix clkref clocks handling
  clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling
  dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs
  clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs
  clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock
  clk: qcom: ipq5332: drop the mem noc clocks
  clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks
  ...

Merge branches 'clk-imx', 'clk-samsung', 'clk-annotate', 'clk-marvell' and 'clk-lmk' into clk-next

 - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc
 - Remove non-OF mmp clk drivers
 - Move number of clks from DT headers to drivers

* clk-imx:
  clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz
  clk: imx: pll14xx: align pdiv with reference manual
  clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op
  clk: imx25: make __mx25_clocks_init return void
  clk: imx25: print silicon revision during init
  dt-bindings: clocks: imx8mp: make sai4 a dummy clock
  clk: imx8mp: fix sai4 clock
  clk: imx: imx8ulp: update SPLL2 type
  clk: imx: pllv4: Fix SPLL2 MULT range
  clk: imx: imx8: add audio clock mux driver
  dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support
  clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource()
  clk: imx: clk-gpr-mux: Simplify .determine_rate()
  clk: imx: Add 519.75MHz frequency support for imx9 pll
  clk: imx93: Add PDM IPG clk
  dt-bindings: clock: imx93: Add PDM IPG clk

* clk-samsung:
  dt-bindings: clock: samsung: remove define with number of clocks
  clk: samsung: exynoautov9: do not define number of clocks in bindings
  clk: samsung: exynos850: do not define number of clocks in bindings
  clk: samsung: exynos7885: do not define number of clocks in bindings
  clk: samsung: exynos5433: do not define number of clocks in bindings
  clk: samsung: exynos5420: do not define number of clocks in bindings
  clk: samsung: exynos5410: do not define number of clocks in bindings
  clk: samsung: exynos5260: do not define number of clocks in bindings
  clk: samsung: exynos5250: do not define number of clocks in bindings
  clk: samsung: exynos4: do not define number of clocks in bindings
  clk: samsung: exynos3250: do not define number of clocks in bindings

* clk-annotate:
  clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by
  clk: Annotate struct clk_hw_onecell_data with __counted_by

* clk-marvell:
  clk: pxa910: Move number of clocks to driver source
  clk: pxa1928: Move number of clocks to driver source
  clk: pxa168: Move number of clocks to driver source
  clk: mmp2: Move number of clocks to driver source
  clk: mmp: Remove old non-OF clock drivers

* clk-lmk:
  clk: lmk04832: Support using PLL1_LD as SPI readback pin
  clk: lmk04832: Don't disable vco clock on probe fail
  clk: lmk04832: Set missing parent_names for output clocks

Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next

 - Add Versa3 clk generator to support 48KHz playback/record with audio
   codec on RZ/G2L SMARC EVK
 - Introduce kstrdup_and_replace() and use it

* clk-versa:
  clk: vc7: Use i2c_get_match_data() instead of device_get_match_data()
  clk: vc5: Use i2c_get_match_data() instead of device_get_match_data()
  clk: versaclock3: Switch to use i2c_driver's probe callback
  clk: Add support for versa3 clock driver
  dt-bindings: clock: Add Renesas versa3 clock generator bindings

* clk-strdup:
  clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace()
  clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace()
  driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace()
  lib/string_helpers: Add kstrdup_and_replace() helper

* clk-amlogic: (22 commits)
  dt-bindings: soc: amlogic: document System Control registers
  dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema
  dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema
  clk: meson: axg-audio: move bindings include to main driver
  clk: meson: meson8b: move bindings include to main driver
  clk: meson: a1: move bindings include to main driver
  clk: meson: eeclk: move bindings include to main driver
  clk: meson: aoclk: move bindings include to main driver
  dt-bindings: clk: axg-audio-clkc: expose all clock ids
  dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
  dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids
  dt-bindings: clk: meson8b-clkc: expose all clock ids
  dt-bindings: clk: g12a-aoclkc: expose all clock ids
  dt-bindings: clk: g12a-clks: expose all clock ids
  dt-bindings: clk: axg-clkc: expose all clock ids
  dt-bindings: clk: gxbb-clkc: expose all clock ids
  clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS
  clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS
  clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
  clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS
  ...

* clk-allwinner:
  clk: sunxi-ng: nkm: Prefer current parent rate
  clk: sunxi-ng: a64: select closest rate for pll-video0
  clk: sunxi-ng: div: Support finding closest rate
  clk: sunxi-ng: mux: Support finding closest rate
  clk: sunxi-ng: nkm: Support finding closest rate
  clk: sunxi-ng: nm: Support finding closest rate
  clk: sunxi-ng: Add helper function to find closest rate
  clk: sunxi-ng: Add feature to find closest rate
  clk: sunxi-ng: a64: allow pll-mipi to set parent's rate
  clk: sunxi-ng: nkm: consider alternative parent rates when determining rate
  clk: sunxi-ng: nkm: Use correct parameter name for parent HW
  clk: sunxi-ng: Modify mismatched function name
  clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource()

* clk-rockchip:
  clk: rockchip: rv1126: Add PD_VO clock tree
  clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
  clk: rockchip: rk3568: Add PLL rate for 101MHz

Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next

 - Remove OXNAS clk driver

* clk-bindings:
  dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml
  dt-bindings: clock: xlnx,versal-clk: drop select:false
  dt-bindings: clock: versal: Add versal-net compatible string
  dt-bindings: clock: ast2600: Add I3C and MAC reset definitions
  dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding

* clk-starfive:
  reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support
  clk: starfive: Simplify .determine_rate()
  clk: starfive: Add StarFive JH7110 Video-Output clock driver
  clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver
  clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
  clk: starfive: jh7110-sys: Add PLL clocks source from DTS
  clk: starfive: Add StarFive JH7110 PLL clock driver
  dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
  dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
  dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
  dt-bindings: soc: starfive: Add StarFive syscon module
  dt-bindings: clock: Add StarFive JH7110 PLL clock generator

* clk-rm:
  dt-bindings: clk: oxnas: remove obsolete bindings
  clk: oxnas: remove obsolete clock driver

* clk-renesas:
  clk: renesas: rcar-gen3: Add ADG clocks
  clk: renesas: r8a77965: Add 3DGE and ZG support
  clk: renesas: r8a7796: Add 3DGE and ZG support
  clk: renesas: r8a7795: Add 3DGE and ZG support
  clk: renesas: emev2: Remove obsolete clkdev registration
  clk: renesas: r9a07g043: Add MTU3a clock and reset entry
  clk: renesas: rzg2l: Simplify .determine_rate()
  clk: renesas: r9a09g011: Add CSI related clocks
  clk: renesas: r8a774b1: Add 3DGE and ZG support
  clk: renesas: r8a774e1: Add 3DGE and ZG support
  clk: renesas: r8a774a1: Add 3DGE and ZG support
  clk: renesas: rcar-gen3: Add support for ZG clock

* clk-cleanup:
  clk: mvebu: Convert to devm_platform_ioremap_resource()
  clk: nuvoton: Convert to devm_platform_ioremap_resource()
  clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()
  clk: ti: Use devm_platform_get_and_ioremap_resource()
  clk: mediatek: Convert to devm_platform_ioremap_resource()
  clk: hsdk-pll: Convert to devm_platform_ioremap_resource()
  clk: gemini: Convert to devm_platform_ioremap_resource()
  clk: fsl-sai: Convert to devm_platform_ioremap_resource()
  clk: bm1880: Convert to devm_platform_ioremap_resource()
  clk: axm5516: Convert to devm_platform_ioremap_resource()
  clk: actions: Convert to devm_platform_ioremap_resource()
  clk: cdce925: Remove redundant of_match_ptr()
  drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init()
  clk: Explicitly include correct DT includes

clk: qcom: Fix SM_GPUCC_8450 dependencies

CONFIG_SM_GCC_8450 depends on ARM64 but it is selected by
CONFIG_SM_GPUCC_8450, which can be selected on ARM, resulting in a
Kconfig warning.

WARNING: unmet direct dependencies detected for SM_GCC_8450
  Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n])
  Selected by [y]:
  - SM_GPUCC_8450 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y]

Add the same dependencies to CONFIG_SM_GPUCC_8450 to resolve the
warning.

Fixes: 728692d49edc ("clk: qcom: Add support for SM8450 GPUCC")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/20230829-fix-sm_gpucc_8550-deps-v1-1-d751f6cd35b2@kernel.org
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: lmk04832: Support using PLL1_LD as SPI readback pin

The PLL1_PD pin (a.k.a. STATUS_LD1) can be used as SPI readback pin. Make
this possible.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Link: https://lore.kernel.org/r/20230802064100.15793-3-mike.looijmans@topic.nl
Reviewed-by: Liam Beguin <liambeguin@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: lmk04832: Don't disable vco clock on probe fail

The probe() method never calls clk_prepare_enable(), so it should not
call clk_disable_unprepare() for the vco.clk in the error path. Fixes
a "lmk-vco already disabled" BUG when probe fails.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Link: https://lore.kernel.org/r/20230802064100.15793-2-mike.looijmans@topic.nl
Reviewed-by: Liam Beguin <liambeguin@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: lmk04832: Set missing parent_names for output clocks

lmk04832_register_clkout forgot to fill in the parent_names, resulting
in the error message "Must specify parents if num_parents > 0".

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Link: https://lore.kernel.org/r/20230802064100.15793-1-mike.looijmans@topic.nl
Reviewed-by: Liam Beguin <liambeguin@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mvebu: Convert to devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() to simplify code.

Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230705065313.67043-13-frank.li@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: nuvoton: Convert to devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() to simplify code.

Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230705065313.67043-12-frank.li@vivo.com
Acked-by: Jacky Huang <ychuang3@nuvoton.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() to simplify code.

Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230705065313.67043-11-frank.li@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: ti: Use devm_platform_get_and_ioremap_resource()

Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.

Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230705065313.67043-10-frank.li@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mediatek: Convert to devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() to simplify code.

Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230705065313.67043-9-frank.li@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: hsdk-pll: Convert to devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() to simplify code.

Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230705065313.67043-7-frank.li@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: gemini: Convert to devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() to simplify code.

Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230705065313.67043-6-frank.li@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: fsl-sai: Convert to devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() to simplify code.

Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230705065313.67043-5-frank.li@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: bm1880: Convert to devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() to simplify code.

Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230705065313.67043-4-frank.li@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: axm5516: Convert to devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() to simplify code.

Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230705065313.67043-3-frank.li@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: actions: Convert to devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() to simplify code.

Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230705065313.67043-2-frank.li@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: cdce925: Remove redundant of_match_ptr()

The driver depends on CONFIG_OF, it is not necessary to use
of_match_ptr() here.

Signed-off-by: Ruan Jinjie <ruanjinjie@huawei.com>
Link: https://lore.kernel.org/r/20230808125341.4073115-1-ruanjinjie@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: pxa910: Move number of clocks to driver source

The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.

Move this number of clocks into the driver source.

Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-4-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: pxa1928: Move number of clocks to driver source

The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.

Move this number of clocks into the driver source.

Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-3-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: pxa168: Move number of clocks to driver source

The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.

Move this number of clocks into the driver source.

Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-2-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mmp2: Move number of clocks to driver source

The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.

Move this number of clocks into the driver source.

Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-1-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mmp: Remove old non-OF clock drivers

There are no MMP2, PXA168 or PXA910 boards still using board files which
would use these drivers, so remove them.

Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20230804-drop-old-mmp-clk-v1-1-0c07db6cee90@skole.hr
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by

Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS
(for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
functions).

As found with Coccinelle[1], add __counted_by for struct spmi_pmic_div_clk_cc.

[1] https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci

Cc: Bjorn Andersson <andersson@kernel.org>
Cc: Andy Gross <agross@kernel.org>
Cc: Konrad Dybcio <konrad.dybcio@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20230817202941.never.657-kees@kernel.org
Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: Annotate struct clk_hw_onecell_data with __counted_by

Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS
(for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
functions).

As found with Coccinelle[1], add __counted_by for struct clk_hw_onecell_data.
Additionally, since the element count member must be set before accessing
the annotated flexible array member, move its initialization earlier.

[1] https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Joel Stanley <joel@jms.id.au>
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: Taichi Sugaya <sugaya.taichi@socionext.com>
Cc: Takao Orito <orito.takao@socionext.com>
Cc: Qin Jian <qinjian@cqplus1.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <andersson@kernel.org>
Cc: Konrad Dybcio <konrad.dybcio@linaro.org>
Cc: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: David Airlie <airlied@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Samuel Holland <samuel@sholland.org>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Kishon Vijay Abraham I <kishon@kernel.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-aspeed@lists.ozlabs.org
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-mediatek@lists.infradead.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-sunxi@lists.linux.dev
Cc: linux-phy@lists.infradead.org
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/20230817203019.never.795-kees@kernel.org
Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Merge tag 'qcom-clk-for-6.6' of https://git./linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - Support for the Global Clock Controller in IPQ5018 is added.
 - The SMD RPM driver is cleaned up, with interconnect bus clocks moved
   out to the interconnect drivers. Due to being tangled with the
   related interconnect updates, the topic branch with interconnect
   patches was merged in as well.
 - Various bugs in PM runtime integration is fixes across many platforms.
 - The MSM8996 core bus framework gains support for MSM8996 Pro.
 - MDM9615 is transitioned to parent_hw and parent_data, with related
   cleanups. With this the cxo proxy clock is dropped from the driver.
   And LCC support for MDM9615 is merged into the MSM8960 driver, to
   avoid duplication.
 - Network-related resets are added on IPQ4019
 - A couple of missing USB-related clocks are added for IPQ9574
 - The missing gpll0_sleep_clk_src is added to MSM8917 global clock
   controller
 - A few minor fixes for MSM8998 global clock controller.
 - In the QDU1000 global clock controller GDSCs, clkrefs, and GPLL1 are
   added, while PCIe pipe clock, SDCC rcg ops are corrected.
 - Missing GDSCs are added to SC8280XP global clock controller driver,
   flags for existing GDSCs are corrected, by enabling retention and
   dropping the always-on flags. Retention is also enabled for the
   display clock controller GDSCs.
 - SDCC apps_clk_src is marked CLK_OPS_PARENT_ENABLE to fix issues with
   missing parent clocks across sc7180, sm7150, sm6350 and sm8250, while
   sm8450 is corrected to use floor ops.
 - SM6350 GPU clock controller clock supplies are corrected.
 - Unwanted clocks from the IPQ5332 GCC are dropped.
 - The missing OXILICX GDSC is added to MSM8226 GCC.
 - The delay in the reset controller is transitioned to fsleep() to
   invoke the appropriate sleep method depending on duration.
 - The SM83550 Video clock controller is extended to support SC8280XP.

* tag 'qcom-clk-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (86 commits)
  clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC
  clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags
  clk: qcom: gcc-ipq5018: change some variable static
  clk: qcom: gcc-ipq4019: add missing networking resets
  dt-bindings: clock: qcom: ipq4019: add missing networking resets
  clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC
  dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC
  clk: qcom: gcc-qdu1000: Update the RCGs ops
  clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops
  clk: qcom: gcc-qdu1000: Add support for GDSCs
  clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support
  clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock
  clk: qcom: gcc-qdu1000: Fix clkref clocks handling
  clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling
  dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs
  clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs
  clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock
  clk: qcom: ipq5332: drop the mem noc clocks
  clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks
  clk: qcom: gpucc-msm8998: Use the correct GPLL0 leg with old DTs
  ...

clk: vc7: Use i2c_get_match_data() instead of device_get_match_data()

The device_get_match_data(), is to get match data for firmware interfaces
such as just OF/ACPI. This driver has I2C matching table as well. Use
i2c_get_match_data() to get match data for I2C, ACPI and DT-based
matching.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230721070019.96627-3-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: vc5: Use i2c_get_match_data() instead of device_get_match_data()

The device_get_match_data(), is to get match data for firmware interfaces
such as just OF/ACPI. This driver has I2C matching table as well. Use
i2c_get_match_data() to get match data for I2C, ACPI and DT-based
matching.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230721070019.96627-2-biju.das.jz@bp.renesas.com
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Merge tag 'samsung-clk-6.6' of https://git./linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung SoC clock drivers changes from Krzysztof Kozlowski:

Remove from the bindings the #defines with number of clocks supported by
each clock controller driver.  This number can vary, e.g. when we
implement more clocks in the driver.  Having the number in the bindings
prevents changing it.  Instead, this should be just a #define inside the
driver.

* tag 'samsung-clk-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  dt-bindings: clock: samsung: remove define with number of clocks
  clk: samsung: exynoautov9: do not define number of clocks in bindings
  clk: samsung: exynos850: do not define number of clocks in bindings
  clk: samsung: exynos7885: do not define number of clocks in bindings
  clk: samsung: exynos5433: do not define number of clocks in bindings
  clk: samsung: exynos5420: do not define number of clocks in bindings
  clk: samsung: exynos5410: do not define number of clocks in bindings
  clk: samsung: exynos5260: do not define number of clocks in bindings
  clk: samsung: exynos5250: do not define number of clocks in bindings
  clk: samsung: exynos4: do not define number of clocks in bindings
  clk: samsung: exynos3250: do not define number of clocks in bindings

Merge tag 'clk-imx-6.6' of git://git./linux/kernel/git/abelvesa/linux into clk-imx

Pull i.MX clk driver updates from Abel Vesa:

 - Add the PDM IPC clock for i.MX93
 - Add 519.75MHz frequency support for i.MX9 PLL
 - Simplify the .determine_rate() for GPR mux
 - Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource
 - Add the audio mux clock to i.MX8
 - Fix the SPLL2 MULT range for PLLv4
 - Update the SPLL2 type in i.MX8ULP
 - Fix the SAI4 clock on i.MX8MP
 - Add silicon revision print for i.MX25 on clocks init
 - Drop the return value from __mx25_clocks_init
 - Fix the clock pauses on no-op set_rate for i.MX8M composite clock
 - Drop restrictions for PLL14xx and fix its max prediv value
 - Drop the 393216000 and 361267200 from PLL14xx rate table to allow
   glitch free switching

* tag 'clk-imx-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
  clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz
  clk: imx: pll14xx: align pdiv with reference manual
  clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op
  clk: imx25: make __mx25_clocks_init return void
  clk: imx25: print silicon revision during init
  dt-bindings: clocks: imx8mp: make sai4 a dummy clock
  clk: imx8mp: fix sai4 clock
  clk: imx: imx8ulp: update SPLL2 type
  clk: imx: pllv4: Fix SPLL2 MULT range
  clk: imx: imx8: add audio clock mux driver
  dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support
  clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource()
  clk: imx: clk-gpr-mux: Simplify .determine_rate()
  clk: imx: Add 519.75MHz frequency support for imx9 pll
  clk: imx93: Add PDM IPG clk
  dt-bindings: clock: imx93: Add PDM IPG clk

Merge tag 'v6.6-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - PLL rates for rk3568 and the display clock tree for rv1126 which wasn't present before

* tag 'v6.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: rv1126: Add PD_VO clock tree
  clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
  clk: rockchip: rk3568: Add PLL rate for 101MHz

Merge tag 'renesas-clk-for-v6.6-tag2' of git://git./linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull another Renesas clk driver update from Geert Uytterhoeven:

 - Add Audio Clock Generator (ADG) clocks on R-Car Gen3 and RZ/G2 SoCs

* tag 'renesas-clk-for-v6.6-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rcar-gen3: Add ADG clocks

clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC

On all supported SoCs to date, the PCNoC (a.k.a CNoC_PERIPH) clock must
be always-on as long as the APSS is online and only has to run
at 19.2 MHz. Define it to be as such in the ACTIVE domain.

Some SoCs use that clock for bus scaling, while others just need it for
reaching the hardware. This commit will hurt neither.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230731-topic-pcnoc-v1-2-452dd36d11d7@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags

Some clocks, at least PCNoC (a.k.a CNoC_PERIPH) need to be always on,
at least on the ACTIVE side, regardless of whether they're used for bus
scaling or not.

Introduce a new macro to preset non-INT_MAX rates and clk flags to make
it easy and work implicitly through the CCF.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230731-topic-pcnoc-v1-1-452dd36d11d7@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: gcc-ipq5018: change some variable static

lpass_axim_clk_src and lpass_sway_clk_src are only
used in gcc-ipq5018.c now, change them to static.

Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230816080113.1222352-1-yangyingliang@huawei.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: gcc-ipq4019: add missing networking resets

IPQ4019 has more networking related resets that will be required for future
wired networking support, so lets add them.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Link: https://lore.kernel.org/r/20230814104119.96858-2-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

dt-bindings: clock: qcom: ipq4019: add missing networking resets

Add bindings for the missing networking resets found in IPQ4019 GCC.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230814104119.96858-1-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: renesas: rcar-gen3: Add ADG clocks

R-Car Sound needs to enable "ADG" on RMSTPCR9/SMSTPCR9 bit 22 to use
clk_i which came from the internal S0D4 or ZA2 clock.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Vincenzo De Michele <vincenzo.michele@davinci.de> # R-Car M3-N
Tested-by: Patrick Keil <patrick.keil@conti-engineering.com> # R-Car M3-N
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/87pm47prox.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87o7jrpros.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87mszbpron.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87leevproh.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87jzufprod.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87il9zpro8.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87h6pjpro4.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87fs53prny.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87edknprnt.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

dt-bindings: clock: samsung: remove define with number of clocks

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Remove it entirely from the bindings, once Linux drivers stopped using
them.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-12-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

clk: samsung: exynoautov9: do not define number of clocks in bindings

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-11-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

clk: samsung: exynos850: do not define number of clocks in bindings

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-10-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

clk: samsung: exynos7885: do not define number of clocks in bindings

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-9-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

clk: samsung: exynos5433: do not define number of clocks in bindings

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-8-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

clk: samsung: exynos5420: do not define number of clocks in bindings

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

clk: samsung: exynos5410: do not define number of clocks in bindings

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

clk: samsung: exynos5260: do not define number of clocks in bindings

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

clk: samsung: exynos5250: do not define number of clocks in bindings

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

clk: samsung: exynos4: do not define number of clocks in bindings

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

clk: samsung: exynos3250: do not define number of clocks in bindings

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Merge tag 'sunxi-clk-for-6.6-2' of https://git./linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver changes from Chen-Yu Tsai:

 - Parameter name correction for ccu_nkm_round_rate()
 - Implement CLK_SET_RATE_PARENT for NKM clocks, i.e. consider alternative
   parent rates when determining clock rates
 - Set CLK_SET_RATE_PARENT for A64 pll-mipi
 - Support finding closest (as opposed to closest but not higher) clock
   rate for NM, NKM, mux and div type clocks, as use it for A64
   pll-video0
 - Prefer current parent rate if able to generate ideal clock rate for
   NKM clocks

* tag 'sunxi-clk-for-6.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: nkm: Prefer current parent rate
  clk: sunxi-ng: a64: select closest rate for pll-video0
  clk: sunxi-ng: div: Support finding closest rate
  clk: sunxi-ng: mux: Support finding closest rate
  clk: sunxi-ng: nkm: Support finding closest rate
  clk: sunxi-ng: nm: Support finding closest rate
  clk: sunxi-ng: Add helper function to find closest rate
  clk: sunxi-ng: Add feature to find closest rate
  clk: sunxi-ng: a64: allow pll-mipi to set parent's rate
  clk: sunxi-ng: nkm: consider alternative parent rates when determining rate
  clk: sunxi-ng: nkm: Use correct parameter name for parent HW

clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz

Since commit b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates"),
the driver has the ability to dynamically compute PLL parameters to
approximate the requested rates. This is not always used, because the
logic is as follows:

  - Check if the target rate is hardcoded in the frequency table
  - Check if varying only kdiv is possible, so switch over is glitch free
  - Compute rate dynamically by iterating over pdiv range

If we skip the frequency table for the 1443x PLL, we find that the
computed values differ to the hardcoded ones. This can be valid if the
hardcoded values guarantee for example an earlier lock-in or if the
divisors are chosen, so that other important rates are more likely to
be reached glitch-free.

For rates (393216000 and 361267200, this doesn't seem to be the case:
They are only approximated by existing parameters (393215995 and
361267196 Hz, respectively) and they aren't reachable glitch-free from
other hardcoded frequencies. Dropping them from the table allows us
to lock-in to these frequencies exactly.

This is immediately noticeable because they are the assigned-clock-rates
for IMX8MN_AUDIO_PLL1 and IMX8MN_AUDIO_PLL2, respectively and a look
into clk_summary so far showed that they were a few Hz short of the target:

imx8mn-board:~# grep audio_pll[12]_out /sys/kernel/debug/clk/clk_summary
audio_pll2_out           0        0        0   361267196 0     0  50000   N
audio_pll1_out           1        1        0   393215995 0     0  50000   Y

and afterwards:

imx8mn-board:~# grep audio_pll[12]_out /sys/kernel/debug/clk/clk_summary
audio_pll2_out           0        0        0   361267200 0     0  50000   N
audio_pll1_out           1        1        0   393216000 0     0  50000   Y

This change is equivalent to adding following hardcoded values:

  /*               rate     mdiv  pdiv  sdiv   kdiv */
  PLL_1443X_RATE(393216000, 655,    5,    3,  23593),
  PLL_1443X_RATE(361267200, 497,   33,    0, -16882),

Fixes: 053a4ffe2988 ("clk: imx: imx8mm: fix audio pll setting")
Cc: stable@vger.kernel.org # v5.18+
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.kernel.org/r/20230807084744.1184791-2-m.felsch@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

clk: imx: pll14xx: align pdiv with reference manual

The PLL14xx hardware can be found on i.MX8M{M,N,P} SoCs and always come
with a 6-bit pre-divider. Neither the reference manuals nor the
datasheets of these SoCs do mention any restrictions. Furthermore the
current code doesn't respect the restrictions from the comment too.

Therefore drop the restriction and align the max pre-divider (pdiv)
value to 63 to get more accurate frequencies.

Fixes: b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates")
Cc: stable@vger.kernel.org
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.kernel.org/r/20230807084744.1184791-1-m.felsch@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op

Reconfiguring the clock divider to the exact same value is observed
on an i.MX8MN to often cause a longer than usual clock pause, probably
because the divider restarts counting whenever the register is rewritten.

This issue doesn't show up normally, because the clock framework will
take care to not call set_rate when the clock rate is the same.
However, when we reconfigure an upstream clock, the common code will
call set_rate with the newly calculated rate on all children, e.g.:

  - sai5 is running normally and divides Audio PLL out by 16.
  - Audio PLL rate is increased by 32Hz (glitch-free kdiv change)
  - rates for children are recalculated and rates are set recursively
  - imx8m_clk_composite_divider_set_rate(sai5) is called with
    32/16 = 2Hz more
  - imx8m_clk_composite_divider_set_rate computes same divider as before
  - divider register is written, so it restarts counting from zero and
    MCLK is briefly paused, so instead of e.g. 40ns, MCLK is low for 120ns.

Some external clock consumers can be upset by such unexpected clock pauses,
so let's make sure we only rewrite the divider value when the value to be
written is actually different.

Fixes: d3ff9728134e ("clk: imx: Add imx composite clock")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20230807082201.2332746-1-a.fatoum@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

clk: imx25: make __mx25_clocks_init return void

The __mx25_clocks_init function always returns 0 and its only
caller does not check the return value. Let's remove it.

Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20230802184046.153394-3-martin@kaiser.cx
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

clk: imx25: print silicon revision during init

Print the imx25 silicon revision when the clocks are initialised.

Use the same mechanism as for imx27, i.e. call mx25_revision.
This function is unused at the moment.

Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20230802184046.153394-2-martin@kaiser.cx
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

dt-bindings: clocks: imx8mp: make sai4 a dummy clock

The hardware don't have a SAI4 instance so remove the define. Use a
comment to keep it as reference and to avoid confusion.

Fixes: 108869144739 ("dt-bindings: imx: Add clock binding doc for i.MX8MP")
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.kernel.org/r/20230731142150.3186650-2-m.felsch@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

clk: imx8mp: fix sai4 clock

The reference manual don't mention a SAI4 hardware block. This would be
clock slice 78 which is skipped (TRM, page 237). Remove any reference to
this clock to align the driver with the reality.

Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver")
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.kernel.org/r/20230731142150.3186650-1-m.felsch@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

clk: imx: imx8ulp: update SPLL2 type

The SPLL2 on iMX8ULP is different with other frac PLLs, it can
support VCO from 650Mhz to 1Ghz. Following the changes to pllv4,
use the new type IMX_PLLV4_IMX8ULP_1GHZ.

Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230625123340.4067536-2-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

clk: imx: pllv4: Fix SPLL2 MULT range

The SPLL2 on iMX8ULP is different with other frac PLLs, it can
support VCO from 650Mhz to 1Ghz. According to RM, the MULT is
using a range from 27 to 54, not some fixed values. If using
current PLL implementation, some clock rate can't be supported.

Fix the issue by adding new type for the SPLL2 and use MULT range
to replace MULT table

Fixes: 5f0601c47c33 ("clk: imx: Update the pllv4 to support imx8ulp")
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230625123340.4067536-1-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

clk: imx: imx8: add audio clock mux driver

The Audio Clock Mux (ACM) is a collection of control registers
and multiplexers that are used to route the audio source clocks
to the audio peripherals.

Each audio peripheral has its dedicated audio clock mux
(which differ based on usage) and control register.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/1690260984-25744-3-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support

Add the clock dt-binding file for Audio Clock Mux. which
is the IP for i.MX8QM, i.MX8QXP, i.MX8DXL.

Add the clockid for clocks in header file.

The Audio Clock Mux is binded with all the audio IP and audio clocks
in the subsystem, so need to list the power domain of related clocks
and IPs. Each clock and IP has a power domain, so there are so many
power domains.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/1690260984-25744-2-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource()

Use devm_platform_ioremap_resource() to simplify code.

Signed-off-by: Yangtao Li <frank.li@vivo.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230705065313.67043-8-frank.li@vivo.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC

This is the parent clock of gpll0_early, so it needs to be enabled
for gpll0_early to return the correct rate. Enable GPLL0_SLEEP_CLK_SRC
by adding its existing definition to the clock list.

This clock also doesn't work with clk_alpha_pll_ops, use
clk_branch_simple_ops instead to make it enable and disable correctly.

Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
Link: https://lore.kernel.org/r/20230802170317.205112-3-otto.pflueger@abscue.de
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC

Add the missing #define for GPLL0_SLEEP_CLK_SRC, the parent clock of
GPLL0_EARLY.

Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230802170317.205112-2-otto.pflueger@abscue.de
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: gcc-qdu1000: Update the RCGs ops

The clock RCGs are required to be parked at safe clock source(XO)
during disable as per the hardware expectation and clk_rcg2_shared_ops
are the closest implementation for the same. Hence update the clock
RCG ops to clk_rcg2_shared_ops.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-9-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops

Update the GCC SDCC clock RCG ops to clk_rcg2_floor_ops to avoid
the overclocking issues on QDU1000 and QRU1000 SoCs.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-8-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: gcc-qdu1000: Add support for GDSCs

Add the GDSCs support for QDU1000 and QRU1000 SoCs.

Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-7-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support

Add the gcc_ddrss_ecpri_gsi_clk support as per the latest hardware
version of QDU1000 and QRU100 SoCs.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-6-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock

gcc_gpll1_out_even clock is referenced as a parent, but not registered
with the clock framework. Hence add support to register the same.

Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-5-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: gcc-qdu1000: Fix clkref clocks handling

Update the GCC clkref clock's halt_check to BRANCH_HALT, as it's
status bit is not inverted in the latest hardware version of QDU1000
and QRU1000 SoCs. While at it, fix the gcc clkref clock ops as well.

Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-4-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling

Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops
implementation to let the clock framework automatically park the clock
at XO when the clock is switched off and restore the parent when the
clock is switched on.

Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-3-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs

Add support for GCC_GPLL1_OUT_EVEN and GCC_DDRSS_ECPRI_GSI_CLK clock
bindings for QDU1000 and QRU1000 SoCs. While at it, update the
maintainers list.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-2-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs

Use the floor ops to prevent warnings like this at suspend exit and boot:

mmc0: Card appears overclocked; req 800000 Hz, actual 25000000 Hz

Fixes: db0c944ee92b ("clk: qcom: Add clock driver for SM8450")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20230811-topic-8450_clk-v1-1-88031478d548@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock

With the removal of the mem noc clocks in the commit e224dc703521 ("clk:
qcom: gcc-ipq5332: drop the mem noc clocks"), we can drop the
gcc_apss_axi_clk_src clock as well, since there are no clocks uses this
clock as a parent.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20230710102807.1189942-3-quic_kathirav@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: ipq5332: drop the mem noc clocks

Due to the recent design changes, all the mem noc clocks will be
configured by the bootloaders and it will be access protected by the TZ
firmware. So drop these clocks from the GCC driver.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20230710102807.1189942-2-quic_kathirav@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks

Some branch clocks are governed externally and we're only supposed to
send a request concerning their shutdown, not actually ensure it happens.

Use the BRANCH_HALT_SKIP define to skip checking the halt bit.

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-6-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: gpucc-msm8998: Use the correct GPLL0 leg with old DTs

GPUCC has its own GPLL0 legs - one for 1-1 and one for div-2 output.
Add .name lookup to make sure older DTs consume the correct clock.

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Tested-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-5-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: mmcc-msm8998: Properly consume GPLL0 inputs

Up until now, the GPLL0_DIV MMSS input has been modeled as a fixed
child of MMSS_GPLL0_DIV that's always-on. Properly representing the
former in the GCC driver makes us unable to keep doing so.

Consume MSS_GPLL0_DIV through fw_name ("gpll0_div") as well as add a
fixed .name link to keep backwards compatibility.

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Tested-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-4-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: gcc-msm8998: Control MMSS and GPUSS GPLL0 outputs properly

Up until now, we've been relying on some non-descript hardware magic
to pinkypromise turn the clocks on for us. While new SoCs shine with
that feature, MSM8998 can not always be fully trusted.

Register the MMSS and GPUSS GPLL0 legs with the CCF to allow for manual
enable voting.

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Tested-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-3-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

dt-bindings: clock: qcom,mmcc: Add GPLL0_DIV for MSM8998

We've not been consuming that clock for no apparent reason. Describe it.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-2-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

Merge branch '20230622-topic-8998clk-v2-1-6222fbc2916b@linaro.org' into clk-for-6.6

Merge additional MSM8998 GCC DeviceTree binding constants through a
topic branch to make them available to the DeviceTree source tree as
well.

dt-bindings: clk: qcom,gcc-msm8998: Add missing GPU/MMSS GPLL0 legs

GPLL0 has two separate outputs to both GPUSS and MMSS: one that's
2-divided and one that runs at the same rate as the GPLL0 itself.

Add the missing ones to the binding.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-1-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018

Add support for the global clock controller found on IPQ5018
based devices.

Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/1690533192-22220-3-git-send-email-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

Merge branch '1690533192-22220-2-git-send-email-quic_srichara@quicinc.com' into clk-for-6.6

Merge the IPQ5018 GCC Devicetree binding through a topic branch, in
order to the the clock defines.

dt-bindings: clock: Add IPQ5018 clock and reset

This patch adds support for the global clock controller found on
the IPQ5018 based devices.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/1690533192-22220-2-git-send-email-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

clk: rockchip: rv1126: Add PD_VO clock tree

PD_VO clock tree diagram in RV1126 is connected to
- BIU_VO
- VOP
- RGA
- IEP
- DSIHOST

Add entire PD_VO clock tree for rv1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20230731110012.2913742-3-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Merge tag 'sunxi-clk-for-6.6-1' of https://git./linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Jernej Skrabec:

 - Convert sun9i-mmc clock to use devm_platform_get_and_ioremap_resource()
 - Fix function name in a comment in ccu_mmc_timing.c

* tag 'sunxi-clk-for-6.6-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: Modify mismatched function name
  clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource()

Merge tag 'clk-meson-v6.6-1' of https://github.com/BayLibre/clk-meson into clk-amlogic

Pull Amlogic clk driver updates from Jerome Brunet:

 - dt-bindings: expose all Amlogic clock ids
 - Migrate Amlogic gxbb clock controllers dt-bindings to schema

* tag 'clk-meson-v6.6-1' of https://github.com/BayLibre/clk-meson: (22 commits)
  dt-bindings: soc: amlogic: document System Control registers
  dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema
  dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema
  clk: meson: axg-audio: move bindings include to main driver
  clk: meson: meson8b: move bindings include to main driver
  clk: meson: a1: move bindings include to main driver
  clk: meson: eeclk: move bindings include to main driver
  clk: meson: aoclk: move bindings include to main driver
  dt-bindings: clk: axg-audio-clkc: expose all clock ids
  dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids
  dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids
  dt-bindings: clk: meson8b-clkc: expose all clock ids
  dt-bindings: clk: g12a-aoclkc: expose all clock ids
  dt-bindings: clk: g12a-clks: expose all clock ids
  dt-bindings: clk: axg-clkc: expose all clock ids
  dt-bindings: clk: gxbb-clkc: expose all clock ids
  clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS
  clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS
  clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS
  clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS
  ...

clk: sunxi-ng: nkm: Prefer current parent rate

Similar to ccu_mp, if the current parent rate allows getting the ideal
rate, prefer to not change the parent clock's rate.

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-11-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

clk: sunxi-ng: a64: select closest rate for pll-video0

Selecting the closest rate for pll-video0 instead of the closest rate
that is less than the requested rate has no downside for this clock,
while allowing for selecting a more suitable rate, e.g. for the
connected panels.

Furthermore, the algorithm that sets an NKM clock's parent benefits from
the closest rate. Without it, the NKM clock's rate might drift away from
the requested rate in the multiple successive calls to
ccu_nkm_determine_rate that the clk framework performs when setting a
clock rate.

Therefore, configure pll-video0 and, in consequence, all of its
descendents to select the closest rate.

Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-10-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

clk: sunxi-ng: div: Support finding closest rate

Add initalization macros for divisor clocks with mux
(SUNXI_CCU_M_WITH_MUX) to support finding the closest rate. This clock
type requires the appropriate flags to be set in the .common structure
(for the mux part of the clock) and the .div part.

Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-9-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

clk: sunxi-ng: mux: Support finding closest rate

When finding the best rate for a mux clock, consider rates that are
higher than the requested rate when CCU_FEATURE_ROUND_CLOSEST is used.
Furthermore, introduce an initialization macro that sets this flag.

Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-8-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

clk: sunxi-ng: nkm: Support finding closest rate

When finding the best rate for a NKM clock, consider rates that are
higher than the requested rate, if the CCU_FEATURE_CLOSEST_RATE flag is
set by using the helper function ccu_is_better_rate().

Accommodate ccu_mux_helper_determine_rate to this change.

Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-7-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

clk: sunxi-ng: nm: Support finding closest rate

Use the helper function ccu_is_better_rate() to determine the rate that
is closest to the requested rate, thereby supporting rates that are
higher than the requested rate if the clock uses the
CCU_FEATURE_CLOSEST_RATE.

Add the macro SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST which
sets CCU_FEATURE_CLOSEST_RATE.

To avoid code duplication, add the macros
SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT that allows selecting
arbitrary features and use it in the original
SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX as well as the newly introduced
SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST macros.

Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-6-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

clk: sunxi-ng: Add helper function to find closest rate

The default behaviour of clocks in the sunxi-ng driver is to select a
clock rate that is closest to but less than the requested rate.

Add the ccu_is_better_rate() helper function that - depending on the
fact if thc CCU_FEATURE_CLOSEST_RATE flag is set - decides if a rate is
closer than another rate.

Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-5-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

clk: sunxi-ng: Add feature to find closest rate

The default behaviour of clocks in the sunxi-ng driver is to select a
clock rate that is closest to but less than the requested rate.

Add the CCU_FEATURE_CLOSEST_RATE flag, which can be used to allow clocks
to find the closest rate instead.

Acked-by: Maxime Ripard <mripard@kernel.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-4-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

clk: sunxi-ng: a64: allow pll-mipi to set parent's rate

The nkm clock now supports setting the parent's rate. Utilize this
option to find the optimal rate for pll-mipi.

Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-3-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

clk: sunxi-ng: nkm: consider alternative parent rates when determining rate

In case the CLK_SET_RATE_PARENT flag is set, consider using a different
parent rate when determining a new rate.

To find the best match for the requested rate, perform the following
steps for each NKM combination:
 - calculate the optimal parent rate,
 - find the best parent rate that the parent clock actually supports
 - use that parent rate to calculate the effective rate.

In case the clk does not support setting the parent rate, use the same
algorithm as before.

Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20230807-pll-mipi_set_rate_parent-v6-2-f173239a4b59@oltmanns.dev
Signed-off-by: Chen-Yu Tsai <wens@csie.org>