iris: Disable PIPE_CAP_PREFER_BACK_BUFFER_REUSE

This cap bit only affects DRI_PRIME setups.  Since iris now uses the
blitter to perform dGPU -> iGPU copies asynchronously, it's better to
always use at least two backbuffers so the 3D engine can start rendering
the next frame during the copy.

See commit d17e75285732878bc3ee8307541c1b4f09cbee7c where this change
was made for radeonsi.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13877>

iris: Use the hardware blitter for DRI PRIME blits

In a hybrid graphics setup, Mesa allocates two buffers for the window
surface.  The first is what the discrete card renders to; it lives in
VRAM and is usually tiled and possibly compressed.  The second is a
shadow copy that lives in system memory (readable by the integrated
card with the displays); it's usually linear and uncompressed.

Mesa's window system code schedules blits to update the shadow copy
when needed, typically at the end of a frame.  These can be fairly
costly when running a full-screen application at high resolutions.

We'd like to use the blitter for these copies, as it lets us perform
the copy asynchronously, letting the 3D engine race ahead and start
rendering the next frame.  If we used the 3D engine, the next frame
could not start rendering until the PRIME blit finishes, giving us
less time to draw the frame.  Fortunately, Tigerlake introduced new
blitter commands which can operate at full memory bandwidth.

DRI PRIME blits happen via the Gallium blit() hook.  We can detect that
case by looking for the PIPE_BIND_PRIME_BLIT_DST flag on the destination
resource.  This patch detects that case and calls iris_copy_region() on
IRIS_BATCH_BLITTER to handle it.  We know a priori that the blitter can
handle this operation (it's not a scaled blit, the formats match and
should not be 96bpp, there's no combined depth stencil, or other weird
edge cases).  blorp_copy() will also assert that edge cases don't occur.

Together with the next patch, this improves performance on DG1 Hybrid
scenarios by about 5-6%.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13877>

iris: Allow IRIS_BATCH_BLITTER in iris_copy_region()

This updates iris_copy_region() to support using the blitter batch.
(Future patches will actually do so; for now, we keep using render.)

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13877>

broadcom/simulator: enable multisync in the simulator

Use drmSyncobjSignal to signal out_syncobjs when a GPU job submission
ends in the simulator. With this, we can enable multisync support in the
simulator and keep the multisync approach to process fence by submitting
a serialized no-op job that adds the fence to the array of out syncobjs,
i.e.  syncobjs to be signaled in the kernel when a job completes (job
post deps).

Signed-off-by: Melissa Wen <mwen@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14768>

translate: improve sse2 32-bit unsigned -> float conversion

The existing logic would drop the low bit. Instead, let's drop the high
bit, do the conversion, and then add the fixed constant back in if the
value had the high bit set originally.

Fixes KHR-GL45.direct_state_access.vertex_arrays_attribute_format on
drivers that use this module to handle the format conversion.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14922>

rtasm: add pcmpgtd operation

This will be used shortly by the translate code. Available in SSE2.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14922>

rtasm: fix printf specifier for ptrdiff_t

In practice it's a small number, but new gcc versions complain.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emma Anholt <emma@anholt.net>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14922>

zink: ci updates

hooray

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14932>

zink: do not copy colors through floats

Copying per compoents might flush NaN values, leading to changes in the
values, so it'd be safer to copy as unsigned integers here. But in one
of the cases here we can do even better, and just copy the whole damn
union instead.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14932>

zink: Re-interpret formats when using vkCmdClearColorImage()

vkCmdClearColorImage() doesn't take a view format so it always uses the
underlying format of the image.  If there's texture views going on, we
need to manually mangle the colors into the image format.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14932>

st/mesa: only enable ARB_enhanced_layouts if there are xfb buffers

It really doesn't make sense without any xfb support. One could limp
along, but our validation does not work as-is. Doesn't seem important to
support this use-case.

This disables GL_ARB_enhanced_layouts on crocus with gen4/5.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14869>

glsl: only validate xfb_buffer values when we have enhanced layouts

XFB might not be supported, and the shader wouldn't be setting this
flag. But validation would still fail, since the number of xfb buffers
would be 0. So only validate if an xfb_buffer is set in the qualifiers.

See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5415
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14869>

glsl: simplify conditions for setting various allowed flags

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14869>

nir_to_tgsi: Add a flag for lowering fabs, and use it in r300/i915.

Saves instructions if the same fabs value is used multiple times.

i915g:
total instructions in shared programs: 397005 -> 396525 (-0.12%)
instructions in affected programs: 11061 -> 10581 (-4.34%)
LOST:   0
GAINED: 22

r300 (not r500):
total instructions in shared programs: 180286 -> 179767 (-0.29%)
instructions in affected programs: 27102 -> 26583 (-1.91%)
total temps in shared programs: 29692 -> 29638 (-0.18%)
temps in affected programs: 356 -> 302 (-15.17%)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14938>

nir: Split the flag for lowering of fabs and fneg to source modifiers.

i915 and r300 have fneg source modifier but not fabs, and doing it in NIR
can save us some backend pain.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14938>

r300: Throw a compile error instead of an assert in r300 swizzle rewrites.

I hit this on shader-db, but I really just want to get stats for unrelated
changes.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14938>

r300: Demote a compiler assert(0) to a compile failure.

This triggers in shader-db and doesn't have an obvious fix.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14938>

d3d12: Fix take_ownership semantic for constant buffers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14941>

r300: Request that nir-to-tgsi avoid generating TGSI_OPCODE_CMP.

Given that our fcsels are on float-bools, we can emit the LRP directly and
save the backend having to emit a SLT to turn the CMP src[0] into a bool.

This required passing a codegen flags struct for nir-to-tgsi.  I think
this is a good way forward for it, as the alternative I think has mostly
been adding flags to nir_shader_compiler_options (since adding
PIPE_SHADER_CAPs is an unreasonable amount of pain).

r300 shader-db:
total instructions in shared programs: 1484320 -> 1472463 (-0.80%)
instructions in affected programs: 243588 -> 231731 (-4.87%)
total temps in shared programs: 212485 -> 212143 (-0.16%)
temps in affected programs: 3845 -> 3503 (-8.89%)

Acked-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14886>

ci/lavapipe: update lvp asan results after leak fixes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14939>

lavapipe: fix sampler + sampler view leaks.

The compute sampler views are using a different method
of generation so have to be deleted explicitly.

Fixes: e94fd4cc6589 ("lavapipe: rename vallium to lavapipe")

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14939>

r300: fix transformation of abs modifiers with negate

It is being overwritten by the memset. Just set the only remaining
member RelAddr explicitly.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip.gawin@zoho.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14915>

ci: Bump VK-GL-CTS to 1.3.1.0.

The main thing is VK 1.3 testing, but also includes test bugfixes.  The
1.3 CTS required an uprev of deqp-runner to handle a new style of test
output, and that deqp-runner brings in some neat new features, too (piglit
in your deqp-runner suite, and extension list checking).

A bunch of VK tests got renamed, so I replaced panvk's custom test list
with simple include filters on the main test list.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> (panvk)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14920>

ci/broadcom: Remove unused v3dv xfails file.

It's actually in broadcom-rpi4-fails.txt.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14920>

ci/panfrost: Add a flake a few of us have run into in the last couple days.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14920>

d3d12: Allow 8bit index buffer conversions by vbuf

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Use CPU storage in TC for buffers

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Add a buffer busy callback to the bufmgr

Not all cached buffers can be mapped, so using map with do-not-wait
is a terrible heuristic. Use an explicit buffer busy callback which
is always false, since buffers are only put into the cache once they're
free.

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Actually suballocate and cache buffers

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Fix offset for buf/image copies with suballocated buffers

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Don't suballocate TBO buffers

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Fix TBOs from suballocated buffers

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Delete make_resource_writeable

This never did anything useful AFAICT since we didn't actually
suballocate buffers, and when this ended up being invoked it breaks
the ability to read back XFB data.

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Always respect offsets when mapping a bo, not just when there's a range

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Fix range calculation for suballocated buffers in d3d12_bo_unmap

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

d3d12: Fix set constant buffers

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

tc: CPU storage needs to be freed with align_free

Cc: mesa-stable
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>

panfrost: Fix Depth Source enum

As I suspected... sigh.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

panfrost: Remove unused layout enums

Folded into Valhall-specific plane descriptor enums.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

panfrost: Remove some indexed formats on Valhall

Block compressed formats like ETC2 are now indicated in the plane descriptor,
rather than the pixel format descriptor. Various other minor formats were
removed in Valhall; remove them from the XML so we don't accidentally try to use
them.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

panfrost: Update supported job types

Remove a few that no longer exist, and rename IDVS helper to Malloc Vertex. The
distinction between Malloc Vertex jobs and regular Indexed Vertex jobs is that
the hardware allocates varying buffers dynamically for Malloc Vertex jobs.
Regular IDVS and even legacy tiler jobs are also supported where desired.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

panfrost: Flesh out tiler heap descriptor

Merged with the Buffer descriptor, hence why it shares a type nibble. However,
Bifrost uses a dedicated tiler heap descriptor, and I see no benefit to merging.
So pretending it's a dedicated descriptor on Valhall too allows us to reuse the
Bifrost code with no modifications.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

panfrost: Strip % in GenXML names

A new Valhall enum will represent percentages, so allow that.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

panfrost: Flesh out Buffer descriptor

Add fields required for structured buffers.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14935>

vulkan,lavapipe: Simplify command recording code-gen

The Entrypoint class already has utilities for gettingt he parameter
list as either declarations or as comma-separated argument names for a
call.  Use that instead of hand-rolling it.  The only modification we
need to make is to add the ability to start the list somewhere other
than at the beginning.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14919>

lavapipe: ci updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14911>

zink: ci updates

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14911>

lavapipe: use util_pack_color_union() for generating clear colors

this enables clamping for packed formats (e.g., RGB10_A2UI) where color
values may exceed the width of the component

cc: mesa-stable

fixes (zink):
KHR-GL45.direct_state_access.renderbuffers_storage*

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14911>

ci/freedreno: Add another unsizedArrayLength flake.

Started appearing on Feb 1, but given that the rest of this test group
flakes, I assume it's similar.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14934>

venus: Allow usage of virtio-mmio based device

Libdrm reports bustype as DRM_BUS_PLATFORM for virtio-mmio
based device. DRM_BUS_PCI is reported only for virtio-pci based
devices. Add possibility to use devices with DRM_BUS_PLATFORM.

Signed-off-by: Andrii Pauk <Andrii.Pauk@opensynergy.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14531>

aco: optimize discard_if when WQM is not needed afterwards

Totals from 11560 (8.57% of 134913) affected shaders: (GFX10.3)
CodeSize: 12092560 -> 11997652 (-0.78%)
Instrs: 2205325 -> 2181598 (-1.08%)
Latency: 15376048 -> 15356958 (-0.12%); split: -0.12%, +0.00%
InvThroughput: 3526105 -> 3525120 (-0.03%); split: -0.03%, +0.00%
Copies: 98543 -> 87601 (-11.10%)
Branches: 16919 -> 16873 (-0.27%)
PreSGPRs: 291584 -> 291532 (-0.02%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14805>

aco: merge block_kind_uses_[demote|discard_if]

These serve the same purpose. The new name is
block_kind_uses_discard.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14805>

aco: make Preserve_WQM independent from block_kind_uses_discard_if

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14805>

aco: remove block_kind_discard

This case doesn't seem to happen in practice.
No need to micro-optimize it.

This patch merges instruction selection for discard/discard_if.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14805>

aco: emit nir_intrinsic_discard() as p_discard_if()

This simplifies the code and emits a slightly better
sequence in some cases.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14805>

mesa: align constant/uniform uploads to driver expected alignment

This fixed a problem for Zink where uniform buffer alignment varies by
GPU, e.g. 64 bytes for an RTX 2070 SUPER but 256 bytes for a GTX 1070
Ti.

Tested running Superposition on Windows 10 with Nvidia 1070 Ti with
496.13 driver.  Without the fix Superposition soft locks on its splash
screen.  With the fix Superposition runs through its benchmark.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14674>

zink: Fix MSVC RTC in zink_get_framebuffer_imageless()

The bit fields in zink_framebuffer_state cause a false positive with
MSVC's run-time checks enabled.  setting state.num_attachments in
zink_get_framebuffer_imageless().  Writing some bits of num_attachments
involves reading bits from layers and samples that haven't been
initialized.

Fixed by assigning to num_attachments earlier in the function.  Not
quite sure why that makes a difference but at a guess there's a
heuristic that considers assignment close to declaration as
initialization.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14566>

zink: export PIPE_CAP_CULL_DISTANCE_NOCOMBINE

fixes:
KHR-GL46.cull_distance.functional

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14878>

gallium: add PIPE_CAP_CULL_DISTANCE_NOCOMBINE

for drivers where separate cull distance variables are required, this
lets them avoid having to write yet another pass to undo gallium's mangling
of shader info

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14878>

anv: fix conditional render for vkCmdDrawIndirectByteCountEXT

We just forgot about conditional render for this entry point.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2be89cbd826f9a ("anv: Implement vkCmdDrawIndirectByteCountEXT")
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14891>

anv: enable ray queries

Only on platforms that support it.

v3: Split out code setting up ray query shadow buffer (Caio)
    Don't forget to setup ray query globals even when no shadow buffer
    is used (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/fs: lower ray query intrinsics

v2: Add helper for acceleration->root_node computation (Caio)

v3: Update comment on "done" bit (Caio)
    Remove progress bool value for impl function (Caio)
    Don't use nir_shader_instructions_pass to search the shader (Caio)

v4: Rename variable for if/else block (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/nir: document RT builder

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

nir/lower_shader_calls: consider relocated constants as rematerializable

After all they're constants.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/nir/rt: add more helpers for ray queries

v2: Split stack_id helper in sync/async version (Caio)
    Fixup a few bit field mistake (Caio)
    Simplify some bitfield manipulations (Caio)

v3: Remove duplicated helper (Caio)
    Simplify brw_nir_rt_set_dword_bit_at (Caio)
    Comment brw_nir_rt_query_mark_init (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/nir/rt: make RT manipulation helpers helper invocations ready

Since we need to be able to perform ray queries in helper invocations,
we need to have all the helpers properly tag their load/store
operations so that they operate in helper lanes.

v2: Switch from macros to inline functions (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/nir: document committed argument

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/fs: make trivial shader complete tracing operations with missing shaders

v2: Apply workaround only on < DG2-512-C0 & < DG2-128-B0

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/nir/rt: load bvh_level value off mem_hit structure

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel: add a new intrinsic to get the shader stage from bindless shaders

We'll use this to apply ray tracing operations in our trivial return
shader based on the stage we're in.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

nir/builder: add nir_ior_imm() helper

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/nir: use a single intel intrinsic to deal with ray traversal

In the future we'll want to reuse this intrinsic to deal with ray
queries. Ray queries will use a different global pointer and
programmatically change the control/level arguments of the trace send
instruction.

v2: Comment on barrier after sync trace instruction (Caio)
    Generalize lsc helper (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/nir: fix shader call lowering

We're replacing a generic instruction by an intel specific one, we
need to remove the previous instruction.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c5a42e401036 ("intel/fs: fix shader call lowering pass")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/fs: limit FS dispatch to SIMD16 when using ray queries

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/compiler: tracker number of ray queries in prog_data

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/fs: load more fields from BVH instance leafs

v2: Fixup mask (Caio)
    Drop old comment (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/fs: don't set allow_sample_mask for CS intrinsics

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 77486db867bd ("intel/fs: Disable sample mask predication for scratch stores")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/fs: add support for ACCESS_ENABLE_HELPER

v2: Factor out fragment shader masking on send messages (Caio)
    Update comments (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/fs: name sources for A64 opcodes

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/nir/rt: add a new number of SIMD lanes per DSS helper

v2: Add prefix brw_nir_rt (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/fs: add support for Eu/Thread/Lane id

This index will be used for accessing ray query data in memory.

v2: Drop a MOV (Caio)

v3: Rework back code emission (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/fs: rework dss_id opcode into generic opcode

We'll want different types of IDs based on topology. Let's make this
more flexible and also move the bit shifting code a layer above where
it's easier to do bitshifting operations, especially if you need to
stash things into temporary registers.

v2: Keep previous comment.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

nir: change intel dss_id intrinsic to topology_id

This will allow to reuse the same intrinsic for various topology based
ID.

v2: fix intrinsic comment (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>

intel/ds: fix compilation with perfetto

Forgot to test with perfetto...

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9da3d714b87c ("anv: add dynamic rendering traces")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5992
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Tested-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14914>

meson: add radv to meson devenv

I either rebased this out of the original PR, just failed to commit it
and then reset it.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14879>

vk/sync: add asserts for timeline semaphore count matching

spec requires that the number of timeline waits/signals matches the
base number of waits/signals if there are any timeline semaphores
being processed by the submit, so asserting here is in line with what
validation will yield

failure to match these will also hang every driver I've tested, so asserting
here potentially saves some people their desktop session

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14741>

zink: min/max blit region in coverage functions

these regions might not have the coords in the correct order, which will
cause them to fail intersection tests, resulting in clears that are never
applied

cc: mesa-stable

fixes:
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_all_buffer_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_color_and_depth_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_color_and_stencil_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_linear_filter_color_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_magnifying_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_minifying_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_missing_buffers_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_nearest_filter_color_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_negative_dimensions_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_negative_height_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_negative_width_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_scissor_blit

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14867>

zink: reject invalid draws

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14859>

zink: fix PIPE_CAP_TGSI_BALLOT export conditional

this requires VK_EXT_shader_subgroup_ballot

cc: mesa-stable

fixes (lavapipe):
KHR-GL46.shader_ballot_tests.ShaderBallotAvailability
KHR-GL46.shader_ballot_tests.ShaderBallotFunctionRead

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14858>

zink: export PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED

this is supported and has been for a while

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14858>

radeonsi/blit: relax conditions to use sdma copy for prime buffers

We don't need to check if it's imported: PIPE_BIND_DRI_PRIME is enough.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14615>

radeonsi: create prime buffers as uncached

8791e831b11 marked imported prime buffers as uncached (useful when prime
buffer is allocated by the display GPU), but they should also be created
as uncached (useful when allocated by the render GPU).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14615>

gallium: rename PIPE_BIND_DRI_PRIME

The new name PIPE_BIND_PRIME_BLIT_DST is more precise.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14615>

gallium/dri: add missing PIPE_BIND_DRI_PRIME handling

e9c3dbd0461 added PIPE_BIND_DRI_PRIME but it was only set when
importing a prime buffer.

This commit adds handling of this flag in the other codepath = the
one where the prime buffer is allocated by the render GPU.

With this change PIPE_BIND_DRI_PRIME is still only set for the
render GPU - the display GPU will never see this flag; a future
commit will rename it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14615>

ci/iris: Mark qbo tests as flakes

These appear to have some kind of race condition and usually fail,
but sometimes pass.  We had already attempted to mark them as flakes
on amly, but need to mark them as flakes on KBL+ too.

See https://gitlab.freedesktop.org/mesa/mesa/-/jobs/18522605 and
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/18527737 where these
unexpectedly passed on KBL, and also where the top-level test not
being caught by the regex led to failures.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14916>

crocus: Enable compat profile the same way as core profile

Signed-off-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11756>

iris: Add support for flushing the blitter (hackily)

To flush the blitter, we need to use MI_FLUSH_DW rather than the usual
PIPE_CONTROL we use on the 3D engine.  Most of our code is set up to
suggest flushes via PIPE_CONTROL commands, however, so we hackily just
emit MI_FLUSH_DW when they ask for any kind of PIPE_CONTROL flush.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14912>

blorp: Assert that blorp_copy() on the blitter can handle it

Safeguards against callers that don't guarantee the necessary things.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14912>

intel/genxml: Add missing MI_FLUSH_DW::Flush CCS field

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14912>

radv: fix R_02881C_PA_CL_VS_OUT_CNTL with mixed cull/clip distances

Matches radeonsi.

Seems Vulkan CTS doesn't really test cull distances. Removing
VARYING_SLOT_CULL_DIST0/VARYING_SLOT_CULL_DIST1 variables doesn't break
any of dEQP-VK.clipping.*, except for tests which read the variables in
the fragment shader.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5984
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14882>