Arnd Bergmann [Thu, 21 May 2020 20:41:15 +0000 (22:41 +0200)]
Merge tag 'ux500-dts-v5.8' of git://git./linux/kernel/git/linusw/linux-stericsson into arm/dt
Ux500 DTS updates for the v5.8 kernel series:
- Add proximity sensor and magnetometer to the Samsung Golden
devicetree.
- Add magnetometer and touchscreen to the Samsung Skomer
devicetree.
* tag 'ux500-dts-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: dts: ux500: Add touchscreen to the Skomer
ARM: dts: ux500: samsung-skomer: Add magnetometer
ARM: dts: ux500: samsung-golden: Add magnetometer
ARM: dts: ux500: samsung-golden: Add proximity sensor
Link: https://lore.kernel.org/r/CACRpkdbukO33SxAZ_yn-1N8=hq3hF5OBOtP_V0fbjRT-fAa87A@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:40:27 +0000 (22:40 +0200)]
Merge tag 'v5.7-next-dts32' of git://git./linux/kernel/git/matthias.bgg/linux into arm/dt
MT2701:
- add MUSB device to the SoC and the EVB
MT7623:
- add Mali-450 device node and bindings
- add phy to gmac2
* tag 'v5.7-next-dts32' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
arm: dts: mt2701: Add usb2 device nodes
dt-bindings: gpu: mali-utgard: add mediatek, mt7623-mali compatible
arm: dts: mt7623: add Mali-450 device node
arm: dts: mt7623: add phy-mode property for gmac2
Link: https://lore.kernel.org/r/ec17cf62-5463-9537-6618-2db9b2b5036e@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:39:46 +0000 (22:39 +0200)]
Merge tag 'socfpga_dts_update_for_v5.8' of git://git./linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA DTS updates for v5.8
- Leave the FPGA bridges disabled in base dtsi
- Add fpga2hps and fpga2sdram bridges on base Cyclone5/Arria5 dtsi
* tag 'socfpga_dts_update_for_v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridges
ARM: dts: socfgpa: set bridges status to disabled
Link: https://lore.kernel.org/r/20200515193029.11318-2-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:35:34 +0000 (22:35 +0200)]
Merge tag 'sunxi-dt-for-5.8-1' of git://git./linux/kernel/git/sunxi/linux into arm/dt
Our usual number of patches to improve the Allwinner Device Tree
support, including:
- Support for the IOMMU on the H6
- Support for cpufreq / thermal throttling on the H6
- Support for the mailbox on the A64, A83t, H3, H5 and H6
- New boards: A20-OLinuXino-LIME-eMMC
* tag 'sunxi-dt-for-5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (23 commits)
arm64: dts: allwinner: h6: Add IOMMU
arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6
arm64: dts: allwinner: h6: add voltage range to OPP table
arm64: dts: allwinner: sun50i-a64: Add missing address/size-cells
arm64: dts: allwinner: h6: Enable CPU opp tables for Pine H64
arm64: dts: allwinner: Sort Pine H64 device-tree nodes
arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3
arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1
arm64: dts: allwinner: h6: Add CPU Operating Performance Points table
arm64: dts: allwinner: h6: Add thermal trip points/cooling map
arm64: dts: allwinner: h6: Add clock to CPU cores
arm64: allwinner: h6: orangepi-lite2: Support BT+WIFI combo module
arm64: dts: allwinner: h6: orangepi: Disable OTG mode
arm64: dts: allwinner: h6: orangepi: Add gpio power supply
ARM: dts: sun8i-h2-plus-bananapi-m2-zero: Fix led polarity
arm64: dts: allwinner: h6: Add msgbox node
arm64: dts: allwinner: a64: Add msgbox node
ARM: dts: sunxi: h3/h5: Add msgbox node
ARM: dts: sunxi: a83t: Add msgbox node
ARM: dts: sun8i-h3: add opp table for mali gpu
...
Link: https://lore.kernel.org/r/cfa66bd9-f74c-4614-9ea5-9ef8546cc571.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:34:59 +0000 (22:34 +0200)]
Merge tag 'tegra-for-5.8-arm-dt' of git://git./linux/kernel/git/tegra/linux into arm/dt
ARM: tegra: Device tree changes for v5.8-rc1
This contains a bit of cleanup and CPU frequency scaling support for the
Tegra30 Beaver board.
* tag 'tegra-for-5.8-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: dts: tegra30: beaver: Add CPU Operating Performance Points
ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS
ARM: tegra: Kill off "simple-panel" compatibles
Link: https://lore.kernel.org/r/20200515145311.1580134-11-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 20:30:18 +0000 (22:30 +0200)]
Merge tag 'tegra-for-5.8-dt-bindings' of git://git./linux/kernel/git/tegra/linux into arm/dt
dt-bindings: Changes for v5.8-rc1
This adds bindings for the CSI TPG clock on Tegra210, moves various
clocks from the clock and reset controller to the PMC where their
controls really are, adds bindings for the external memory controller
and video capture controller on Tegra210, as well as CPU frequency
scaling on Tegra20 and Tegra30.
* tag 'tegra-for-5.8-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: i2c: tegra: Document Tegra210 VI I2C
dt-bindings: tegra: Add VI and CSI bindings
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
dt-bindings: memory: tegra: Add external memory controller binding for Tegra210
dt-bindings: clock: tegra: Remove PMC clock IDs
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
Link: https://lore.kernel.org/r/20200515145311.1580134-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 14:03:55 +0000 (16:03 +0200)]
Merge tag 'ti-k3-dt-for-v5.8' of git://git./linux/kernel/git/kristo/linux into arm/dt
Texas Instruments K3 SoC DT updates for v5.8
- Add DSS support for both AM65x and J721e
- Add watchdog support for J721e
- Add EHRPWM support for AM65x
- Add Thermal support for AM65x
* tag 'ti-k3-dt-for-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
arm64: dts: ti: k3-j721e-main: Add main domain watchdog entries
arm64: dts: ti: k3-am65-main: Add ehrpwm nodes
arm64: dts: ti: am654: Add thermal zones
arm64: dts: ti: am65-wakeup: Add VTM node
arm64: dts: ti: k3-j721e-common-proc-board: add assigned clks for DSS
arm64: dts: ti: k3-j721e-main: Add DSS node
arm64: dts: ti: am654: Add DSS node
Link: https://lore.kernel.org/r/7484d3c9-323f-36a3-f0df-1287586f356d@ti.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 14:03:21 +0000 (16:03 +0200)]
Merge tag 'renesas-dt-bindings-for-v5.8-tag2' of git://git./linux/kernel/git/geert/renesas-devel into arm/dt
Renesas DT binding updates for v5.8 (take two)
- Document support for the RZ/G1H-based iWave RainboW Qseven SOM
(G21M) and board (G21D).
* tag 'renesas-dt-bindings-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: arm: renesas: Document iW-RainboW-G21D-Qseven-RZG1H board
dt-bindings: arm: renesas: Document iW-RainboW-G21M-Qseven-RZG1H SoM
Link: https://lore.kernel.org/r/20200515100547.14671-6-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 14:02:11 +0000 (16:02 +0200)]
Merge tag 'renesas-arm-dt-for-v5.8-tag2' of git://git./linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.8 (take two)
- Initial support for the Renesas RZ/G1H SoC on the iWave RainboW
Qseven SOM (G21M) and board (G21D),
- Support for the AISTARVISION MIPI Adapter V2.1 camera board on the
Silicon Linux EK874 RZ/G2E evaluation kit.
* tag 'renesas-arm-dt-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: r8a774c0-cat874: Add support for AISTARVISION MIPI Adapter V2.1
ARM: dts: r8a7742: Add GPIO nodes
ARM: dts: r8a7742: Add [H]SCIF{A|B} support
ARM: dts: r8a7742: Add IRQC support
ARM: dts: r8a7742-iwg21d-q7: Add iWave G21D-Q7 board based on RZ/G1H
ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM
ARM: dts: r8a7742: Initial SoC device tree
clk: renesas: Add r8a7742 CPG Core Clock Definitions
dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
Link: https://lore.kernel.org/r/20200515100547.14671-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 14:00:46 +0000 (16:00 +0200)]
Merge tag 'stm32-dt-for-v5.8-1' of git://git./linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT updates for v5.8, round 1
Highlights:
----------
MCU part:
-fix a typo for DAC io-channel-cells on f429 and h743
MPU part:
-Generic:
-Bump tp PSCI 1.0
-Fix a typo for DAC io-channel-cells
-Add M4 pdds for deep sleep mode
-Add I2C fatmode plus support
-Add new Octavio lxa-mc1 board based on OSDMP15x SiP
-Add new Stinger96 board support. It is a 96Boards IoT Extended board
based on stm32mp157a SoC. Some figures: 256MB DDR, 125MB and flash,
Onboard BG96 modem...
-Add IoT Box board support based on stinger96 board + Wifi/BT, CCS811
VOC sensor, 2 digitals microphones ...
-DH:
-Adapt dhcom-som and dhcom-pdk2 dts(i) files to STM32MP15 SoC diversity
-Add GPIO led and GPIO keys support on PDK2 board
-AV96:
-Major rework to support official avenger96 board based on DHCOR SOM.
-Prototype board is no more supported
* tag 'stm32-dt-for-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (58 commits)
ARM: dts: stm32: Split Avenger96 into DHCOR SoM and Avenger96 board
ARM: dts: stm32: Split SoC-independent parts of DHCOM SOM and PDK2
ARM: dts: stm32: Add GPIO LEDs for STM32MP1 DHCOM PDK2
ARM: dts: stm32: Add GPIO keys for STM32MP1 DHCOM PDK2
ARM: dts: stm32: Add IoT Box board support
dt-bindings: arm: stm32: Document IoT Box compatible
ARM: dts: stm32: Add Stinger96 board support
dt-bindings: arm: stm32: Document Stinger96 compatible
ARM: dts: stm32: Add missing pinctrl entries for STM32MP15
dt-bindings: Add vendor prefix for Shiratech Solutions
ARM: dts: stm32: Add bindings for SPI2 on AV96
ARM: dts: stm32: Add alternate pinmux for SPI2 pins
ARM: dts: stm32: Add bindings for ADC on AV96
ARM: dts: stm32: Add alternate pinmux for ADC pins
ARM: dts: stm32: Add bindings for FDCAN2 on AV96
ARM: dts: stm32: Add alternate pinmux for FDCAN2 pins
ARM: dts: stm32: Add bindings for FDCAN1 on AV96
ARM: dts: stm32: Add alternate pinmux for FDCAN1 pins
ARM: dts: stm32: Repair I2C2 operation on AV96
ARM: dts: stm32: Add alternate pinmux for I2C2 pins
...
Link: https://lore.kernel.org/r/19160355-364d-170c-7ae2-5ba7f714103f@st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 13:51:39 +0000 (15:51 +0200)]
Merge tag 'samsung-dt-5.8' of git://git./linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM changes for v5.8
1. Add DTS for Exynos4210-based Samsung Galaxy S2 (GT-I9100)
mobile phone,
2. Enable WiFi and Bluetooth in multiple boards,
3. Add new features to S5Pv210-based Aries family of mobile phones
(e.g. Samsung Galaxy S): necessary configuration for suspend, audio
support, USB mux, touch keys, panel, i2c-gpio adapters, FM radio, ADC,
4. Many minor fixes (e.g. GPIO polarity, interrupts).
* tag 'samsung-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (29 commits)
ARM: dts: s5pv210: Set MAX8998 GPIO pulls on Aries boards
ARM: dts: s5pv210: Correct FIMC definitions
ARM: dts: s5pv210: Assign clocks to MMC devices on Aries boards
ARM: dts: s5pv210: Enable ADC on Aries boards
ARM: dts: s5pv210: Add an ADC node
ARM: dts: s5pv210: Disable pull for vibrator enable GPIO on Aries boards
ARM: dts: s5pv210: Add si470x FM radio to Galaxy S
ARM: dts: s5pv210: Add remaining i2c-gpio adapters to Aries boards
ARM: dts: s5pv210: Add panel support to Aries boards
ARM: dts: s5pv210: Add touchkey support to Aries boards
ARM: dts: s5pv210: Add FSA9480 support to Aries boards
ARM: dts: s5pv210: Add WM8994 support to Aries boards
ARM: dts: s5pv210: Disable pulls on GPIO I2C adapters for Aries
ARM: dts: s5pv210: Set keep-power-in-suspend for SDHCI1 on Aries
ARM: dts: s5pv210: Correct gpi pinctrl node name
ARM: dts: s5pv210: Add sleep GPIO configuration for Galaxy S
ARM: dts: s5pv210: Add sleep GPIO configuration for Fascinate4G
ARM: dts: s5pv210: Add helper define for sleep gpio config
ARM: dts: exynos: Enable WLAN support for the UniversalC210 board
ARM: dts: exynos: Enable WLAN support for the Rinato board
...
Link: https://lore.kernel.org/r/20200512122922.5700-2-krzk@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 13:45:59 +0000 (15:45 +0200)]
Merge tag 'arm-soc/for-5.8/devicetree' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contains Broadcom ARM-based SoCs Device Tree changes
for v5.8, please pull the following:
- Nicolas updates the Raspberry Pi 4 board DTS to include the GPIO
controlling power to the SD card, adds support for the vmmc regulator
for the emmc2 controller and finally updates the power management
provider for V3D to use the firmware to solve instabilities.
* tag 'arm-soc/for-5.8/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: bcm283x: Use firmware PM driver for V3D
ARM: dts: bcm2711: Add vmmc regulator in emmc2
ARM: dts: bcm2711: Update expgpio's GPIO labels
Link: https://lore.kernel.org/r/20200511210522.28243-2-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 13:43:45 +0000 (15:43 +0200)]
Merge tag 'hisi-arm64-dt-for-5.8' of git://github.com/hisilicon/linux-hisi into arm/dt
ARM64: DT: Hisilicon SoCs DT updates for 5.8
- Add pinconf for spi2 and spi3 nodes and increase the drive
strength to achieve the max speed for the Hikey960 board
- Add CTI nodes for the Hikey620 board
* tag 'hisi-arm64-dt-for-5.8' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hi6220: Add CTI options
arm64: dts: hikey960: pinctrl: Fix spi2/spi3 pinconf
Link: https://lore.kernel.org/r/5EBE430E.6090508@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 10:34:22 +0000 (12:34 +0200)]
Merge tag 'realtek-dt-for-5.8' of git://git./linux/kernel/git/afaerber/linux-realtek into arm/dt
Realtek Arm based SoC DT for v5.8
Add RTD1195, RTD1395 and RTD1619 SoCs as well as Xnano X5 TV box.
Clean up memory nodes and /soc ranges. Factor out r-bus and partition it
into CRT, Iso, Misc, SB2 and SCPU Wrapper blocks.
* tag 'realtek-dt-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-realtek: (35 commits)
dt-bindings: reset: rtd1295: Add SB2 reset
arm64: dts: realtek: rtd16xx: Add SB2 and SCPU Wrapper syscon nodes
arm64: dts: realtek: rtd139x: Add SB2 and SCPU Wrapper syscon nodes
arm64: dts: realtek: rtd129x: Add SB2 and SCPU Wrapper syscon nodes
ARM: dts: rtd1195: Add SB2 and SCPU Wrapper syscon nodes
arm64: dts: realtek: rtd16xx: Add CRT syscon node
ARM: dts: rtd1195: Add UART resets
ARM: dts: rtd1195: Add reset nodes
dt-bindings: reset: Add Realtek RTD1195
ARM: dts: rtd1195: Add CRT syscon node
arm64: dts: realtek: rtd16xx: Introduce iso and misc syscon
arm64: dts: realtek: rtd139x: Introduce CRT, iso and misc syscon
arm64: dts: realtek: rtd129x: Introduce CRT, iso and misc syscon
ARM: dts: rtd1195: Introduce iso and misc syscon
arm64: dts: realtek: rtd1295: Add Xnano X5
dt-bindings: arm: realtek: Add Xnano X5
dt-bindings: vendor-prefixes: Add Xnano
arm64: dts: realtek: rtd16xx: Add memory reservations
arm64: dts: realtek: rtd16xx: Carve out boot ROM from memory
arm64: dts: realtek: Add RTD1619 SoC and Realtek Mjolnir EVB
...
Link: https://lore.kernel.org/r/20200510232158.18477-2-afaerber@suse.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 10:19:04 +0000 (12:19 +0200)]
Merge tag 'aspeed-5.8-devicetree' of git://git./linux/kernel/git/joel/aspeed into arm/dt
ASPEED device tree updates for 5.8
New machines:
- YADRO's ast2500 OpenPower P9 Nicole BMC
- Facebook's ast2500 x86 Yosemite V2 BMC
The AST2600 machines Rainier and Tacoma were fleshed out.
Machines have started describing the GPIO names as userspace attempts
to use the GPIO chardev API.
* tag 'aspeed-5.8-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed: (32 commits)
ARM: dts: aspeed: Change KCS nodes to v2 binding
ARM: dts: Aspeed: AST2600: Add XDMA PCI-E root control reset
ARM: dts: aspeed: ast2600: Add XDMA Engine
ARM: dts: aspeed: ast2500: Add XDMA Engine
ARM: dts: aspeed: Adding Facebook Yosemite V2 BMC
ARM: dts: aspeed: Add YADRO Nicole BMC
ARM: dts: aspeed: mihawk: add aliases for i2c
ARM: dts: aspeed: tacoma: Add TPM
ARM: dts: aspeed: tacoma: Enable the second VUART
ARM: dts: aspeed: tacoma: Add iio-hwmon nodes for IIO devices
ARM: dts: aspeed: rainier: Add VGA reserved memory region
ARM: dts: aspeed: rainier: Add gpio line names
ARM: dts: aspeed: tacoma: Add gpio line names
ARM: dts: aspeed: zaius: Add gpio line names
ARM: dts: aspeed: romulus: Add gpio line names
ARM: dts: aspeed: witherspoon: Add gpio line names
ARM: dts: aspeed: ast2600: Set arch timer always-on
ARM: dts: aspeed: tacoma: Add GPIOs for FSI
ARM: dts: aspeed: mihawk: Change the name of leds
ARM: dts: aspeed: rainier: Remove regulators
...
Link: https://lore.kernel.org/r/CACPK8Xd-=XFREvvS-mK_ECyn14y0GPAMyy5BpEEUYfaw4jAgsw@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 10:03:23 +0000 (12:03 +0200)]
Merge tag 'omap-for-v5.8/dt-signed' of git://git./linux/kernel/git/tmlind/linux-omap into arm/dt
DTS changes for omaps for v5.8 merge window
We add support for beaglebone-ai board that's am5729 based devices.
Then we have a series changes to configure more hardware acceletators found
on omap variants. With the recent ti-sysc related changes, we can now better
configure the accelerators with help of the clock framework and reset driver.
So with a series of changes from Suman Anna and Tero Kristo, let's configure
IPUs and DSPs for dra7 devices like beagle-x15. And let's also configure the
missing crypto accelerators for omap5 as those have been missing.
Note that there are still some pending driver related patches to use IPU and
DSP related features with mainline kernel, but those are independent of the
devicetree changes.
Then there is a display related change for am57xx-idk for tc358778 bridge,
and a change to configure the missing clock source for some PWM timers.
* tag 'omap-for-v5.8/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (26 commits)
ARM: OMAP5: Make L4SEC clock domain SWSUP only
ARM: OMAP4: Make L4SEC clock domain SWSUP only
ARM: dts: omap5: add DES crypto accelerator node
ARM: dts: omap5: add SHA crypto accelerator node
ARM: dts: omap5: add aes2 entry
ARM: dts: omap5: add aes1 entry
ARM: dts: dra7-ipu-dsp-common: Add watchdog timers to IPU and DSP nodes
ARM: dts: am571x-idk: Add CMA pools and enable IPUs & DSP1 rprocs
ARM: dts: am572x-idk-common: Add CMA pools and enable IPU & DSP rprocs
ARM: dts: beagle-x15-common: Add CMA pools and enable IPU & DSP rprocs
ARM: dts: dra76-evm: Add CMA pools and enable IPU & DSP rprocs
ARM: dts: dra71-evm: Add CMA pools and enable IPUs & DSP1 rprocs
ARM: dts: dra72-evm-revc: Add CMA pools and enable IPUs & DSP1 rprocs
ARM: dts: dra72-evm: Add CMA pools and enable IPUs & DSP1 rprocs
ARM: dts: dra7-evm: Add CMA pools and enable IPU & DSP rprocs
ARM: dts: dra7-ipu-dsp-common: Add timers to IPU and DSP nodes
ARM: dts: dra7-ipu-dsp-common: Add mailboxes to IPU and DSP nodes
ARM: dts: dra7-ipu-dsp-common: Move mailboxes into common files
ARM: dts: DRA72x: Add aliases for rproc nodes
ARM: dts: DRA74x: Add aliases for rproc nodes
...
Link: https://lore.kernel.org/r/pull-1588873628-477615@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 09:55:28 +0000 (11:55 +0200)]
Merge tag 'renesas-dt-bindings-for-v5.8-tag1' of git://git./linux/kernel/git/geert/renesas-devel into arm/dt
Renesas DT binding updates for v5.8
- Document System Controller (SYSC) and Reset (RST) support for
RZ/G1H.
* tag 'renesas-dt-bindings-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: reset: rcar-rst: Document r8a7742 reset module
dt-bindings: power: rcar-sysc: Document r8a7742 SYSC binding
Link: https://lore.kernel.org/r/20200430084849.1457-6-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 09:54:41 +0000 (11:54 +0200)]
Merge tag 'renesas-arm-dt-for-v5.8-tag1' of git://git./linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.8
- USB, UART, PWM, and PCIe support for R-Car M3-W+,
- PWM (16-bit Timer Pulse Unit and PWM Timers) support for R-Car M2-W,
- Minor fixes and cleanups.
* tag 'renesas-arm-dt-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: Fix IOMMU device node names
ARM: dts: renesas: Fix IOMMU device node names
ARM: dts: shmobile: Update CMT1 compatible values
ARM: dts: r8a7791: Add PWM device nodes
ARM: dts: r8a7791: Add TPU device node
arm64: dts: renesas: r8a77961: Add PCIe device nodes
arm64: dts: renesas: r8a77961: Add PWM device nodes
arm64: dts: renesas: r8a77961: Add SCIF and HSCIF nodes
arm64: dts: renesas: r8a77961: Add USB3.0 device nodes
arm64: dts: renesas: r8a77961: Add USB2.0 device nodes
Link: https://lore.kernel.org/r/20200430084849.1457-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 09:53:19 +0000 (11:53 +0200)]
Merge tag 'versatile-dts-v5.8-1' of git://git./linux/kernel/git/linusw/linux-integrator into arm/dt
Versatile DTS updates for the v5.8 kernel:
Create a new device tree for the Integrator/AP with the
IM-PD1 expansion module fitted in the first slot.
If we want to augment the slot where it is sitting, we can
alter the device tree or make the bootloader do so.
* tag 'versatile-dts-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: dts: Add devicetree for Integrator/AP with IM-PD1
Link: https://lore.kernel.org/r/CACRpkdZ-28o+pPdP7i_fc+7g4ndPWf+SWTsjnhFEegTggiXVSg@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 21 May 2020 09:51:28 +0000 (11:51 +0200)]
Merge tag 'sti-dt-for-v5.8-round1' of git://git./linux/kernel/git/pchotard/sti into arm/dt
STi DT fixes:
- Remove duplicated rng node in stih407-family.dtsi
- Fix complain about IRQ_TYPE_NONE usage in stih418.dtsi
* tag 'sti-dt-for-v5.8-round1' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
dts: arm: stih407-family: remove duplicated rng nodes
dts: arm: stih418: Fix complain about IRQ_TYPE_NONE usage
Link: https://lore.kernel.org/r/4b0c02e7-a247-50c0-d729-88d16b9dd7fd@st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Chunyan Zhang [Tue, 14 Apr 2020 10:16:36 +0000 (18:16 +0800)]
arm64: dts: Add SC9863A emmc and sd card nodes
Add emmc and sd card devicetree nodes for SC9863A.
Link: https://lore.kernel.org/r/20200414101636.24503-3-zhang.lyra@gmail.com
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Chunyan Zhang [Tue, 14 Apr 2020 10:16:35 +0000 (18:16 +0800)]
arm64: dts: Add SC9863A clock nodes
add clock devicetree nodes for SC9863A.
Link: https://lore.kernel.org/r/20200414101636.24503-2-zhang.lyra@gmail.com
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Linus Walleij [Sat, 16 May 2020 21:29:13 +0000 (23:29 +0200)]
ARM: dts: ux500: Add touchscreen to the Skomer
This adds touchscreen support to the Ux500 Samsung
GT-S7710 "Skomer" mobile phone.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20200516212913.485365-1-linus.walleij@linaro.org
Min Guo [Wed, 11 Dec 2019 01:54:42 +0000 (09:54 +0800)]
arm: dts: mt2701: Add usb2 device nodes
Add musb nodes and usb2 phy nodes for MT2701
Signed-off-by: Min Guo <min.guo@mediatek.com>
Link: https://lore.kernel.org/r/20191211015446.11477-3-min.guo@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Sean Wang [Wed, 24 Jul 2019 09:01:00 +0000 (17:01 +0800)]
dt-bindings: gpu: mali-utgard: add mediatek, mt7623-mali compatible
The MediaTek MT7623 SoC contains a Mali-450, so add a compatible for it
and define its own vendor-specific properties.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/efeadefe3895bcadf1d2e9847b82206dd8c7ec35.1563867856.git.ryder.lee@mediatek.com
[mb: move to yaml file]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Ryder Lee [Wed, 24 Jul 2019 09:00:59 +0000 (17:00 +0800)]
arm: dts: mt7623: add Mali-450 device node
Add a node for Mali-450.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Link: https://lore.kernel.org/r/af7b5a2e00eb3a4b6262807c378e43afd5f74779.1563867856.git.ryder.lee@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Lad Prabhakar [Sun, 3 May 2020 21:46:52 +0000 (22:46 +0100)]
dt-bindings: arm: renesas: Document iW-RainboW-G21D-Qseven-RZG1H board
Document the iW-RainboW-G21D-Qseven-RZG1H device tree bindings,
listing it as a supported board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1588542414-14826-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Sun, 3 May 2020 21:46:51 +0000 (22:46 +0100)]
dt-bindings: arm: renesas: Document iW-RainboW-G21M-Qseven-RZG1H SoM
Document the iW-RainboW-G21M-Qseven-RZG1H device tree bindings,
listing it as a supported system on module.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1588542414-14826-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Maxime Ripard [Sun, 12 Jan 2020 07:51:46 +0000 (08:51 +0100)]
arm64: dts: allwinner: h6: Add IOMMU
Now that we have a driver for the IOMMU, let's start using it.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Marek Vasut [Wed, 13 May 2020 18:10:20 +0000 (20:10 +0200)]
ARM: dts: stm32: Split Avenger96 into DHCOR SoM and Avenger96 board
The Avenger96 is in fact an assembly of DH Electronics DHCOR SoM on top
of an Avenger96 reference board. The DHCOR SoM can be populated with any
STM32MP15xx. Split the DTs to reflect this such that the common SoM and
Avenger96 parts are now in stm32mp15xx-dhcor-*dtsi and a specific example
implementation of STM32MP157A SoM and Avenger96 board is separated into
stm32mp157a-dhcor-*dts* . The stm32mp157a-avenger96.dts is retained for
the sake of backward naming compatibility.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 13 May 2020 18:10:19 +0000 (20:10 +0200)]
ARM: dts: stm32: Split SoC-independent parts of DHCOM SOM and PDK2
The DH Electronics PDK2 can be populated with SoM with any STM32MP15xx
variant. Split the SoC-independent parts of the SoM and PDK2 into the
stm32mp15xx-dhcom-*.dtsi and reduce stm32mp157c-dhcom-*dts* to example
of adding STM32MP157C variant of the SoM into a PDK2 carrier board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 13 May 2020 18:10:18 +0000 (20:10 +0200)]
ARM: dts: stm32: Add GPIO LEDs for STM32MP1 DHCOM PDK2
Add bindings for the four GPIO LEDs on DH PDK2 board. Note that LED5
GPIO-E may conflict with touchscreen interrupt, hence LED5 must be
disabled when using the DH 560-200 display unit with touchscreen.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 13 May 2020 18:10:17 +0000 (20:10 +0200)]
ARM: dts: stm32: Add GPIO keys for STM32MP1 DHCOM PDK2
Add bindings for the four GPIO keys on DH PDK2 board. Note that TA1
key is polled because it's IRQ line conflicts with ethernet IRQ, the
rest of the GPIO keys, TA2, TA3, TA4, are interrupt-driven and wake
up sources.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Manivannan Sadhasivam [Sun, 3 May 2020 15:42:15 +0000 (21:12 +0530)]
ARM: dts: stm32: Add IoT Box board support
IoT Box is an IoT gateway device based on Stinger96 board powered by
STM32MP1 SoC, designed and manufactured by Shiratech Solutions. This
device makes use of Stinger96 board by having it as a base board with
one additional mezzanine on top.
Following are the features exposed by this device in addition to the
Stinger96 board:
* WiFi/BT
* CCS811 VOC sensor
* 2x Digital microphones IM69D130
* 12x WS2812B LEDs
Following peripherals are tested and known to work:
* WiFi/BT
* CCS811
More information about this device can be found in Shiratech website:
https://www.shiratech-solutions.com/products/iot-box/
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Manivannan Sadhasivam [Sun, 3 May 2020 15:42:14 +0000 (21:12 +0530)]
dt-bindings: arm: stm32: Document IoT Box compatible
Document devicetree compatible of Shiratech IoT Box.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Manivannan Sadhasivam [Sun, 3 May 2020 15:42:13 +0000 (21:12 +0530)]
ARM: dts: stm32: Add Stinger96 board support
Stinger96 is a 96Boards IoT Extended edition board designed and
manufactured by Shiratech solutions based on STM32MP1 SoC. Following
are the features of this board:
* 256MB DDR
* 125MB NAND Flash
* Onboard BG96 modem
* 1x uSD
* 2x USB (1 available as external connector and another connected to BG96)
* 1x SPI
* 1x PCM
* 2x UART (apart from serial console)
* 2x I2C (apart from one connected to PMIC)
Following peripherals are tested and known to work:
* BG96 modem
* 1x I2C (LS-I2C0)
* 1x SPI
* 1x UART (LS-UART0)
* USB (Only Gadget mode)
* uSD
More information about this board can be found in Shiratech website:
https://www.shiratech-solutions.com/products/stinger96/
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Manivannan Sadhasivam [Sun, 3 May 2020 15:42:12 +0000 (21:12 +0530)]
dt-bindings: arm: stm32: Document Stinger96 compatible
Document devicetree compatible of Shiratech Stinger96 board.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Manivannan Sadhasivam [Sun, 3 May 2020 15:42:11 +0000 (21:12 +0530)]
ARM: dts: stm32: Add missing pinctrl entries for STM32MP15
These pinctrl definitions will be used by Stinger96/IoTBox boards
from Shiratech.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Manivannan Sadhasivam [Sun, 3 May 2020 15:42:10 +0000 (21:12 +0530)]
dt-bindings: Add vendor prefix for Shiratech Solutions
This commit adds devicetree vendor prefix for Shiratech solutions,
a SOM/embedded board manufacturing company.
https://www.shiratech-solutions.com/
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Clément Péron [Fri, 8 May 2020 19:10:35 +0000 (21:10 +0200)]
arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6
Enable CPU opp tables for Tanix TX6.
Also add the fixed regulator that provided vdd-cpu-gpu required for
CPU opp tables.
This voltage has been found using a voltmeter and could be wrong.
Tested-by: Jernej Škrabec <jernej.skrabec@gmail.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Clément Péron [Fri, 8 May 2020 19:10:34 +0000 (21:10 +0200)]
arm64: dts: allwinner: h6: add voltage range to OPP table
Some boards have a fixed regulator and can't reach the voltage set
by the OPP table.
Add a range where the minimal voltage is the target and the maximal
voltage is 1.2V.
Suggested-by: Ondřej Jirman <megous@megous.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Thierry Reding [Fri, 7 Jun 2019 13:58:34 +0000 (15:58 +0200)]
dt-bindings: i2c: tegra: Document Tegra210 VI I2C
The Tegra210 features an instance of the Tegra I2C controller that is
part of the host1x domain and typically used for camera use-cases. It
uses pretty much the same programming model but the registers are laid
out differently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Sowjanya Komatineni [Tue, 5 May 2020 02:31:56 +0000 (19:31 -0700)]
dt-bindings: tegra: Add VI and CSI bindings
Tegra contains VI controller which can support up to 6 MIPI CSI
camera sensors.
Each Tegra CSI port from CSI unit can be one-to-one mapper to
VI channel and can capture from an external camera sensor or
from built-in test pattern generator.
This patch adds dt-bindings for Tegra VI and CSI.
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Thu, 19 Mar 2020 19:02:25 +0000 (22:02 +0300)]
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
Add device-tree binding that describes CPU frequency-scaling hardware
found on NVIDIA Tegra20/30 SoCs.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Joseph Lo [Wed, 29 May 2019 08:21:32 +0000 (16:21 +0800)]
dt-bindings: memory: tegra: Add external memory controller binding for Tegra210
Add the binding document for the external memory controller (EMC) which
communicates with external LPDDR4 devices. It includes the bindings of
the EMC node and a sub-node of EMC table which under the reserved memory
node. The EMC table contains the data of the rates that EMC supported.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Sowjanya Komatineni [Tue, 14 Jan 2020 07:24:26 +0000 (23:24 -0800)]
dt-bindings: clock: tegra: Remove PMC clock IDs
clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so
these clocks should be provided by the Tegra PMC. IDs for these clocks
have been defined in dt-bindings/soc/tegra-pmc.h.
This patch removes the IDs for these clocks from the Tegra clock device
tree bindings.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Sowjanya Komatineni [Tue, 5 May 2020 02:31:54 +0000 (19:31 -0700)]
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
Tegra210 uses PLLD out internally for CSI TPG. This patch adds a clock
ID for this CSI TPG clock from PLLD.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Lad Prabhakar [Mon, 20 Apr 2020 15:49:54 +0000 (16:49 +0100)]
arm64: dts: renesas: r8a774c0-cat874: Add support for AISTARVISION MIPI Adapter V2.1
This patch adds support for AISTARVISION MIPI Adapter V2.1 board connected
to G2E board. Common file aistarvision-mipi-adapter-2.1.dtsi is created
which have the camera endpoint nodes for imx219 and ov5645 so that this can
be re-used with other G2x platforms.
r8a774c0-ek874-mipi-2.1.dts file enables the required VIN/CSI nodes and by
default ties ov5645 camera endpoint to CSI2.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1587397794-11237-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Wed, 6 May 2020 19:51:35 +0000 (20:51 +0100)]
ARM: dts: r8a7742: Add GPIO nodes
Describe GPIO blocks in the R8A7742 device tree.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588794695-27852-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Wed, 6 May 2020 19:51:33 +0000 (20:51 +0100)]
ARM: dts: r8a7742: Add [H]SCIF{A|B} support
Describe [H]SCIF{A|B} ports in the R8A7742 device tree.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588794695-27852-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Wed, 6 May 2020 19:51:29 +0000 (20:51 +0100)]
ARM: dts: r8a7742: Add IRQC support
Describe the IRQC interrupt controller in the r8a7742 device tree.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/1588794695-27852-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Marek Vasut [Wed, 29 Apr 2020 16:37:41 +0000 (18:37 +0200)]
ARM: dts: stm32: Add bindings for SPI2 on AV96
Add SPI2 bindings to AV96 DT, the SPI2 IOs are present on
low-speed expansion connector X6. This is disabled by default
and can be enabled if something is connected there.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:40 +0000 (18:37 +0200)]
ARM: dts: stm32: Add alternate pinmux for SPI2 pins
Add another mux option for SPI2 pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:39 +0000 (18:37 +0200)]
ARM: dts: stm32: Add bindings for ADC on AV96
Add ADC bindings to AV96 DT, the ADC inputs are present on
low-speed expansion connector X6.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:38 +0000 (18:37 +0200)]
ARM: dts: stm32: Add alternate pinmux for ADC pins
Add another mux option for ADC pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:37 +0000 (18:37 +0200)]
ARM: dts: stm32: Add bindings for FDCAN2 on AV96
Add FDCAN2 bindings to AV96 DT, the FDCAN2 is present on low-speed
expansion connector X6. This is disabled by default to match the
96boards specification though.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:36 +0000 (18:37 +0200)]
ARM: dts: stm32: Add alternate pinmux for FDCAN2 pins
Add another mux option for FDCAN2 pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:35 +0000 (18:37 +0200)]
ARM: dts: stm32: Add bindings for FDCAN1 on AV96
Add FDCAN1 bindings to AV96 DT, the FDCAN1 is present on low-speed
expansion connector X6. This is disabled by default to match the
96boards specification though.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:34 +0000 (18:37 +0200)]
ARM: dts: stm32: Add alternate pinmux for FDCAN1 pins
Add another mux option for FDCAN1 pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:33 +0000 (18:37 +0200)]
ARM: dts: stm32: Repair I2C2 operation on AV96
The I2C2 uses different pinmux on AV96, use correct pinmux and
also add comments about the I2C being present on the "low-speed"
expansion connector X6.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Marek Vasut [Wed, 29 Apr 2020 16:37:32 +0000 (18:37 +0200)]
ARM: dts: stm32: Add alternate pinmux for I2C2 pins
Add another mux option for I2C2 pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Etienne Carriere [Wed, 6 May 2020 17:48:40 +0000 (19:48 +0200)]
ARM: dts: stm32: bump PSCI to version 1.0 on stm32mp15x
Declare PSCI v1.0 support instead of v0.1 as the former is supported
by the PSCI firmware stacks stm32mp15x relies on.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Mike Leach [Wed, 15 Apr 2020 20:12:59 +0000 (21:12 +0100)]
arm64: dts: hi6220: Add CTI options
Adds in CTI device tree information for the Hikey620 board.
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Tested-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Loic Poulain [Tue, 24 Mar 2020 10:07:52 +0000 (11:07 +0100)]
arm64: dts: hikey960: pinctrl: Fix spi2/spi3 pinconf
Only the pinmux was selected, not the pinconf, leading to spi issues.
Increase drive strength so that max speed (25Mhz) can be achieved.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Dmitry Osipenko [Thu, 19 Mar 2020 19:02:29 +0000 (22:02 +0300)]
ARM: dts: tegra30: beaver: Add CPU Operating Performance Points
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on beaver.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dmitry Osipenko [Thu, 19 Mar 2020 19:02:28 +0000 (22:02 +0300)]
ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS
Set min/max voltage and couple CPU/CORE regulators.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tero Kristo [Wed, 29 Apr 2020 14:30:02 +0000 (17:30 +0300)]
ARM: OMAP5: Make L4SEC clock domain SWSUP only
Commit
c2ce5fb3f3f5 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP
only') made DRA7 SoC L4SEC clock domain SWSUP only because of power
state transition issues detected with HWSUP mode. Based on
experimentation similar issue exists on OMAP5, so do the same change
for OMAP5 also.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Wed, 29 Apr 2020 14:30:01 +0000 (17:30 +0300)]
ARM: OMAP4: Make L4SEC clock domain SWSUP only
Commit
c2ce5fb3f3f5 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP
only') made DRA7 SoC L4SEC clock domain SWSUP only because of power
state transition issues detected with HWSUP mode. Based on
experimentation similar issue exists on OMAP4, so do the same change
for OMAP4 also.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Wed, 29 Apr 2020 14:30:00 +0000 (17:30 +0300)]
ARM: dts: omap5: add DES crypto accelerator node
OMAP5 contains a single DES crypto accelerator instance. Add node for
this in DT to enable it.
We keep the node disabled for now, as it appears OMAP5 platform is
running out of available DMA channels, and DES is the least interesting
crypto accelerator available on the device.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Wed, 29 Apr 2020 14:29:59 +0000 (17:29 +0300)]
ARM: dts: omap5: add SHA crypto accelerator node
Add the single available SHA crypto accelerator device for OMAP5 SoC.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Wed, 29 Apr 2020 14:29:58 +0000 (17:29 +0300)]
ARM: dts: omap5: add aes2 entry
OMAP5 has AES hardware cryptographic accelerator, add AES2 instance for
it.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Wed, 29 Apr 2020 14:29:57 +0000 (17:29 +0300)]
ARM: dts: omap5: add aes1 entry
OMAP5 has AES hardware cryptographic accelerator, add AES1 instance for
it.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:44 +0000 (18:12 +0300)]
ARM: dts: dra7-ipu-dsp-common: Add watchdog timers to IPU and DSP nodes
The watchdog timer information has been added to all the IPU and DSP
remote processor device nodes in the DRA7xx/AM57xx SoC families. The
data has been added to the two common dra7-ipu-dsp-common and
dra74-ipu-dsp-common dtsi files that can be included by all the
desired board files. The following timers are chosen as the watchdog
timers, as per the usage on the current firmware images:
IPU2: GPTimers 4 & 9 (one for each Cortex-M4 core)
IPU1: GPTimers 7 & 8 (one for each Cortex-M4 core)
DSP1: GPTimer 10
DSP2: GPTimer 13
Each of the IPUs has two Cortex-M4 processors and so uses a timer
each for providing watchdog support on that processor irrespective of
whether the IPU is running in SMP-mode or non-SMP node. The chosen
timers also need to be unique from the ones used by other processors
(regular timers or watchdog timers) so that they can be supported
simultaneously.
The MPU-side drivers will use this data to initialize the watchdog
timer(s), and listen for any watchdog triggers. The BIOS-side code on
these processors needs to configure/refresh the corresponding timer
properly to not throw a watchdog error.
The watchdog timers are optional in general, but are mandatory to
be added to support watchdog error recovery on a particular processor.
These timers can be changed or removed as per the system integration
needs, alongside appropriate equivalent changes on the firmware side.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:43 +0000 (18:12 +0300)]
ARM: dts: am571x-idk: Add CMA pools and enable IPUs & DSP1 rprocs
The CMA reserved memory nodes have been added for both the IPUs and the
DSP1 remoteproc devices on the AM571x IDK board. These nodes are assigned
to the respective rproc device nodes, and both the IPUs and the DSP1
remote processors are enabled for this board.
The current CMA pools and sizes are defined statically for each device.
The addresses chosen are the same as the respective processors on the
DRA72 EVM board to maintain firmware compatibility between the two boards.
The CMA pools and sizes are defined using 64-bit values to support LPAE.
The starting addresses are fixed to meet current dependencies on the
remote processor firmwares, and this will go away when the remote-side
code has been improved to gather this information runtime during its
initialization.
An associated pair of the rproc node and its CMA node can be disabled
later on if there is no use-case defined to use that remote processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:42 +0000 (18:12 +0300)]
ARM: dts: am572x-idk-common: Add CMA pools and enable IPU & DSP rprocs
The CMA reserved memory nodes have been added for all the IPU and DSP
remoteproc devices in the am572x-idk-common.dtsi file that is common to
both the AM572x and AM574x IDK boards. These nodes are assigned to the
respective rproc device nodes, and all the IPU and DSP remote processors
are enabled.
The current CMA pools and sizes are defined statically for each device.
The addresses chosen are the same as the respective processors on
the AM57xx EVM board to maintain firmware compatibility between the
two boards. The CMA pools and sizes are defined using 64-bit values
to support LPAE. The starting addresses are fixed to meet current
dependencies on the remote processor firmwares, and this will go
away when the remote-side code has been improved to gather this
information runtime during its initialization.
An associated pair of the rproc node and its CMA node can be disabled
later on if there is no use-case defined to use that remote processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:41 +0000 (18:12 +0300)]
ARM: dts: beagle-x15-common: Add CMA pools and enable IPU & DSP rprocs
The CMA reserved memory nodes have been added for all the IPU and DSP
remoteproc devices on all the AM57xx BeagleBoard-X15 boards. These nodes
are assigned to the respective rproc device nodes, and all the IPU and
DSP remote processors are enabled for all these boards.
The current CMA pools and sizes are defined statically for each device.
The addresses chosen are the same as the respective processors on the
DRA7 EVM board to maintain firmware compatibility between the two boards.
The CMA pools and sizes are defined using 64-bit values to support LPAE.
The starting addresses are fixed to meet current dependencies on the
remote processor firmwares, and this will go away when the remote-side
code has been improved to gather this information runtime during its
initialization.
An associated pair of the rproc node and its CMA node can be disabled
later on if there is no use-case defined to use that remote processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:40 +0000 (18:12 +0300)]
ARM: dts: dra76-evm: Add CMA pools and enable IPU & DSP rprocs
The CMA reserved memory nodes have been added for all the IPU and
the DSP remoteproc devices on the DRA76 EVM board, and assigned to
the respective rproc device nodes. These match the configuration
used on the DRA7 EVM board. Both the CMA nodes and the corresponding
rproc nodes are also enabled to enable these processors on the
DRA76 EVM board.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:39 +0000 (18:12 +0300)]
ARM: dts: dra71-evm: Add CMA pools and enable IPUs & DSP1 rprocs
The CMA reserved memory nodes have been added for both the IPUs and the
DSP1 remoteproc devices on DRA71 EVM board. These nodes are assigned to
the respective rproc device nodes, and both the IPUs and the DSP1 remote
processors are enabled for this board.
The current CMA pools and sizes are defined statically for each device.
The addresses chosen are the same as the respective processors on the
DRA72 EVM board to maintain firmware compatibility between the two boards.
The CMA pools and sizes are defined using 64-bit values to support LPAE.
The starting addresses are fixed to meet current dependencies on the
remote processor firmwares, and this will go away when the remote-side
code has been improved to gather this information runtime during its
initialization.
An associated pair of the rproc node and its CMA node can be disabled
later on if there is no use-case defined to use that remote processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:38 +0000 (18:12 +0300)]
ARM: dts: dra72-evm-revc: Add CMA pools and enable IPUs & DSP1 rprocs
The CMA reserved memory nodes have been added for both the IPUs and
the DSP1 remoteproc devices on the DRA72 EVM rev C board, and assigned
to the respective rproc device nodes. These match the configuration
used on the DRA72 EVM board. Both the CMA nodes and the corresponding
rproc nodes are also enabled to enable these processors on the
DRA72 EVM rev C board.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:37 +0000 (18:12 +0300)]
ARM: dts: dra72-evm: Add CMA pools and enable IPUs & DSP1 rprocs
The CMA reserved memory nodes have been added for both the IPUs and the
DSP1 remoteproc devices on DRA72 EVM board. These nodes are assigned to
the respective rproc device nodes, and both the IPUs and the DSP1 remote
processors are enabled for this board.
The current CMA pools and sizes are defined statically for each device.
The addresses chosen are the same as the respective processors on the
DRA7 EVM board to maintain firmware compatibility between the two boards.
The CMA pools and sizes are defined using 64-bit values to support LPAE.
The starting addresses are fixed to meet current dependencies on the
remote processor firmwares, and this will go away when the remote-side
code has been improved to gather this information runtime during its
initialization.
An associated pair of the rproc node and its CMA node can be disabled
later on if there is no use-case defined to use that remote processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:36 +0000 (18:12 +0300)]
ARM: dts: dra7-evm: Add CMA pools and enable IPU & DSP rprocs
The CMA reserved memory nodes have been added for all the IPU and DSP
remoteproc devices on DRA7 EVM board. These nodes are assigned to the
respective rproc device nodes, and all the IPU and DSP remote processors
are enabled for this board.
The current CMA pools and sizes are defined statically for each device.
The CMA pools and sizes are defined using 64-bit values to support LPAE.
The starting addresses are fixed to meet current dependencies on the
remote processor firmwares, and this will go away when the remote-side
code has been improved to gather this information runtime during its
initialization.
An associated pair of the rproc node and its CMA node can be disabled
later on if there is no use-case defined to use that remote processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:35 +0000 (18:12 +0300)]
ARM: dts: dra7-ipu-dsp-common: Add timers to IPU and DSP nodes
The BIOS System Tick timers have been added for all the IPU and
DSP remoteproc devices in the DRA7 SoC family. The data is added
to the two common dra7-ipu-dsp-common and dra74-ipu-dsp-common
dtsi files that are included by all the desired board files. The
following timers are chosen, as per the timers used on the current
firmware images:
IPU2: GPTimer 3
IPU1: GPTimer 11
DSP1: GPTimer 5
DSP2: GPTimer 6
The timers are optional, but are mandatory to support advanced device
management features such as power management and watchdog support.
The above are added to successfully boot and execute firmware images
configured with the respective timers, images that use internal
processor subsystem timers are not affected. The timers can be
changed or removed as per the system integration needs, if needed.
Each of the IPUs has two Cortex-M4 processors, and is currently
expected to be running in SMP-mode, so only a single timer suffices
to provide the BIOS tick timer. An additional timer should be added
for the second processor in IPU if it were to be run in non-SMP mode.
The timer value also needs to be unique from the ones used by other
processors so that they can be run simultaneously.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:34 +0000 (18:12 +0300)]
ARM: dts: dra7-ipu-dsp-common: Add mailboxes to IPU and DSP nodes
Add the required 'mboxes' property to all the IPU and DSP remote
processors (IPU1, IPU2, DSP1 and DSP2) in the two available common
dtsi files - dra7-ipu-dsp-common and dra74-ipu-dsp-common dtsi files.
The latter file is for platforms having DRA74x/DRA76x/AM572x/AM574x
SoCs which do have a DSP2 processor in addition to the other common
remote processors. The common data is added to the former file, and
the DSP2 only data is added to the latter file.
The mailboxes are required for running the Remote Processor Messaging
(RPMsg) stack between the host processor and each of the remote
processors. Each of the remote processors uses a single sub-mailbox
node, the IPUs are assumed to be running in SMP-mode. The chosen
sub-mailboxes match the values used in the current firmware images.
This can be changed, if needed, as per the system integration needs
after making appropriate changes on the firmware side as well.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:33 +0000 (18:12 +0300)]
ARM: dts: dra7-ipu-dsp-common: Move mailboxes into common files
The System Mailboxes 5 and 6 and their corresponding child sub-mailbox
(IPC 3.x) nodes are enabled in each of the DRA7xx and AM57xx board
dts files individually at present. These mailboxes enable the Remote
Processor Messaging (RPMsg) communication stack between the MPU host
processor and each of the IPU1, IPU2, DSP1 and DSP2 remote processors.
Move these nodes into two common dtsi files - dra7-ipu-dsp-common and
dra74-ipu-dsp-common files, which are then included in various board
dts files. These files can be used to add all the common configuration
properties (except memory data) required by remote processor nodes.
The memory pools and the remote processor nodes themselves are to be
enabled in the actual board dts files. The first file is to used by
platforms using DRA72x/DRA71x/AM571x/AM570x SoCs, and the second file
is to be used by platforms using DRA74x/DRA76x/AM572x/AM574x SoCs.
The second file includes the first file and contains additional data
only applicable for DSP2 remote processor.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:32 +0000 (18:12 +0300)]
ARM: dts: DRA72x: Add aliases for rproc nodes
Add aliases for all the 3 remote processor nodes common to
all DRA72x/DRA71x/AM571x/AM570x boards. The aliases uses the
stem "rproc", and are defined in the order of the most common
processors on the DRA72x family. The ids are same as DRA74x
except for the missing DSP2.
The aliases can be overridden, if needed, in the respective
derivative board dts files.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:31 +0000 (18:12 +0300)]
ARM: dts: DRA74x: Add aliases for rproc nodes
Add aliases for all the IPU and DSP remoteproc processor
nodes common to all DRA74x/DRA76x/AM572x/AM574x boards.
The aliases uses the stem "rproc". The aliases are defined
in the order of the most common processors on the DRA74x
family.
The aliases can be overridden, if needed, in the respective
derivative board dts files.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:30 +0000 (18:12 +0300)]
ARM: dts: DRA74x: Add DSP2 processor device node
The DRA7xx family of SoCs can contain upto two identical DSP
processor subsystems. The second DSP processor subsystem is
present only on the DRA74x/DRA76x variants. The processor
device DT node has therefore been added in disabled state for
this processor subsystem in the DRA74x specific DTS file.
NOTE:
1. The node does not have any mailboxes, timers or CMA region
assigned, they should be added in the respective board dts
files.
2. The node should also be enabled as per the individual product
configuration in the corresponding board dts files.
Signed-off-by: Suman Anna <s-anna@ti.com>
[t-kristo@ti.com: converted to support ti-sysc from legacy hwmod]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Fri, 24 Apr 2020 15:12:29 +0000 (18:12 +0300)]
ARM: dts: DRA7: Add common IPU and DSP nodes
The DRA7xx family of SOCs have two IPUs and upto two DSP
processor subsystems in general. The IPU processor subsystem
contains dual-core ARM Cortex-M4 processors, while the DSP
processor subsystem is based on the TI's standard TMS320C66x
DSP CorePac core. The IPUs are very similar to those on OMAP5.
Two IPUs and one DSP processor subsystems is the most common
configuration. The processor device DT nodes have been added
for these processor subsystems, with the internal memories
added through 'reg' and 'reg-names' properties. The IPUs only
have an L2 RAM, whereas the DSPs have L1P, L1D and L2 RAM
memories.
NOTE:
1. The nodes do not have any mailboxes, timers or CMA regions
assigned, they should be added in the respective board dts
files.
2. The nodes haven been disabled by default and the enabling
of these nodes is also left to the respective board dts
files.
Signed-off-by: Suman Anna <s-anna@ti.com>
[t-kristo@ti.com: convert to ti-sysc support from legacy hwmod]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Fri, 24 Apr 2020 15:12:28 +0000 (18:12 +0300)]
ARM: dts: dra7: add timer_sys_ck entries for IPU/DSP timers
With this, the clocksource driver can setup the timers properly.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren [Tue, 5 May 2020 18:09:38 +0000 (11:09 -0700)]
Merge branch 'omap-for-v5.8/dt-timer' into omap-for-v5.8/dt
Lokesh Vutla [Mon, 27 Apr 2020 17:26:04 +0000 (22:56 +0530)]
ARM: dts: Add 32KHz clock as default clock source
Clocksource to timer configured in pwm mode can be selected using the DT
property ti,clock-source. There are few pwm timers which are not
selecting the clock source and relying on default value in hardware or
selected by driver. Instead of relying on default value, always select
the clock source from DT.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Pascal Paillet [Thu, 30 Apr 2020 13:02:35 +0000 (15:02 +0200)]
ARM: dts: stm32: Enable thermal sensor support on stm32mp15xx-dkx
Enable STM32 Digital Thermal Sensor driver for stm32mp15xx-dkx boards.
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Yann Gautier [Thu, 30 Apr 2020 10:16:49 +0000 (12:16 +0200)]
ARM: dts: stm32: add sd-uhs properties in SD-card node for stm32mp157c-ed1
The sdmmc1 peripheral is connected on SD-card on STM32MP1-ED1 board.
Add the UHS features the controller is able to manage.
Those features require a level shifter on the board, and the support of
the voltage switch in driver, which is done in Linux v5.7.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Linus Walleij [Thu, 30 Apr 2020 15:02:45 +0000 (17:02 +0200)]
ARM: dts: ux500: samsung-skomer: Add magnetometer
Add the ALPS magnetometer to the Skomer phone.
Cc: Stephan Gerhold <stephan@gerhold.net>
Cc: Nick Reitemeyer <nick.reitemeyer@web.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20200430150245.7935-2-linus.walleij@linaro.org
Nick Reitemeyer [Thu, 30 Apr 2020 15:02:44 +0000 (17:02 +0200)]
ARM: dts: ux500: samsung-golden: Add magnetometer
Add the ALPS magnetometer to the Golden phone.
Cc: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Nick Reitemeyer <nick.reitemeyer@web.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20200430150245.7935-1-linus.walleij@linaro.org
Lad Prabhakar [Sun, 3 May 2020 21:46:54 +0000 (22:46 +0100)]
ARM: dts: r8a7742-iwg21d-q7: Add iWave G21D-Q7 board based on RZ/G1H
Add support for iWave RainboW-G21D-Qseven board based on RZ/G1H.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588542414-14826-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Sun, 3 May 2020 21:46:53 +0000 (22:46 +0100)]
ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM
Add support for iWave RZ/G1H Qseven System On Module.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588542414-14826-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Lad Prabhakar [Sun, 3 May 2020 21:46:50 +0000 (22:46 +0100)]
ARM: dts: r8a7742: Initial SoC device tree
The initial R8A7742 SoC device tree including CPU[0-8], PMU, PFC,
CPG, RST, SYSC, ICRAM[0-2], SCIFA2, MMC1, DMAC[0-1], GIC, PRR, timer
and the required clock descriptions.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1588542414-14826-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Geert Uytterhoeven [Tue, 5 May 2020 07:44:13 +0000 (09:44 +0200)]
Merge tag 'renesas-r8a7742-dt-binding-defs-tag' into renesas-arm-dt-for-v5.8
Renesas RZ/G1H DT Binding Definitions
Clock and Power Domain definitions for the Renesas RZ/G1H (R8A7742) SoC,
shared by driver and DT source files.
Andrew Jeffery [Sat, 11 Apr 2020 02:14:58 +0000 (11:44 +0930)]
ARM: dts: aspeed: Change KCS nodes to v2 binding
Fixes the following warnings for both g5 and g6 SoCs:
arch/arm/boot/dts/aspeed-g5.dtsi:376.19-381.8: Warning
(unit_address_vs_reg): /ahb/apb/lpc@
1e789000/lpc-bmc@0/kcs1@0: node
has a unit name, but no reg property
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
projects / platform / kernel / linux-starfive.git / log