Christian Gmeiner [Sun, 25 Mar 2018 20:30:04 +0000 (22:30 +0200)]
etnaviv: support MC performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
Christian Gmeiner [Sun, 25 Mar 2018 20:30:03 +0000 (22:30 +0200)]
etnaviv: support TX performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
Christian Gmeiner [Sun, 25 Mar 2018 20:30:02 +0000 (22:30 +0200)]
etnaviv: support RA performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
Christian Gmeiner [Sun, 25 Mar 2018 20:30:01 +0000 (22:30 +0200)]
etnaviv: support SE performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
Christian Gmeiner [Sun, 25 Mar 2018 20:30:00 +0000 (22:30 +0200)]
etnaviv: support PA performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
Christian Gmeiner [Sun, 25 Mar 2018 20:29:59 +0000 (22:29 +0200)]
etnaviv: support SH performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
Christian Gmeiner [Sun, 25 Mar 2018 20:29:58 +0000 (22:29 +0200)]
etnaviv: support PE performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
Christian Gmeiner [Sun, 25 Mar 2018 20:29:57 +0000 (22:29 +0200)]
etnaviv: support HI performance counters
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
Christian Gmeiner [Sun, 25 Mar 2018 20:29:56 +0000 (22:29 +0200)]
etnaviv: add perfmon query implementation
Add needed infrastructure to use performance monitor
requests for queries.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Chris Healy <cphealy@gmail.com>
Christian Gmeiner [Fri, 6 Apr 2018 06:41:32 +0000 (08:41 +0200)]
etnaviv: sw queries: return correct number of groups
Fixes:
3d912bd742ed ("etnaviv: add query_group_info for sw counters")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Lucas Stach [Thu, 29 Mar 2018 14:15:15 +0000 (16:15 +0200)]
etnaviv: advertise YUV formats as external only
We only support importing YUV as OES external resources.
This will change in the future, but for now this fixes the
advertised capabilities in eglQueryDmaBufModifiersEXT.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Lucas Stach [Thu, 29 Mar 2018 14:15:14 +0000 (16:15 +0200)]
gallium/util: implement util_format_is_yuv
This adds a helper to check if a pipe format is in YUV color space.
Drivers want to know about this, as YUV mostly needs special handling.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Rhys Perry [Thu, 5 Apr 2018 21:49:52 +0000 (22:49 +0100)]
nvc0: finish implementation of PIPE_QUERY_SO_OVERFLOW_PREDICATE
This also removes some useless code leftover from old changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Rhys Perry [Thu, 5 Apr 2018 21:31:26 +0000 (22:31 +0100)]
nvc0: change ACQUIRE_EQUAL to ACQUIRE_GEQUAL in nvc0_hw_query_fifo_wait
If a fence is created in between nvc0_hw_end_query and
nvc0_hw_query_fifo_wait, the sequence number in nvc0->screen->fence.bo can
be larger than hq->fence->sequence before the semaphore is created,
resulting in the semaphore never being triggered.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Rhys Perry [Thu, 5 Apr 2018 21:31:25 +0000 (22:31 +0100)]
nvc0: ensure the query's fence has been emitted in nvc0_hw_query_fifo_wait
If the fence has not been emitted, hq->fence->sequence would be zero. This
would result in the semaphore never being triggered, blocking all later
commands in the pushbuf.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
[imirkin: use nouveau_fence_emit instead]
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Tue, 3 Apr 2018 04:00:59 +0000 (00:00 -0400)]
st/mesa: tex offsets can't be in a const or 2d-indexed
All consts are now implicitly 2d (they set .Dimension), so trigger
asserts. Also, the texture offset can't handle any sort of 2d indexing.
While this could be tacked on, this seems unnecessary, just move it off
into a separate temp.
Fixes assertion failure in
tests/spec/arb_gpu_shader5/compiler/builtin-functions/fs-gatherOffset-uniform-offset.frag
Note that this was an issue even before the const-always-2d thing, since
there was no detection of when even a proper second dimension was used,
e.g. for UBO or geom/tess inputs.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Thu, 29 Mar 2018 03:45:26 +0000 (23:45 -0400)]
nvc0: restore image binding on RGB10A2, remove from BGR10A2
Fixes a bunch of new CTS pbo tests that use those as an output format,
which the state tracker converts into buffer image writes.
No part of the driver is ready for BGR10A2. It could probably be enabled
on Maxwell+, but seems unnecessary. This error was introduced when
flipping the displayable bit on those formats, which accidentally also
moved the image bit.
Fixes:
e1a70aed10d (nv50,nvc0: mark ABGR format as displayable instead of ARGB format)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Rob Clark [Fri, 6 Apr 2018 12:54:25 +0000 (08:54 -0400)]
freedreno/ir3: use lower_global_vars_to_local in cmdline compiler
tgsi_to_nir emits things with arrays as global vars.. and nir->ir3 does
lower_locals_to_regs. But nothing was lowering global to local, which
breaks compiling tgsi shaders
Signed-off-by: Rob Clark <robdclark@gmail.com>
Kenneth Graunke [Sat, 7 Apr 2018 05:56:48 +0000 (22:56 -0700)]
i965: Use %x instead of %u in debug print.
I mistakenly printed out the address as 0x<decimal number> instead of
printing a proper hex number. This was...surprising.
Dylan Baker [Thu, 15 Mar 2018 20:30:22 +0000 (13:30 -0700)]
meson: fix warnings about comparing unlike types
In the old days (0.42.x), when mesa's meson system was written the
recommendation for handling conditional dependencies was to define them
as empty lists. When meson would evaluate the dependencies of a target
it would recursively flatten all of the arguments, and empty lists would
be removed. There are some problems with this, among them that lists and
dependencies have different methods (namely .found()), so the
recommendation changed to use `dependency('', required : false)` for
such cases. This has the advantage of providing a .found() method, so
there is no need to do things like `dep_foo != [] and dep_foo.found()`,
such a dependency should never exist.
I've tested this with 0.42 (the minimum we claim to support) and 0.45.
On 0.45 this removes warnings about comparing unlike types, such as:
meson.build:1337: WARNING: Trying to compare values of different types
(DependencyHolder, list) using !=.
v2: - Use dependency('', required : false) instead of
declare_dependency(), the later will always report that it is
found, which is not what we want.
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Ian Romanick [Thu, 29 Mar 2018 18:29:09 +0000 (11:29 -0700)]
intel/compiler: Explicitly cast register type in switch
brw_reg::type is "enum brw_reg_type type:4". For whatever reason, GCC
is treating this as an int instead of an enum. As a result, it doesn't
detect missing switch cases and it doesn't detect that flow can get out
of the switch.
This silences the warning:
src/intel/compiler/brw_reg.h: In function ‘bool brw_regs_negative_equal(const brw_reg*, const brw_reg*)’:
src/intel/compiler/brw_reg.h:305:1: warning: control reaches end of non-void function [-Wreturn-type]
}
^
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Axel Davy [Mon, 2 Apr 2018 16:25:35 +0000 (18:25 +0200)]
st/nine: Declare lighting consts for ff shaders
The lighting constants were not declared previously,
but were accessed with indirect addressing, which is
illegal.
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105442
Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
CC: "17.3 18.0" <mesa-stable@lists.freedesktop.org>
Caio Marcelo de Oliveira Filho [Wed, 4 Apr 2018 23:16:39 +0000 (16:16 -0700)]
nir: rename variables in nir_lower_io_to_temporaries for clarity
In the emit_copies() function, the use of "newv" and "temp" names made
sense when only copies from temporaries to the new variables were
being done. But now there are other calls to copy with other pairings,
and "temp" doesn't always refer to a temporary created in this
pass. Use the names "dest" and "src" instead.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Samuel Pitoiset [Thu, 5 Apr 2018 09:34:57 +0000 (11:34 +0200)]
radv: don't pass the pipeline to radv_flush_constants()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 5 Apr 2018 09:30:53 +0000 (11:30 +0200)]
radv: rename radv_cmd_buffer_update_vertex_descriptors()
... to radv_flush_vertex_descriptors().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Thu, 5 Apr 2018 09:27:10 +0000 (11:27 +0200)]
radv: do not try to skip draw calls when VBOs upload failed
This is unnecessary because we record an error which should
be returned by vkEndCommandBuffer(), and the app shouldn't
submit a command buffer when this happens.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 5 Apr 2018 09:19:21 +0000 (11:19 +0200)]
radv: fix prefetching compute shaders on CIK and older chips
Because the check was moved to radv_emit_prefetch_L2().
Fixes:
4ad7595f35 ("radv: rename radv_emit_prefetch() to radv_emit_prefetch_L2()")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 5 Apr 2018 08:27:22 +0000 (10:27 +0200)]
radv: only enable PERFECT_ZPASS_COUNTS for precision occlusion queries
This unnecessary when the precision bit flag is not set, and this
might hurt performance. The Vulkan explains that not setting
VK_QUERY_CONTROL_PRECISE_BIT might be more efficient on some
implementations.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 5 Apr 2018 08:27:07 +0000 (10:27 +0200)]
radv: enable the Polaris small primitive filter control
Enable it directly in the preamble, but do not enable line
on Polaris10/11/12 because there is a hw bug.
There is possibly an issue when MSAA is off, but this doesn't
regress any CTS and AMDVLK doesn't have a workaround as well.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Jason Ekstrand [Tue, 13 Feb 2018 22:26:05 +0000 (14:26 -0800)]
anv: Add WSI support for the I915_FORMAT_MOD_Y_TILED_CCS
v2 (Jason Ekstrand):
- Return the correct enum values from anv_layout_to_fast_clear_type
v3 (Jason Ekstrand):
- Always return ANV_FAST_CLEAR_NONE and leave doing the right thing for
the patch which adds a modifier which supports fast-clears.
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Daniel Stone <daniels@collabora.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Anuj Phogat [Thu, 5 Apr 2018 21:19:40 +0000 (14:19 -0700)]
Add more Coffee Lake brand strings
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jan Vesely [Thu, 5 Apr 2018 20:34:00 +0000 (16:34 -0400)]
radeonsi: Reorder checks in si_check_render_feedback
si_get_total_colormask accesses NULL pointer on compute shaders
Fixes crashes on clover
Fixes:
0669dca9c00261849cee14d69fdea0a5e323c7f7 ("radeonsi: skip DCC render feedback checking if color writes are disabled")
CC: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Kevin Rogovin [Fri, 9 Feb 2018 01:11:25 +0000 (17:11 -0800)]
intel/tools: new intel_sanitize_gpu tool
Adds a new debug tool to pad each GEM BO allocated with (weak)
pseudo-random noise values which are then checked after each
batchbuffer dispatch to the kernel. This can be quite valuable to
find diffucult to track down heisenberg style bugs.
[scott.d.phillips@intel.com: split to separate tool]
v2: (by Scott D Phillips)
- track gem handles per fd (Kevin)
- remove handles on GEM_CLOSE (Kevin)
- ignore prime handles
- meson & shell script
v3: (by Scott D Phillips)
- don't track prime bos at all (Kevin)
- protect the hash table with a mutex (Kevin)
- hook fds by drm_version.name, not path (Chris Wilson)
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Reviewed-by: Kevin Rogovin <kevin.rogovin@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Jason Ekstrand [Mon, 19 Mar 2018 20:43:35 +0000 (13:43 -0700)]
prog/nir: Simplify some load/store operations
Reviewed-by: Eric Anholt <eric@anholt.net>
Marek Olšák [Thu, 5 Apr 2018 19:53:52 +0000 (15:53 -0400)]
radeonsi: fix a crash if ps_shader.cso is NULL in si_get_total_colormask
Marek Olšák [Mon, 2 Apr 2018 02:49:58 +0000 (22:49 -0400)]
radeonsi: remove more R600 references
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Mon, 2 Apr 2018 00:56:07 +0000 (20:56 -0400)]
radeonsi: try to fix android
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Mon, 2 Apr 2018 00:49:35 +0000 (20:49 -0400)]
radeonsi: try to fix meson
This is not fully tested. Meson can't link LLVM even though automake can.
PATH=/usr/llvm/x86_64-linux-gnu/bin:$PATH meson build/ -Dgallium-va=false \
-Dplatforms=x11,drm -Dgallium-drivers=radeonsi -Ddri-drivers= \
-Dgallium-omx=disabled -Dgallium-xvmc=false -Dgles1=false \
-Dtexture-float=true -Dvulkan-drivers=
src/gallium/auxiliary/libgallium.a(gallivm_lp_bld_misc.cpp.o):
(.data.rel.ro._ZTI26DelegatingJITMemoryManager[_ZTI26DelegatingJITMemoryManager]+0x10):
undefined reference to `typeinfo for llvm::RTDyldMemoryManager'
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Mon, 2 Apr 2018 00:34:40 +0000 (20:34 -0400)]
radeonsi: don't build libradeon.la separately
for better parallelism
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 23:58:22 +0000 (19:58 -0400)]
radeonsi: clean up GET_MAX_VIEWPORT_RANGE definition
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 23:44:25 +0000 (19:44 -0400)]
radeonsi: remove r600_common_context
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 23:03:10 +0000 (19:03 -0400)]
radeonsi: remove r600_pipe_common::screen
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 23:01:32 +0000 (19:01 -0400)]
radeonsi: move r600_buffer_common.c and r600_texture.c into radeonsi
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 22:51:44 +0000 (18:51 -0400)]
radeonsi: move r600_gpu_load.c to si_gpu_load.c
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 22:47:05 +0000 (18:47 -0400)]
radeonsi: move r600_query.c/h files to si_query.c/h
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 22:42:33 +0000 (18:42 -0400)]
radeonsi: move r600_cs.h contents into si_pipe.h, si_build_pm4.h
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 22:32:54 +0000 (18:32 -0400)]
radeonsi: rename query definitions R600_ -> SI_
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 22:30:47 +0000 (18:30 -0400)]
radeonsi: move and rename R600_ERR out of r600_pipe_common.h
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 22:28:20 +0000 (18:28 -0400)]
radeonsi: rename a few R600/r600_ -> SI_/si_
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 22:24:21 +0000 (18:24 -0400)]
radeonsi: move definitions out of r600_pipe_common.h
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 22:12:34 +0000 (18:12 -0400)]
radeonsi: move functions out of and remove r600_pipe_common.c
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 21:52:55 +0000 (17:52 -0400)]
radeonsi: rename r600 -> si in some places
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 21:08:35 +0000 (17:08 -0400)]
radeonsi: use si_context instead of pipe_context in parameters pt3
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 21:08:35 +0000 (17:08 -0400)]
radeonsi: use si_context instead of pipe_context in parameters pt2
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 21:08:35 +0000 (17:08 -0400)]
radeonsi: use si_context instead of pipe_context in parameters pt1
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 21:02:01 +0000 (17:02 -0400)]
radeonsi: pass sctx to si_rebind_buffer and clean up
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 19:37:11 +0000 (15:37 -0400)]
radeonsi: use r600_common_context less pt7
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 19:37:11 +0000 (15:37 -0400)]
radeonsi: use r600_common_context less pt6
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 20:49:48 +0000 (16:49 -0400)]
radeonsi: update copyrights
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 20:40:30 +0000 (16:40 -0400)]
radeonsi: switch radeon_add_to_buffer_list parameter to si_context
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 19:37:11 +0000 (15:37 -0400)]
radeonsi: use r600_common_context less pt5
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 19:37:11 +0000 (15:37 -0400)]
radeonsi: use r600_common_context less pt4
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 19:37:11 +0000 (15:37 -0400)]
radeonsi: use r600_common_context less pt3
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 19:37:11 +0000 (15:37 -0400)]
radeonsi: use r600_common_context less pt2
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 19:37:11 +0000 (15:37 -0400)]
radeonsi: use r600_common_context less pt1
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 19:24:07 +0000 (15:24 -0400)]
radeonsi: don't use r600_common_context in si_emit_cache_flush
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 19:16:26 +0000 (15:16 -0400)]
radeonsi: switch r600_atom::emit parameter to si_context
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 19:07:58 +0000 (15:07 -0400)]
radeonsi: flatten / remove struct r600_ring
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 19:03:23 +0000 (15:03 -0400)]
radeonsi: remove r600_ring::flush callback
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:59:44 +0000 (14:59 -0400)]
radeonsi: make radeon_add_to_buffer_list_check_mem be gfx-only
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:52:42 +0000 (14:52 -0400)]
radeonsi: add_to_buffer_list functions can return void
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:46:05 +0000 (14:46 -0400)]
radeonsi: move saved_cs functions from r600_pipe_common.c to si_debug.c
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:40:34 +0000 (14:40 -0400)]
radeonsi: move DMA CS functions from r600_pipe_common.c to si_dma_cs.c
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:31:02 +0000 (14:31 -0400)]
radeonsi: move EOP event code from r600_pipe_common.c to si_fence.c
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:24:53 +0000 (14:24 -0400)]
radeonsi: rename si_hw_context.c -> si_gfx_cs.c
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:22:54 +0000 (14:22 -0400)]
radeonsi: move si_destroy_saved_cs to si_debug.c
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:18:17 +0000 (14:18 -0400)]
radeonsi: rename si_begin_new_cs -> si_begin_new_gfx_cs
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:17:23 +0000 (14:17 -0400)]
radeonsi: rename si_need_cs_space -> si_need_gfx_cs_space
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:15:34 +0000 (14:15 -0400)]
radeonsi: remove r600_pipe_common::blit_decompress_depth
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:13:22 +0000 (14:13 -0400)]
radeonsi: remove r600_pipe_common::decompress_dcc
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:06:06 +0000 (14:06 -0400)]
radeonsi: remove r600_pipe_common::invalidate_buffer
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:04:04 +0000 (14:04 -0400)]
radeonsi: remove r600_pipe_common::rebind_buffer
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 18:00:14 +0000 (14:00 -0400)]
radeonsi: remove r600_common_context::set_occlusion_query_state
and remove unused old_enable parameter.
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 17:55:34 +0000 (13:55 -0400)]
radeonsi: remove r600_pipe_common::save_qbo_state
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 17:51:09 +0000 (13:51 -0400)]
radeonsi: remove unused query code
The get_size perf counter callback is also inlined and removed.
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 17:40:41 +0000 (13:40 -0400)]
radeonsi: use num_cs_dw_queries_suspend
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 17:32:47 +0000 (13:32 -0400)]
radeonsi: remove r600_pipe_common::need_gfx_cs_space
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 17:30:02 +0000 (13:30 -0400)]
radeonsi: remove r600_pipe_common::set_atom_dirty
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 17:29:04 +0000 (13:29 -0400)]
radeonsi: remove r600_pipe_common::check_vm_faults
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 1 Apr 2018 17:24:43 +0000 (13:24 -0400)]
radeonsi: call CS flush functions directly whenever possible
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sat, 31 Mar 2018 02:15:52 +0000 (22:15 -0400)]
radeonsi: skip DCC render feedback checking if color writes are disabled
Dylan Baker [Wed, 4 Apr 2018 17:23:02 +0000 (10:23 -0700)]
meson: fix megadriver symlinking
Which should be relative instead of absolute.
Fixes:
f7f1b30f81e842db6057591470ce3cb6d4fb2795
("meson: extend install_megadrivers script to handle symmlinking")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105567
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-and-Tested-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Dylan Baker [Wed, 4 Apr 2018 17:53:16 +0000 (10:53 -0700)]
meson: Set .so version for xa like autotools does
Fixes:
0ba909f0f111824223bc38563d1a6bc73e69c2cc
("meson: build gallium xa state tracker")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Rafael Antognolli [Tue, 6 Mar 2018 17:21:40 +0000 (09:21 -0800)]
anv: Make blorp update the clear color.
Instead of updating the clear color in anv before a resolve, just let
blorp handle that for us during fast clears.
v5: Update comment about HiZ clear color (Jordan).
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Rafael Antognolli [Fri, 19 Jan 2018 01:19:30 +0000 (17:19 -0800)]
anv: Use clear address for HiZ fast clears too.
Store the default clear address for HiZ fast clears on a global bo, and
point to it when needed.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Rafael Antognolli [Thu, 18 Jan 2018 17:50:48 +0000 (09:50 -0800)]
anv: Emit the fast clear color address, instead of value.
On Gen10+, instead of copying the clear color from the state buffer to
the surface state, just use the address of the state buffer in the
surface state directly. This way we can avoid the copy from state buffer
to surface state.
v4:
- Remove use_clear_address from anv code. (Jason)
- Use the helper to extract clear color from attachment (Jason)
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Rafael Antognolli [Wed, 28 Feb 2018 01:06:13 +0000 (17:06 -0800)]
anv: Add a helper to extract clear color from the attachment.
Extract the code from color_attachment_compute_aux_usage, so we can
later reuse it to update the clear color state buffer.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Rafael Antognolli [Tue, 29 Aug 2017 23:30:26 +0000 (16:30 -0700)]
i965/surface_state: Emit the clear color address instead of value.
On Gen10, when emitting the surface state, use the value stored in the
clear color entry buffer by using a clear color address in the surface
state.
v4: Use the clear color offset from the clear_color_bo, when available.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Rafael Antognolli [Tue, 29 Aug 2017 23:25:30 +0000 (16:25 -0700)]
i965/blorp: Update the fast clear value buffer.
On Gen10, whenever we do a fast clear, blorp will update the clear color
state buffer for us, as long as we set the clear color address
correctly.
However, on a hiz clear, if the surface is already on the fast clear
state we skip the actual fast clear operation and, before gen10, only
updated the miptree. On gen10+ we need to update the clear value state
buffer too, since blorp will not be doing a fast clear and updating it
for us.
v4:
- do not use clear_value_size in the for loop
- Get the address of the clear color from the aux buffer or the
clear_color_bo, depending on which one is available.
- let core blorp update the clear color, but also update it when we
skip a fast clear depth.
v5: Better subject (Jordan).
v6: Remove outdated comment (Jason).
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rafael Antognolli [Mon, 5 Mar 2018 19:25:12 +0000 (11:25 -0800)]
i965: Add aux_buf variable to simplify code.
In a follow up patch, we make use of clear_color_bo, which is in
mt->mcs_buf or mt->hiz_buf. To avoid duplicating more code that does the
same thing on both aux buffers, just use aux_buf already.
v5: Add aux_buf to brw_wm_surface_state too.
v6: Drop aux_surf and use aux_buf->surf instead (Jason).
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>