Alyssa Rosenzweig [Fri, 17 Jun 2022 16:58:55 +0000 (12:58 -0400)]
pan/bi: Tune lower_vars_to_scratch
Increase the threshold to lower indirect indexing of arrays to scratch memory
all the way up to 256 bytes, which was the lowest power-of-two threshold for
which enabling the pass on Mali-G57 was a win in shaderdb.
It's difficult to tell what threshold is optimal here. The shader-db stats are
based on a rough cycle model that assumes a 16:1 ratio between CVT and
load/store on Valhall, and a 24:1 ratio between arithmetic and load/store on
Bifrost. Those ratios are at most rules of thumb, as the number of cycles
required by a load/store instruction will vary tremendously based on caching and
the memory controller. However, they may well be lower bounds (if those are the
upper bounds on instruction issuing in the Mali shader cores). As such, a large
threshold seems well motivated.
shader-db results on Mali-G52 follow, results on Mali-G57 were similar. Note the
shader that's hurt for spills/fills is *helped* for load/store overall.
cycles helped: 129 -> 98 (-24.03%) (spills: 17 -> 20 (17.65%); fills: 34 -> 40 (17.65%))
ldst helped: 129 -> 98 (-24.03%) (spills: 17 -> 20 (17.65%); fills: 34 -> 40 (17.65%))
total instructions in shared programs: 2415410 -> 2415372 (<.01%)
instructions in affected programs: 1041 -> 1003 (-3.65%)
helped: 3
HURT: 0
helped stats (abs) min: 2.0 max: 31.0 x̄: 12.67 x̃: 5
helped stats (rel) min: 2.08% max: 6.02% x̄: 3.90% x̃: 3.60%
total tuples in shared programs: 1928558 -> 1928527 (<.01%)
tuples in affected programs: 826 -> 795 (-3.75%)
helped: 2
HURT: 1
helped stats (abs) min: 6.0 max: 26.0 x̄: 16.00 x̃: 16
helped stats (rel) min: 3.72% max: 9.68% x̄: 6.70% x̃: 6.70%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 1.54% max: 1.54% x̄: 1.54% x̃: 1.54%
total clauses in shared programs: 355013 -> 354981 (<.01%)
clauses in affected programs: 220 -> 188 (-14.55%)
helped: 3
HURT: 0
helped stats (abs) min: 2.0 max: 27.0 x̄: 10.67 x̃: 3
helped stats (rel) min: 13.99% max: 21.43% x̄: 16.93% x̃: 15.38%
total cycles in shared programs: 166610.27 -> 166574.90 (-0.02%)
cycles in affected programs: 138 -> 102.62 (-25.63%)
helped: 3
HURT: 0
helped stats (abs) min: 0.
4583330000000001 max: 31.0 x̄: 11.79 x̃: 3
helped stats (rel) min: 15.28% max: 65.28% x̄: 34.86% x̃: 24.03%
total arith in shared programs: 73690.13 -> 73690.58 (<.01%)
arith in affected programs: 29.71 -> 30.17 (1.54%)
helped: 1
HURT: 2
helped stats (abs) min: 0.
0833339999999998 max: 0.
0833339999999998 x̄: 0.08 x̃: 0
helped stats (rel) min: 3.85% max: 3.85% x̄: 3.85% x̃: 3.85%
HURT stats (abs) min: 0.125 max: 0.
4166659999999993 x̄: 0.27 x̃: 0
HURT stats (rel) min: 1.66% max: 5.17% x̄: 3.42% x̃: 3.42%
total ldst in shared programs: 135611 -> 135571 (-0.03%)
ldst in affected programs: 138 -> 98 (-28.99%)
helped: 3
HURT: 0
helped stats (abs) min: 3.0 max: 31.0 x̄: 13.33 x̃: 6
helped stats (rel) min: 24.03% max: 100.00% x̄: 74.68% x̃: 100.00%
total quadwords in shared programs: 1674599 -> 1674523 (<.01%)
quadwords in affected programs: 838 -> 762 (-9.07%)
helped: 3
HURT: 0
helped stats (abs) min: 2.0 max: 65.0 x̄: 25.33 x̃: 9
helped stats (rel) min: 3.39% max: 15.00% x̄: 9.14% x̃: 9.04%
total spills in shared programs: 37 -> 40 (8.11%)
spills in affected programs: 17 -> 20 (17.65%)
helped: 0
HURT: 1
total fills in shared programs: 190 -> 196 (3.16%)
fills in affected programs: 34 -> 40 (17.65%)
helped: 0
HURT: 1
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17101>
Alyssa Rosenzweig [Fri, 17 Jun 2022 15:59:09 +0000 (11:59 -0400)]
pan/va: Replace MKVEC.v4i8 with MKVEC.v2i8
This is the instruction that the hardware actually supports. Do the rename, use
the more specific accurate model in the IR, and rework the Valhall texturing
code to emit MKVEC.v2i8 instead of MKVEC.v4i8.
Will fix:
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.*
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17101>
Alyssa Rosenzweig [Fri, 17 Jun 2022 15:56:21 +0000 (11:56 -0400)]
pan/va: Pack MKVEC.v2i8 byte lanes
They are in a different place, but the encoding is otherwise as usual. This will
be required for texture gathers with dynamic offsets.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17101>
Alyssa Rosenzweig [Fri, 17 Jun 2022 15:55:23 +0000 (11:55 -0400)]
pan/bi: Constant fold MKVEC.v2i8
Constant MKVEC.v2i8 will be generated during texturing on Valhall, just like
constant MKVEC.v4i8 is currently generated.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17101>
Alyssa Rosenzweig [Fri, 17 Jun 2022 15:53:53 +0000 (11:53 -0400)]
pan/bi: Model MKVEC.v2i8
Valhall does not have Bifrost's 4-source MKVEC.v4i8. Instead, it has a (somewhat
limtied) 3-source MKVEC.v2i8. The full MKVEC.v4i8 may be lowered to a pair of
MKVEC.v2i8 instructions.
For good code quality on both Bifrost and Valhall, we need to model both
instructions in their full generality.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17101>
Alyssa Rosenzweig [Fri, 17 Jun 2022 15:35:41 +0000 (11:35 -0400)]
pan/bi: Remove FRSCALE from IR
It's just LDEXP in different clothing.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17101>
Alyssa Rosenzweig [Fri, 17 Jun 2022 15:34:51 +0000 (11:34 -0400)]
pan/va: Rename RSCALE to LDEXP
This avoids needless variation from Bifrost. While at it, fix the opcode
definition: there are no abs/neg/swizzle modifiers on the signed integer source,
and there's no clamp. However, there are round and infinity modes, like on
Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17101>
Alyssa Rosenzweig [Fri, 17 Jun 2022 14:47:23 +0000 (10:47 -0400)]
pan/va: Implement sample positions FAU packing
This will fix:
dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_offset.at_sample_position.default_framebuffer
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17101>
Alyssa Rosenzweig [Fri, 17 Jun 2022 14:40:27 +0000 (10:40 -0400)]
pan/va: Lower FADD_RSCALE.f32 to FMA_RSCALE.f32
We generate FADD_RSCALE.f32 in our sample variables implementations. Valhall
doesn't have a dedicated FADD_RSCALE.f32 implementation, it should be aliased to
FMA_RSCALE.f32. Handle that alias in isel lowering. This will fix:
dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_offset.*
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17101>
Alyssa Rosenzweig [Thu, 16 Jun 2022 23:14:58 +0000 (19:14 -0400)]
pan/bi: Align accesses with packed TLS
When lowering vars to scratch, we need to be careful with alignment on Valhall,
where packed TLS access must not straddle a 16-byte boundary. Fixes regressions
when enabling indirect access to temps on Valhall.
Fixes:
6761dbf8915 ("panfrost: Use packed TLS on Valhall")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17101>
Alyssa Rosenzweig [Thu, 16 Jun 2022 23:04:13 +0000 (19:04 -0400)]
pan/bi: Fix LD_BUFFER.i16 definition
This was missing the message, breaking UBO-to-push and who-knows-what-else, when
enabling fp16 const buffers.
Fixes:
3dc2095b079 ("pan/bi: Model LD_BUFFER instructions")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17101>
Alyssa Rosenzweig [Wed, 15 Jun 2022 21:19:56 +0000 (17:19 -0400)]
pan/va: Unit test va_mark_last
This pass is super easy to unit test, so we have no excuse not to test
thoroughly. va_mark_last only inserts annotations in a shader without any
annotations, so our test cases are simply annotated shaders. The CASE macro just
has to compare the case against the case with the annotations stripped and added
back with va_mark_last.
In retrospect, I should have used that technique for the flow control insertion
tests too.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
Alyssa Rosenzweig [Wed, 15 Jun 2022 20:52:39 +0000 (16:52 -0400)]
pan/va: Mark last register reads
On Valhall, register reads may be marked as "last" [1]. Setting the last flag
promises the hardware that the value of the register is no longer required. This
may enable hardware optimizations. In particular, it may permit the hardware to
avoid register file writes if a write to the marked register is still in the
forwarding buffer. This may improve power efficiency.
In principle, this is trivial: run liveness analysis and mark killed sources,
like we would in an SSA-based register allocator. In practice, there are a few
wrinkles to avoid hazards around staging registers and 64-bit register pairs,
requiring some additional data flow analysis and fix ups. However, nothing here
is particularly "hard", and all the ideas are already in use for the Bifrost
scheduler and the Bifrost/Valhall scoreboard analyses.
[1] In Mesa's compiler, this is called discard for historical reasons.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
Alyssa Rosenzweig [Thu, 16 Jun 2022 19:16:30 +0000 (15:16 -0400)]
pan/va: Use validate_register_pair for BLEND pack
Instead of open-coding. Noticed by inspection.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
Alyssa Rosenzweig [Thu, 16 Jun 2022 19:46:22 +0000 (15:46 -0400)]
pan/va: Include BLEND for va_swap_12
This helps "contain the crazy" and avoids special casing BLEND in compiler
passes. The Valhall instruction is roughly the same as its Bifrost counterpart,
as long as we fix up the source order (as we already do for bitwise operations)
everything works out.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
Alyssa Rosenzweig [Thu, 16 Jun 2022 18:50:09 +0000 (14:50 -0400)]
pan/va: Move va_flow_is_wait_or_none to common
We want to use this helper in the "mark last" pass too.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
Alyssa Rosenzweig [Thu, 16 Jun 2022 18:49:41 +0000 (14:49 -0400)]
pan/va: Add header guards to valhall_enums.h
Otherwise we can't #include in multiple places.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
Alyssa Rosenzweig [Thu, 16 Jun 2022 18:47:05 +0000 (14:47 -0400)]
pan/bi: Constify bi_is_staging_src argument
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
Alyssa Rosenzweig [Thu, 16 Jun 2022 16:14:20 +0000 (12:14 -0400)]
pan/bi: Mark bi_postra_liveness_ins as MUST_CHECK
Post-RA liveness relies on the caller updating the live variable with the
results of bi_postra_liveness_ins. It is not automatic, as with regular
liveness. This means ignoring the result of bi_postra_liveness_ins is surely an
error. Mark it as MUST_CHECK to catch that error at compile time.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
Alyssa Rosenzweig [Mon, 20 Jun 2022 20:49:27 +0000 (16:49 -0400)]
pan/va: Unit test barrier handling
Add a unit test for the quirk discovered in the previos commit, because this
will cause flakes (instead of fails) if we get it wrong. Better have a
deterministic fail mode.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
Alyssa Rosenzweig [Mon, 20 Jun 2022 20:52:19 +0000 (16:52 -0400)]
pan/va: Workaround quirk of barrier handling
For some unknown reason, waiting for general slots (at least for memory stores)
doesn't work properly on a BARRIER instruction. We need to wait for all general
slots right before issuing the BARRIER in addition to the general wait on the
BARRIER itself. I don't know if this is a hardware bug or some hideous
gate-saving quirk, but I observe the Mali-G78 DDK using the same workaround,
which implies this really is necessary.
Fixes rare flakes in:
dEQP-GLES31.functional.compute.shared_var.work_group_size.float_128_1_1
Note that the flakes from that test are extremely timing dependent. Without this
change, that test is racy but we almost always win the race. Reproducing the
issue reliably requires high system load (e.g. running the CTS in the
background) and simultaneously running that test a large number of times.
Minimal shader-db impact. In particular, no cycle count regressions.
total instructions in shared programs: 2699419 -> 2699458 (<.01%)
instructions in affected programs: 22014 -> 22053 (0.18%)
helped: 2
HURT: 25
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.12% max: 0.12% x̄: 0.12% x̃: 0.12%
HURT stats (abs) min: 1.0 max: 3.0 x̄: 1.64 x̃: 1
HURT stats (rel) min: 0.07% max: 2.82% x̄: 0.69% x̃: 0.49%
95% mean confidence interval for instructions value: 1.01 1.87
95% mean confidence interval for instructions %-change: 0.38% 0.88%
Instructions are HURT.
total cvt in shared programs: 14468.81 -> 14469.42 (<.01%)
cvt in affected programs: 221.33 -> 221.94 (0.28%)
helped: 2
HURT: 25
helped stats (abs) min: 0.015625 max: 0.015625 x̄: 0.02 x̃: 0
helped stats (rel) min: 0.18% max: 0.18% x̄: 0.18% x̃: 0.18%
HURT stats (abs) min: 0.015625 max: 0.046875 x̄: 0.03 x̃: 0
HURT stats (rel) min: 0.10% max: 4.44% x̄: 1.06% x̃: 0.79%
95% mean confidence interval for cvt value: 0.02 0.03
95% mean confidence interval for cvt %-change: 0.57% 1.36%
Cvt are HURT.
total quadwords in shared programs: 1462496 -> 1462528 (<.01%)
quadwords in affected programs: 4632 -> 4664 (0.69%)
helped: 0
HURT: 4
HURT stats (abs) min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
HURT stats (rel) min: 0.35% max: 7.69% x̄: 4.03% x̃: 4.03%
95% mean confidence interval for quadwords value: 8.00 8.00
95% mean confidence interval for quadwords %-change: -2.71% 10.76%
Inconclusive result (%-change mean confidence interval includes 0).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
Alyssa Rosenzweig [Thu, 16 Jun 2022 18:34:41 +0000 (14:34 -0400)]
pan/va: Simplify insert flow tests
Test cases for insert flow are necessarily the reference test cases with the
NOPs stripped out. That means we don't need to duplicate the test bodies.
Deduplicate.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
Alyssa Rosenzweig [Thu, 16 Jun 2022 20:38:35 +0000 (16:38 -0400)]
pan/va: Move VA_NUM_GENERAL_SLOTS to common
This definition is a hardware property. It's not specific to the flow control
insertion pass, so move it to common code where other passes can use it.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
Emma Anholt [Thu, 16 Jun 2022 22:26:53 +0000 (15:26 -0700)]
ci: Remove the unused .test-manual
Everyone uses .test-manual-mr now, retire the one you don't want.
Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17096>
Emma Anholt [Thu, 16 Jun 2022 21:38:50 +0000 (14:38 -0700)]
ci/bare-metal: Add test phase timeouts to all boards.
This should help with "marge got stuck for an hour and all I got was this
failed job with no results/" when a system intermittently wedges.
This replaces the BM_POE_TIMEOUT ("did we get something on serial in the
last 3 minutes?") that rpi had, in favor of checking that the whole test
job gets through in 20 minutes.
Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17096>
Emma Anholt [Thu, 16 Jun 2022 21:18:35 +0000 (14:18 -0700)]
ci/bare-metal: Add handling of netboot firmwares for servo boards.
My local trogdor has a netboot firmware and I want to be able to use it to
test the timeout code I'm working on.
Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17096>
Emma Anholt [Thu, 16 Jun 2022 21:05:38 +0000 (14:05 -0700)]
ci/bare-metal: Get rid of servo's serial feed threads.
If the SerialBuffers can just feed the same line queue, then we don't need
the extra threads reading line queues into a new merged line queue.
Less python threading code is always better. Plus, now we can pass args
to SerialBuffer.lines() for timeout/phase.
Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17096>
Emma Anholt [Thu, 16 Jun 2022 20:37:55 +0000 (13:37 -0700)]
ci/bare-metal: Add per-boot-stage timeouts for fastboot and poe.
This should avoid the 1-hour timeouts if something goes wrong, and just
restart.
Fixes: #6682
Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17096>
Emma Anholt [Thu, 16 Jun 2022 21:55:45 +0000 (14:55 -0700)]
ci/bare-metal: Apply autopep8 to our python scripts.
My editor likes to pep8 as I edit, and I'm tired of carefully not
committing those changes.
Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17096>
Danylo Piliaiev [Tue, 21 Jun 2022 09:46:49 +0000 (12:46 +0300)]
tu: Reset xfb_used at the end of a renderpass
Otherwise xfb_used could be true until the end of command buffer,
which is not what we intended it to be.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17162>
Emma Anholt [Tue, 7 Jun 2022 21:08:52 +0000 (14:08 -0700)]
turnip: Document some fields about resolves.
I noticed the unk12 pattern, and cwabbott and danylo had figured out some
more details.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17126>
Emma Anholt [Wed, 1 Jun 2022 19:29:07 +0000 (12:29 -0700)]
ci: Terminate capture-devcoredump before tarring up artifacts.
Every few weeks we'd get a flake where the script noticed the devcore
right as we were wrapping up, and then tar would exit because the file it
was tarring changed underneath it. Just kill devcores before we do that
-- even if we kill it while it's working, it's so rare that it probably
won't bother anyone.
Fixes: #5867
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16820>
Lionel Landwerlin [Mon, 20 Jun 2022 13:00:38 +0000 (13:00 +0000)]
vulkan/wsi: fix crash with debug names on swapchain
If you set a name of on a swapchain object, because the base object
struct has not been initialized with a VkDevice,
vk_object_base_finish() will segfault when trying to free the object
name.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
cb1e0db23e3f ("vulkan/wsi: Make wsi_swapchain inherit from vk_object_base")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17165>
Lionel Landwerlin [Sun, 12 Jun 2022 20:54:12 +0000 (23:54 +0300)]
anv: fix index buffer emission
In the following case :
vkCmdBindPipeline(compute_pipeline);
vkCmdDispatch(...);
vkCmdBindPipeline(graphics_pipeline);
vkCmdBindIndexBuffer(buffer)
vkCmdDraw(...);
We're emitting the 3DSTATE_INDEX_BUFFER instruction while the HW is
still in GPGPU mode, because we're dealing the pipeline selection to
vkCmdDraw().
Found while debugging Age Of Empire 4, HW is hung on
3DSTATE_INDEX_BUFFER instruction.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17153>
Timur Kristóf [Wed, 8 Jun 2022 16:26:16 +0000 (18:26 +0200)]
zink: Always enable depth clamping, make depth clipping independent.
Enabling depth clamping ensures that the Vulkan driver respects
the depth range that zink sets on viewport objects in zink_draw.
When depth clipping is required, use VK_EXT_depth_clip_enable to
enable that independently of depth clamping.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16929>
Timur Kristóf [Wed, 8 Jun 2022 16:25:54 +0000 (18:25 +0200)]
zink: Enable the VK_EXT_depth_clip_enable extension.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16929>
Timur Kristóf [Wed, 8 Jun 2022 18:13:24 +0000 (20:13 +0200)]
gallium/u_blitter: Fix depth.
Fix the transform to make sure it doesn't disturb the depth range
of the blitted image. Set the Z coordinates of the vertices
by hand instead of relying on the transform to do it.
This is a pre-requisite to Zink always enabling depth clamping.
Fixes:
26c6640835936a77d87030ce8e90f9b9f5be783e
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16929>
Sarah Walker [Fri, 27 May 2022 13:51:39 +0000 (14:51 +0100)]
pvr: Update for firmware 1.17@6256262
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17139>
Erik Faye-Lund [Tue, 21 Jun 2022 08:40:28 +0000 (10:40 +0200)]
docs: set language to english
It seems recent versions of Sphinx has started issuing a warning when
language isn't set to a recognized value. Since we're building with
warnings as errors on CI, this causes issues for people.
We're writing English docs, so we should set this to English. I probably
confused this setting with the highlight_language setting or something
when I set this up initially.
Fixes:
00cd1346bf0 ("docs: use sphinx")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6711
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17159>
Danylo Piliaiev [Mon, 20 Jun 2022 12:59:36 +0000 (15:59 +0300)]
tu: Disable sample counting for 3d blits during occlusion query
Per Vulkan spec only "Draw" commands should be counted towards
occlusion query.
Apparently RB_SAMPLE_COUNT_CONTROL::UNK0 bool controls whether
sample counting is enabled, so we could use it to disable
sample counting for 3d blits which are sometimes used for
clear/copy/blit/gmem-store/resolve operations.
Fixes GL CTS tests running through Zink:
dEQP-GLES3.functional.occlusion_query.depth_clear
dEQP-GLES3.functional.occlusion_query.depth_clear_stencil_clear
dEQP-GLES3.functional.occlusion_query.scissor_depth_clear_stencil_clear
dEQP-GLES3.functional.occlusion_query.scissor_stencil_clear
dEQP-GLES3.functional.occlusion_query.stencil_clear
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6559
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17138>
Gert Wollny [Sun, 17 Apr 2022 09:51:58 +0000 (11:51 +0200)]
virgl: Don't let ntt optimize the register allocation
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15995>
Martin Roukala (né Peres) [Mon, 20 Jun 2022 07:40:15 +0000 (10:40 +0300)]
ci/radv: add a missing flake
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17131>
Martin Roukala (né Peres) [Mon, 20 Jun 2022 07:31:24 +0000 (10:31 +0300)]
ci/radv: move a test from the fail list to the flake list
The test was misidentified as a "fail", when it actually has a very
high failure rate (>95%). The test happened to pass twice within the
last week, so let's mark this test as a flake.
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17131>
Boris Brezillon [Tue, 21 Jun 2022 06:59:13 +0000 (23:59 -0700)]
dzn: Fix the 2DMSArray case in dzn_image_get_dsv_desc()
Texture2DMSArray element is not initialized, making 2DMSArray DS
views buggy.
Reported-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17158>
Samuel Pitoiset [Thu, 16 Jun 2022 14:32:56 +0000 (16:32 +0200)]
radv,aco: rename radv_prolog_binary/radv_shader_prolog to shader_part
The same structures and functions will be re-used for PS epilogs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17084>
Christian Gmeiner [Sun, 19 Jun 2022 12:44:37 +0000 (14:44 +0200)]
ir3: Create at least one thread for async shader compile
On a single core CPU system we end with num_threads being 0 and we do
_NOT_ create any async compile threads in util_queue_init(..).
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17124>
Christian Gmeiner [Sun, 19 Jun 2022 12:36:08 +0000 (14:36 +0200)]
freedreno: Wait for async compile jobs to finish
initial_variants_synchronous(..) allows initial shader variant
compilation asynchronously if debug.debug_message == NULL. If the
debug callback gets changed it seems like a good idea to wait until
all async shader compiles are done.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17124>
Vinson Lee [Thu, 16 Jun 2022 22:30:23 +0000 (15:30 -0700)]
microsoft/compiler: Fix assert.
Fix defect reported by Coverity Scan.
Side effect in assertion (ASSERT_SIDE_EFFECT)
assignment_where_comparison_intended: Assignment var->type =
glsl_int_type() has a side effect. This code will work differently in a
non-debug build.
Fixes:
afb64e10c1f ("microsoft/compiler: Move d3d12_fix_io_uint_type() to dxil_nir.c")
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17097>
Vinson Lee [Thu, 16 Jun 2022 23:03:20 +0000 (16:03 -0700)]
radv: Remove unnecessary null check.
Fix defect reported by Coverity Scan.
Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking subpass suggests that it may be null,
but it has already been dereferenced on all paths leading to the check.
Fixes:
779e09639b5 ("radv: configure DB_Z_INFO.NUM_SAMPLES correctly on GFX11")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17100>
David Heidelberg [Mon, 20 Jun 2022 13:34:53 +0000 (15:34 +0200)]
ci: Uprev apitrace to
790380e05854
Better context error reporting, fix crash for replaying PlagueIncEvolved
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17136>
Filip Gawin [Sat, 18 Jun 2022 11:57:14 +0000 (13:57 +0200)]
r300: prefer old not native swizzle in constant folding
r300 and r400 have strict rules with swizzles, so we
will need to convert swizzle back.
Operating on 0, 1, H in this case unnecessarily makes
rest of r300 overly complicated.
(also it's not currently able to handle this)
helps with:
deqp-gles2@functional@shaders@random@exponential@fragment@24
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17117>
Alyssa Rosenzweig [Wed, 15 Jun 2022 20:06:00 +0000 (16:06 -0400)]
panfrost: Implement provoking vertices on Valhall
Starting with Valhall, the provoking vertex state is specified per-framebuffer
(batch) instead of per-draw. We use the pan_tristate infrastructure to translate
between desktop OpenGL's per-draw semantics to Valhall's per-framebuffer
semantic. This is notably not required for GLES or Vulkan.
If the provoking vertex is unset when the tiler context is generated, it could
be set (incompatibly) later in the batch, and the tiler context's provoking
vertex field would no longer match the framebuffer's. That would violate a
hardware invariant. To ensure that doesn't happen, we make sure to set provoking
vertexes *before* generating the tiler context so it can't change after.
Fixes arb-provoking-vertex-render on Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17068>
Alyssa Rosenzweig [Wed, 15 Jun 2022 20:03:32 +0000 (16:03 -0400)]
panfrost: Add tristate_is_defined helper
This is useful to ensure that the tri-state has been set. It could be inlined,
but the tri-state structure is designed to be opaque so this matches better.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17068>
Alyssa Rosenzweig [Wed, 15 Jun 2022 19:54:08 +0000 (15:54 -0400)]
panfrost: Fix batch state changes on Valhall
If we need to change batch state (currently just point coord origins), not only
do we need to flush the old batch, but also set the desired state on the new
batch. That second step was missing. Fix that so this mechanism works as
intended.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Fixes:
3641dfe4367 ("panfrost: Flip point coords in hardware")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17068>
Alyssa Rosenzweig [Wed, 15 Jun 2022 19:56:24 +0000 (15:56 -0400)]
panfrost: Disable QUADS on Valhall
Even with the fixes in the rest of the series, arb-provoking-vertex-render is
still failing on Valhall for a single subcase (involving QUADS). It seems likely
that QUADS support is broken on Valhall, given it's not used in any of the APIs
for which Arm ships drivers.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17068>
Marcin Ślusarz [Mon, 13 Jun 2022 12:44:30 +0000 (14:44 +0200)]
intel/compiler: vectorize task payload loads/stores
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17000>
Marcin Ślusarz [Mon, 13 Jun 2022 12:43:45 +0000 (14:43 +0200)]
nir/opt_load_store_vectorize: handle task payloads
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17000>
Karmjit Mahil [Wed, 15 Jun 2022 14:35:14 +0000 (15:35 +0100)]
pvr: Extend hard coding infra to allow per stage per device coding.
This commit extends the graphics hard coding infrastructure to
allow the independent hard coding of stages, i.e. hard code fragment
stage and vertex stage separately instead of having to hard code
everything.
It also extends the infrastructure to allow per device hard coding.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17106>
Karmjit Mahil [Wed, 11 May 2022 12:39:21 +0000 (13:39 +0100)]
pvr: Enable 33.15.11.3 (AXE-1-16M).
This commit adds 33.15.11.3 in the supported BVNCs and addresses
differences in the descriptor limits between devices so that the
physical device limit is accurate.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17106>
Frank Binns [Thu, 24 Mar 2022 14:47:03 +0000 (14:47 +0000)]
pvr: Add TI AM62 as a supported device.
The AM62 platform contains an IMG AXE-1-16M GPU.
Co-Authored-By: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17106>
David Heidelberg [Mon, 20 Jun 2022 13:23:21 +0000 (15:23 +0200)]
ci/freedreno: disable non-existing trace
Never existed in the repository.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17137>
Juan A. Suarez Romero [Mon, 20 Jun 2022 14:28:54 +0000 (16:28 +0200)]
v3dv/ci: Update expected results
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17141>
Boris Brezillon [Mon, 20 Jun 2022 12:14:54 +0000 (14:14 +0200)]
ci/dzn: Move to a .toml description
This way we don't force a CI run on all platforms anytime we add a
group of test, and, as a bonus, we make dozen CI consistent with other
platforms.
Suggested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Suggested-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17074>
David Heidelberg [Mon, 13 Jun 2022 22:03:34 +0000 (00:03 +0200)]
ci/freedreno: smuggle myself into restricted traces access list
Already have access into traces-db-restricted repository, so this just
allow me to trigger the job without patching.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17016>
David Heidelberg [Mon, 13 Jun 2022 21:44:06 +0000 (23:44 +0200)]
ci/freedreno: update restricted traces to the brotli compressed version
Save some space on proxies and speedup network transfer to the runners.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17016>
Matti Hamalainen [Thu, 16 Jun 2022 14:01:39 +0000 (17:01 +0300)]
gallium/tools: fixes to option handling
Not all options in the options object are set by all tools.
Instead of using argparse result objects directly, use separate
with default settings and copy relevant attributes there.
Signed-off-by: Matti Hamalainen <ccr@tnsp.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17108>
Mykhailo Skorokhodov [Sun, 19 Jun 2022 20:56:12 +0000 (23:56 +0300)]
anv: Use sampleLocationsEnable for sample locations
The spec says: "sampleLocationsEnable controls whether custom sample
locations are used. If sampleLocationsEnable is VK_FALSE, the default
sample locations are used and the values specified in
sampleLocationsInfo are ignored."
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6675
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17134>
Erik Faye-Lund [Mon, 20 Jun 2022 10:11:57 +0000 (12:11 +0200)]
dzn: correct order of src_subres and dst_subres args
Fixes:
2d0798440b4 ("dzn: Add support for dynamic rendering")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17133>
Georg Lehmann [Sun, 19 Jun 2022 20:16:28 +0000 (22:16 +0200)]
radv: Check descriptor pool entry count before allocating a new set.
It's simpler and more efficient.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17127>
Georg Lehmann [Sun, 19 Jun 2022 20:12:54 +0000 (22:12 +0200)]
radv: Remove redundant memset in radv_descriptor_set_create.
The memset below also clears this memory, plus the descriptor set header.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17127>
Karmjit Mahil [Tue, 7 Jun 2022 14:29:46 +0000 (15:29 +0100)]
pvr: Add graphics pipeline hard coding infrastructure.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16999>
Karmjit Mahil [Mon, 6 Jun 2022 13:59:23 +0000 (14:59 +0100)]
pvr: Remove unused output_selects from vertex shader state.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16999>
Karmjit Mahil [Wed, 1 Jun 2022 14:04:59 +0000 (15:04 +0100)]
pvr: Change compute hard coding infrastructure.
This commit changes the way in which the hard coding is done in
the compute pipeline to allow easier hard coding for demos other
than the simple-compute demo.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16999>
Marcin Ślusarz [Wed, 15 Jun 2022 17:21:23 +0000 (19:21 +0200)]
intel/dev: fixup max_cs_workgroup_threads after hwconfig is read
Without it we get max value from gfx12 on gfx>12.
Fixes:
d9ff9ea9c33 ("intel/dev: Read hwconfig from i915")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17063>
Samuel Pitoiset [Thu, 16 Jun 2022 12:49:24 +0000 (14:49 +0200)]
aco: fix validation of SOP1 instructions without definitions
Like s_setpc_b64.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17082>
Samuel Pitoiset [Thu, 16 Jun 2022 15:20:14 +0000 (17:20 +0200)]
radv/amdgpu: do not add "global" BO to the virtual BO list
To avoid dangling BO references if it's destroyed without being
previously unbound. This is under Vulkan spec clarification but it
looks like the "global" BO fix is simple enough to workaround the
issue for now.
This fixes a CPU hang with Halo Infinite because the kernel rejects
a submission (invalid BO handle found).
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17085>
Samuel Pitoiset [Fri, 17 Jun 2022 07:10:00 +0000 (09:10 +0200)]
radv/amdgpu: make sure to reset the number of BO when there is no ranges
If an application binds a sparse resource and then unbind it with NULL,
the number of "real" BOs in the virtual BO list should be reset to 0.
Otherwise, it might use a dangling BO reference if it's destroyed just
after being unbound.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17085>
Samuel Pitoiset [Fri, 17 Jun 2022 07:25:14 +0000 (09:25 +0200)]
ci: uprev vkd3d-proton to
39d07dea2cef34bfb3ed39741f026bc637e3eec4
The 2.6 version is old (released 4 months ago), the latest contains
even more useful tests (+2900 tests). Use the master branch by default,
so it could be regularly updated.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17105>
Mike Blumenkrantz [Mon, 20 Jun 2022 00:49:37 +0000 (20:49 -0400)]
zink: ci updates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
Mike Blumenkrantz [Sat, 18 Jun 2022 14:05:55 +0000 (10:05 -0400)]
zink: relax zink_resource_buffer_needs_barrier checks
this now matches zink_resource_image_needs_barrier
cc: mesa-stable
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
Mike Blumenkrantz [Sat, 18 Jun 2022 13:48:51 +0000 (09:48 -0400)]
zink: don't short-circuit gfx stage finding during barrier generation
according to spec, all stages must be specified, not just the first one
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
Mike Blumenkrantz [Sat, 18 Jun 2022 13:47:13 +0000 (09:47 -0400)]
zink: collect gfx stages for all bindings during barrier generation
it's important to get the full mask in order to accurately provide
dependency info
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
Mike Blumenkrantz [Sat, 18 Jun 2022 13:43:01 +0000 (09:43 -0400)]
zink: add a #define for vk shader bits
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
Mike Blumenkrantz [Sat, 18 Jun 2022 13:41:43 +0000 (09:41 -0400)]
zink: track image binds
track all the things
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
Mike Blumenkrantz [Fri, 17 Jun 2022 14:55:37 +0000 (10:55 -0400)]
zink: rework buffer barrier generation
by passing through the draw buffers, more accurate barriers can be generated
to ensure synchronization for both the draw buffer scopes and
descriptor binding scopes
ref #6597
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
Mike Blumenkrantz [Fri, 17 Jun 2022 14:55:10 +0000 (10:55 -0400)]
zink: track vertex buffer bind counts on resources
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
Mike Blumenkrantz [Fri, 17 Jun 2022 14:14:00 +0000 (10:14 -0400)]
zink: move draw-time barrier generation down a little
ensure that this occurs after potential rebind handling
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
Mike Blumenkrantz [Thu, 16 Jun 2022 20:58:37 +0000 (16:58 -0400)]
mesa/st: increment num_uniforms for hw accel select shaders
this otherwise breaks nir_lower_uniforms_to_ubo() and probably lots
of drivers
Fixes:
9b22ab4167e ("mesa/st: implement hardware accelerated GL_SELECT")
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17092>
Mike Blumenkrantz [Wed, 23 Sep 2020 14:08:02 +0000 (10:08 -0400)]
zink: unset PIPE_CAP_DITHERING
there's no point in updating blend state for this when it does nothing,
so skip updates for this functionality
in the future, I expect zink will export this conditionally based on
the underlying driver, and some sort of functionality will be implemented
to do something
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17043>
Mike Blumenkrantz [Wed, 23 Sep 2020 14:06:53 +0000 (10:06 -0400)]
mesa/st: add PIPE_CAP_DITHERING
this is for drivers like zink that may or may not
handle dithering and so getting blend state changes
when this state changes isn't useful
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17043>
Martin Roukala (né Peres) [Thu, 16 Jun 2022 13:39:32 +0000 (16:39 +0300)]
radv/ci: test vkd3d on kabini
The machine is extremely slow and fails to finish vkcts, but vkd3d may
still be used as a way to detect extreme regressions.
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17081>
Martin Roukala (né Peres) [Sat, 18 Jun 2022 14:48:34 +0000 (17:48 +0300)]
Revert "ci/valve: uprev boot2container"
This reverts commit
48243965723e53f283d7c9fbfc801c1406795e31.
The newest version of b2c has changed the mount point of the cache
device, which is has proven to be working very well in my local
testing, but ends up confusing podman when the cache device had been
initialized using an older version of b2c. The end result is that we
end up using tmpfs to run our jobs, and some machines just run out of
RAM before the end of the job...
We'll be fixing this issue, cut a new b2c release, then re-introduce
in Mesa.
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17120>
Jason Ekstrand [Wed, 15 Jun 2022 17:05:51 +0000 (12:05 -0500)]
anv: Properly clamp attachment layer counts
Vulkan requires that the acutal layer count come from
VkRenderingInfo::layerCount or VkFramebufferCreateInfo::layers rather
than from the image view itself.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17060>
Chia-I Wu [Fri, 20 May 2022 23:49:42 +0000 (16:49 -0700)]
freedreno/fdl: use XYZW swap for PIPE_FORMAT_X24S8_UINT
We used to use WZYX and apply swizzles. Because swizzles apply for
border colors as well, the gallium driver un-swizzled the border colors
to cancel out swizzles. That did not work for turnip because turnip
advertises customBorderColorWithoutFormat and does not know when to
un-swizzle.
This change replaces WZYX by XYZW and removes the swizzles.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6516
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16647>
Icecream95 [Fri, 10 Jun 2022 11:03:33 +0000 (23:03 +1200)]
panfrost: Remove sync arguments from panfrost_batch_submit
Whether a sync object is used cannot depend on where the batch is
submitted from, remove the in_sync and out_sync fields from
panfrost_batch_submit.
Always use an output syncobj, this is required for glFinish to work
correctly. This could be skipped for batches which another batch
depends on, but because of the existence of empty batches which emit
no job, doing so is not trivial.
Never use an input syncobj. There appears to be no point to this, the
kernel driver does implicit sync anyway.
Fixes "seconds per frame" rendering with Neverball; previously, every
batch was submitted with out_sync=0, so DRI's frame throttling could
do nothing. New jobs would keep getting submitted until more than a
thousand were queued in the kernel, which increased rendering latency
for the compositor far beyond acceptable levels.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16966>
Icecream95 [Fri, 10 Jun 2022 10:51:07 +0000 (22:51 +1200)]
panfrost: Use a macro for checking for a shared bind type
PAN_BIND_SHARED_MASK is all binding flags that mean that a resource
might be shared and accessible by other contexts.
Don't replace the usage of this pattern in panfrost_should_afbc and
panfrost_should_tile in case a new binding is introduced that not all
layouts can support.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16966>
Andres Calderon Jaramillo [Sat, 21 May 2022 23:27:34 +0000 (23:27 +0000)]
mesa/st: Account for YUV color space and range.
This patch plumbs the YUV color space and range provided through
EGL_EXT_image_dma_buf_import all the way to nir_lower_tex().
NIR already accounts for the YUV color space courtesy of commit
d8fdb8da. However, the color space was wired only for i965/i915 (see
6c11a799) and not for Gallium.
Tested-by: Andres Calderon Jaramillo <andrescj@chromium.org>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16651>
Andres Calderon Jaramillo [Sat, 21 May 2022 23:25:02 +0000 (23:25 +0000)]
nir: Account for YUV range.
This patch expands on what commit
d8fdb8dab4658de2d255718627ee671e84fedf2d did. It adds support for
YUV-to-RGB conversions depending on the range of the YUV samples.
The conversion matrices and offsets are derived from
https://gist.github.com/yohhoy/
dafa5a47dade85d8b40625261af3776a.
Tested-by: Andres Calderon Jaramillo <andrescj@chromium.org>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16651>
Ian Romanick [Tue, 14 Jun 2022 19:30:21 +0000 (12:30 -0700)]
intel/fs: Add missing synchronization for WaW dependency
v2: Do the synchronization in the correct place. Noticed by Curro.
Fixes:
b5fa43952aa ("intel/fs: Better handle constant sources of FS_OPCODE_PACK_HALF_2x16_SPLIT")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17037>
Rob Clark [Fri, 17 Jun 2022 13:13:41 +0000 (06:13 -0700)]
Revert "ci: freedreno farm is down"
They seem to be responding again.
This reverts commit
551442b53ebf531ab010dad2a3127ce41432ed4c.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17110>
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