GDB Administrator [Thu, 4 Jan 2024 00:01:45 +0000 (00:01 +0000)]
Automatic date update in version.in
Mike Frysinger [Wed, 3 Jan 2024 08:12:42 +0000 (03:12 -0500)]
sim: ppc: unify igen filter modules
The common igen code was forked from the ppc long ago. The filter
module is still pretty similar in API, so we can unfork them with
a little bit of effort.
The filter.c module is still here because of the unique it_is API.
The common igen code doesn't seem to have an equiv API as this only
operates on two strings and not an actual filter object, and it's
easy enough to leave behind to unfork the rest.
Mike Frysinger [Wed, 3 Jan 2024 07:54:37 +0000 (02:54 -0500)]
sim: ppc: unify igen line number output modules
The common igen code was forked from the ppc long ago. The lf module
is still pretty similar in API, so we can unfork them with a little
bit of effort.
Some of the generated ppc code is now slightly different, but that's
because of fixes the common igen code has gained, but not the ppc igen
code (e.g. fixing of #line numbers).
The ppc code retains lf_print__c_code because the common igen code
rewrote the logic to a new table.c API. Let's delay that in the ppc
code to at least unfork all this code.
Mike Frysinger [Wed, 3 Jan 2024 08:07:25 +0000 (03:07 -0500)]
sim: igen: clean up headers a bit
Add standard multiple inclusion protection, and add a few missing
local includes when one header uses another. This isn't complete,
but fixes some short comings seen when merging the ppc igen.
Mike Frysinger [Wed, 3 Jan 2024 07:17:16 +0000 (02:17 -0500)]
sim: ppc: switch to common endian code
The common sim-endian is a forked & updated version of the ppc code.
Fortunately, they didn't diverge from the basic APIs, so they are
still compatible, which means we can just delete the ppc version now
that the build env is merged at the top-level.
Mike Frysinger [Wed, 3 Jan 2024 07:15:54 +0000 (02:15 -0500)]
sim: common: include sim-types.h in the endian header directly
This is a bit redundant for most ports as they go through sim-basics.h
which always includes sim-types.h before including sim-endian.h, but in
order to unify ppc's sim-endian code, we need this include here. Plus,
it's the directly we generally want to go to get away from one header
that defines all APIs and causes hard to untangle dependencies.
Mike Frysinger [Wed, 3 Jan 2024 07:13:55 +0000 (02:13 -0500)]
sim: ppc: rename local ALU SIGNED64 macros
The common/ code has macros with the same name but different behavior:
it's for declaring integer constants as 64-bit, not for casting them.
Rename ppc's local variant since it's only used in this file in order
to avoid conflicts.
Mike Frysinger [Wed, 3 Jan 2024 07:10:52 +0000 (02:10 -0500)]
sim: ppc: sync WITH_TARGET_{ADDRESS,CELL}_BITSIZE with common/
This will make it easier to share common/ code that rely on these
additional defines.
Mike Frysinger [Wed, 3 Jan 2024 06:54:57 +0000 (01:54 -0500)]
sim: cr16: cleanup unused variable compiler warnings
Mike Frysinger [Wed, 3 Jan 2024 01:26:53 +0000 (20:26 -0500)]
sim: configure: switch to m4_map
Minor reduction in boilerplate here. No real functional changes.
Mike Frysinger [Tue, 2 Jan 2024 15:23:09 +0000 (10:23 -0500)]
sim: drop support for recursive makes entirely
Now that all ports have been merged to the top-level, we no longer need
this framework to pass settings down to sub-makefiles. Delete it all.
Mike Frysinger [Tue, 2 Jan 2024 14:58:07 +0000 (09:58 -0500)]
sim: ppc: hoist compilation up to top-level
This removes all recursive makes from the ppc port.
Mike Frysinger [Tue, 2 Jan 2024 15:02:39 +0000 (10:02 -0500)]
sim: drop support for automatic subdir recursion
No port relies on this anymore, so we can scrub it all.
Mike Frysinger [Tue, 2 Jan 2024 14:50:43 +0000 (09:50 -0500)]
sim: ppc: move libsim.a creation to top-level
The objects are still compiled in the subdir, but the creation of the
archive itself is in the top-level. This is a required step before we
can move compilation itself up, and makes it easier to review.
The downside is that each object compile is a recursive make instead of
a single one. It adds some overhead, so it's not great, but it shouldn't
be a big deal. This will go away once compilation is hoisted up.
Mike Frysinger [Tue, 2 Jan 2024 13:28:34 +0000 (08:28 -0500)]
sim: ppc: move main.o compilation to top-level
mengqinggang [Wed, 3 Jan 2024 03:27:35 +0000 (11:27 +0800)]
LoongArch: delete bfd/.elfnn-loongarch.c.swp
GDB Administrator [Wed, 3 Jan 2024 00:02:14 +0000 (00:02 +0000)]
Automatic date update in version.in
Carl Love [Tue, 2 Jan 2024 22:46:12 +0000 (17:46 -0500)]
Fix GDB reverse-step and reverse-next command behavior
Currently GDB when executing in reverse over multiple statements in a single
line of source code, GDB stops in the middle of the line. Thus requiring
multiple commands to reach the previous line. GDB should stop at the first
instruction of the line, not in the middle of the line.
The following description of the incorrect behavior was taken from an
earlier message by Pedro Alves <pedro@palves.net>:
https://sourceware.org/pipermail/gdb-patches/2023-January/196110.html
---------------------------------
The source line looks like:
func1 (); func2 ();
in the test case:
(gdb) list 1
1 void func1 ()
2 {
3 }
4
5 void func2 ()
6 {
7 }
8
9 int main ()
10 {
11 func1 (); func2 ();
12 }
compiled with:
$ gcc reverse.c -o reverse -g3 -O0
$ gcc -v
...
gcc version 11.3.0 (Ubuntu 11.3.0-1ubuntu1~22.04)
Now let's debug it with target record, using current gdb git master
(
f3d8ae90b236),
$ gdb ~/reverse
GNU gdb (GDB) 14.0.50.
20230124-git
...
Reading symbols from /home/pedro/reverse...
(gdb) start
Temporary breakpoint 1 at 0x1147: file reverse.c, line 11.
Starting program: /home/pedro/reverse
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
Temporary breakpoint 1, main () at reverse.c:11
11 func1 (); func2 ();
(gdb) record
(gdb) disassemble /s
Dump of assembler code for function main:
reverse.c:
10 {
0x000055555555513f <+0>: endbr64
0x0000555555555143 <+4>: push %rbp
0x0000555555555144 <+5>: mov %rsp,%rbp
11 func1 (); func2 ();
=> 0x0000555555555147 <+8>: mov $0x0,%eax
0x000055555555514c <+13>: call 0x555555555129 <func1>
0x0000555555555151 <+18>: mov $0x0,%eax
0x0000555555555156 <+23>: call 0x555555555134 <func2>
0x000055555555515b <+28>: mov $0x0,%eax
12 }
0x0000555555555160 <+33>: pop %rbp
0x0000555555555161 <+34>: ret
End of assembler dump.
(gdb) n
12 }
So far so good, a "next" stepped over the whole of line 11 and stopped at
line 12.
Let's confirm where we are now:
(gdb) disassemble /s
Dump of assembler code for function main:
reverse.c:
10 {
0x000055555555513f <+0>: endbr64
0x0000555555555143 <+4>: push %rbp
0x0000555555555144 <+5>: mov %rsp,%rbp
11 func1 (); func2 ();
0x0000555555555147 <+8>: mov $0x0,%eax
0x000055555555514c <+13>: call 0x555555555129 <func1>
0x0000555555555151 <+18>: mov $0x0,%eax
0x0000555555555156 <+23>: call 0x555555555134 <func2>
0x000055555555515b <+28>: mov $0x0,%eax
12 }
=> 0x0000555555555160 <+33>: pop %rbp
0x0000555555555161 <+34>: ret
End of assembler dump.
Good, we're at the first instruction of line 12.
Now let's undo the "next", with "reverse-next":
(gdb) reverse-next
11 func1 (); func2 ();
Seemingly stopped at line 11. Let's see exactly where:
(gdb) disassemble /s
Dump of assembler code for function main:
reverse.c:
10 {
0x000055555555513f <+0>: endbr64
0x0000555555555143 <+4>: push %rbp
0x0000555555555144 <+5>: mov %rsp,%rbp
11 func1 (); func2 ();
0x0000555555555147 <+8>: mov $0x0,%eax
0x000055555555514c <+13>: call 0x555555555129 <func1>
=> 0x0000555555555151 <+18>: mov $0x0,%eax
0x0000555555555156 <+23>: call 0x555555555134 <func2>
0x000055555555515b <+28>: mov $0x0,%eax
12 }
0x0000555555555160 <+33>: pop %rbp
0x0000555555555161 <+34>: ret
End of assembler dump.
(gdb)
And lo, we stopped in the middle of line 11! That is a bug, we should have
stepped back all the way to the beginning of the line. The "reverse-next"
should have fully undone the prior "next" command.
--------------------
This patch fixes the incorrect GDB behavior by ensuring that GDB stops at
the first instruction in the line.
The test case gdb.reverse/func-map-to-same-line.exp is added to testsuite
to verify this fix when the line table information is and is not available.
Carl Love [Tue, 2 Jan 2024 22:46:02 +0000 (17:46 -0500)]
PowerPC and aarch64: Fix reverse stepping failure
When running GDB's testsuite on aarch64-linux/Ubuntu 20.04 (also spotted on
the ppc backend), there are failures in gdb.reverse/solib-precsave.exp and
gdb.reverse/solib-reverse.exp.
The failure happens around the following code:
38 b[1] = shr2(17); /* middle part two */
40 b[0] = 6; b[1] = 9; /* generic statement, end part two */
42 shr1 ("message 1\n"); /* shr1 one */
Normal execution:
- step from line 38 will land on line 40.
- step from line 40 will land on line 42.
Reverse execution:
- step from line 42 will land on line 40.
- step from line 40 will land on line 40.
- step from line 40 will land on line 38.
The problem here is that line 40 contains two contiguous but distinct
PC ranges in the line table, like so:
Line 40 - [0x7ec ~ 0x7f4]
Line 40 - [0x7f4 ~ 0x7fc]
The two distinct ranges are generated because GCC started outputting source
column information, which GDB doesn't take into account at the moment.
When stepping forward from line 40, we skip both of these ranges and land on
line 42. When stepping backward from line 42, we stop at the start PC of the
second (or first, going backwards) range of line 40.
Since we've reached ecs->event_thread->control.step_range_start, we stop
stepping backwards.
The above issues were fixed by introducing a new function that looks for
adjacent PC ranges for the same line, until we notice a line change. Then
we take that as the start PC of the range. The new start PC for the range
is used for the control.step_range_start when setting up a step range.
The test case gdb.reverse/map-to-same-line.exp is added to test the fix
for the above reverse step issues.
Patch has been tested on PowerPC, X86 and AArch64 with no regressions.
Carl Love [Tue, 2 Jan 2024 22:45:55 +0000 (17:45 -0500)]
Add gdb_compile options column-info and no-column-info
This patch adds two new options to gdb_compile to specify if the compile
should or should not generate the line table information. The
options are supported on clang and gcc version 7 and newer.
Patch has been tested on PowerPC with both gcc and clang.
Guinevere Larsen [Wed, 1 Nov 2023 16:25:32 +0000 (17:25 +0100)]
gdb/dwarf2: Add support for DW_LNS_set_epilogue_begin in line-table
This commit adds a mechanism for GDB to detect the linetable opcode
DW_LNS_set_epilogue_begin. This opcode is set by compilers to indicate
that a certain instruction marks the point where the frame is destroyed.
While the standard allows for multiple points marked with epilogue_begin
in the same function, for performance reasons, the function that
searches for the epilogue address will only find the last address that
sets this flag for a given block.
This commit also changes amd64_stack_frame_destroyed_p_1 to attempt to
use the epilogue begin directly, and only if an epilogue can't be found
will it attempt heuristics based on the current instruction.
Finally, this commit also changes the dwarf assembler to be able to emit
epilogue-begin instructions, to make it easier to test this patch
Approved-By: Tom Tromey <tom@tromey.com>
Mike Frysinger [Tue, 2 Jan 2024 07:18:53 +0000 (02:18 -0500)]
sim: ppc: hoist pk.h creation to top-level
Mike Frysinger [Tue, 2 Jan 2024 07:11:11 +0000 (02:11 -0500)]
sim: ppc: hoist hw.[ch] creation to top-level
Mike Frysinger [Tue, 2 Jan 2024 07:00:09 +0000 (02:00 -0500)]
sim: ppc: hoist igen execution to top-level
Invoke ppc's igen from the top-level like we do for all other ports.
Mike Frysinger [Tue, 2 Jan 2024 06:40:06 +0000 (01:40 -0500)]
sim: ppc: merge configure logic into top-level
Now that the ppc configure script is just namespaced options, we can
move it to ppc/acinclude.m4 and include it directly in the top-level
configure script and kill off the last subdir configure script.
Mike Frysinger [Tue, 2 Jan 2024 06:30:53 +0000 (01:30 -0500)]
sim: ppc: scope configure options to --enable-sim-ppc-xxx
To prepare for moving these into the top-level configure, namespace
then with the port name like we do with all other ports.
Mike Frysinger [Tue, 2 Jan 2024 06:13:44 +0000 (01:13 -0500)]
sim: ppc: standardize configure option processing
Switch from ad-hoc $silent checks & echo calls to standard
AC_MSG_CHECKING & AC_MSG_RESULT calls. Also delete pointless
variable setting after calling AC_MSG_ERROR.
Mike Frysinger [Tue, 2 Jan 2024 05:55:33 +0000 (00:55 -0500)]
sim: ppc: switch to AS_HELP_STRING for automatic formatting
Mike Frysinger [Tue, 2 Jan 2024 05:39:08 +0000 (00:39 -0500)]
sim: ppc: drop now unused config.in
Mike Frysinger [Tue, 2 Jan 2024 05:24:22 +0000 (00:24 -0500)]
sim: ppc: move defines.h generation to the top-level
Since we rely on the top-level config.h now, the defines.h generation
step should live here too.
Mike Frysinger [Tue, 2 Jan 2024 05:12:51 +0000 (00:12 -0500)]
sim: ppc: drop configure compiler checks
Now that the ppc script only checks configure options and sets up
variables in the Makefile from those, delete all the compile related
logic to greatly simplify the configure script.
Mike Frysinger [Tue, 2 Jan 2024 05:11:38 +0000 (00:11 -0500)]
sim: ppc: drop custom config.h header
Now that everything has moved to the top-level, we can drop the
custom ppc config.h and reuse the common one.
Mike Frysinger [Tue, 2 Jan 2024 05:10:33 +0000 (00:10 -0500)]
sim: ppc: stop including headers from gdb/
The common sim code doesn't snoop in gdb/, and the ppc code doesn't
need to either. Any common code we pull from gnulib/ now only.
Mike Frysinger [Tue, 2 Jan 2024 04:57:12 +0000 (23:57 -0500)]
sim: ppc: move termios probes to top-level
This is the last compile-time logic in the ppc subdir.
Mike Frysinger [Tue, 2 Jan 2024 04:42:45 +0000 (23:42 -0500)]
sim: ppc: switch to AC_CACHE_CHECK
This macro replaces the AC_MSG_CHECKING+AC_CACHE_VAL+AC_MSG_RESULT
which reduces the boilerplate in here a little bit.
Mike Frysinger [Tue, 2 Jan 2024 04:53:53 +0000 (23:53 -0500)]
sim: ppc: switch struct member checks to AC_CHECK_MEMBER
This covers a lot of the AC_MSG_CHECKING+AC_TRY_COMPILE+AC_MSG_RESULT
boilerplate and matches what we do in the top-level platform checks.
Mike Frysinger [Tue, 2 Jan 2024 04:37:11 +0000 (23:37 -0500)]
sim: ppc: move termio defines to config.h
Move the defines from explicit -D options to config.h defines to simplify
the build and make it easier to move to the top-level configure.
Mike Frysinger [Tue, 2 Jan 2024 04:32:29 +0000 (23:32 -0500)]
sim: ppc: move struct statfs to top-level
Mike Frysinger [Tue, 2 Jan 2024 04:22:17 +0000 (23:22 -0500)]
sim: ppc: move long long test to top-level
While the sim code doesn't utilize HAVE_LONG_LONG itself, other code
(like libiberty) seem to, so check for it in the top-level for all
ports to leverage.
Mike Frysinger [Tue, 2 Jan 2024 04:15:46 +0000 (23:15 -0500)]
sim: ppc: hoist sysv tests to top-level
Now that the sysv tests turn into config.h defines and everything
checks that, we can move the tests to the top-level and out of the
ppc subdir.
Mike Frysinger [Tue, 2 Jan 2024 01:22:45 +0000 (20:22 -0500)]
sim: ppc: always compile in the sysv sem & shm device files
Move the stub logic to the device files themselves. This makes the
configure & build logic more static which will make it easier to move
to the top-level build, and matches what we did with the common/ hw
tree already.
This also decouples the logic from the two -- in the past, you needed
both sem & shm in order to enable the device models, but now each one
is tied to its own independent knob. Practically speaking, this will
probably not make a difference, but it simplifies the build a bit.
Mike Frysinger [Tue, 2 Jan 2024 01:11:52 +0000 (20:11 -0500)]
sim: ppc: change SysV sem & shm tests to compile-time
Instead of executing code to see if SysV semaphores & shared memory
are available, switch to just a compile-time test. The system used
to compile might not match the system used to run the code wrt the
current kernel & OS settings, but the library APIs should. So move
the failures from compile-time to runtime so the program is more
portable, and works correctly even when cross-compiling.
Mike Frysinger [Tue, 2 Jan 2024 01:03:26 +0000 (20:03 -0500)]
sim: ppc: merge System V semaphores checks
Compile tests can use earlier defines, so hoist the HAVE_UNION_SEMUN
define to before the semaphore check, and use it in the test so that
we can merge the 2 versions into one.
This also defines HAVE_UNION_SEMUN even when ac_cv_sysv_sem is not
set, but that's OK as this define is only about a type existing, not
about whether the overall code is usable.
Mike Frysinger [Tue, 2 Jan 2024 00:54:10 +0000 (19:54 -0500)]
sim: ppc: fix bad AC_CACHE_CHECK call with semun
The first arg is the cache var name, and this one was typoed relative
to what the call actually set. We also don't need the manual call to
AC_MSG_RESULT as the AC_CACHE_CHECK takes care of it for us.
Mike Frysinger [Tue, 2 Jan 2024 05:27:12 +0000 (00:27 -0500)]
sim: ppc: delete unused build compile & link settings
These should have been removed as part of the ppc/igen merging into the
top-level, but they were missed. Clean up now.
GDB Administrator [Tue, 2 Jan 2024 00:00:57 +0000 (00:00 +0000)]
Automatic date update in version.in
Mike Frysinger [Mon, 1 Jan 2024 23:14:13 +0000 (18:14 -0500)]
sim: ppc: merge misc igen APIs
The common igen code provides the same misc APIs as the ppc version,
so delete the ppc code and pull in the common one. There is one
minor difference: the ppc code has a unique dumpf function. The
common code switched to lf_printf for the same functionality, but
since that requires changes throughout the igen codebase, delay that
cleanup for now so we can merge the rest.
Mike Frysinger [Mon, 1 Jan 2024 22:34:01 +0000 (17:34 -0500)]
sim: ppc: rework igen error to match common
Switch to an ERROR macro and tweak the error signature to match the
common igen version in preparation for merging the two implementations.
Mike Frysinger [Mon, 1 Jan 2024 22:28:51 +0000 (17:28 -0500)]
sim: igen: extend error to take arguments
The ppc igen error helper allows arbitrary printf calls, so extend
the common one to do the same.
Mike Frysinger [Mon, 1 Jan 2024 22:17:50 +0000 (17:17 -0500)]
sim: ppc: rename igen max_insn_bit_size
We want to avoid conflicts with the common igen enums. This should
get migrated over to the common parsing logic, but for now, switch
the name to avoid redefinition.
Mike Frysinger [Mon, 1 Jan 2024 22:09:02 +0000 (17:09 -0500)]
sim: igen: minor constify logic
Copy some improvements from the ppc igen code.
Mike Frysinger [Mon, 1 Jan 2024 21:44:50 +0000 (16:44 -0500)]
sim: ppc: unify igen filter_filename implementations
Now that both igen implementations are in the top-level, we can unify
the filter_filename implementation between them since they're the same
(literally the same code).
Mike Frysinger [Mon, 1 Jan 2024 21:32:48 +0000 (16:32 -0500)]
sim: ppc: replace filter_filename with lbasename
The lbasename function from libiberty provides the same API as this
custom function. The common/ code already made the switch, so make
the same change to the ppc code to avoid target duplication.
Mike Frysinger [Mon, 1 Jan 2024 20:48:15 +0000 (15:48 -0500)]
sim: ppc: hoist igen compilation into top-level
This simplifies the build a bit (especially for deps in port subdirs),
and avoids recursive make. This in turn speeds up the build, and lets
us reuse existing build-time vs host-time logic from Makefile.am.
Mike Frysinger [Mon, 1 Jan 2024 20:26:21 +0000 (15:26 -0500)]
sim: ppc: drop build-config.h usage
This header is only used by the igen tool, and none of the igen code
depends on the configure-time checks. Delete the logic to simplify
to prepare for moving it to the local.mk code.
Mike Frysinger [Mon, 1 Jan 2024 20:24:12 +0000 (15:24 -0500)]
sim: ppc: simplify filter_host.c logic
Switch this from a build-time generation to a static include. This
makes the build rules a bit simpler, especially as we move them to
Automake from hand-written makefiles.
Mike Frysinger [Mon, 1 Jan 2024 20:38:10 +0000 (15:38 -0500)]
sim: igen: remove libigen.a when cleaning
Mike Frysinger [Mon, 1 Jan 2024 16:04:08 +0000 (11:04 -0500)]
sim: ppc: drop unused host bitsize settings
This is never set anywhere, so it's always empty. Scrub it.
Mike Frysinger [Sun, 24 Dec 2023 10:21:30 +0000 (05:21 -0500)]
sim: frv: fix cmpb uninitialized variable usage
This code sets up the cc variable based on the comparison of other
registers, but it does so incrementally with bit operations, and it
never initializes the cc variable. Initialize it to 0 which the
cmpba insn is already doing.
Mike Frysinger [Fri, 22 Dec 2023 01:06:10 +0000 (20:06 -0500)]
sim: arm: mark local read-only arrays as static const
Move it into read-only data sections to avoid constructing them on the
stack at runtime.
Mike Frysinger [Wed, 6 Dec 2023 13:39:25 +0000 (06:39 -0700)]
sim: warnings: enable -Wunused-variable
Mike Frysinger [Tue, 19 Dec 2023 01:55:58 +0000 (20:55 -0500)]
cpu: or1k: drop unused l.swa flag
The "flag" argument isn't set/used in this insn, so drop it.
This fixes an unused variable warning in the generated sim.
Tom Tromey [Sun, 31 Dec 2023 21:55:58 +0000 (14:55 -0700)]
sim: fix pervasive typo
I noticed a typo in a sim constant. This patch fixes it.
permenant -> permanent
GDB Administrator [Mon, 1 Jan 2024 00:00:49 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom Tromey [Sun, 31 Dec 2023 23:36:44 +0000 (16:36 -0700)]
Run 'black' on tui-window.py
Mark pointed out that a recent patch of mine caused the buildbot to
complain about the formatting of some Python test code. This patch
re-runs 'black' to fix the problem.
Tom de Vries [Sun, 31 Dec 2023 08:39:45 +0000 (09:39 +0100)]
[gdb/testsuite] Fix typo in gdb.base/catch-syscall.exp
On aarch64-linux with a gdb build without libexpat, I run into:
...
(gdb) PASS: gdb.base/catch-syscall.exp: determine pipe syscall: \
catch syscall 59
continue
Continuing.
Catchpoint 5 (call to syscall 59), 0x0000fffff7e04578 in pipe () from \
/lib64/libc.so.6
(gdb) FAIL: gdb.base/catch-syscall.exp: determine pipe syscall: continue
...
In the test-case, this pattern handles either the syscall name or number for
the pipe syscall:
...
-re -wrap "Catchpoint $decimal \\(call to syscall (pipe|$SYS_pipe)\\).*" {
...
but the pattern for the pipe2 syscall mistakenly uses SYS_pipe instead of
SYS_pipe2:
...
-re -wrap "Catchpoint $decimal \\(call to syscall (pipe2|$SYS_pipe)\\).*" {
...
and consequently doesn't handle the pipe2 syscall number.
Fix the typo by using SYS_pipe2 instead.
Tested on aarch64-linux.
GDB Administrator [Sun, 31 Dec 2023 00:00:10 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom Tromey [Wed, 13 Dec 2023 05:49:52 +0000 (22:49 -0700)]
Add keywords to TuiWindow.write
The gdb docs promise that methods with more than two or more arguments
will accept keywords. However, I found that TuiWindow.write didn't
allow them. This patch adds the missing support.
Tom de Vries [Sat, 30 Dec 2023 19:04:10 +0000 (20:04 +0100)]
[gdb/testsuite] Fix gdb.base/gdb-index-err.exp for root user
When running test-case gdb.base/gdb-index-err.exp in a container as root user,
I run into:
...
FAIL: gdb.base/gdb-index-err.exp: flag=: \
try to write index to a non-writable directory
FAIL: gdb.base/gdb-index-err.exp: flag=-dwarf-5: \
try to write index to a non-writable directory
...
The test-case creates a directory without write permissions:
...
$ ls -ald private
dr-xr-xr-x 2 root root 4096 Dec 29 06:26 private/
...
but apparently the root user is still able to write in it.
Fix this by making the test unsupported for the root user.
Tested on x86_64-linux.
Reviewed-By: Lancelot SIX <lancelot.six@amd.com>
PR testsuite/31197
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31197
Alan Modra [Thu, 28 Dec 2023 11:42:17 +0000 (22:12 +1030)]
LoongArch: Commas inside double quotes
This adds an extra feature: Commas inside double quotes are not an
arg delimiter, and thus can be part of the arg.
* loongarch-coder.c (loongarch_split_args_by_comma): Commas
inside quotes are not arg delimiters.
Alan Modra [Sat, 30 Dec 2023 02:27:42 +0000 (12:57 +1030)]
Regen bfd-in2.h
Please DON'T edit this file. READ THE COMMENT!
Joseph Myers [Sat, 30 Dec 2023 00:32:00 +0000 (00:32 +0000)]
MAINTAINERS: Update my email address
There will be another update in January.
GDB Administrator [Sat, 30 Dec 2023 00:00:23 +0000 (00:00 +0000)]
Automatic date update in version.in
H.J. Lu [Fri, 29 Dec 2023 23:46:59 +0000 (15:46 -0800)]
x86: Append "#pass" to APX tests
Append "#pass" to APX tests for targets which pad text sections with NOPs.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Append
"#pass".
* testsuite/gas/i386/x86-64-apx-ndd-optimize.d: Likewise.
* testsuite/gas/i386/x86-64-apx-ndd.d: Likewise.
* testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d: Likewise.
* testsuite/gas/i386/x86-64-apx-pushp-popp.d: Likewise.
H.J. Lu [Fri, 29 Dec 2023 23:43:07 +0000 (15:43 -0800)]
x86: Don't use .insn with '/'
'/' starts a comment for some targets. Use .byte instead of .insn with
'/'.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Use .byte
instead of .insn with '/'.
H.J. Lu [Fri, 29 Dec 2023 20:43:11 +0000 (12:43 -0800)]
Fix x86-64: Add R_X86_64_CODE_4_GOTPCRELX
commit
3d5a60de52556f6a53d71d7e607c6696450ae3e4
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Thu Jun 8 10:01:03 2023 -0700
x86-64: Add R_X86_64_CODE_4_GOTPCRELX
added a new field, fx_tcbit3, to fix. But it didn't initialize it.
Fix it by clearing it in fix_new_internal.
* wrtite.c (fix_new_internal): Clear fx_tcbit3.
Nils-Christian Kempke [Mon, 21 Mar 2022 14:43:38 +0000 (15:43 +0100)]
dwarf, fortran: add support for DW_TAG_entry_point
Fortran provides additional entry points for subroutines and functions.
These entry points may use only a subset (or a different set) of the
parameters of the original subroutine. The entry points may be described
via the DWARF tag DW_TAG_entry_point.
This commit adds support for parsing the DW_TAG_entry_point DWARF tag.
Currently, between ifx/ifort/gfortran, only ifort is actually emitting
this tag. Both, ifx and gfortran use the DW_TAG_subprogram tag as
workaround/alternative. Thus, this patch really only adds more ifort
support. Even so, some of the attached tests still fail for ifort, due
to some wrong line info generated for the entry points in ifort.
After this patch it is possible to set a breakpoint in gdb with the
ifort compiled example at the entry points 'foo' and 'foobar', which was not
possible before.
As gcc and ifx do not emit the tag I also added a test to gdb.dwarf2
which uses some underlying c compiled code and adds some Fortran style DWARF
to it emitting the DW_TAG_entry_point. Before this patch it was not
possible to actually define breakpoint at the entry point tags.
For gfortran there actually exists a bug on bugzilla, asking for the use
of DW_TAG_entry_point over DW_TAG_subprogram:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=37134
This patch was originally posted here
https://sourceware.org/legacy-ml/gdb-patches/2017-07/msg00317.html
but its review/pinging got lost after a while. I reworked it to fit the
current GDB.
Co-authored-by: Bernhard Heckel <bernhard.heckel@intel.com>
Co-authored-by: Tim Wiederhake <tim.wiederhake@intel.com>
Approved-by: Tom Tromey <tom@tromey.com>
Nils-Christian Kempke [Wed, 13 Jul 2022 09:23:36 +0000 (11:23 +0200)]
gdb, dwarf: add assert to dwarf2_get_pc_bounds
In dwarf2_get_pc_bounds we were writing unchecked to *lowpc. This
commit adds a gdb_assert to first check that lowpc != nullptr.
Approved-by: Tom Tromey <tom@tromey.com>
Nils-Christian Kempke [Wed, 13 Jul 2022 08:57:27 +0000 (10:57 +0200)]
gdb, dwarf: move part of dwarf2_get_pc_bounds into separate function
This commit is in preparation of the next commit. There, we will add
a second variation to retrieve the pc bounds for DIEs tagged with
DW_TAG_entry_point. Instead of dwarf_get_pc_bounds_ranges_or_highlow_pc
we will call a separate method for entry points. As the validity checks
at the endo f dwarf2_get_pc_bounds are the same for both variants,
we introduced the new dwarf_get_pc_bounds_ranges_or_highlow_pc method,
outsourcing part of dwarf2_get_pc_bounds.
This commit should have no functional impact on GDB.
Approved-by: Tom Tromey <tom@tromey.com>
changjiachen [Thu, 28 Dec 2023 12:01:15 +0000 (20:01 +0800)]
LoongArch: ld: Add support for tls le relax.
Add tls le relax related testsuites in ld.
The new test cases are mainly tested in three aspects:
1. tls le relax function correctness test.
2. tls le relax boundary check test.
3. tls le relax function compatibility test.
ld/testsuite/ChangeLog:
* ld/testsuite/ld-loongarch-elf/relax.exp: Modify test.
* ld/testsuite/ld-loongarch-elf/old-tls-le.s: New test.
* ld/testsuite/ld-loongarch-elf/relax-bound-check-tls-le.s: Likewise.
* ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-new.s: Likewise.
* ld/testsuite/ld-loongarch-elf/relax-tls-le.s: Likewise.
* ld/testsuite/ld-loongarch-elf/tls-relax-compatible-check-old.s: Likewise.
changjiachen [Thu, 28 Dec 2023 11:59:39 +0000 (19:59 +0800)]
LoongArch: gas: Add support for tls le relax.
Add tls le relax related relocs support and testsuites in gas.
The main test is three new relocation items,
R_LARCH_TLS_LE_ADD_R, R_LARCH_TLS_LE_HI20_R,
R_LARCH_TLS_LE_LO12_R can be generated properly
and tls le insn format check.
gas/ChangeLog:
* config/tc-loongarch.c:
(loongarch_args_parser_can_match_arg_helper): Add support for relax.
* gas/testsuite/gas/loongarch/reloc.d: Likewise.
* gas/testsuite/gas/loongarch/reloc.s: Likewise.
* gas/testsuite/gas/loongarch/loongarch.exp: Likewise.
* gas/testsuite/gas/loongarch/tls_le_insn_format_check.s: New test.
changjiachen [Thu, 28 Dec 2023 11:58:28 +0000 (19:58 +0800)]
LoongArch: opcodes: Add support for tls le relax.
Add new opcode for tls le relax.
opcode/ChangeLog:
* loongarch-opc.c: Add new loongarch opcode.
changjiachen [Thu, 28 Dec 2023 11:57:30 +0000 (19:57 +0800)]
LoongArch: include: Add support for tls le relax.
Add new relocs number for tls le relax.
include/ChangeLog:
* elf/loongarch.h:
(RELOC_NUMBER (R_LARCH_TLS_LE_HI20_R, 121)): New relocs number.
(RELOC_NUMBER (R_LARCH_TLS_LE_ADD_R, 122)): Likewise.
(RELOC_NUMBER (R_LARCH_TLS_LE_LO12_R, 123)): Likewise.
changjiachen [Thu, 28 Dec 2023 12:07:54 +0000 (20:07 +0800)]
LoongArch: bfd: Add support for tls le relax.
Add tls le relax support and related relocs in bfd.
New relocation related explanation can refer to the following url:
https://github.com/loongson/la-abi-specs/blob/release/laelf.adoc
This support does two main things:
1. Implement support for three new relocation items in bfd.
The three new relocation items are shown below:
R_LARCH_TLS_LE_ADD_R
R_LARCH_TLS_LE_HI20_R
R_LARCH_TLS_LE_LO12_R
2. ADD a new macro RELOCATE_TLS_TP32_HI20
Handle problems caused by symbol extensions in TLS LE, The processing
is similar to the macro RELOCATE_CALC_PC32_HI20 method.
3. Implement the tls le relax function.
bfd/ChangeLog:
* bfd-in2.h: Add relocs related to tls le relax.
* elfnn-loongarch.c:
(loongarch_relax_tls_le): New function.
(RELOCATE_TLS_TP32_HI20): New macro.
(loongarch_elf_check_relocs): Add new reloc support.
(perform_relocation): Likewise.
(loongarch_elf_relocate_section): Handle new relocs related to relax.
(loongarch_elf_relax_section): Likewise.
* elfxx-loongarch.c:
(LOONGARCH_HOWTO (R_LARCH_TLS_LE_ADD_R)): New reloc how to type.
(LOONGARCH_HOWTO (R_LARCH_TLS_LE_HI20_R)): Likewise.
(LOONGARCH_HOWTO (R_LARCH_TLS_LE_LO12_R)): Likewise.
* libbfd.h: Add relocs related to tls le relax.
* reloc.c: Likewise.
Jin Ma [Mon, 25 Dec 2023 08:49:21 +0000 (16:49 +0800)]
RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extension
In order to make it easier to complete the compiler's support for
the XTheadVector extension and to be as compatible as possible
with the programming model of the 'V' extension ([1]), we consider
adding a few pseudo instructions ([2]).
th.vmmv.m vd,vs => th.vmand.mm vd,vs,vs
th.vneg.v vd,vs => th.vrsub.vx vd,vs,x0
th.vncvt.x.x.v vd,vs,vm => th.vnsrl.vx vd,vs,x0,vm
th.vfneg.v vd,vs => th.vfsgnjn.vv vd,vs,vs
th.vfabs.v vd,vs => th.vfsgnjx.vv vd,vs,vs
Ref:
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641302.html
[2] https://github.com/T-head-Semi/thead-extension-spec/pull/40
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for new
pseudoinstructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
opcodes/ChangeLog:
* riscv-opc.c: Add new pseudoinstructions.
GDB Administrator [Fri, 29 Dec 2023 00:00:37 +0000 (00:00 +0000)]
Automatic date update in version.in
H.J. Lu [Thu, 28 Dec 2023 16:46:31 +0000 (08:46 -0800)]
ld: Mention support for Intel APX relocations in NEWS
H.J. Lu [Sun, 2 Jul 2023 14:46:21 +0000 (07:46 -0700)]
Gold: Handle R_X86_64_CODE_4_GOTPC32_TLSDESC/R_X86_64_CODE_4_GOTTPOFF
Handle R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC.
Convert
add name@gottpoff(%rip), %reg
mov name@gottpoff(%rip), %reg
to
add $name@tpoff, %reg
mov $name@tpoff, %reg
and
lea name@tlsdesc(%rip), %reg
to
mov $name@tpoff, %reg
mov name@gottpoff(%rip), %reg
if the instruction is encoded with the REX2 prefix when possible.
elfcpp/
* x86_64.h (R_X86_64_CODE_4_GOTTPOFF): New.
(R_X86_64_CODE_4_GOTPC32_TLSDESC): Likewise.
gold/
* x86_64.cc (Target_x86_64::optimize_tls_reloc): Handle
R_X86_64_CODE_4_GOTPC32_TLSDESC and R_X86_64_CODE_4_GOTTPOFF.
(Target_x86_64::Scan::get_reference_flags): Likewise.
(Target_x86_64::Scan::local): Likewise.
(Target_x86_64::Scan::global): Likewise.
(Target_x86_64::Relocate::relocate): Likewise.
(Target_x86_64::Relocate::relocate_tls): Likewise.
(Target_x86_64::Relocate::tls_desc_gd_to_ie): Handle
R_X86_64_CODE_4_GOTPC32_TLSDESC.
(Target_x86_64::Relocate::tls_desc_gd_to_le): Likewise.
(Target_x86_64::Relocate::tls_ie_to_le): Handle.
R_X86_64_CODE_4_GOTTPOFF.
* testsuite/Makefile.am: Add x86_64_ie_to_le test.
* testsuite/Makefile.in: Regenerated.
* testsuite/x86_64_gd_to_le.s: Add R_X86_64_CODE_4_GOTPC32_TLSDESC
test.
* testsuite/x86_64_gd_to_le.sh: Check GDesc to LE conversion.
* testsuite/x86_64_ie_to_le.s: New file.
* testsuite/x86_64_ie_to_le.sh: Likewise.
H.J. Lu [Fri, 9 Jun 2023 20:50:22 +0000 (13:50 -0700)]
x86-64: Add R_X86_64_CODE_4_GOTTPOFF/R_X86_64_CODE_4_GOTPC32_TLSDESC
For
add name@gottpoff(%rip), %reg
mov name@gottpoff(%rip), %reg
add
# define R_X86_64_CODE_4_GOTTPOFF 44
and for
lea name@tlsdesc(%rip), %reg
add
# define R_X86_64_CODE_4_GOTPC32_TLSDESC 45
if the instruction starts at 4 bytes before the relocation offset.
They are similar to R_X86_64_GOTTPOFF and R_X86_64_GOTPC32_TLSDESC,
respectively. Linker can covert GOTTPOFF to
add $name@tpoff, %reg
mov $name@tpoff, %reg
and GOTPC32_TLSDESC to
mov $name@tpoff, %reg
mov name@gottpoff(%rip), %reg
if the instruction is encoded with the REX2 prefix when possible.
bfd/
* elf64-x86-64.c (x86_64_elf_howto_table): Add
R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC.
(R_X86_64_standard): Updated.
(x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF
and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC.
(elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_4_GOTTPOFF
and R_X86_64_CODE_4_GOTPC32_TLSDESC.
(elf_x86_64_tls_transition): Likewise.
(elf_x86_64_scan_relocs): Likewise.
(elf_x86_64_relocate_section): Likewise.
* reloc.c (bfd_reloc_code_real): Add
BFD_RELOC_X86_64_CODE_4_GOTTPOFF and
BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
gas/
* config/tc-i386.c (tc_i386_fix_adjustable): Handle
BFD_RELOC_X86_64_CODE_4_GOTTPOFF and
BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC.
(md_assemble): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF.
(output_insn): Don't add empty REX prefix with REX2 prefix.
(output_disp): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and
BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC.
(md_apply_fix): Likewise.
(i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTTPOFF or
BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC if ixp->fx_tcbit3 is set.
(tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and
BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC.
* testsuite/gas/i386/x86-64-gottpoff.d: New file.
* testsuite/gas/i386/x86-64-gottpoff.s: Likewise.
* testsuite/gas/i386/x86-64-tlsdesc.d: Likewise.
* testsuite/gas/i386/x86-64-tlsdesc.s: Likewise.
include/
* elf/x86-64.h (elf_x86_64_reloc_type): Add
R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC
ld/
* testsuite/ld-x86-64/tlsbindesc.d: Updated.
* testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
* testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_4_GOTTPOFF
and R_X86_64_CODE_4_GOTPC32_TLSDESC tests.
H.J. Lu [Thu, 8 Jun 2023 19:12:48 +0000 (12:12 -0700)]
gold: Handle R_X86_64_CODE_4_GOTPCRELX
Handle R_X86_64_CODE_4_GOTPCRELX and convert
mov name@GOTPCREL(%rip), %r31
to
lea name@GOTPCREL(%rip), %r31
if the instruction is encoded with the REX2 prefix when possible.
elfcpp/
* x86_64.h (R_X86_64_CODE_4_GOTPCRELX): New.
gold/
* x86_64.cc (Target_x86_64::can_convert_mov_to_lea): Handle
R_X86_64_CODE_4_GOTPCRELX.
(Target_x86_64::Scan::get_reference_flags): Likewise.
(Target_x86_64::Scan::local): Likewise.
(Target_x86_64::Scan::possible_function_pointer_reloc): Likewise.
(Target_x86_64::Scan::global): Likewise.
(Target_x86_64::Relocate::relocate): Likewise.
* testsuite/x86_64_mov_to_lea1.s: Add a test for
R_X86_64_CODE_4_GOTPCRELX.
* testsuite/x86_64_mov_to_lea2.s: Likewise.
* testsuite/x86_64_mov_to_lea3.s: Likewise.
* testsuite/x86_64_mov_to_lea4.s: Likewise.
* testsuite/x86_64_mov_to_lea5.s: Likewise.
* testsuite/x86_64_mov_to_lea.sh: Updated.
H.J. Lu [Thu, 8 Jun 2023 17:01:03 +0000 (10:01 -0700)]
x86-64: Add R_X86_64_CODE_4_GOTPCRELX
For
mov name@GOTPCREL(%rip), %reg
test %reg, name@GOTPCREL(%rip)
binop name@GOTPCREL(%rip), %reg
where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions,
add
# define R_X86_64_CODE_4_GOTPCRELX 43
if the instruction starts at 4 bytes before the relocation offset. It
similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX
as R_X86_64_GOTPCREL or convert the above instructions to
lea name(%rip), %reg
mov $name, %reg
test $name, %reg
binop $name, %reg
if the instruction is encoded with the REX2 prefix when possible.
bfd/
* elf64-x86-64.c (x86_64_elf_howto_table): Add
R_X86_64_CODE_4_GOTPCRELX.
(R_X86_64_standard): Updated.
(x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX.
(elf_x86_64_convert_load_reloc): Handle R_X86_64_CODE_4_GOTPCRELX.
(elf_x86_64_scan_relocs): Likewise.
(elf_x86_64_relocate_section): Likewise.
* reloc.c (bfd_reloc_code_real): Add
BFD_RELOC_X86_64_CODE_4_GOTPCRELX.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
gas/
* write.h (fix): Add fx_tcbit3. Change fx_unused to 1 bit.
* config/tc-i386.c (tc_i386_fix_adjustable): Handle
BFD_RELOC_X86_64_CODE_4_GOTPCRELX.
(tc_gen_reloc): Likewise.
(output_disp): Set fixP->fx_tcbit3 for REX2 prefix.
(i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTPCRELX
if fixp->fx_tcbit3 is set.
* config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Add
BFD_RELOC_X86_64_CODE_4_GOTPCRELX.
(TC_FORCE_RELOCATION_ABS): Likewise.
* testsuite/gas/i386/x86-64-gotpcrel.s: Add tests for
R_X86_64_CODE_4_GOTPCRELX.
* testsuite/gas/i386/x86-64-localpic.s: Likewise.
* testsuite/gas/i386/x86-64-gotpcrel.d: Updated.
* testsuite/gas/i386/x86-64-localpic.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise.
include/
* elf/x86-64.h (elf_x86_64_reloc_type): Add
R_X86_64_CODE_4_GOTPCRELX.
ld/
* testsuite/ld-x86-64/apx-load1.s: New file.
* testsuite/ld-x86-64/apx-load1a.d: Likewise.
* testsuite/ld-x86-64/apx-load1b.d: Likewise.
* testsuite/ld-x86-64/apx-load1c.d: Likewise.
* testsuite/ld-x86-64/apx-load1d.d: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run apx-load1a, apx-load1b,
apx-load1c and apx-load1d.
H.J. Lu [Thu, 28 Dec 2023 16:19:39 +0000 (08:19 -0800)]
gas: Mention initial support for Intel APX in NEWS
Schimpe, Christina [Wed, 27 Dec 2023 14:19:21 +0000 (14:19 +0000)]
x86: Add NT_X86_SHSTK note
Define NT_X86_SHSTK which is the note for x86 Shadow Stack (SHSTK) to
support Intel SHSTK in Linux kernel.
For now only userspace shadow stack and kernel IBT are supported by the
linux kernel. This note should be used instead of NT_X86_CET introduced
in the commit "x86: Add NT_X86_CET note", as it is outdated and only
used by old binutils versions.
Hu, Lin1 [Thu, 28 Dec 2023 01:06:41 +0000 (01:06 +0000)]
Support APX JMPABS for disassembler
gas/ChangeLog:
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/x86-64-apx-jmpabs-intel.d: Ditto.
* testsuite/gas/i386/x86-64-apx-jmpabs-inval.d: Ditto.
* testsuite/gas/i386/x86-64-apx-jmpabs-inval.s: Ditto.
* testsuite/gas/i386/x86-64-apx-jmpabs.d: Ditto.
* testsuite/gas/i386/x86-64-apx-jmpabs.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (JMPABS_Fixup): New Fixup function to disassemble jmpabs.
(print_insn): Add #UD exception for jmpabs.
(dis386): Modify a1 unit for support jmpabs.
* i386-mnem.h: Regenerated.
* i386-opc.tbl: New insns.
* i386-tbl.h: Regenerated.
Hu, Lin1 [Thu, 28 Dec 2023 01:06:41 +0000 (01:06 +0000)]
Support APX NDD optimized encoding.
This patch aims to optimize:
add %r16, %r15, %r15 -> add %r16, %r15
gas/ChangeLog:
* config/tc-i386.c (check_Rex_required): New function.
(can_convert_NDD_to_legacy): Ditto.
(match_template): If we can optimzie APX NDD insns, so rematch
template.
* testsuite/gas/i386/x86-64.exp: Add test.
* testsuite/gas/i386/x86-64-apx-ndd-optimize.d: New test.
* testsuite/gas/i386/x86-64-apx-ndd-optimize.s: Ditto.
Cui, Lili [Thu, 28 Dec 2023 01:06:41 +0000 (01:06 +0000)]
Support APX pushp/popp
gas/ChangeLog:
* config/tc-i386.c (process_operands): Handle "PUSHP/POPP requires
rex2.w == 1."
* testsuite/gas/i386/x86-64.exp: Add new test for PUSHP/POPP.
* testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-pushp-popp-inval.l: Ditto.
* testsuite/gas/i386/x86-64-apx-pushp-popp-inval.s: Ditto.
* testsuite/gas/i386/x86-64-apx-pushp-popp.d: Ditto.
* testsuite/gas/i386/x86-64-apx-pushp-popp.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (putop): print pushp and popp.
* i386-opc.tbl: Added new insns.
* i386-init.h : Regenerated.
* i386-mnem.h : Regenerated.
* i386-tbl.h: Regenerated.
Mo, Zewei [Thu, 28 Dec 2023 01:06:40 +0000 (01:06 +0000)]
Support APX Push2/Pop2
PPX functionality for PUSH/POP is not implemented in this patch
and will be implemented separately.
gas/ChangeLog:
2023-12-28 Zewei Mo <zewei.mo@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
* config/tc-i386.c: (enum i386_error):
New unsupported_rsp_register and invalid_src_register_set.
(md_assemble): Add handler for unsupported_rsp_register and
invalid_src_register_set.
(check_APX_operands): Add invalid check for push2/pop2.
(match_template): Handle check_APX_operands.
* testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/x86-64-apx-push2pop2.d: New test.
* testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto.
* testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto.
* testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto.
* testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto.
* testsuite/gas/i386/apx-push2pop2-inval.s: Ditto.
* testsuite/gas/i386/apx-push2pop2-inval.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad
testcases for POP2.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F.
* i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6
* i386-dis-evex.h: Add REG_EVEX_MAP4_8F.
* i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2.
(get_valid_dis386): Add handler for vector length and address_mode for
APX-Push2/Pop2 insn.
(nd): define nd as b for EVEX-promoted instrutions.
(OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn.
* i386-gen.c: Add Push2Pop2 bitfield.
* i386-opc.h: Regenerated.
* i386-opc.tbl: Regenerated.
konglin1 [Thu, 28 Dec 2023 01:06:40 +0000 (01:06 +0000)]
Support APX NDD
opcodes/ChangeLog:
* opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80,
REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6,
REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF.
* opcodes/i386-dis-evex.h: Add NDD insn.
* opcodes/i386-dis.c (nd): New define.
(VexGb): Ditto.
(VexGv): Ditto.
(get_valid_dis386): Change for NDD decode.
(print_insn): Ditto.
(putop): Ditto.
(intel_operand_size): Ditto.
(OP_E_memory): Ditto.
(OP_VEX): Ditto.
* opcodes/i386-opc.h (VexVVVV_DST): New.
* opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV.
* opcodes/i386-tbl.h: Regenerated.
gas/ChangeLog:
* gas/config/tc-i386.c (operand_size_match):
Support APX NDD that the number of operands is 3.
(build_apx_evex_prefix): Change for ndd encode.
(process_operands): Ditto.
(build_modrm_byte): Ditto.
(match_template): Support swap the first two operands for
APX NDD.
* testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd.
* testsuite/gas/i386/x86-64-apx-ndd.d: New test.
* testsuite/gas/i386/x86-64-apx-ndd.s: Ditto.
* testsuite/gas/i386/x86-64-pseudos.d: Add test.
* testsuite/gas/i386/x86-64-pseudos.s: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
Cui, Lili [Thu, 28 Dec 2023 01:06:40 +0000 (01:06 +0000)]
Add tests for APX GPR32 with extend evex prefix
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
* testsuite/gas/i386/x86-64-apx-egpr-inval.l: Add some insn don't
support gpr32.
* testsuite/gas/i386/x86-64-apx-egpr-inval.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Add new test.
* testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: New test.
* testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: New test.
* testsuite/gas/i386/x86-64-apx-evex-egpr.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-egpr.s: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted.s: New test.
Cui, Lili [Thu, 28 Dec 2023 01:06:40 +0000 (01:06 +0000)]
Support APX GPR32 with extend evex prefix
This patch adds non-ND, non-NF forms of EVEX promotion insn.
EVEX extension of legacy instructions:
All promoted legacy instructions are placed in EVEX map 4, which is
currently reserved.
EVEX extension of EVEX instructions:
All existing EVEX instructions are extended by APX using the extended
EVEX prefix, so that they can access all 32 GPRs.
EVEX extension of VEX instructions:
Promoting a VEX instruction into the EVEX space does not change the map
id, the opcode, or the operand encoding of the VEX instruction.
Note: The promoted versions of MOVBE will be extended to include the “MOVBE
reg1, reg2”.
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
* config/tc-i386.c (struct _i386_insn): Add has_egpr.
(need_evex_encoding): Adjusted for apx.
(cpu_flags_match): Ditto.
(install_template): Handled APX combines.
(is_apx_evex_encoding): Test apx evex encoding.
(build_apx_evex_prefix): Enabe APX evex prefix.
(md_assemble): Handle apx with evex encoding.
(process_suffix): Handle apx map4 prefix.
(check_register): Assign i.vec_encoding for APX evex instructions.
* testsuite/gas/i386/x86-64-evex.d: Adjust test cases.
* testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe.
opcodes/ChangeLog:
* i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3.
* i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0,
PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8,
PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB,
PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD,
PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF,
PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1,
PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8.
* i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0.
* i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn
promote to apx to use gpr32
* opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90,
X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2,
X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6,
X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91.
* i386-dis.c
(struct instr_info): Deleted bool r.
(PREFIX_NP_OR_DATA): New.
(NO_PREFIX): New.
(putop): Ditto.
(X86_64_EVEX_FROM_VEX_TABLE): Diito.
(get_valid_dis386): Decode insn erex in extend evex prefix.
Handle EVEX_MAP4
(print_insn): Handle PREFIX_DATA_AND_NP_ONLY.
(print_register): Handle apx instructions decode.
(OP_E_memory): Diito.
(OP_G): Diito.
(OP_XMM): Diito.
(DistinctDest_Fixup): Diito.
* i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4.
* i386-opc.h (SPACE_EVEXMAP4): Add legacy insn
promote to evex.
* i386-opc.tbl: Handle some legacy and vex insns don't
support gpr32. And add some legacy insn (map2 / 3) promote
to evex.