GCC_CET_HOST_FLAGS: Check if host supports multi-byte NOPs

Check if host supports multi-byte NOPs before enabling CET on host.

gcc/

PR bootstrap/99703
* configure: Regenerated.

libbacktrace/

PR bootstrap/99703
* configure: Regenerated.

libcc1/

PR bootstrap/99703
* configure: Regenerated.

libcpp/

PR bootstrap/99703
* configure: Regenerated.

libdecnumber/

PR bootstrap/99703
* configure: Regenerated.

lto-plugin/

PR bootstrap/99703
* configure: Regenerated.

GCC_CET_HOST_FLAGS: Check if host supports multi-byte NOPs

Sync with binutils for PR binutils/27397.  Check if host supports
multi-byte NOPs before enabling CET on host.

config/

PR bootstrap/99703
* cet.m4 (GCC_CET_HOST_FLAGS): Check if host supports multi-byte
NOPs.

libiberty/

PR bootstrap/99703
* configure: Regenerated.

IBM Z: Handle hard registers in s390_md_asm_adjust()

gen_fprx2_to_tf() and gen_tf_to_fprx2() cannot handle hard registers,
since the subregs they create do not pass validation.  Change
s390_md_asm_adjust() to manually copy between hard VRs and FPRs instead
of using these two functions.

gcc/ChangeLog:

PR target/100217
* config/s390/s390.c (s390_hard_fp_reg_p): New function.
(s390_md_asm_adjust): Handle hard registers.

gcc/testsuite/ChangeLog:

PR target/100217
* gcc.target/s390/vector/long-double-asm-in-out-hard-fp-reg.c: New test.
* gcc.target/s390/vector/long-double-asm-inout-hard-fp-reg.c: New test.

tree-ssa-dse: Fix up go.test/test/fixedbugs/issue16095.go miscompilation [PR100382]

The new DCE code inside of tree DSE removes in -fnon-call-exceptions
go code a load from NULL pointer the testcase relies on throwing an
exception and so the test hangs.

The following patch just repeats a check that e.g. tree-ssa-dce.c
uses to prevent this.

2021-05-03  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/100382
* tree-ssa-dse.c: Include tree-eh.h.
(dse_dom_walker::before_dom_children): Don't remove stmts if
stmt_unremovable_because_of_non_call_eh_p is true.

[Ada] Ada.Strings.Unbounded.Aux.Set_String

gcc/ada/

* libgnat/a-stunau.ads, libgnat/a-stunau.adb,
libgnat/a-stunau__shared.adb (Set_String): Remove old version,
replace by a new version taking a callback to set the string.

[Ada] Missing Preelaborate_Initialization on Ada.Containers.Ordered_Maps.Map

gcc/ada/

* libgnat/a-coorma.ads (Map): Add missing
Preelaborate_Initialization.

[Ada] Reuse Is_Universal_Numeric_Type where possible

gcc/ada/

* exp_ch4.adb (Analyze_Number_Declaration, Expand_N_Op_Expon):
Simplify with Is_Universal_Numeric_Type.
* sem_attr.adb (Resolve_Attribute): Likewise.
* sem_ch3.adb: Likewise.
* sem_ch4.adb (Check_Common_Type, Check_Arithmetic_Pair):
Likewise.
* sem_eval.adb (Eval_Unary_Op, Test_In_Range): Likewise.
* sem_res.adb (Resolve_Arithmetic_Op, Resolve_Membership_Op,
Resolve_Op_Expon, Resolve_Unary_Op, Set_Mixed_Mode_Operand,
Set_Operand_Type): Likewise.
* sem_type.adb (Disambiguate, Find_Unique_Type): Likewise.
* sem_util.adb (Universal_Interpretation): Likewise.

[Ada] Minor style fixes in Max_Aggregate_Size

gcc/ada/

* exp_aggr.adb (Max_Aggregate_Size): Add header boxes for nested
routines; move a local constant after nested subprogram bodies;
refill comment.

[Ada] Reuse a wrapper for Resolve with implicit type where possible

gcc/ada/

* sem_attr.adb (Analyze_Attribute): Reuse Resolve with implicit
type when analysing attribute Priority.
* sem_ch5.adb (Analyze_Case_Statement): Likewise for a rare case
in analysis of case statements.
(Analyze_Iterator_Specification): Likewise for non-overloaded
domain of iteration.

[Ada] Replace low-level membership test with a high-level Is_Record_Type

gcc/ada/

* einfo.adb (Write_Entity_Info): Simplify an Ekind membership
test.
* exp_aggr.adb (Is_CCG_Supported_Aggregate): Likewise.

[Ada] Refine type of a counter object from Int to Nat

gcc/ada/

* exp_ch7.adb (Build_Finalize_Statements): Refine type of a
local counter variable.
* exp_dist.adb (Append_Record_Traversal): Refine type of Counter
parameter.
(Add_Process_Element): Likewise.
(Build_From_Any_Call): Refine type of a local counter variable.
(Build_From_Any_Function): Likewise.
(Build_To_Any_Function): Likewise.
(FA_Rec_Add_Process_Element): Likewise.
(TA_Append_Record_Traversal): Likewise.
(TA_Rec_Add_Process_Element): Likewise.

[Ada] Simplify implicit loading for GNATprove with Discard_Node

gcc/ada/

* rtsfind.adb (SPARK_Implicit_Load): Simplify with Discard_Node.

[Ada] Update copyright notice

gcc/ada/

* Makefile.rtl: Update copyright notice.
* ada_get_targ.adb: Likewise.
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* adabkend.ads: Likewise.
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* alloc.ads: Likewise.
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* aspects.ads: Likewise.
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* atree.ads: Likewise.
* atree.h: Likewise.
* aux-io.c: Likewise.
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* bcheck.ads: Likewise.
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* binderr.ads: Likewise.
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* bindgen.ads: Likewise.
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* exp_aggr.adb: Likewise.
* exp_aggr.ads: Likewise.
* exp_atag.adb: Likewise.
* exp_atag.ads: Likewise.
* exp_attr.adb: Likewise.
* exp_attr.ads: Likewise.
* exp_cg.adb: Likewise.
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* exp_spark.adb: Likewise.
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* exp_util.adb: Likewise.
* exp_util.ads: Likewise.
* expander.adb: Likewise.
* expander.ads: Likewise.
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* fe.h: Likewise.
* final.c: Likewise.
* fmap.adb: Likewise.
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* freeze.adb: Likewise.
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* frontend.adb: Likewise.
* frontend.ads: Likewise.
* gcc-interface/ada-tree.h: Likewise.
* gcc-interface/ada.h: Likewise.
* gcc-interface/cuintp.c: Likewise.
* gcc-interface/decl.c: Likewise.
* gcc-interface/gadaint.h: Likewise.
* gcc-interface/gigi.h: Likewise.
* gcc-interface/lang-specs.h: Likewise.
* gcc-interface/misc.c: Likewise.
* gcc-interface/system.ads: Likewise.
* gcc-interface/targtyps.c: Likewise.
* gcc-interface/trans.c: Likewise.
* gcc-interface/utils.c: Likewise.
* gcc-interface/utils2.c: Likewise.
* get_scos.adb: Likewise.
* get_scos.ads: Likewise.
* get_targ.adb: Likewise.
* get_targ.ads: Likewise.
* ghost.adb: Likewise.
* ghost.ads: Likewise.
* gnat1drv.adb: Likewise.
* gnat1drv.ads: Likewise.
* gnat_cuda.adb: Likewise.
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* gnatbind.adb: Likewise.
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* gnatvsn.adb: Likewise.
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* gnatxref.adb: Likewise.
* gprep.adb: Likewise.
* gprep.ads: Likewise.
* gsocket.h: Likewise.
* hostparm.ads: Likewise.
* impunit.adb: Likewise.
* impunit.ads: Likewise.
* indepsw-aix.adb: Likewise.
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* indepsw-gnu.adb: Likewise.
* indepsw.adb: Likewise.
* indepsw.ads: Likewise.
* init.c: Likewise.
* initialize.c: Likewise.
* inline.adb: Likewise.
* inline.ads: Likewise.
* itypes.adb: Likewise.
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[Ada] Remove unused initial values in expansion of distributed calls

gcc/ada/

* exp_dist.adb (Build_From_Any_Call): Remove initial value for
Fnam; fix style.
(Build_To_Any_Call): Remove initial value for Fnam.
(Build_TypeCode_Call): Likewise.

[Ada] Replace calls to RTE with Is_RTE where possible

gcc/ada/

* checks.adb, exp_aggr.adb, exp_attr.adb, exp_ch6.adb,
exp_disp.adb, exp_imgv.adb, exp_util.adb, sem_attr.adb,
sem_ch13.adb, sem_ch8.adb, sem_eval.adb, sem_scil.adb,
sem_util.adb: Replace calls to RTE with Is_RTE.

[Ada] Replace call with a reference to a local constant

gcc/ada/

* sem_ch4.adb (Try_Object_Operation): Reuse local constant.

[Ada] Error message on invalid prefixed procedure call

gcc/ada/

* sem_ch4.adb (Try_Object_Operation): When a prefixed call is
overloaded and illegal, and the All_Errors flag is off, generate
an error message if the re-analysis of some candidate
interpretation fails to produce one.

[Ada] Rename package instead of each routine

gcc/ada/

* libgnat/g-casuti.adb: Replace with "pragma No_Body".
* libgnat/g-casuti.ads: Replace with a package renaming.

[Ada] Fix attributes Version and Body_Version for concurrent units

gcc/ada/

* sem_attr.adb (Check_Program_Unit): Fix references to
Concurrent_Kind and Is_Concurrent_Type; avoid repeated calls to
Entity.

[Ada] Allow attributes Version and Body_Version prefixed by entries

gcc/ada/

* sem_attr.adb (Check_Program_Unit): Replace tests for Task_Kind
and Protected_Kind with a collective test for Concurrent_Kind;
likewise, replace calls to Is_Task_Type and Is_Protected_Type
with a collective call to Is_Concurrent_Type; simplify into a
single membership test; add missing Entry_Kind alternative.

[Ada] Fix typos in calls to Error_Msg_NE

gcc/ada/

* sem_aggr.adb (Resolve_Record_Aggregate): Fix casing in error
message.
* sem_ch3.adb (Add_Internal_Interface_Entities): Fix unbalanced
parens.
* sem_elim.adb (Eliminate_Error_Msg): Add insertion character.

[Ada] Fix calls to Error_Msg_NE instead of Error_Msg_N

gcc/ada/

* freeze.adb (Freeze_Profile): Replace Error_Msg_NE with
Error_Msg_N; change to continuation message.
* sem_cat.adb, sem_ch10.adb, sem_ch12.adb, sem_ch5.adb: Replace
calls to Error_Msg_NE with calls to Error_Msg_N.

[Ada] Remove leading and trailing spaces in error messages

gcc/ada/

* exp_disp.adb, sem_aggr.adb, sem_cat.adb, sem_ch10.adb,
sem_ch12.adb, sem_ch3.adb, sem_ch4.adb, sem_ch5.adb,
sem_ch6.adb, sem_ch8.adb, sem_ch9.adb, sem_prag.adb,
sem_res.adb: Remove extra leading and trailing space in error
messages.

[Ada] Remove confusing warning on type export

gcc/ada/

* sem_prag.adb (Set_Exported): Do not warn on exporting a type.

[Ada] Spurious warning about premature use of selected component

gcc/ada/

* sem_warn.adb (Check_References): Do not emit warning on a
selected component when enclosing type has no discriminant and
type of component has partial initialization.

[Ada] Expansion in _postconditions confusing CodePeer

gcc/ada/

* contracts.adb (Build_Postconditions_Procedure): Remove
internally generated if statement used to control finalization
actions.
* exp_ch6.adb (Add_Return, Expand_Non_Function_Return,
Expand_Simple_Function_Return): Add if statement around
_postconditions to control finalization.
* exp_ch7.adb (Build_Finalizer): Likewise.
* sem_prag.adb (Find_Related_Declaration_Or_Body): Add case to
handle Context itself being a handled sequence of statements.

[Ada] Spurious accessibility error on call in return statement

gcc/ada/

* sem_util.adb (In_Return_Value): Modified to detect when
implicit dereference is specified on the return type of a
function call within the expression being checked.

[Ada] Crash on aggregate in function call in object declaration

gcc/ada/

* exp_aggr.adb (Expand_Array_Aggregate): If the parent node of
the aggregate is a subprogram call there is no target in which
to build the aggregate, and it has to be expanded into component
assignments.

[Ada] Code and style cleanups for CUDA

gcc/ada/

* exp_prag.adb (Expand_Pragma_CUDA_Execute): Refill comments;
remove periods after single-line comments; use procedural
variant of Next_Entity.
* gnat_cuda.adb: Refill comments; remove periods after
single-line comments; replace calls to UI_From_Int with
constants; change iteration bounds so they match the comments.
* sem_prag.adb (Analyze_Pragma): Add checks for malformed pragma
CUDA_Kernel aggregate; simplify processing of pragma CUDA_Global
with Check_Arg_Count; sync comment with code for CUDA_Global.

[Ada] No_Implicit_Loops restriction and pragma Assert

gcc/ada/

* tbuild.adb (Make_Implicit_Loop_Statement): Disable restriction
checking on dead paths.

[Ada] Spurious warning on postcondition and result

gcc/ada/

* sem_util.adb (Check_Result_And_Post_State): Replace custom
Has_In_Out_Parameter with existing Has_Out_Or_In_Out_Parameter
flag which corresponds exactly to what we need.

[Ada] Code cleanup

gcc/ada/

* libgnat/a-ztcoio.adb: Remove unused with clause.

[Ada] Cleanup processing of aspect Dynamic_Predicate

gcc/ada/

* sem_ch13.adb (Build_Predicate_Functions): Fix typo in comment.
(Resolve_Aspect_Expressions): Fix typo in comment; remove
redundant check for no aspects; simplify with Discard_Node.

[Ada] Compiler aborts on a constrained subtype of a predicated type

gcc/ada/

* sem_util.adb (Build_Constrained_Itype): Remove prior patch,
issue is better handled in Sem_Ch13.Build_Predicate_Functions.
* sem_ch13.adb (Build_Predicate_Functions): Do not build
predicate function for an Itype with a defined
Predicated_Parent, even if that designated parent does not yet
have a Predicate_Function. This can happen in instance bodies
nested within a generic unit.

Daily bump.

libstdc++: Move unix.org reference to https

libstdc++-v3/ChangeLog:

* doc/xml/manual/ctype.xml: Move unix.org reference to https.
* doc/html/manual/facets.html: Regenerate.

aix: Redesign section encoding and selection

AIX symbol references can refer to either the symbol (a label) or a
symbol with a qualifier (the storage mapping class).  The storage mapping
class provide information about the underlying COFF section into which the
symbol will be placed, e.g. [RO] for read-only in the text section,
[RW] for read-writer in the data section, or [BS] for the BSS section.
A label is distinct from a qualname in the assembler language, e.g.,
foo and foo[RW] are different, but the symbol table of an object file strips
the storage mapping class from the name, so that it no longer is relevant
when referring to symbols across object files and libraries.

.csect .data[RW]
i:

is a label "i" in the .data CSECT, which has storage mapping class [RW]
so that it is placed in the read-write COFF section.

.csect i[RW]

is a CSECT "i[RW]".  BSS does not allow interior labels.

The AIX port of GCC had been emitting the storage mapping class where
appropriate but not consistently using the storage mapping class on
the DECL or SYM name.  This patch updates the section encoding to properly
place storage mapping class on symbol names and remove the decorations
placed when emitting the symbol.

The mapping classes correspond to sections and the encoding choices must
exactly match the section choices made by get_section, so the logic for
the computation of reloc in get_variable_section is split into its own
function that XCOFF encode section info can call.

gcc/ChangeLog:

* varasm.c (compute_reloc_for_var): Split out from...
(get_variable_section): Use it.
* output.h (compute_reloc_for_var): Declare.
* config/rs6000/rs6000-protos.h
(rs6000_xcoff_asm_output_aligned_decl_common): Change alignment to
unsigned int.
* config/rs6000/rs6000.c (rs6000_legitimize_tls_address_aix):
Don't append storage mapping class to symbol.
(rs6000_xcoff_asm_named_section): Add BS and UL mapping classes.
Don't convert TLS BSS to common.
(rs6000_xcoff_unique_section): Don't fall back to select_secton.
(rs6000_xcoff_section_type_flags): Add SECTION_BSS if DECL is
bss_initializer.
(rs6000_xcoff_asm_globalize_decl_name): Don't strip storage
mapping class.
(rs6000_xcoff_asm_output_aligned_decl_common): Align is unsigned int.
If align is 0 from TLS class, use the same rules as varasm.c
If not common, switch to BSS section manually.
If common, emit appropriate comm or lcomm directive.
(rs6000_xcoff_encode_section_info): Add logic to append all
storage mapping classes.
(rs6000_asm_weaken_decl): Adjust for qualname symbols.
* config/rs6000/xcoff.h (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Use
rs6000_xcoff_asm_output_aligned_decl_common.
(ASM_OUTPUT_ALIGNED_DECL_LOCAL): Use
rs6000_xcoff_asm_output_aligned_decl_common.
(ASM_OUTPUT_TLS_COMMON): Use
rs6000_xcoff_asm_output_aligned_decl_common.

gcc/testsuite/ChangeLog:
* g++.dg/ext/visibility/fvisibility-inlines-hidden-4.C: Expect [BS]
mapping class on AIX.
* gcc.c-torture/compile/pr61159.c: XFAIL on AIX.
* gcc.c-torture/execute/alias-2.c: Same.
* gcc.dg/alias-7.c: Same.

Fortran: Async I/O - avoid unlocked unlocking [PR100352]

Follow up to PR100352, which moved unit unlocking to st_*_done_worker to
avoid lock order reversal; however, as async_io uses a different lock,
the (unlocked locked) unit lock shall not be unlocked there.

libgfortran/ChangeLog:

PR libgomp/100352
* io/transfer.c (st_read_done_worker, st_write_done_worker): Add new
arg whether to unlock unit.
(st_read_done, st_write_done): Call it with true.
* io/async.c (async_io): Call it with false.
* io/io.h (st_write_done_worker, st_read_done_worker): Update prototype.

nvptx: Fix up nvptx build against latest libstdc++ [PR100375]

The r12-220-gd96db15967e78d7cecea3b1cf3169ceb924678ac change
deprecated some non-standard std::pair constructors and that apparently
broke nvptx.c build, where pseudo_node_t is std::pair<struct basic_block_def *, int>
and so nullptr (or NULL) needs to be used for the first argument of the
ctors instead of 0.

2021-05-02  Jakub Jelinek  <jakub@redhat.com>

PR target/100375
* config/nvptx/nvptx.c (nvptx_sese_pseudo): Use nullptr instead of 0
as first argument of pseudo_node_t constructors.

i386: Fix up plugin header install on x86 [PR100336]

The recent addition of i386-isa.def which is included from i386.h results
in failures to build gcc plugins, the i386.h header is installed, but
i386-isa.def is not.

2021-05-02  Jakub Jelinek  <jakub@redhat.com>

PR target/100336
* config/i386/t-i386 (TM_H): Add $(srcdir)/config/i386/i386-isa.def.

Daily bump.

c++: C++11 range-for and ovl/lkp_iterator

We can't use C++11 range-based 'for' over a tree directly, because we don't
know what kind of range we want to use it as.  I suppose in some cases we
could guess, but it seems better to tersely make it explicit.  This patch
adds range adaptors ovl_range and lkp_range for use as the range of a
range-for, e.g.

  for (tree fn : lkp_range (fns)) { ... }

This patch also removes the private copy ops from ovl_iterator; it's
necessary for range-for, and these are effectively C++ forward_iterators,
which allow copying, so I don't see a reason to prevent it.  A bit more
would need to be done to make them actually conform as C++11 forward
iterators, but I don't think we particularly want to #include <iterator>
yet.

gcc/cp/ChangeLog:

* cp-tree.h (class ovl_iterator): Allow copying.  Add op==.
(class ovl_range, class lkp_range): New.
* call.c (build_op_call_1, add_candidates): Use them.
(build_op_delete_call, has_trivial_copy_assign_p): Likewise.
(has_trivial_copy_p): Likewise.
* class.c (handle_using_decl, get_basefndecls): Likewise.
(maybe_warn_about_overly_private_class): Likewise.
(warn_hidden, add_implicitly_declared_members): Likewise.
(check_methods, clone_constructors_and_destructors): Likewise.
(type_has_user_nondefault_constructor): Likewise.

Add GTY support for irange.

Right now we have GTY support for static storage iranges
(int_range<>).  However, there's no reason why the base
class can't be used with GC, other than it was an oversight.

For that matter, the base class has a pointer to the sub-range
storage, so we can use the same implementation for both.  This
patch does so.

I have also removed the DEFINE_INT_RANGE_GC_STUBS
stuff, and have documented why we need a separate
gt_pch_nx (int_range<1> *&) version.  This has to do with
hash-traits.h, which ipa-prop.c is using to store a value_range.
The header file hash-traits.h is defining an extern of
gt_pch_nx (int_range<1> *&) etc, instead of calling the
more generic (int_range<1> *) which is already available.

It seems suspect that has-traits.h has their own externs
for GC functions, and if someone has a better solution, I'd
be glad to hear it.

gcc/ChangeLog:

* value-range.cc (DEFINE_INT_RANGE_GC_STUBS): Remove.
(gt_pch_nx (int_range<1> *&)): New.
(gt_ggc_mx (int_range<1> *&)): New.
* value-range.h (class irange): Add GTY support for
the base class.

doc/options.texi: Fix the description of 'Negative'.

gcc/ChangeLog:
* doc/options.texi (Negative): Change either or to both and.

Daily bump.

libstdc++: Implement P2328 changes to join_view

This implements the wording changes of P2328R0 "join_view should join
all views of ranges".

libstdc++-v3/ChangeLog:

* include/std/ranges (__detail::__non_propating_cache): Define
as per P2328.
(join_view): Remove constraints on the value and reference types
of the wrapped iterator type as per P2328.
(join_view::_Iterator::_M_satisfy): Adjust as per P2328.
(join_view::_Iterator::operator++): Likewise.
(join_view::_M_inner): Use __non_propating_cache as per P2328.
Remove now-redundant use of __maybe_present_t.
* testsuite/std/ranges/adaptors/join.cc: Include <array>.
(test10): New test.

libstdc++: Fix inconsistent feature test macros

The __cpp_lib_constexpr_string and __cpp_lib_semaphore feature test
macros are not defined consistently in <version> and the relevant header
for the feature.

libstdc++-v3/ChangeLog:

* include/bits/basic_string.h (__cpp_lib_constexpr_string):
Only define for C++17 and later.
* include/std/version (__cpp_lib_semaphore): Fix condition
to match the one in <semaphore>.

libstdc++: Remove GLIBCXX_CHECK_INT64_T checks

This simplifies the definition of std::streamoff by using the predefined
__INT64_TYPE__ macro, instead of the _GLIBCXX_HAVE_INT64_T_LONG,
_GLIBCXX_HAVE_INT64_T_LONG_LONG and _GLIBCXX_HAVE_INT64_T macros defined
by configure.

By using the __INT64_TYPE__ macro (which all of GCC, Clang and Intel
define) we do not need to determine the type of int64_t in configure, we
can just use that type directly.

The background for the change was explained by David Edelsohn:

  Currently the type of streamoff is determined at libstdc++ configure
  time, chosen by the definitions of _GLIBCXX_HAVE_INT64_T_LONG and
  _GLIBCXX_HAVE_INT64_T_LONG_LONG.  For a multilib configuration, the
  difference is encoded in the different multilib header file paths.
  For "FAT" library targets that package 32 bit and 64 bit libraries
  together, G++ also expects a single header file directory hierarchy,
  causing an incorrect value for streamoff in some situations.

And in a subsequent mail:

  Most of the libstdc++ headers are architecture-neutral, OS neutral and
  ABI neutral.  The differences are localized in bits/c++config.h.  And
  most of c++config.h is identical for 32 bit AIX and 64 bit AIX.  The
  only differences that matter are __int128 and __int64_t.

This change removes some of those differences. With the only uses of the
INT64_T configure macros removed, the configure checks themselves can
also be removed.

Co-authored-by: David Edelsohn <dje.gcc@gmail.com>
libstdc++-v3/ChangeLog:

* acinclude.m4 (GLIBCXX_CHECK_INT64_T): Delete.
* config.h.in: Regenerate.
* configure: Regenerate.
* configure.ac: Do not use GLIBCXX_CHECK_INT64_T.
* include/bits/postypes.h: Remove include of <stdint.h> and
definition/undefinition of the __STDC_LIMIT_MACROS and
__STDC_CONSTANT_MACROS macros.
(streamoff): Use __INT64_TYPE__ if defined.

testsuite: aarch64: Add fusion tests for FP vml[as] intrinsics

Add compilation tests to make sure that the output of vmla/vmls
floating-point Neon intrinsics (fmul, fadd/fsub) is not fused into
fmla/fmls instructions.

gcc/testsuite/ChangeLog:

2021-02-16  Jonathan Wright  <jonathan.wright@arm.com>

* gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c:
New test.
* gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c:
New test.

aarch64: Use RTL builtins for FP ml[as][q]_laneq intrinsics

Rewrite floating-point vml[as][q]_laneq Neon intrinsics to use RTL
builtins rather than relying on the GCC vector extensions. Using RTL
builtins allows control over the emission of fmla/fmls instructions
(which we don't want here.)

With this commit, the code generated by these intrinsics changes from
a fused multiply-add/subtract instruction to an fmul followed by an
fadd/fsub instruction. If the programmer really wants fmla/fmls
instructions, they can use the vfm[as] intrinsics.

gcc/ChangeLog:

2021-02-17  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add
float_ml[as][q]_laneq builtin generator macros.
* config/aarch64/aarch64-simd.md (mul_laneq<mode>3): Define.
(aarch64_float_mla_laneq<mode>): Define.
(aarch64_float_mls_laneq<mode>): Define.
* config/aarch64/arm_neon.h (vmla_laneq_f32): Use RTL builtin
instead of GCC vector extensions.
(vmlaq_laneq_f32): Likewise.
(vmls_laneq_f32): Likewise.
(vmlsq_laneq_f32): Likewise.

aarch64: Use RTL builtins for FP ml[as][q]_lane intrinsics

Rewrite floating-point vml[as][q]_lane Neon intrinsics to use RTL
builtins rather than relying on the GCC vector extensions. Using RTL
builtins allows control over the emission of fmla/fmls instructions
(which we don't want here.)

With this commit, the code generated by these intrinsics changes from
a fused multiply-add/subtract instruction to an fmul followed by an
fadd/fsub instruction. If the programmer really wants fmla/fmls
instructions, they can use the vfm[as] intrinsics.

gcc/ChangeLog:

2021-02-16  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add
float_ml[as]_lane builtin generator macros.
* config/aarch64/aarch64-simd.md (*aarch64_mul3_elt<mode>):
Rename to...
(mul_lane<mode>3): This, and re-order arguments.
(aarch64_float_mla_lane<mode>): Define.
(aarch64_float_mls_lane<mode>): Define.
* config/aarch64/arm_neon.h (vmla_lane_f32): Use RTL builtin
instead of GCC vector extensions.
(vmlaq_lane_f32): Likewise.
(vmls_lane_f32): Likewise.
(vmlsq_lane_f32): Likewise.

aarch64: Use RTL builtins for FP ml[as] intrinsics

Rewrite floating-point vml[as][q] Neon intrinsics to use RTL builtins
rather than relying on the GCC vector extensions. Using RTL builtins
allows control over the emission of fmla/fmls instructions (which we
don't want here.)

With this commit, the code generated by these intrinsics changes from
a fused multiply-add/subtract instruction to an fmul followed by an
fadd/fsub instruction. If the programmer really wants fmla/fmls
instructions, they can use the vfm[as] intrinsics.

gcc/ChangeLog:

2021-02-16  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add float_ml[as]
builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_float_mla<mode>):
Define.
(aarch64_float_mls<mode>): Define.
* config/aarch64/arm_neon.h (vmla_f32): Use RTL builtin
instead of relying on GCC vector extensions.
(vmla_f64): Likewise.
(vmlaq_f32): Likewise.
(vmlaq_f64): Likewise.
(vmls_f32): Likewise.
(vmls_f64): Likewise.
(vmlsq_f32): Likewise.
(vmlsq_f64): Likewise.
* config/aarch64/iterators.md: Define VDQF_DF mode iterator.

aarch64: Use RTL builtins for FP ml[as]_n intrinsics

Rewrite floating-point vml[as][q]_n Neon intrinsics to use RTL
builtins rather than inline assembly code, allowing for better
scheduling and optimization.

gcc/ChangeLog:

2021-01-18  Jonathan Wright  <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add
float_ml[as]_n_builtin generator macros.
* config/aarch64/aarch64-simd.md (*aarch64_mul3_elt_from_dup<mode>):
Rename to...
(mul_n<mode>3): This, and re-order arguments.
(aarch64_float_mla_n<mode>): Define.
(aarch64_float_mls_n<mode>): Define.
* config/aarch64/arm_neon.h (vmla_n_f32): Use RTL builtin
instead of inline asm.
(vmlaq_n_f32): Likewise.
(vmls_n_f32): Likewise.
(vmlsq_n_f32): Likewise.

aarch64: Use RTL builtins for vmull[_high]_p8 intrinsics

Rewrite vmull[_high]_p8 Neon intrinsics to use RTL builtins rather
than inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-02-05  Jonathan Wright  <joanthan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add pmull[2]
builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_pmullv8qi): Define.
(aarch64_pmull_hiv16qi_insn): Define.
(aarch64_pmull_hiv16qi): Define.
* config/aarch64/arm_neon.h (vmull_high_p8): Use RTL builtin
instead of inline asm.
(vmull_p8): Likewise.

AVR cc0 conversion - adjust peepholes

This patch adjusts peepholes to match and generate parallels with
a clobber of REG_CC.

It also sets mov<mode>_insn as the name of the pattern for the split
insn (rather than the define_insn_and_split), so that
avr_2word_insn_p, which looks for CODE_FOR_mov<mode>_insn, works
correctly. This is required for the *cpse.eq peephole to fire, and
also helps generate better code for avr_out_sbxx_branch.

gcc/ChangeLog:

* config/avr/avr.md: Adjust peepholes to match and
generate parallels with clobber of REG_CC.
(mov<mode>_insn): Rename to mov<mode>_insn_split.
(*mov<mode>_insn): Rename to mov<mode>_insn.

middle-end: Disable section anchors for VAR_DECLs if -fdata-sections

-fdata-sections places data symbols into their own, unique, named sections.
-fsection-anchors create an anchor to access neighboring symbols
within a section.

When both are enabled, a separate section anchor is created for each
symbol, which provides no benefit.

This patch updates the common gating function use_blocks_for_decl_p() to
return false if -fdata-sections is enabled.

gcc/ChangeLog:

* varasm.c (use_blocks_for_decl_p): Don't use section anchors
for VAR_DECLs if -fdata-sections enabled.

Define target hook to emit KFmode constants for libgcc.

This patch defines a target hook so that the KFmode constants
(__LIBGCC_KF_MAX__, __LIBGCC_KF_MIN__, and __LIBGCC_KF_EPSILON__) needed to
build _divkc3.c in libgcc are defined.  The need for these constants were added
in the April 28th changes to libgcc that added complex division optimizations.

We only define the KFmode constants if IEEE 128-bit floating point is
supported, but long double does not use the IEEE 128-bit format.  If long
double uses the IEEE 128-bit format, it will use TFmode and not KFmode.

gcc/
2021-04-30  Michael Meissner  <meissner@linux.ibm.com>

PR bootstrap/100327
* config/rs6000/rs6000.c
(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Define.
(rs6000_libgcc_floating_mode_supported_p): New target hook.

Refactor backward threader registry and profitability code into classes.

This refactors the registry and the profitability code from the
backwards threader into two separate classes.  It cleans up the code,
and makes it easier for alternate implementations to share code.

gcc/ChangeLog:

* tree-ssa-threadbackward.c (class thread_jumps): Split out code
from here...
(class back_threader_registry): ...to here...
(class back_threader_profitability): ...and here...
(thread_jumps::thread_through_all_blocks): Remove argument.
(back_threader_registry::back_threader_registry): New.
(back_threader_registry::~back_threader_registry): New.
(back_threader_registry::thread_through_all_blocks): New.
(thread_jumps::profitable_jump_thread_path): Move from here...
(back_threader_profitability::profitable_path_p): ...to here.
(thread_jumps::find_taken_edge): New.
(thread_jumps::convert_and_register_current_path): Move...
(back_threader_registry::register_path): ...to here.
(thread_jumps::register_jump_thread_path_if_profitable): Move...
(thread_jumps::maybe_register_path): ...to here.
(thread_jumps::handle_phi): Call find_taken_edge and
maybe_register_path.
(thread_jumps::handle_assignment): Same.
(thread_jumps::fsm_find_control_statement_thread_paths): Remove
tree argument to handle_phi and handle_assignment.
(thread_jumps::find_jump_threads_backwards): Set m_name.  Remove
set of m_speed_p and m_max_threaded_paths.
(pass_thread_jumps::execute): Remove second argument from
find_jump_threads_backwards.
(pass_early_thread_jumps::execute): Same.

Jump threader refactor.

This is an overall refactor of the jump threader, both for the low level
bits in tree-ssa-threadupdate.* and the high level bits in
tree-ssa-threadedge.*.

There should be no functional changes.

Some of the benefits of the refactor are:

a) Eliminates some icky global state (for example the x_vr_values hack).

b) Provides some semblance of an API for the threader.

c) Makes it clearer to see what parts are from the high level
threader, and what parts belong in the low level path registry and
BB threading mechanism.

d) Avoids passing a ton of variables around.

e) Provides for easier sharing with the backward threader.

f) Merged simplify stmt code in VRP and DOM as they were nearly
identical.

This has been bootstrapped and regression tested on x86-64 Linux.
Jeff had also been testing this path as part of his Fedora throughout the
off-season.

gcc/ChangeLog:

* tree-ssa-dom.c (class dom_jump_threader_simplifier): New.
(class dom_opt_dom_walker): Initialize some class variables.
(pass_dominator::execute): Pass evrp_range_analyzer and
dom_jump_threader_simplifier to dom_opt_dom_walker.
Adjust for some functions moving into classes.
(simplify_stmt_for_jump_threading): Adjust and move to...
(jump_threader_simplifier::simplify): ...here.
(dom_opt_dom_walker::before_dom_children): Adjust for
m_evrp_range_analyzer.
(dom_opt_dom_walker::after_dom_children): Remove x_vr_values hack.
(test_for_singularity): Place in dom_opt_dom_walker class.
(dom_opt_dom_walker::optimize_stmt): The argument
evrp_range_analyzer is now a class field.
* tree-ssa-threadbackward.c (class thread_jumps): Add m_registry.
(thread_jumps::thread_through_all_blocks): New.
(thread_jumps::convert_and_register_current_path): Use m_registry.
(pass_thread_jumps::execute): Adjust for thread_through_all_blocks
being in the threader class.
(pass_early_thread_jumps::execute): Same.
* tree-ssa-threadedge.c (threadedge_initialize_values): Move...
(jump_threader::jump_threader): ...here.
(threadedge_finalize_values): Move...
(jump_threader::~jump_threader): ...here.
(jump_threader::remove_jump_threads_including): New.
(jump_threader::thread_through_all_blocks): New.
(record_temporary_equivalences_from_phis): Move...
(jump_threader::record_temporary_equivalences_from_phis): ...here.
(record_temporary_equivalences_from_stmts_at_dest): Move...
(jump_threader::record_temporary_equivalences_from_stmts_at_dest):
Here...
(simplify_control_stmt_condition_1): Move to jump_threader class.
(simplify_control_stmt_condition): Move...
(jump_threader::simplify_control_stmt_condition): ...here.
(thread_around_empty_blocks): Move...
(jump_threader::thread_around_empty_blocks): ...here.
(thread_through_normal_block): Move...
(jump_threader::thread_through_normal_block): ...here.
(thread_across_edge): Move...
(jump_threader::thread_across_edge): ...here.
(thread_outgoing_edges): Move...
(jump_threader::thread_outgoing_edges): ...here.
* tree-ssa-threadedge.h: Move externally facing functings...
(class jump_threader): ...here...
(class jump_threader_simplifier): ...and here.
* tree-ssa-threadupdate.c (struct redirection_data): Remove comment.
(jump_thread_path_allocator::jump_thread_path_allocator): New.
(jump_thread_path_allocator::~jump_thread_path_allocator): New.
(jump_thread_path_allocator::allocate_thread_edge): New.
(jump_thread_path_allocator::allocate_thread_path): New.
(jump_thread_path_registry::jump_thread_path_registry): New.
(jump_thread_path_registry::~jump_thread_path_registry): New.
(jump_thread_path_registry::allocate_thread_edge): New.
(jump_thread_path_registry::allocate_thread_path): New.
(dump_jump_thread_path): Make extern.
(debug (const vec<jump_thread_edge *> &path)): New.
(struct removed_edges): Move to tree-ssa-threadupdate.h.
(struct thread_stats_d): Remove.
(remove_ctrl_stmt_and_useless_edges): Make static.
(lookup_redirection_data): Move...
(jump_thread_path_registry::lookup_redirection_data): ...here.
(ssa_redirect_edges): Make static.
(thread_block_1): Move...
(jump_thread_path_registry::thread_block_1): ...here.
(thread_block): Move...
(jump_thread_path_registry::thread_block): ...here.
(thread_through_loop_header):  Move...
(jump_thread_path_registry::thread_through_loop_header): ...here.
(mark_threaded_blocks): Move...
(jump_thread_path_registry::mark_threaded_blocks): ...here.
(debug_path): Move...
(jump_thread_path_registry::debug_path): ...here.
(debug_all_paths): Move...
(jump_thread_path_registry::dump): ..here.
(rewire_first_differing_edge): Move...
(jump_thread_path_registry::rewire_first_differing_edge): ...here.
(adjust_paths_after_duplication): Move...
(jump_thread_path_registry::adjust_paths_after_duplication): ...here.
(duplicate_thread_path): Move...
(jump_thread_path_registry::duplicate_thread_path): ..here.
(remove_jump_threads_including): Move...
(jump_thread_path_registry::remove_jump_threads_including): ...here.
(thread_through_all_blocks): Move to...
(jump_thread_path_registry::thread_through_all_blocks): ...here.
(delete_jump_thread_path): Remove.
(register_jump_thread): Move...
(jump_thread_path_registry::register_jump_thread): ...here.
* tree-ssa-threadupdate.h: Move externally facing functions...
(class jump_thread_path_allocator): ...here...
(class jump_thread_path_registry): ...and here.
(thread_through_all_blocks): Remove.
(struct removed_edges): New.
(register_jump_thread): Remove.
(remove_jump_threads_including): Remove.
(delete_jump_thread_path): Remove.
(remove_ctrl_stmt_and_useless_edges): Remove.
(free_dom_edge_info): New prototype.
* tree-vrp.c: Remove x_vr_values hack.
(class vrp_jump_threader_simplifier): New.
(vrp_jump_threader_simplifier::simplify): New.
(vrp_jump_threader::vrp_jump_threader): Adjust method signature.
Remove m_dummy_cond.
Instantiate m_simplifier and m_threader.
(vrp_jump_threader::thread_through_all_blocks): New.
(vrp_jump_threader::simplify_stmt): Remove.
(vrp_jump_threader::after_dom_children): Do not set m_dummy_cond.
Remove x_vr_values hack.
(execute_vrp): Adjust for thread_through_all_blocks being in a
class.

libstdc++: Implement proposed resolution for LWG 3532

libstdc++-v3/ChangeLog:

* include/std/ranges (split_view::_InnerIter::operator++):
Depend on _Base instead of _Vp directly, as per LWG 3532.

libstdc++: Implement P2367 changes to avoid some list-initialization

This implements the wording changes of P2367R0 "Remove misuses of
list-initialization from Clause 24", modulo the parts that depend
on P1739R4 which we don't yet implement (due to LWG 3407).

libstdc++-v3/ChangeLog:

* include/bits/ranges_util.h (subrange::subrange): Avoid
list-initialization in delegating constructor.
* include/std/ranges (single_view): Replace implicit guide
with explicit deduction guide that decays its argument.
(_Single::operator()): Avoid CTAD when constructing the
single_view object.
(_Iota::operator()): Avoid list-initialization.
(__detail::__can_filter_view, _Filter::operator()): Likewise.
(__detail::__can_transform_view, _Transform::operator()): Likewise.
(take_view::begin): Likewise.
(__detail::__can_take_view, _Take::operator()): Likewise.
(__detail::__can_take_while_view, _TakeWhile::operator()): Likewise.
(__detail::__can_drop_view, _Drop::operator()): Likewise.
(__detail::__can_drop_while_view, _DropWhile::operator()): Likewise.
(split_view::split_view): Use views::single when initializing
_M_pattern.
(__detail::__can_split_view, _Split::operator()): Avoid
list-initialization.
(_Counted::operator()): Likewise.
* testsuite/std/ranges/p2367.cc: New test.

libstdc++: Use std::addressof to avoid ADL for operator& [PR 60497]

This is another small step towards avoiding the problems described in PR
60497, by using std::addressof to avoid ADL, so that we don't require
all template arguments to be complete.

libstdc++-v3/ChangeLog:

PR libstdc++/60497
* include/bits/basic_ios.tcc (basic_ios::copyfmt): use
std::addressof.
* include/bits/basic_string.tcc (basic_string::swap)
(basic_string::assign): Likewise.
* include/bits/deque.tcc (deque::operator=(const deque&)):
Likewise.
* include/bits/stl_tree.h (_Rb_tree::operator=(const * _Rb_tree&)):
Likewise.
* include/bits/vector.tcc (vector::operator=(const vector&)):
Likewise.

libstdc++: Implement LWG 1203 for rvalue iostreams

This implements the resolution of LWG 1203 so that the constraints for
rvalue stream insertion/extraction are simpler, and the return type is
the original rvalue stream type not its base class.

Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:

* include/std/istream (operator>>(Istream&&, x&)): Simplify, as
per LWG 1203.
* include/std/ostream (operator<<(Ostream&&, const x&)):
Likewise.
* testsuite/27_io/basic_istream/extractors_character/char/lwg2499_neg.cc:
Adjust dg-error pattern.
* testsuite/27_io/basic_istream/extractors_character/wchar_t/lwg2499_neg.cc:
Likewise.
* testsuite/27_io/basic_istream/extractors_other/char/4.cc: Define
is_extractable trait to replace std::__is_extractable. Make it
work with rvalue streams as well as lvalues, to replace f() and
g() helper functions.
* testsuite/27_io/basic_istream/extractors_other/wchar_t/4.cc:
Likewise.
* testsuite/27_io/basic_ostream/inserters_other/char/6.cc:
Define is_insertable trait to replace std::__is_insertable. Make
it work with rvalue streams as well as lvalues, to replace f()
and g() helper functions.
* testsuite/27_io/basic_ostream/inserters_other/wchar_t/6.cc:
Likewise.
* testsuite/27_io/filesystem/path/io/dr2989.cc: Prune additional
errors from new constraints.
* testsuite/27_io/rvalue_streams-2.cc: Remove PR 80675 checks,
which are no longer expected to compile.
* testsuite/27_io/rvalue_streams.cc: Adjust existing test.
Verify LWG 1203 changes.

libstdc++: Use <sys/socket.h> features conditionally [PR 100285]

This makes the uses of getsockopt and setsockopt in
<experimental/socket> conditional on the availability of <sys/socket.h>.

It also fixes a test to check for <sys/socket.h> instead of <socket.h>.

libstdc++-v3/ChangeLog:

PR libstdc++/100285
* include/experimental/socket (__basic_socket_impl::set_option)
(__basic_socket_impl::get_option) [!_GLIBCXX_HAVE_SYS_SOCKET_H]:
Just set error code.
* testsuite/experimental/net/socket/socket_base.cc: CHeck
for <sys/socket.h> not <socket.h>.

libstdc++: Define effective-target for net::ip features [PR 100351]

Define a new effective-target keyword so that tests for the Networking
TS <experimental/internet> header can be skipped on targets where none
of it can be usefully defined.

libstdc++-v3/ChangeLog:

PR libstdc++/100180
PR libstdc++/100286
PR libstdc++/100351
* testsuite/experimental/net/internet/address/v4/comparisons.cc:
Use new effective-target keyword.
* testsuite/experimental/net/internet/address/v4/cons.cc:
Likewise.
* testsuite/experimental/net/internet/address/v4/creation.cc:
Likewise.
* testsuite/experimental/net/internet/address/v4/members.cc:
Likewise.
* testsuite/experimental/net/internet/address/v6/members.cc:
Likewise.
* testsuite/experimental/net/internet/resolver/base.cc:
Likewise.
* testsuite/experimental/net/internet/resolver/ops/lookup.cc:
Likewise.
* testsuite/experimental/net/internet/resolver/ops/reverse.cc:
Likewise.
* testsuite/experimental/net/internet/socket/opt.cc:
Likewise.
* testsuite/experimental/net/internet/tcp.cc:
Likewise.
* testsuite/experimental/net/internet/udp.cc:
Likewise.
* testsuite/lib/libstdc++.exp (check_effective_target_net_ts_ip):
New proc to check net_ts_ip et.

gcc/genflags.c: Improve error message

When an iterator cannot be expanded, it is helpful to see the expanded
name which is causing problems.  It would be better to also print the
current iterator value (which couldn't match), but I couldn't find
how.

2021-04-30  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* genflags.c (gen_insn): Print failed expansion string.

c++/98032 - add testcase

This adds another testcase for PR95719.

2021-04-30  Richard Biener  <rguenther@suse.de>

PR c++/98032
* g++.dg/pr98032.C: New testcase.

Update alignment_for_piecewise_move

alignment_for_piecewise_move is called only with MOVE_MAX_PIECES or
STORE_MAX_PIECES, which are the number of bytes at a time that we
can move or store efficiently.  We should call mode_for_size without
limit to MAX_FIXED_MODE_SIZE, which is an integer expression for the
size in bits of the largest integer machine mode that should actually
be used, may be smaller than MOVE_MAX_PIECES or STORE_MAX_PIECES, which
may use vector.

* expr.c (alignment_for_piecewise_move): Call mode_for_size
without limit to MAX_FIXED_MODE_SIZE.

Don't use nullptr return from simplify_gen_subreg

Check nullptr return from simplify_gen_subreg.  Don't use it if it is
nullptr.

PR middle-end/90773
* builtins.c (builtin_memset_gen_str): Don't use return from
simplify_gen_subreg.

tree-optimization/96513 - add testcase for fixed bug

This adds a testcase for a bug that was fixed with the
hybrid SLP detection rewrite.

2021-04-30  Richard Biener  <rguenther@suse.de>

PR tree-optimization/96513
* gcc.dg/torture/pr96513.c: New testcase.

i386: Introduce reversed ADC and SBB patterns [PR98060]

The compiler is able to merge LTU comparisons with PLUS or MINUS pattern to
form addition with carry (ADC) and subtraction with borrow (SBB) instructions:

op = op + carry [ADC $0, op]
op = op - carry [SBB $0, op]

The patch introduces reversed ADC and SBB insn patterns:

op = op + !carry [SBB $-1, op]
op = op - !carry [ADC $-1, op]

allowing the compiler to also merge GEU comparisons.

2021-04-30  Uroš Bizjak  <ubizjak@gmail.com>

gcc/
PR target/98060
* config/i386/i386.md (*add<mode>3_carry_0r): New insn pattern.
(*addsi3_carry_zext_0r): Ditto.
(*sub<mode>3_carry_0): Ditto.
(*subsi3_carry_zext_0r): Ditto.
* config/i386/predicates.md (ix86_carry_flag_unset_operator):
New predicate.
* config/i386/i386.c (ix86_rtx_costs) <case PLUS, case MINUS>:
Also consider ix86_carry_flag_unset_operator to calculate
the cost of adc/sbb insn.

gcc/testsuite/

PR target/98060
* gcc.target/i386/pr98060.c: New test.

modulo-sched: skip loops with strange register defs [PR100225]

PR84878 fix adds an assertion which can fail, e.g. when stack pointer
is adjusted inside the loop.  We have to prevent it and search earlier
for any 'strange' instruction.  The solution is to skip the whole loop
if using 'note_stores' we found that one of hard registers is in
'df->regular_block_artificial_uses' set.

Also patch properly prohibit not single-set instruction in loop body.

gcc/ChangeLog:

PR rtl-optimization/100225
PR rtl-optimization/84878
* modulo-sched.c (sms_schedule): Use note_stores to skip loops
where we have an instruction which touches (writes) any hard
register from df->regular_block_artificial_uses set.
Allow not-single-set instruction only right before basic block
tail.

gcc/testsuite/ChangeLog:

PR rtl-optimization/100225
PR rtl-optimization/84878
* gcc.dg/pr100225.c: New test.

libgomp/ChangeLog:

* testsuite/libgomp.oacc-c-c++-common/atomic_capture-3.c: New test.

RISC-V: For '-march' and '-mabi' options, add 'Negative' property mentions itself.

When use multi-lib riscv-tool-chain. A bug is triggered when there are two
'-march' at command line.
riscv64-unknown-elf-gcc -march=rv32gcp -mabi=ilp32f -march=rv32gcpzp64 HelloWorld.c
/lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/lib/crt0.o: ABI is incompatible with that of the selected emulation:
  target emulation `elf64-littleriscv' does not match `elf32-littleriscv'
/lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/lib/crt0.o
/lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/crtbegin.o: ABI is incompatible with that of the selected emulation:
  target emulation `elf64-littleriscv' does not match `elf32-littleriscv'
/lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/crtbegin.o
......

This patch fix it. And the DRIVER would prune the extra '-march' and '-mabi'
options and keep only the last one valid.

gcc/ChangeLog:
* config/riscv/riscv.opt (march=,mabi=): Negative itself.

RISC-V: Add patterns for builtin overflow.

gcc/
* config/riscv/riscv.c (riscv_min_arithmetic_precision): New.
* config/riscv/riscv.h (TARGET_MIN_ARITHMETIC_PRECISION): New.
* config/riscv/riscv.md (addv<mode>4, uaddv<mode>4): New.
(subv<mode>4, usubv<mode>4, mulv<mode>4, umulv<mode>4): New.

Daily bump.

merge ix86- and x86_64-*-* in config.gcc

Uros observed that i[34567]86-*-* and x86_64-*-* cpu_type-setting
target cases were equivalent.  I've verified that this was the case,
and combined them.

for  gcc/ChangeLog

* config.gcc: Merged x86 and x86_64 cpu_type-setting cases.

add ASM_OUTPUT_MAX_SKIP_ALIGN to i386.h

Several i386 align tests expect p2align to be used, but not all
configurations define ASM_OUTPUT_MAX_SKIP_ALIGN, even when
HAVE_GAS_MAX_SKIP_P2ALIGN.

i386.h had an equivalent ASM_OUTPUT_MAX_SKIP_PAD.  I've renamed it and
its uses to the documented _ALIGN spelling, and dropped all redundant
defines elsewhere in gcc/config/i386/.

for  gcc/ChangeLog

* config/i386/i386.h (ASM_OUTPUT_MAX_SKIP_PAD): Rename to...
(ASM_OUTPUT_MAX_SKIP_ALIGN): ... this.  Enclose in do/while(0).
* config/i386/i386.c: Adjust.
* config/i386/i386.md: Adjust.
* config/i386/darwin.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Drop.
* config/i386/dragonfly.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise.
* config/i386/freebsd.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise.
* config/i386/gas.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise.
* config/i386/gnu-user.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise.
* config/i386/iamcu.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise.
* config/i386/lynx.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise.
* config/i386/netbsd-elf.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise.
* config/i386/openbsdelf.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise.
* config/i386/x86-64.h (ASM_OUTPUT_MAX_SKIP_ALIGN): Likewise.
(ASM_OUTPUT_MAX_SKIP_PAD): Likewise.

Update gcc sv.po.

* sv.po: Update.

i386: Optimize carry flag comparisons a bit

In ix86_int_compare, opportunistically swap operands of GTU and LEU comparisons
to emit carry flag comparison, with the expectation that the comparison will
combine to *add<mode>3_carry_0 or *sub<mode>3_carry_0 insn pattern.

Do not use ix86_expand_carry_flag_compare because this function prefers
carry flag comparisons too much - it forces the constants into registers
and/or emits additional arithmetic instructions to convert simple
comparisons into carry flag comparisons - but simply swap operands to
convert GTU and LEU comparisons into GEU and LTU ones.

Also, change the insn predicates of *add<mode>3_carry_0 and
*sub<mode>3_carry_0 insn patterns to allow more combine opportunities
with memory operands.

2021-04-29  Uroš Bizjak  <ubizjak@gmail.com>

gcc/
* config/i386/i386-expand.c (ix86_expand_int_compare):
Swap operands of GTU and LEU comparison to emit carry flag comparison.
* config/i386/i386.md (*add<mode>3_carry_0): Change insn
predicate to allow more combine opportunities with memory operands.
(*sub<mode>3_carry_0): Ditto.

preprocessor: Handle digit separators in #line [PR82359]

As reported in bug 82359, the preprocessor does not allow C++ digit
separators in the line number in a #line directive, despite the
standard syntax for that directive using digit-sequence which allows
digit separators.

There is some confusion in that bug about whether C++ is meant to
allow digit separators there or not, but the last comment there
suggests they are meant to be allowed, and the version of digit
separators accepted for C2X at the March meeting explicitly mentions
digit separators in the #line specification to avoid any ambiguity
there.

This patch thus adds code to handle digit separators in the line
number in #line, as part of the preparation for enabling digit
separators in C2X mode.  The code changed does not contain any
conditionals for whether digit separators are supported in the chosen
language version, because that was handled earlier in pp-number lexing
and if they aren't supported they won't appear in the string passed to
that function.  It does however make sure not to allow adjacent digit
separators because those are only handled at a later stage of lexing
at present.  (Problems with how certain source character sequences
involving digit separators that don't actually match the pp-number
syntax get lexed as a pp-number and only diagnosed later, if at all,
are bugs 83873 and 97604, to be addressed separately.)

Making the change in this location will have the effect of allowing
digit separators in the "# <line-number> <file> <flags>" form of
directive as well as #line; I don't think that's a problem.

Bootstrapped with no regressions for x86_64-pc-linux-gnu.

libcpp/
PR preprocessor/82359
* directives.c (strtolinenum): Handle digit separators.

gcc/testsuite/
PR preprocessor/82359
* g++.dg/cpp1y/digit-sep-line.C,
g++.dg/cpp1y/digit-sep-line-neg.C: New tests.

c++: Add using-declaration testcase

gcc/testsuite/ChangeLog:

* g++.dg/lookup/using-decl1.C: New test.

c++: Use empty field in constexpr eval.

In discussion of PR98463, Jakub noted that cxx_fold_indirect_ref_1 was
bailing out early for empty bases even when we do have fields for them (in
C++17 mode or later).  This corrects that.

gcc/cp/ChangeLog:

* constexpr.c (cxx_fold_indirect_ref_1): Only set *empty_base if we
don't find a field.

c++: Fix friend attributes [PR51344]

51344 was a problem with calling save_template_attributes twice for the same
friend function: once from do_friend and once from grokmethod.  The 2012
patch for the bug avoided creating an infinite loop when this happens, but
it's better to avoid the duplication in the first place.  This also restores
the dependent attributes to the beginning of the attribute list, as
originally intended.  And then apply_late_template_attributes can avoid
copying the non-dependent attributes.

gcc/cp/ChangeLog:

PR c++/51344
* decl2.c (grokfield): Call cplus_decl_attributes for friend.
(save_template_attributes): Use chainon.
* friend.c (do_friend): Remove attrlist parm.
* cp-tree.h (do_friend): Adjust.
* class.c (add_implicitly_declared_members): Adjust.
* decl.c (grokdeclarator): Adjust.
* pt.c (apply_late_template_attributes): Optimize.

c++: ICE with anonymous union [PR97974]

While working on the GCC 11 patch, it occurred to me that we could move
the errors about invalid members from finish_struct_anon_r to here, so we
properly get a diagnostic in g++.law/union4.C.

gcc/cp/ChangeLog:

PR c++/97974
* class.c (finish_struct_anon_r): Drop complain parm.
Remove non-field diagnostic.
(finish_struct_anon): Adjust.
* decl.c (fixup_anonymous_aggr): Move non-field diagnostic here.

gcc/testsuite/ChangeLog:

PR c++/97974
* g++.old-deja/g++.law/union4.C: Add expected diagnostic.

c++: constant expressions are evaluated [PR93314]

My GCC 11 patch for PR93314 turned off cp_unevaluated_operand while
processing an id-expression that names a non-static data member, but the
broader issue is that in general, a constant-expression is evaluated even in
an unevaluated operand.

gcc/cp/ChangeLog:

* cp-tree.h (cp_evaluated): Add reset parm to constructor.
* parser.c (cp_parser_constant_expression): Change
allow_non_constant_p to int.  Use cp_evaluated.
(cp_parser_initializer_clause): Pass 2 to allow_non_constant_p.
* semantics.c (finish_id_expression_1): Don't mess with
cp_unevaluated_operand here.

c++: unset COMPOUND_LITERAL_P [PR100079]

Once a CONSTRUCTOR has been digested and used as an initializer, it no
longer represents a compound literal by itself, so we can clear the flag,
letting us use it consistently to distinguish between digested and
undigested initializer-lists.

gcc/cp/ChangeLog:

* cp-tree.h: Clarify comments.
* pt.c (get_template_parm_object): Add assert.
* semantics.c (finish_compound_literal): Clear TREE_HAS_CONSTRUCTOR.
* tree.c (zero_init_expr_p): Check TREE_HAS_CONSTRUCTOR.
* typeck2.c (store_init_value): Likewise.

c++: Overeager use of deleted function before ADL [PR68942]

Here, at template definition time, ordinary name lookup for 'foo(t)'
finds only the deleted function, and so we form a CALL_EXPR thereof.
Later at instantiation time, when initially substituting into this
CALL_EXPR with T=N::A, we end up calling mark_used on this deleted
function (since it's the only function in the overload set), triggering
a bogus "use of deleted function error", before we get to augment the
overload set via ADL.

This patch fixes this issue by using the tf_conv flag to disable
mark_used during the initial substitution into the callee of a
CALL_EXPR when KOENIG_P, since at this point we're still figuring out
which functions are candidates.

gcc/cp/ChangeLog:

PR c++/68942
* pt.c (tsubst_copy_and_build) <case CALL_EXPR>: When KOENIG_P,
set tf_conv during the initial substitution into the function.

gcc/testsuite/ChangeLog:

PR c++/68942
* g++.dg/template/koenig12.C: New test.

c++: Add testcase for already fixed PR [PR94102]

We correctly accept this testcase since r11-1571.

gcc/testsuite/ChangeLog:

PR c++/94102
* g++.dg/cpp1z/class-deduction87.C: New test.

Update gcc fr.po.

* fr.po: Update.

rtl-ssa: Fix -fcompare-debug failure [PR100303]

This patch fixes an oversight in the handling of debug instructions
in rtl-ssa.  At the moment (and whether this is a good idea or not
remains to be seen), we maintain a linear RPO sequence of definitions
and non-debug uses.  If a register is defined more than once, we use
a degenerate phi to reestablish a previous definition where necessary.

However, debug instructions shouldn't of course affect codegen,
so we can't create a new definition just for them.  In those situations
we instead hang the debug use off the real definition (meaning that
debug uses do not follow a linear order wrt definitions).  Again,
it remains to be seen whether that's a good idea.

The problem in the PR was that we weren't taking this into account
when increasing (or potentially increasing) the live range of an
existing definition.  We'd create the phi even if it would only
be used by debug instructions.

The patch goes for the simple but inelegant approach of passing
a bool to say whether the use is a debug use or not.  I imagine
this area will need some tweaking based on experience in future.

gcc/
PR rtl-optimization/100303
* rtl-ssa/accesses.cc (function_info::make_use_available): Take a
boolean that indicates whether the use will only be used in
debug instructions.  Treat it in the same way that existing
cross-EBB debug references would be handled if so.
(function_info::make_uses_available): Likewise.
* rtl-ssa/functions.h (function_info::make_uses_available): Update
prototype accordingly.
(function_info::make_uses_available): Likewise.
* fwprop.c (try_fwprop_subst): Update call accordingly.

Fix nios2 build failure

gcc

* config/nios2/nios2-protos.h (nios2_fpu_insn_enabled): Move outside
of RTX_CODE guard.

i386: Mark x86 masked load builtins pure [PR100312]

Mark x86 AVX and AVX2 masked load builtins pure to enable dead code
elimination and more appropriate alias analysis.

2021-04-29  Uroš Bizjak  <ubizjak@gmail.com>
    Richard Biener  <rguenther@suse.de>
gcc/
PR target/100312
* config/i386/i386-builtin.def (IX86_BUILTIN_MASKLOADPD)
(IX86_BUILTIN_MASKLOADPS, IX86_BUILTIN_MASKLOADPD256)
(IX86_BUILTIN_MASKLOADPS256, IX86_BUILTIN_MASKLOADD)
(IX86_BUILTIN_MASKLOADQ, IX86_BUILTIN_MASKLOADD256)
(IX86_BUILTIN_MASKLOADQ256): Move from SPECIAL_ARGS
to PURE_ARGS category.
* config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins):
Handle PURE_ARGS category.
* config/i386/i386-expand.c (ix86_expand_builtin): Ditto.

Add parallelism support to gcov for MinGW platforms

If you attempt a profiled bootstrap on the MinGW platforms with -jN, N > 1,
it miserably fails because of profile mismatches all over the place, the
reason being that gcov has no support for parallelism on these platforms.

libgcc/
* libgcov.h: For the target, define GCOV_LOCKED_WITH_LOCKING
if __MSVCRT__ and, for the host, define it if HOST_HAS_LK_LOCK.
* libgcov-driver.c: Add directives if GCOV_LOCKED_WITH_LOCKING.
gcc/
* configure.ac: Check for the presence of sys/locking.h header and
for whether _LK_LOCK is supported by _locking.
* configure: Regenerate.
* config.in: Likewise.
* gcov-io.h: Define GCOV_LOCKED_WITH_LOCKING if HOST_HAS_LK_LOCK.
* gcov-io.c (gcov_open): Add support for GCOV_LOCKED_WITH_LOCKING.
* system.h: Include <sys/locking.h> if HAVE_SYS_LOCKING_H.

i386: Cleanup comparison predicates.

CCCmode is allowed only with GEU and LTU comparison codes.  Also allow
CCGZmode for these two codes.  There is no need to check for trivial FP
comparison operator, ix86_fp_compare_code_to_integer will return
UNKNOWN code for unsupported operators.

2021-04-29  Uroš Bizjak  <ubizjak@gmail.com>

gcc/
* config/i386/predicates.md (fcmov_comparison_operator):
Do not check for trivial FP comparison operator.
<case GEU, case LTU>: Allow CCGZmode.
<case GTU, case LEU>: Do not allow CCCmode.
(ix86_comparison_operator) <case GTU, case LEU>: Allow only CCmode.
(ix86_carry_flag_operator): Match only LTU and UNLT code.
Do not check for trivial FP comparison operator.  Allow CCGZmode.

[omp, simt] Handle alternative IV

Consider the test-case libgomp.c/pr81778.c added in this commit, with
this core loop (note: CANARY_SIZE set to 0 for simplicity):
...
  int s = 1;
  #pragma omp target simd
  for (int i = N - 1; i > -1; i -= s)
    a[i] = 1;
...
which, given that N is 32, sets a[0..31] to 1.

After omp-expand, this looks like:
...
  <bb 5> :
  simduid.7 = .GOMP_SIMT_ENTER (simduid.7);
  .omp_simt.8 = .GOMP_SIMT_ENTER_ALLOC (simduid.7);
  D.3193 = -s;
  s.9 = s;
  D.3204 = .GOMP_SIMT_LANE ();
  D.3205 = -s.9;
  D.3206 = (int) D.3204;
  D.3207 = D.3205 * D.3206;
  i = D.3207 + 31;
  D.3209 = 0;
  D.3210 = -s.9;
  D.3211 = D.3210 - i;
  D.3210 = -s.9;
  D.3212 = D.3211 / D.3210;
  D.3213 = (unsigned int) D.3212;
  D.3213 = i >= 0 ? D.3213 : 0;

  <bb 19> :
  if (D.3209 < D.3213)
    goto <bb 6>; [87.50%]
  else
    goto <bb 7>; [12.50%]

  <bb 6> :
  a[i] = 1;
  D.3215 = -s.9;
  D.3219 = .GOMP_SIMT_VF ();
  D.3216 = (int) D.3219;
  D.3220 = D.3215 * D.3216;
  i = D.3220 + i;
  D.3209 = D.3209 + 1;
  goto <bb 19>; [100.00%]
...

On nvptx, the first time bb6 is executed, i is in the 0..31 range (depending
on the lane that is executing) at bb entry.

So we have the following sequence:
- a[0..31] is set to 1
- i is updated to -32..-1
- D.3209 is updated to 1 (being 0 initially)
- bb19 is executed, and if condition (D.3209 < D.3213) == (1 < 32) evaluates
  to true
- bb6 is once more executed, which should not happen because all the elements
  that needed to be handled were already handled.
- consequently, elements that should not be written are written
- with CANARY_SIZE == 0, we may run into a libgomp error:
  ...
  libgomp: cuCtxSynchronize error: an illegal memory access was encountered
  ...
  and with CANARY_SIZE unmodified, we run into:
  ...
  Expected 0, got 1 at base[-961]
  Aborted (core dumped)
  ...

The cause of this is as follows:
- because the step s is a variable rather than a constant, an alternative
  IV (D.3209 in our example) is generated in expand_omp_simd, and the
  loop condition is tested in terms of the alternative IV rather than
  the original IV (i in our example).
- the SIMT code in expand_omp_simd works by modifying step and initial value.
- The initial value fd->loop.n1 is loaded into a variable n1, which is
  modified by the SIMT code and then used there-after.
- The step fd->loop.step is loaded into a variable step, which is modified
  by the SIMT code, but afterwards there are uses of both step and
  fd->loop.step.
- There are uses of fd->loop.step in the alternative IV handling code,
  which should use step instead.

Fix this by introducing an additional variable orig_step, which is not
modified by the SIMT code and replacing all remaining uses of fd->loop.step
by either step or orig_step.

Build on x86_64-linux with nvptx accelerator, tested libgomp.

This fixes for-5.c and for-6.c FAILs I'm currently seeing on a quadro m1200
with driver 450.66.

gcc/ChangeLog:

2020-10-02  Tom de Vries  <tdevries@suse.de>

* omp-expand.c (expand_omp_simd): Add step_orig, and replace uses of
fd->loop.step by either step or orig_step.

libgomp/ChangeLog:

2020-10-02  Tom de Vries  <tdevries@suse.de>

* testsuite/libgomp.c/pr81778.c: New test.

Small housekeeping work in SPARC back-end

gcc/
* config/sparc/sparc.c (gen_load_pcrel_sym): Delete.
(load_got_register): Do the PIC dance here.
(sparc_legitimize_tls_address): Simplify.
(sparc_emit_probe_stack_range): Likewise.
(sparc32_initialize_trampoline): Likewise.
(sparc64_initialize_trampoline): Likewise.
* config/sparc/sparc.md (load_pcrel_sym<P:mode>): Add @ marker.
(probe_stack_range<P:mode>): Likewise.
(flush<P:mode>): Likewise.
(tgd_hi22<P:mode>): Likewise.
(tgd_lo10<P:mode>): Likewise.
(tgd_add<P:mode>): Likewise.
(tgd_call<P:mode>): Likewise.
(tldm_hi22<P:mode>): Likewise.
(tldm_lo10<P:mode>): Likewise.
(tldm_add<P:mode>): Likewise.
(tldm_call<P:mode>): Likewise.
(tldo_hix22<P:mode>): Likewise.
(tldo_lox10<P:mode>): Likewise.
(tldo_add<P:mode>): Likewise.
(tie_hi22<P:mode>): Likewise.
(tie_lo10<P:mode>): Likewise.
(tie_add<P:mode>): Likewise.
(tle_hix22<P:mode>): Likewise.
(tle_lox10<P:mode>): Likewise.
(stack_protect_setsi): Rename to...
(stack_protect_set32): ...this.
(stack_protect_setdi): Rename to...
(stack_protect_set64): ...this.
(stack_protect_set): Adjust calls to above.
(stack_protect_testsi): Rename to...
(stack_protect_test32): ...this.
(stack_protect_testdi): Rename to...
(stack_protect_test64): ...this.
(stack_protect_test): Adjust calls to above.

Generate offset adjusted operation for op_by_pieces operations

Add an overlap_op_by_pieces_p target hook for op_by_pieces operations
between two areas of memory to generate one offset adjusted operation
in the smallest integer mode for the remaining bytes on the last piece
operation of a memory region to avoid doing more than one smaller
operations.

Pass the RTL information from the previous iteration to m_constfn in
op_by_pieces operation so that builtin_memset_[read|gen]_str can
generate the new RTL from the previous RTL.

Tested on Linux/x86-64.

gcc/

PR middle-end/90773
* builtins.c (builtin_memcpy_read_str): Add a dummy argument.
(builtin_strncpy_read_str): Likewise.
(builtin_memset_read_str): Add an argument for the previous RTL
information and generate the new RTL from the previous RTL info.
(builtin_memset_gen_str): Likewise.
* builtins.h (builtin_strncpy_read_str): Update the prototype.
(builtin_memset_read_str): Likewise.
* expr.c (by_pieces_ninsns): If targetm.overlap_op_by_pieces_p()
returns true, round up size and alignment to the widest integer
mode for maximum size.
(pieces_addr::adjust): Add a pointer to by_pieces_prev argument
and pass it to m_constfn.
(op_by_pieces_d): Add m_push and m_overlap_op_by_pieces.
(op_by_pieces_d::op_by_pieces_d): Add a bool argument to
initialize m_push.  Initialize m_overlap_op_by_pieces with
targetm.overlap_op_by_pieces_p ().
(op_by_pieces_d::run): Pass the previous RTL information to
pieces_addr::adjust and generate overlapping operations if
m_overlap_op_by_pieces is true.
(PUSHG_P): New.
(move_by_pieces_d::move_by_pieces_d): Updated for op_by_pieces_d
change.
(store_by_pieces_d::store_by_pieces_d): Updated for op_by_pieces_d
change.
(can_store_by_pieces): Use by_pieces_constfn on constfun.
(store_by_pieces): Use by_pieces_constfn on constfun.  Updated
for op_by_pieces_d change.
(clear_by_pieces_1): Add a dummy argument.
(clear_by_pieces): Updated for op_by_pieces_d change.
(compare_by_pieces_d::compare_by_pieces_d): Likewise.
(string_cst_read_str): Add a dummy argument.
* expr.h (by_pieces_constfn): Add a dummy argument.
(by_pieces_prev): New.
* target.def (overlap_op_by_pieces_p): New target hook.
* config/i386/i386.c (TARGET_OVERLAP_OP_BY_PIECES_P): New.
* doc/tm.texi.in: Add TARGET_OVERLAP_OP_BY_PIECES_P.
* doc/tm.texi: Regenerated.

gcc/testsuite/

PR middle-end/90773
* g++.dg/pr90773-1.h: New test.
* g++.dg/pr90773-1a.C: Likewise.
* g++.dg/pr90773-1b.C: Likewise.
* g++.dg/pr90773-1c.C: Likewise.
* g++.dg/pr90773-1d.C: Likewise.
* gcc.target/i386/pr90773-1.c: Likewise.
* gcc.target/i386/pr90773-2.c: Likewise.
* gcc.target/i386/pr90773-3.c: Likewise.
* gcc.target/i386/pr90773-4.c: Likewise.
* gcc.target/i386/pr90773-5.c: Likewise.
* gcc.target/i386/pr90773-6.c: Likewise.
* gcc.target/i386/pr90773-7.c: Likewise.
* gcc.target/i386/pr90773-8.c: Likewise.
* gcc.target/i386/pr90773-9.c: Likewise.
* gcc.target/i386/pr90773-10.c: Likewise.
* gcc.target/i386/pr90773-11.c: Likewise.
* gcc.target/i386/pr90773-12.c: Likewise.
* gcc.target/i386/pr90773-13.c: Likewise.
* gcc.target/i386/pr90773-14.c: Likewise.

tree-optimization/100253 - fix bogus aligned vectorized loads/stores

At some point DR_MISALIGNMENT was supposed to be -1 when the
access was not element aligned.  That's obviously not true at this
point so this adjusts both store and load vectorizing to no longer
assume this which in turn allows simplifying the code.

2021-04-29  Richard Biener  <rguenther@suse.de>

PR tree-optimization/100253
* tree-vect-stmts.c (vectorizable_load): Do not assume
element alignment when DR_MISALIGNMENT is -1.
(vectorizable_store): Likewise.

* g++.dg/pr100253.C: New testcase.

testsuite: Remove dg-options from pr100305.c [PR100305]

The test FAILs on i?86-linux (due to -Wpsabi warnings).  But, on closer
inspection it seems there is another problem, the dg-options in the testcase
means that the test is compiled with -O0 -O, -O1 -O, -O2 -O, -O3 -O, -Os -O
etc. options, so effectively is tested multiple times with the same options.

Fixed by dropping the dg-options line, then we have -w by default and iterate
over all the optimization levels (including the -O).

2021-04-29  Jakub Jelinek  <jakub@redhat.com>

PR target/100305
* gcc.c-torture/compile/pr100305.c: Remove dg-options.  Add PR line.

aarch64: Fix ICE in aarch64_add_offset_1_temporaries [PR100302]

In PR94121 I've changed aarch64_add_offset_1 to use absu_hwi instead of
abs_hwi because offset can be HOST_WIDE_INT_MIN.  As can be seen with
the testcase below, aarch64_add_offset_1_temporaries suffers from the same
problem and should be in sync with aarch64_add_offset_1, i.e. for
HOST_WIDE_INT_MIN it needs a temporary.

2021-04-29  Jakub Jelinek  <jakub@redhat.com>

PR target/100302
* config/aarch64/aarch64.c (aarch64_add_offset_1_temporaries): Use
absu_hwi instead of abs_hwi.

* gcc.target/aarch64/sve/pr100302.c: New test.