tu: Fix the size of patch control points state

tu6_emit_patch_control_points was called with CS size calculated
at compile time, but HS params have dynamic size. Account for this.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7479

Fixes: 68f3c38c8011e3ff304a67b6ffb33fd21ee65b0c
("tu: Implement extendedDynamicState2PatchControlPoints")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19075>

aco/spill: Fix spilling of Phi operands

By adding the renamed variable, phi operands got spilled twice at the precessors.

Fixes: dEQP-VK.ray_query.misc.dynamic_indexing
Closes: #7493
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19109>

pan/mdg: Fix 16-bit alignment with spiller

The loop over sources has to happen for every instruction, regardless of whether
we also need to register allocate the destination. The other source loops handle
this properly, but this one was missed.

Fixes spilling failure in shaders/android/angle/aztec_ruins/16.shader_test when
the input NIR is shuffled a bit (from reordering passes).

Fixes: 129d390bd8c ("pan/mdg: Fix bound setting in RA for sources")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19093>

pan/mdg: Limit work registers for large workgroups

When more than 8 registers are used, Midgard can only fit 64 threads in a
thread group. For barriers to work properly, a threadgroup must fit an entire
work group. The GL driver configures the hardware to have threadgroups the size
of work groups. That means if more than 64 threads are used in a workgroup, and
more than 8 registers are used, the hardware will fault spawning threads.

To workaround this hardware limitation, we need to limit the number of work
registers used depending on the size of the workgroup. Typically, the work group
size is known at compile-time so that determination can usually be made without
variants. To avoid variants, we make a pessimistic estimate in the case when
it's not known at compile-time.

shader-db shows 6 shaders affected. I expect that all of these would fault with
DATA_INVALID_FAULT if they tried to execute before this patch, due to the
oversize local size, and faulting is even slower than spilling ;-)

Fixes dEQP-GLES31.functional.synchronization.* on Mali-T860.

instructions HURT:   shaders/android/gfxbench/carchase/6.shader_test MESA_SHADER_COMPUTE: 121 -> 157 (29.75%)
instructions HURT:   shaders/android/gfxbench/carchase/386.shader_test MESA_SHADER_COMPUTE: 121 -> 157 (29.75%)
instructions HURT:   shaders/android/gfxbench/carchase/374.shader_test MESA_SHADER_COMPUTE: 141 -> 184 (30.50%)
instructions HURT:   shaders/android/gfxbench/carchase/4-1.shader_test MESA_SHADER_COMPUTE: 141 -> 184 (30.50%)
instructions HURT:   shaders/android/com.miHoYo.GenshinImpact/18.shader_test MESA_SHADER_COMPUTE: 513 -> 933 (81.87%)
instructions HURT:   shaders/android/com.miHoYo.GenshinImpact/16.shader_test MESA_SHADER_COMPUTE: 505 -> 1002 (98.42%)

bundles HURT:   shaders/android/gfxbench/carchase/374.shader_test MESA_SHADER_COMPUTE: 73 -> 116 (58.90%)
bundles HURT:   shaders/android/gfxbench/carchase/4-1.shader_test MESA_SHADER_COMPUTE: 73 -> 116 (58.90%)
bundles HURT:   shaders/android/gfxbench/carchase/6.shader_test MESA_SHADER_COMPUTE: 61 -> 97 (59.02%)
bundles HURT:   shaders/android/gfxbench/carchase/386.shader_test MESA_SHADER_COMPUTE: 61 -> 97 (59.02%)
bundles HURT:   shaders/android/com.miHoYo.GenshinImpact/18.shader_test MESA_SHADER_COMPUTE: 281 -> 701 (149.47%)
bundles HURT:   shaders/android/com.miHoYo.GenshinImpact/16.shader_test MESA_SHADER_COMPUTE: 278 -> 775 (178.78%)

registers helped:   shaders/android/gfxbench/carchase/374.shader_test MESA_SHADER_COMPUTE: 11 -> 8 (-27.27%)
registers helped:   shaders/android/gfxbench/carchase/4-1.shader_test MESA_SHADER_COMPUTE: 11 -> 8 (-27.27%)
registers helped:   shaders/android/gfxbench/carchase/6.shader_test MESA_SHADER_COMPUTE: 14 -> 8 (-42.86%)
registers helped:   shaders/android/gfxbench/carchase/386.shader_test MESA_SHADER_COMPUTE: 14 -> 8 (-42.86%)
registers helped:   shaders/android/com.miHoYo.GenshinImpact/16.shader_test MESA_SHADER_COMPUTE: 16 -> 8 (-50.00%)
registers helped:   shaders/android/com.miHoYo.GenshinImpact/18.shader_test MESA_SHADER_COMPUTE: 16 -> 8 (-50.00%)

threads helped:   shaders/android/gfxbench/carchase/6.shader_test MESA_SHADER_COMPUTE: 1 -> 2 (100.00%)
threads helped:   shaders/android/gfxbench/carchase/386.shader_test MESA_SHADER_COMPUTE: 1 -> 2 (100.00%)
threads helped:   shaders/android/gfxbench/carchase/374.shader_test MESA_SHADER_COMPUTE: 1 -> 2 (100.00%)
threads helped:   shaders/android/gfxbench/carchase/4-1.shader_test MESA_SHADER_COMPUTE: 1 -> 2 (100.00%)
threads helped:   shaders/android/com.miHoYo.GenshinImpact/16.shader_test MESA_SHADER_COMPUTE: 1 -> 2 (100.00%)
threads helped:   shaders/android/com.miHoYo.GenshinImpact/18.shader_test MESA_SHADER_COMPUTE: 1 -> 2 (100.00%)

spills HURT:   shaders/android/gfxbench/carchase/374.shader_test MESA_SHADER_COMPUTE: 0 -> 5
spills HURT:   shaders/android/gfxbench/carchase/4-1.shader_test MESA_SHADER_COMPUTE: 0 -> 5
spills HURT:   shaders/android/gfxbench/carchase/6.shader_test MESA_SHADER_COMPUTE: 0 -> 8
spills HURT:   shaders/android/gfxbench/carchase/386.shader_test MESA_SHADER_COMPUTE: 0 -> 8
spills HURT:   shaders/android/com.miHoYo.GenshinImpact/18.shader_test MESA_SHADER_COMPUTE: 0 -> 112
spills HURT:   shaders/android/com.miHoYo.GenshinImpact/16.shader_test MESA_SHADER_COMPUTE: 0 -> 146

fills HURT:   shaders/android/gfxbench/carchase/6.shader_test MESA_SHADER_COMPUTE: 0 -> 26
fills HURT:   shaders/android/gfxbench/carchase/386.shader_test MESA_SHADER_COMPUTE: 0 -> 26
fills HURT:   shaders/android/gfxbench/carchase/374.shader_test MESA_SHADER_COMPUTE: 0 -> 33
fills HURT:   shaders/android/gfxbench/carchase/4-1.shader_test MESA_SHADER_COMPUTE: 0 -> 33
fills HURT:   shaders/android/com.miHoYo.GenshinImpact/18.shader_test MESA_SHADER_COMPUTE: 0 -> 209
fills HURT:   shaders/android/com.miHoYo.GenshinImpact/16.shader_test MESA_SHADER_COMPUTE: 0 -> 234

total instructions in shared programs: 1521691 -> 1522766 (0.07%)
instructions in affected programs: 1542 -> 2617 (69.71%)
helped: 0
HURT: 6
HURT stats (abs)   min: 36.0 max: 497.0 x̄: 179.17 x̃: 43
HURT stats (rel)   min: 29.75% max: 98.42% x̄: 50.13% x̃: 30.50%
95% mean confidence interval for instructions value: -49.36 407.69
95% mean confidence interval for instructions %-change: 17.14% 83.12%
Inconclusive result (value mean confidence interval includes 0).

total bundles in shared programs: 649296 -> 650371 (0.17%)
bundles in affected programs: 827 -> 1902 (129.99%)
helped: 0
HURT: 6
HURT stats (abs)   min: 36.0 max: 497.0 x̄: 179.17 x̃: 43
HURT stats (rel)   min: 58.90% max: 178.78% x̄: 94.01% x̃: 59.02%
95% mean confidence interval for bundles value: -49.36 407.69
95% mean confidence interval for bundles %-change: 36.20% 151.83%
Inconclusive result (value mean confidence interval includes 0).

total registers in shared programs: 90681 -> 90647 (-0.04%)
registers in affected programs: 82 -> 48 (-41.46%)
helped: 6
HURT: 0
helped stats (abs) min: 3.0 max: 8.0 x̄: 5.67 x̃: 6
helped stats (rel) min: 27.27% max: 50.00% x̄: 40.04% x̃: 42.86%
95% mean confidence interval for registers value: -8.03 -3.30
95% mean confidence interval for registers %-change: -50.95% -29.13%
Registers are helped.

total threads in shared programs: 55717 -> 55723 (0.01%)
threads in affected programs: 6 -> 12 (100.00%)
helped: 6
HURT: 0
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
95% mean confidence interval for threads value: 1.00 1.00
95% mean confidence interval for threads %-change: 100.00% 100.00%
Threads are helped.

total spills in shared programs: 1108 -> 1392 (25.63%)
spills in affected programs: 0 -> 284
helped: 0
HURT: 6

total fills in shared programs: 4721 -> 5282 (11.88%)
fills in affected programs: 0 -> 561
helped: 0
HURT: 6

Cc: mesa-stable
Closes: #7228
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19092>

pan/mdg: Lower PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK on Midgard

The register file on Midgard is not large enough to sustain 256 threads in a
threadgroup when all ISA-defined registers are used. As such, we want
to advertise the smallest MAX_THREADS_PER_BLOCK permissible by the spec to
avoid compiling shaders that will necessarily spill. The minimum-maximum in
OpenGL ES 3.1 is 128, so set that on Midgard.

6 compute shaders LOST in shader-db due to exceeding this new limit. These
shaders would fault if they were attempted to be executed.

Cc: mesa-stable
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19092>

panfrost/ci: Remove stale fail

Due to fractional run. This whole section passes.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19092>

anv: Enable 16 bit float ops on devices that have a LSC

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17988>

intel/compiler: Support 16 bit float ops

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17988>

Revert "panfrost/ci: Disable t720 jobs"

This reverts commit b3a69d1c31a0c4073e7865945b9f70f96be6c34e.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19113>

v3dv/pipeline: keep qpu_insts around if we expect them to be used later

If the pipeline was created with the creation flags
VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR or
VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR it is
really likely that methods from VK_KHR_pipeline_executable_properties
that would require having access to the qpu insts around will be
called.

Instead of getting those back from the BO where we upload them, we
just keep them around. This could require more host memory, but would
allow us to avoid needing to handle map/unmap the BO when needed (so
needing the host memory in any case). This can be tricky if those
methods are being called from different threads (so we can avoid
adding a mutex there).

In the same way, if the pipeline was not created with those flags, we
skip collecting data that requires the QPU. Only
GetPipelineExecutableProperties is allowed to be called without any of
those flags, and doesn't require that info.

This fixes a race condition crash at GetPipelineExecutableProperties
when using fossilize-replay with some fossils with several shaders,
and using several threads, as some thread would be unmapping the bo
before other thread stopped to use it.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18859>

glthread: leave dlist dispatch in place for Begin/End

If Begin/End are called from a display list make sure to leave
the dlist.c's dispatch table in place just like the non-glthread
code does.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7335
Fixes: 7f1cac7ba682 ("mesa/glthread: enable immediate mode")

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19088>

radv: discard the PS epilog when the pipeline doesn't use a fragment shader

This makes no sense and this was broken.

Fixes dEQP-VK.mesh_shader.ext.smoke.*_lib.mesh_shader_triangle_rasterization_disabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19019>

radv: do not create a noop FS when the FS is imported from a library

The entrypoint can be NULL even if the FS is imported from a library,
but we shouldn't overwrite the pre-compiled FS by a noop.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19019>

Revert "CI: Igalia farm is down"

This reverts commit aa405b789ebf1797fdb3a1891fac49d0cca21c42.

Igalia farm is up again. Switch died and it needed to be replaced.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19102>

mesa: add EXT_debug_label support

KHR_debug provides the same functionality but this extension is
still in use and adding support for it seems fairly harmless.

For example its used by Unity and without it we keep
getting given apitraces from Unity games that just spew out
unsupported function errors due to the missing support.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19029>

ci/windows: Getting the default supported windows version to be 7 when using mingw

MSVC are already tested with default windows version 8

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19096>

ci/windows: Remove -Dlibelf:warning_level=1 as libelf subproject are already removed

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19096>

ci/windows: Enable gles1 for msvc

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19096>

radv/rra: Use the accel struct type for header validation

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19089>

radv/rra: Continue dumping accel structs if validation fails

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19089>

radv/rra: Add basic header validation

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19089>

radv/rra: Validate before gathering bvh info

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19089>

radv/rra: Fix dumps in the case of aliasing

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19089>

CI: Igalia farm is down

It seems a power outage affected the Raspberry Pi farm nodes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19095>

util: Turn -DWINDOWS_NO_FUTEX to be pre_args

Turn -DWINDOWS_NO_FUTEX to be pre_args for not need add direct dependencies
to dep_futex for libraries and executables.
So only add dependencies to idep_mesautil is enough.

And this will make sure all source code are either using Windows futex,
or use mtx_t consistently across different sources, other than mixed usage of
futex and mtx_t before this commit.

If -DWINDOWS_NO_FUTEX is not globally available, that would cause
/src/util/simple_mtx.h:116: undefined reference to `futex_wait'

This error is raised when
 * compiled with -D min-windows-version=7
 * moved futex_wait from futex.h to futex.c
 * used simple_mtx_t in more codes

Or linkage error:
src/compiler/libcompiler.a.p/glsl_types.cpp.obj: in function `futex_wake':
/../../src/util/futex.h:154: undefined reference to `WaitOnAddress'
When:
 * compiled with -D min-windows-version=7
 * used simple_mtx_t in more codes

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7494
Fixes: c002bbeb2f7 ("util: Add a Win32 futex impl")

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19087>

mesa,gallium: Revert "Make point coord origin a CAP"

This reverts commit e749f67f8989874f6795d95422c1f3eb4d2706ba, which added a CAP
to support drivers that can only do upside-down point coordinates. That was
added specifically for Asahi, since Metal's point coordinate convention is
opposite Mesa's. Since then, additional reverse-engineering aided by the PowerVR
headers led me to the bit doing the flip in hardware, so Asahi does not use the
CAP since baadc1ec13f ("asahi: Don't use lower_wpos_pntc"). Garbage collect it.

[If it's needed for future hardware, we can revive it. But the plan is Vulkan
anyway.]

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19078>

intel: Add and use intel_engines_class_to_string()

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18975>

intel: Convert i915 engine type to intel in tools/ common/ and ds/

This ones were left to be done after initial conversion.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18975>

intel: Convert missing i915 engine types to intel

This convertions were missed due to bad rebased in my end, sorry.

Fixes: 03b959286e2c ("intel: Make engine related functions and types not i915 dependent")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18975>

nir: Be smarter fusing ffma

If there is a single use of fmul, and that single use is fadd, it makes
sense to fuse ffma, as we already do. However, if there are multiple
uses, fusing may impede code gen. Consider the source fragment:

   a = fmul(x, y)
   b = fadd(a, z)
   c = fmin(a, t)
   d = fmax(b, c)

The fmul has two uses. The current ffma fusing is greedy and will
produce the following "optimized" code.

   a = fmul(x, y)
   b = ffma(x, y, z)
   c = fmin(a, t)
   d = fmax(b, c)

Actually, this code is worse! Instead of 1 fmul + 1 fadd, we now have 1
fmul + 1 ffma. In effect, two multiplies (and a fused add) instead of
one multiply and an add. Depending on the ISA, that could impede
scheduling or increase code size. It can also increase register
pressure, extending the live range.

It's tempting to gate on is_used_once, but that would hurt in cases
where we really do fuse everything, e.g.:

   a = fmul(x, y)
   b = fadd(a, z)
   c = fadd(a, t)

For ISAs that fuse ffma, we expect that 2 ffma is faster than 1 fmul + 2
fadd. So what we really want is to fuse ffma iff the fmul will get
deleted. That occurs iff all uses of the fmul are fadd and will
themselves get fused to ffma, leaving fmul to get dead code eliminated.
That's easy to implement with a new NIR search helper, checking that all
uses are fadd.

shader-db results on Mali-G57 [open shader-db + subset of closed]:

total instructions in shared programs: 179491 -> 178991 (-0.28%)
instructions in affected programs: 36862 -> 36362 (-1.36%)
helped: 190
HURT: 27

total cycles in shared programs: 10573.20 -> 10571.75 (-0.01%)
cycles in affected programs: 72.02 -> 70.56 (-2.02%)
helped: 28
HURT: 1

total fma in shared programs: 1590.47 -> 1582.61 (-0.49%)
fma in affected programs: 319.95 -> 312.09 (-2.46%)
helped: 194
HURT: 1

total cvt in shared programs: 812.98 -> 813.03 (<.01%)
cvt in affected programs: 118.53 -> 118.58 (0.04%)
helped: 65
HURT: 81

total quadwords in shared programs: 98968 -> 98840 (-0.13%)
quadwords in affected programs: 2960 -> 2832 (-4.32%)
helped: 20
HURT: 4

total threads in shared programs: 4693 -> 4697 (0.09%)
threads in affected programs: 4 -> 8 (100.00%)
helped: 4
HURT: 0

v2: Update trace checksums for virgl due to numerical differences.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18814>

glthread: fix buffer allocation size with non-signed buffer offset path

this needs to always add the start_offset to avoid creating
buffers that are too small

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18994>

gallium/vl: Add opaque rgb pixel formats

Signed-off-by: Andri Yngvason <andri@yngvason.is>
Reviewed-by: Simon Ser <contact@emersion.fr>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18959>

mesa/main: remove driver-cap for ARB_point_sprite

It's always supported, no need for checks here.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Begrudgingly-reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19049>

mesa/st: rip out point-sprite cap

All current drivers reports supporting this cap, let's just assume
it's always supported.

It seems better to lower this in the drivers, like we already do for
etnaviv, panfrost and zink...

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Begrudgingly-reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19049>

rusticl: correctly check global argument size

As the spec that is quoted in the comment says, if the argument is a
memory object, arg_size should be different than sizeof(cl_mem). The
previous verification only worked if the underlying type has the same
size as sizeof(cl_mem).

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18985>

rusticl: use 32-bit address format for 32-bit devices

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18985>

clc: add 32-bit target

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18985>

panfrost/ci: Disable t720 jobs

They're dead, Jim!

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19084>

zink: use util_dynarray_clear

We already have a helper for this, let's use it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19068>

zink: fixup dynarray-type

This doesn't make a functional difference, because the size here ends up
being the same; the size of a pointer. But let's use the right type for
consistency.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19068>

zink: fix broken pool-alloc consolidation

When appending the content of a util_dynarray to another util_dynarray, we
need to copy the content to the *end* of the util_dynarray, not the
beginning.

As we've already resized the dynarray, We also shouldn't add to the size
once more at the end, otherwise we'll end up with garbage.

Fixes: 43dcdf33654 ("zink: rework/improve descriptor pool overflow handling on batch reset")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7485
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19068>

anv: reduce BT emissions & surface state writes with push descriptors

Zink on Anv running Gfxbench gl_driver2 is significantly slower than
Iris.

The reason is simple, whereas Iris implements uniform updates using
push constants and only has to emit 3DSTATE_CONSTANT_* packets, Zink
uses push descriptors with a uniform buffer, which on our
implementation use both push constants & binding tables.

Anv ends up doing the following for each uniform update :
   - allocate 2 surface states :
      - one for the uniform buffer as the offset specify by zink
      - one for the descriptor set buffer
   - pack the 2 RENDER_SURFACE_STATE
   - re-emit binding tables
   - re-emit push constants

Of all of those operations, only the last one ends up being useful in
this benchmark because all the uniforms have been promoted to push
constants.

This change defers the 3 first operations at draw time and executes
them only if the pipeline needs them.

Vkoverhead before / after :
  descriptor_template_1ubo_push:                      40670 / 85786
  descriptor_template_12ubo_push:                      4050 / 13820
  descriptor_template_1combined_sampler_push,         34410 / 34043
  descriptor_template_16combined_sampler_push,         2746 / 2711
  descriptor_template_1sampled_image_push,            34765 / 34089
  descriptor_template_16sampled_image_push,            2794 / 2649
  descriptor_template_1texelbuffer_push,             108537 / 111342
  descriptor_template_16texelbuffer_push,             20619 / 20166
  descriptor_template_1ssbo_push,                     41506 / 85976
  descriptor_template_8ssbo_push,                      6036 / 18703
  descriptor_template_1image_push,                    88932 / 89610
  descriptor_template_16image_push,                   20937 / 20959
  descriptor_template_1imagebuffer_push,             108407 / 113240
  descriptor_template_16imagebuffer_push,             32661 / 34651

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>

anv: add analysis for push descriptor uses and store it in shader cache

We'll use this information to avoid :
   - binding table emission
   - allocation of surface states

v2: Fix anv_nir_push_desc_ubo_fully_promoted()

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>

anv: initialization pipeline layout to 0s

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>

anv: track descriptor set layout flags

To identify push descriptors.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>

anv: limit push constant reemission

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>

isl: avoid gfx version switch cases on the hot path

Some of the surface state packing functions are called from the hot
path in Anv. We can use function pointers to avoid repeatedly going
through switch/case.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>

anv: remove multiple push descriptors

VUID-VkPipelineLayoutCreateInfo-pSetLayouts-00293

   pSetLayouts must not contain more than one descriptor set layout
   that was created with
   VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR set

There is only one push descriptor set with all the descriptor sets, so
no need to have an array.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>

anv: optimize 3DSTATE_VF emission

We can avoid reemitting this when the index buffer index type doesn't
change.

Also we don't need to update this when the pipeline changes as we do
not pull any value from the pipeline. Instead rely on the dynamic
state to tell if dyn->ia.primitive_restart_enable changed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>

anv: limit calls into cmd_buffer_flush_dynamic_state

Avoids a bunch of checks if we can.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>

anv: comment out the Gfx8/9 VB cache key workaround for newer Gens

This code shows up a little on profiling on Gfx12 and since it's only
a gfx8/9 workaround we might as well ifdef it out.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>

anv: remove unused code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>

vulkan/runtime: don't lookup the pipeline disk cache if disabled

When the Anv pipeline got migrated to the runtime, we gain/lost a bit
of functionality which is that the disk cache is always read
regardless of VK_ENABLE_PIPELINE_CACHE=0.

This change brings the old behavior back.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 591da9877900c ("vulkan: Add a common VkPipelineCache implementation")
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19050>

radv: Mark dEQP-VK.ray_query.misc.dynamic_indexing as crashing in CI.

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7493
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19073>

vulkan/wsi: Add dep_libudev to idep dependencies

Otherwise users of `idep_vulkan_wsi` won't pull in the udev dependency,
which will cause the linker to fail later on in compiling.

The user of this dependency is lavapipe which would fail to link if this
isn't provided.

Fixes: 4885e63a6d20c57f98b7b641ea3c39a8ff3ae2dd (vulkan/wsi: implement missing wsi_register_device_event)

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19037>

ci/traces: Blender demo (Cube Diorama) flakes on Intel APL

Acked-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19067>

nir: move fusing csel and comparisons to opt_late_algebraic

With that simple comparisons are cleaned up properly.

This helps with some tesselation shaders on r600.

Shader-db stats R600/Cayman:

--------------------------------------------------------------
total dw in shared programs: 1621806 -> 1620884 (-0.06%)
dw in affected programs: 41650 -> 40728 (-2.21%)
helped: 211
HURT: 4
helped stats (abs) min: 2 max: 26 x̄: 4.46 x̃: 4
helped stats (rel) min: 0.30% max: 9.68% x̄: 2.87% x̃: 2.52%
HURT stats (abs)   min: 2 max: 8 x̄: 5.00 x̃: 5
HURT stats (rel)   min: 0.23% max: 1.67% x̄: 1.02% x̃: 1.09%
95% mean confidence interval for dw value: -4.81 -3.77
95% mean confidence interval for dw %-change: -3.03% -2.57%
Dw are helped.

total gprs in shared programs: 41192 -> 41182 (-0.02%)
gprs in affected programs: 731 -> 721 (-1.37%)
helped: 53
HURT: 45
helped stats (abs) min: 1 max: 3 x̄: 1.23 x̃: 1
helped stats (rel) min: 5.88% max: 40.00% x̄: 16.56% x̃: 14.29%
HURT stats (abs)   min: 1 max: 2 x̄: 1.22 x̃: 1
HURT stats (rel)   min: 7.69% max: 40.00% x̄: 19.42% x̃: 20.00%
95% mean confidence interval for gprs value: -0.37 0.16
95% mean confidence interval for gprs %-change: -3.92% 3.85%
Inconclusive result (value mean confidence interval includes 0).

total alu_groups in shared programs: 203677 -> 203632 (-0.02%)
alu_groups in affected programs: 2876 -> 2831 (-1.56%)
helped: 68
HURT: 30
helped stats (abs) min: 1 max: 4 x̄: 1.46 x̃: 1
helped stats (rel) min: 0.84% max: 25.00% x̄: 7.48% x̃: 5.41%
HURT stats (abs)   min: 1 max: 6 x̄: 1.80 x̃: 1
HURT stats (rel)   min: 1.98% max: 33.33% x̄: 10.09% x̃: 5.61%
95% mean confidence interval for alu_groups value: -0.81 -0.11
95% mean confidence interval for alu_groups %-change: -4.20% <.01%
Alu_groups are helped.

total loops in shared programs: 72 -> 72 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total cf in shared programs: 88230 -> 88233 (<.01%)
cf in affected programs: 71 -> 74 (4.23%)
helped: 1
HURT: 4
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 33.33% max: 33.33% x̄: 33.33% x̃: 33.33%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.89% max: 33.33% x̄: 17.14% x̃: 16.67%
95% mean confidence interval for cf value: -0.51 1.71
95% mean confidence interval for cf %-change: -24.20% 38.29%
Inconclusive result (value mean confidence interval includes 0).

total stack in shared programs: 3827 -> 3827 (0.00%)
stack in affected programs: 0 -> 0
helped: 0
HURT: 0

LOST:   0
GAINED: 0

Total CPU time (seconds): 45.32 -> 41.69 (-8.01%)
--------------------------------------------------------------

v2: Simplify replacement pattern (Rhys Perry)
v3: fix ws (Alexander Orzechowski)
v4: move the original lowering to opt_late_algebraic and
    drop cleanup code (Alyssa)
v5: Add shader-sb stats (Alyssa)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18970>

r600/sfn: run cleanup passes after late algebraic opt

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18970>

hasvk: Correctly set NonPerspectiveBarycentricEnable on gfx7

The incorrect #else has existed since commit bfd9942cdc0, but the issue
was already present before that. NonPerspectiveBarycentricEnable must be
enabled if non-perspective interpolation is used.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7449
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19004>

nir: fix NIR_DEBUG=validate_ssa_dominance

validate_ssa_def_dominance() asserts :

   validate_assert(state, !BITSET_TEST(state->ssa_defs_found, def->index));

Because the previous validation lefts bits set when it processed the
IR.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18966>

util/mesa/wide: Rename _SIMPLE_MTX_INITIALIZER_NP to SIMPLE_MTX_INITIALIZER

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18393>

ci/bin: Remove whitespace from token files

There was a security problem with some `gitlab_gql.py` scenarios because
of `\r` and `\n` in the token file, which interrupted the requests for
Gitlab endpoints.

Stripping the token file after reading the file content solves the
problem.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18066>

ci/bin: Fix requirements.txt

Add missing aiohttp and PyYAML packages

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18066>

agx: Reserve live-in regs at the start of block

...Rather than reserving the union of the registers live-out of the
predecessors. This avoids reserving registers that are killed along a
control flow edge (where the predecessor has another successor that does
use the register).

glmark2 subset of shaderdb:

total instructions in shared programs: 6442 -> 6440 (-0.03%)
instructions in affected programs: 42 -> 40 (-4.76%)
helped: 1
HURT: 0

total bytes in shared programs: 42186 -> 42174 (-0.03%)
bytes in affected programs: 270 -> 258 (-4.44%)
helped: 1
HURT: 0

total halfregs in shared programs: 1769 -> 1757 (-0.68%)
halfregs in affected programs: 75 -> 63 (-16.00%)
helped: 3
HURT: 0
helped stats (abs) min: 4.0 max: 4.0 x̄: 4.00 x̃: 4
helped stats (rel) min: 16.00% max: 16.00% x̄: 16.00% x̃: 16.00%

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Pass in max regs as a paramter to RA

This will allow us to restrict max regs later.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Introduce ra_ctx data structure

We have more parameters to pass, this will get unwieldly otherwise.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Write to r0l with a "nesting" instruction

This avoids modeling the r0l register explicitly in the IR, which would
complicate RA for little benefit at this stage. Do the simplest thing
that could possibly work in SSA.

glmark2 subset.

total instructions in shared programs: 6442 -> 6442 (0.00%)
instructions in affected programs: 701 -> 701 (0.00%)
helped: 4
HURT: 5
helped stats (abs) min: 1.0 max: 3.0 x̄: 2.00 x̃: 2
helped stats (rel) min: 1.46% max: 7.69% x̄: 4.03% x̃: 3.48%
HURT stats (abs)   min: 1.0 max: 3.0 x̄: 1.60 x̃: 1
HURT stats (rel)   min: 0.81% max: 7.41% x̄: 2.67% x̃: 1.14%
95% mean confidence interval for instructions value: -1.58 1.58
95% mean confidence interval for instructions %-change: -3.70% 3.08%
Inconclusive result (value mean confidence interval includes 0).

total bytes in shared programs: 42196 -> 42186 (-0.02%)
bytes in affected programs: 7768 -> 7758 (-0.13%)
helped: 8
HURT: 5
helped stats (abs) min: 2.0 max: 18.0 x̄: 7.25 x̃: 4
helped stats (rel) min: 0.13% max: 7.26% x̄: 2.02% x̃: 0.97%
HURT stats (abs)   min: 6.0 max: 18.0 x̄: 9.60 x̃: 6
HURT stats (rel)   min: 0.82% max: 6.32% x̄: 2.37% x̃: 1.02%
95% mean confidence interval for bytes value: -7.02 5.48
95% mean confidence interval for bytes %-change: -2.30% 1.63%
Inconclusive result (value mean confidence interval includes 0).

total halfregs in shared programs: 1926 -> 1769 (-8.15%)
halfregs in affected programs: 1395 -> 1238 (-11.25%)
helped: 71
HURT: 0
helped stats (abs) min: 1.0 max: 10.0 x̄: 2.21 x̃: 2
helped stats (rel) min: 1.92% max: 52.63% x̄: 15.33% x̃: 11.76%
95% mean confidence interval for halfregs value: -2.69 -1.73
95% mean confidence interval for halfregs %-change: -17.98% -12.68%
Halfregs are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Preload vertex/instance ID only at start

This means we don't reserve the registers, which improves RA
considerably. Using a special preload psuedo-op instead of a regular
move allows us to constrain semantics and gaurantee coalescing.

shader-db on glmark2 subset:

total instructions in shared programs: 6448 -> 6442 (-0.09%)
instructions in affected programs: 230 -> 224 (-2.61%)
helped: 4
HURT: 0

total bytes in shared programs: 42232 -> 42196 (-0.09%)
bytes in affected programs: 1530 -> 1494 (-2.35%)
helped: 4
HURT: 0

total halfregs in shared programs: 2291 -> 1926 (-15.93%)
halfregs in affected programs: 2185 -> 1820 (-16.70%)
helped: 75
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Print agx_dim appropriately

Easier to read, and gets us closer to proper disasm in Mesa.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Print instructions as "dest = src"

This makes the dataflow easier to read, especially with splits and
collects (which take variable numbers of sources/destinations).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Emit trap at pack-time, not during isel

This makes the shaderdb stats make more sense.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Rename "combine" to "collect"

For consistency with ir3 and bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Dynamically size split instruction

This is more flexible.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Switch to dynamic allocation of srcs/dests

So we can handle parallel copies later.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Improve printing of immediate sources

For floats, decode the float. Regardless, the size speciifer is
redundant.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Don't prefix pseudo-ops

It's not really buying us anything and it clutters the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Emit smaller combines for nir_op_vec2/3

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Set PIPE_SHADER_CAP_INDIRECT_CONST_ADDR

Avoids spilling in t-rex.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

agx: Add iterators for phi/non-phi instructions

We know that phi nodes are always at the start (this is asserted in
agx_validate and a fundamental invariant of SSA form). That means we can
cheaply iterate all n phi nodes forward (or n non-phi nodes backwards)
in O(n) time. We already open code this idiom in a few places, use
common iterators instead so we don't need to justify in random places.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>

zink: disable fbfetch when flushing clears

this ensures there's no weird perf happening, avoids using renderpass
instead of dynamic rendering, and avoids hitting an assert from broken
framebuffer construction

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>

zink: unset rp_changed after initializing renderpass attachments

if fbfetch is setup here, it will flag rp_changed

this is already inside renderpass setup, however, so just unset it
to avoid erroneously trigering the assert

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>

zink: clamp line_stipple_factor to 1 if stipple is disabled

0 is technically an illegal value even though it won't be read in this case

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>

zink: don't add other usage bits for transient images

this is illegal

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>

zink: check core feature for pipeline cache control

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>

zink: Fix dummy CB path decision for VK_EXT_cwe presence.

We have to do the dummy workaround when we *don't* have the ext.  This was
apparently a mis-sedding.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19057>

rusticl/mem: propper CL_MEM_ALLOC_HOST_PTR support

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>

lp: claim being UMA

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>

rusticl/mem: rewrite the (un)mapping code

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>

rusticl: add helper ctx wrapper for coherent and direct mapping

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>

rusticl: rework resource mappings a little

The _async variants will be removed later.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>

rusticl/mesa: add bx() method to PipeTransfer

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>

rusticl: add support for coherent resources

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>

glthread: fix matrix stack depth tracking

Dont bump the depth if the application attempts to overflow or
underflow the stack.

Fixes: 6febe2b880e7 ("glthread: track all matrix stack depths")

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19059>

asahi: Remove no-direct-packing

It's weird.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>

asahi: Use a header more like Intel's GenXML

We're trying to converge on a common schema.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>

asahi,panfrost: Remove exact attribute

Not used, although in the future it might be...

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>

panfrost,asahi: Remove unused function

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>

panfrost,asahi: Remove unused prepare macro

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>

asahi/genxml: Defeature uint/float

Unused, relic from panfrost and not in upstream genxml.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>

asahi: Eliminate "Pixel Format" type from GenXML

This is leaky and hurts compatibility with upstream GenXML. Just use the
actual hardware fields.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>