Tapani Pälli [Thu, 22 Aug 2019 07:49:36 +0000 (10:49 +0300)]
egl: reset blob cache set/get functions on terminate
Fixes errors seen with eglSetBlobCacheFuncsANDROID on Android when
running dEQP that terminates and reinitializes a display.
Fixes:
6f5b57093b3 "egl: add support for EGL_ANDROID_blob_cache"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Kenneth Graunke [Fri, 26 Apr 2019 17:44:18 +0000 (10:44 -0700)]
iris: Avoid unnecessary resolves on transfer maps
We were always resolving the buffer as if we were accessing it via
CPU maps, which don't understand any auxiliary surfaces. But we often
copy to a temporary using BLORP, which understands compression just
fine. So we can avoid the resolve, and accelerate the copy as well.
Fixes:
9d1334d2a0f ("iris: Use copy_region and staging resources to avoid transfer stalls")
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Kenneth Graunke [Wed, 24 Apr 2019 03:19:37 +0000 (20:19 -0700)]
iris: Drop copy format hacks from copy region based transfer path.
This doesn't work for compressed formats, as the source texture and
temporary texture would have different block sizes. (Forcing the driver
to always take the GPU path would expose the bug.) Instead, just use
the source format for the temporary, and let blorp_copy deal with
overrides.
The one case where we can't do this is ASTC, because isl won't let us
create a linear ASTC surface. Fall back to the CPU paths there for now.
Fixes:
9d1334d2a0f ("iris: Use copy_region and staging resources to avoid transfer stalls")
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Kenneth Graunke [Mon, 19 Aug 2019 20:57:46 +0000 (13:57 -0700)]
iris: Update fast clear colors on Gen9 with direct immediate writes.
Gen11 stores the fast clear color in an "indirect clear buffer", as
a packed pixel value. Gen9 hardware stores it as a float or integer
value, which is interpreted via the format. We were trying to store
that in a buffer, for similarity with Icelake, and MI_COPY_MEM_MEM
it from there to the actual SURFACE_STATE bytes where it's stored.
This unfortunately doesn't work for blorp_copy(), which does bit-for-bit
copies, and overrides the format to a CCS-compatible UINT format. This
causes the clear color to be interpreted in the overridden format.
Normally, we provide the clear color on the CPU, and blorp_blit.c:2611
converts it to a packed pixel value in the original format, then unpacks
it in the overridden format, so the clear color we use expands to the
bits we originally desired.
However, BLORP doesn't support this pack/unpack with an indirect clear
buffer, as it would need to do the math on the GPU. On Gen11+, it isn't
necessary, as the hardware does the right thing.
This patch changes Gen9 to stop using an indirect clear buffer and
simply do PIPE_CONTROLs with post-sync write immediate operations
to store the new color over the surface states for regular drawing.
BLORP continues streaming out surface states, and handles fast clear
colors on the CPU.
Fixes:
53c484ba8ac ("iris: blorp using resolve hooks")
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Kenneth Graunke [Tue, 20 Aug 2019 05:36:36 +0000 (22:36 -0700)]
iris: Fix broken aux.possible/sampler_usages bitmask handling
For renderable surfaces, we allocate SURFACE_STATEs for each bit in
res->aux.possible_usages. Sampler views use res->aux.sampler_usages.
When pinning buffers, we call surf_state_offset_for_aux() to calculate
the offset to the desired surface state. surf_state_offset_for_aux()
took an aux_modes parameter, which should be one of those two fields.
However...it was not using that parameter. It always used the broader
res->aux.possible_usages field directly.
One of the callers, update_clear_value(), was passing incorrect masks
for this parameter. It iterated through the bits in order, using
u_bit_scan(), which destructively modifies the mask. So each time we
called it, the count of bits before our selected mode was 0, which would
cause us to always update the SURFACE_STATE for ISL_AUX_USAGE_NONE,
rather than updating each in turn. This was hidden by the earlier bug
where surf_state_offset_for_aux() ignored the parameter.
Fixes:
7339660e803 ("iris: Add aux.sampler_usages.")
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Kenneth Graunke [Mon, 19 Aug 2019 20:52:37 +0000 (13:52 -0700)]
iris: Replace devinfo->gen with GEN_GEN
This is genxml, we can compile out this code.
Fixes:
26606672847 ("iris/gen8: Re-emit the SURFACE_STATE if the clear color changed.")
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Alyssa Rosenzweig [Thu, 22 Aug 2019 20:59:54 +0000 (13:59 -0700)]
pan/midgard: Fix writeout combining
shader-db regression in the scheduler.
Fixes:
dff4986b1aa ("pan/midgard: Emit store_output branch just-in-time")
total bundles in shared programs: 2055 -> 2019 (-1.75%)
bundles in affected programs: 1055 -> 1019 (-3.41%)
helped: 36
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.35% max: 20.00% x̄: 6.71% x̃: 5.16%
95% mean confidence interval for bundles value: -1.00 -1.00
95% mean confidence interval for bundles %-change: -8.45% -4.97%
Bundles are helped.
total quadwords in shared programs: 3444 -> 3408 (-1.05%)
quadwords in affected programs: 1897 -> 1861 (-1.90%)
helped: 36
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.19% max: 14.29% x̄: 3.97% x̃: 2.99%
95% mean confidence interval for quadwords value: -1.00 -1.00
95% mean confidence interval for quadwords %-change: -5.08% -2.86%
Quadwords are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 22 Aug 2019 18:29:23 +0000 (11:29 -0700)]
panfrost: Implement gl_FragCoord correctly
Rather than passing through the transformed gl_Position, we can use the
hardware-level varying for this, which will correctly handle
gl_FragCoord.w
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 22 Aug 2019 15:02:52 +0000 (08:02 -0700)]
panfrost: Remove vertex buffer offset from its size
The offset is added to the base address, so we need to subtract it from
the size to maintain the same end address and thus prevent a buffer
overflow:
end_address = start_address + size
start_address' = start_address + offset
size' = size - offset
end_address' = start_address' + size'
= (start_address + offset) + (size - offset)
= (start_address + size) + (offset - offset)
= start_address + size
= end_address
QED.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 22 Aug 2019 20:27:38 +0000 (13:27 -0700)]
pan/decode: Handle special varyings
We need a special path for special varyings so we parse them correctly
instead of throwing an error when they inevitably point to bad memory.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 22 Aug 2019 20:09:00 +0000 (13:09 -0700)]
pan/decode: Remove size/stride divisibility check
The hardware doesn't care, and a lot of Panfrost code relies on an
oversized buffer. The important part is that (stride *
padded_num_vertices) is no greater than size, which we'll need to check
once we validate instancing.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 22 Aug 2019 20:07:01 +0000 (13:07 -0700)]
pan/decode: Decouple attribute/meta printing
They are independent fields, so the parser should reflect that.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 22 Aug 2019 18:30:13 +0000 (11:30 -0700)]
pan/decode: Print stub for uniforms
We don't need to dump the contents necessary, but having the stub with
the address is useful.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 22 Aug 2019 18:21:35 +0000 (11:21 -0700)]
pan/decode: Decode actual varying_meta address
I don't know who thought this mask was a good idea but unfortunately it
must have been me.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 22 Aug 2019 16:02:48 +0000 (09:02 -0700)]
pan/decode: Downgrade shader property mismatch to warning
If we permit more $whatever through than the shader needs, that's a bit
of a waste, but it isn't an error.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 23:06:23 +0000 (16:06 -0700)]
pan/decode: Validate, but do not print, index buffer
We don't actually care about the *contents* of the index buffer, but we
would rather like to ensure it is present and of the correct size.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 21:57:23 +0000 (14:57 -0700)]
pan/decode: Validate mali_shader_meta stats
We can infer these stats in many cases from the disassembly, so we
should try to sanity check where we can. We may need to be fuzzy about
analysis, since analysis gives us a bound but we don't mind if it's not
used fully by the shader.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 21:28:36 +0000 (14:28 -0700)]
pan/decode: Disassemble before printing shader descriptor
This allows the shader descriptor to access the disassembled stats.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 21:16:32 +0000 (14:16 -0700)]
pan/decode: Promote <no shader> to an error
There is no reason this should happen to an in-spec program, as far as I
know.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 21:15:05 +0000 (14:15 -0700)]
pan/decode: Fix uniform printing
Lazypasting from UBOs.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 21:04:05 +0000 (14:04 -0700)]
pan/decode: Validate blend shaders don't access I/O
We could do better by forcing the checks to *equal* zero (right now, an
indeterminate answer will pass the checks), but this is a start to guard
against some egregious cases.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 19:29:47 +0000 (12:29 -0700)]
pan/decode: Validate and simplify FRAGMENT payloads
There are a number of conditions we need to test for to statically check
for TILE_RANGE_FAULTs, but once these checks are in order, we can print
as-is.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 19:06:50 +0000 (12:06 -0700)]
pan/decode: Validate MFBD tags
These tags need to match up with what's actually described by the MFBD,
so check this. Once this is checked, since the type and contents of the
FBD are obvious from printing above, there's no need to explicitly mark
off the framebuffer line.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 18:52:51 +0000 (11:52 -0700)]
pan/decode: Eliminate non-FBD dumped case
We don't need *more* cases to deal with.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 18:46:06 +0000 (11:46 -0700)]
pan/decode: Removing uniform buffer framing
We can do single line prints:
ubuf_0[192] = memory_161f5000 + 896;
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 18:43:13 +0000 (11:43 -0700)]
pan/decode: Remove mali_attr(_meta) framing
It doesn't give any real added value.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 20:46:00 +0000 (13:46 -0700)]
pan/midgard: Disassemble integer constants in hex
It's usually easier to parse mentally.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 20:45:47 +0000 (13:45 -0700)]
pan/midgard: Explain ffma
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 22:07:36 +0000 (15:07 -0700)]
pan/midgard: Analyze simple loads/store
For shaders using exclusively direct attribute/varyings, we can work
this out statically. For shaders with indirect access, we just set an
upper bound of 16 (the max attributes/varyings we support) and the
actual count will be reported regardless.
We proceed similarly for textures/samplers, as well as for UBOs. While
UBOs can be *indexed* indirectly, the *UBO itself* -- which is what we
count in the shader descriptor (rather than the UBO descriptors) -- is
statically determinable.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 22:02:41 +0000 (15:02 -0700)]
pan/midgard: Compute work_count via writes
This is exact.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 22:18:40 +0000 (15:18 -0700)]
pan/midgard: Sketch static analysis to uniform count
This one is a little tricky, but the idea is that:
r16-r23 are always uniforms
r8-r15 are sometimes work, sometimes uniforms...
...but as work, they are always written before use
...and as uniforms, they are never written before use
So we use that heuristic to determine the count to feed the machine.
We'll record work register use in the next commit.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 21:00:46 +0000 (14:00 -0700)]
pan/decode: Hoist shader-db stats to shared decode
We'll want all this information to validate the shader descriptor.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 17:51:35 +0000 (10:51 -0700)]
nir: Remove nir_const_load_to_arr
There are no remaining users in-tree.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 17:50:31 +0000 (10:50 -0700)]
pan/midgard,bifrost: Expand nir_const_load_to_arr
Panfrost is the only user of the macro; we are better off expanding than
having random stuff in nir.h.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Adam Jackson [Tue, 20 Aug 2019 19:47:22 +0000 (15:47 -0400)]
glx: Make __glXGetDrawableAttribute return true sometimes
Right now it always returns zero, but as of:
commit
a48a6b8a400e6e92961cf7b7b4c287e8e9875f39
Author: Adam Jackson <ajax@redhat.com>
Date: Tue Nov 14 15:13:05 2017 -0500
glx: Prepare driFetchDrawable for no-config contexts
We were hoping it would return true if the drawable could actually be
looked up. It wasn't, so that didn't go very well. With the most recent
update to <GL/glxext.h> glXQueryGLXPbufferSGIX (correctly) returns void,
so there's no longer anything else besides driFetchDrawable that depends
on the return value from __glXGetDrawableAttribute.
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Adam Jackson [Tue, 20 Aug 2019 19:43:06 +0000 (15:43 -0400)]
glx: Sync <GL/glxext.h> with Khronos
Minor fixups required to keep the prototypes matching and to remove
mention of retired enums.
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Adam Jackson [Tue, 20 Aug 2019 19:06:08 +0000 (15:06 -0400)]
glx: Whitespace cleanups
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Engestrom [Sat, 3 Aug 2019 00:38:26 +0000 (01:38 +0100)]
swr: use LLVM version string instead of re-computing it
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Engestrom [Sat, 3 Aug 2019 00:38:20 +0000 (01:38 +0100)]
llvmpipe: use LLVM version string instead of re-computing it
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Engestrom [Sat, 3 Aug 2019 00:49:11 +0000 (01:49 +0100)]
scons: define MESA_LLVM_VERSION_STRING like the other build systems do
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bas Nieuwenhuizen [Sun, 18 Aug 2019 23:36:06 +0000 (01:36 +0200)]
radv: Disable NGG for geometry shaders.
A bunch of remaining issues including some that affect users.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111248
Fixes:
ee21bd7440c "radv/gfx10: implement NGG support (VS only)"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Lionel Landwerlin [Wed, 21 Aug 2019 09:21:05 +0000 (11:21 +0200)]
util/timespec: use unsigned 64 bit integers for nsec values
We added this utility for vulkan where all timeouts are given as
uint64_t values. We can switch from signed to unsigned as this is the
only user and if we ever deal with signed integers somewhere else
we'll have to be careful to use the corresponding
timespec_(add|sub)_msec and always pass absolute values.
v2: Forgot to drop the test calling add_nsec() with a negative number
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Fixes:
d2d70c3bb5 ("util: add a timespec helper")
Acked-by: Daniel Stone <daniels@collabora.com>
Tapani Pälli [Tue, 13 Aug 2019 07:34:06 +0000 (10:34 +0300)]
iris/android: fix build and link with libmesa_intel_perf
Fixes:
0fd4359733e "iris/perf: implement routines to return counter info"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Samuel Pitoiset [Wed, 21 Aug 2019 14:29:46 +0000 (16:29 +0200)]
ac: fix exclusive scans on GFX8-GFX9
This fixes a regression introduced with scan&reduce operations
on GFX10. Note that some subgroups CTS still fail on GFX10 but
I assume it's a different issue.
This fixes dEQP-VK.subgroups.arithmetic.*.subgroupexclusive*.
Fixes:
227c29a80de "amd/common/gfx10: implement scan & reduce operations"
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tapani Pälli [Tue, 20 Aug 2019 05:59:23 +0000 (08:59 +0300)]
util: fix os_create_anonymous_file on android
Commit fixes current crashes with Vulkan applications on Android.
Fixes:
c0376a123418 "util: add anon_file.h for all memfd/temp file usage"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Lionel Landwerlin [Thu, 8 Aug 2019 08:40:30 +0000 (11:40 +0300)]
i965: honor scanout requirement from DRI
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Kenneth Graunke [Tue, 13 Aug 2019 21:33:35 +0000 (14:33 -0700)]
gallium/noop: Implement resource_get_param
v2: Pass through to oscreen rather than faking it (review from Marek).
Fixes:
0346b700833 ("gallium/screen: Add pipe_screen::resource_get_param")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Kenneth Graunke [Tue, 13 Aug 2019 21:32:57 +0000 (14:32 -0700)]
gallium/rbug: Wrap resource_get_param if available
Fixes:
0346b700833 ("gallium/screen: Add pipe_screen::resource_get_param")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Kenneth Graunke [Tue, 13 Aug 2019 21:32:26 +0000 (14:32 -0700)]
gallium/trace: Wrap resource_get_param if available
Fixes:
0346b700833 ("gallium/screen: Add pipe_screen::resource_get_param")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Kenneth Graunke [Tue, 13 Aug 2019 21:28:56 +0000 (14:28 -0700)]
gallium/ddebug: Wrap resource_get_param if available
Fixes:
0346b700833 ("gallium/screen: Add pipe_screen::resource_get_param")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jose Maria Casanova Crespo [Wed, 21 Aug 2019 12:16:16 +0000 (13:16 +0100)]
mesa: recover target_check before get_current_tex_objects
At compressed_tex_sub_image we only can obtain the tex_object after
compressed_subtexture_target_check is validated for TEX_MODE_CURRENT.
So if the target is wrong the error is raised to the user.
This completes the fix for the regression introduced on "mesa: refactor
compressed_tex_sub_image function" of the pending failing tests:
dEQP-GLES3.functional.negative_api.texture.compressedtexsubimage3d
dEQP-GLES31.functional.debug.negative_coverage.get_error.texture.compressedtexsubimage3d
v2: Fix warning that texObj might be used uninitialized (Gert Wollny)
Fixes:
7df233d68dc ("mesa: refactor compressed_tex_sub_image function")
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Kevin Strasser [Fri, 25 Jan 2019 01:29:31 +0000 (17:29 -0800)]
gallium: Add buffer and configs handling or fp16 formats
Expose configs when allow_fp16_configs has been enabled and
DRI_LOADER_CAP_FP16 is set in the loader.
Also, make kms_swrast_dri respect format bpp, to allow for allocating
buffers wider than 32 bpp.
Make fp16 opt-in for gallium.
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Kevin Strasser [Fri, 25 Jan 2019 01:26:31 +0000 (17:26 -0800)]
i965: Add handling for fp16 configs
Expose configs when allow_fp16_configs has been enabled and
DRI_LOADER_CAP_FP16 is set in the loader.
Also, define a new dri configuration option so users can disable exposure of
fp16 formats. Make fp16 opt-in for i965.
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Kevin Strasser [Fri, 25 Jan 2019 01:32:36 +0000 (17:32 -0800)]
gbm: Add buffer handling and visuals for fp16 formats
Define and set a new loader cap DRI_LOADER_CAP_FP16, indicating that gbm can
handle fp16 formats.
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kevin Strasser [Fri, 25 Jan 2019 01:10:02 +0000 (17:10 -0800)]
dri: Add fp16 formats
Add dri formats for RGBA ordered 64 bpp IEEE 754 half precision floating
point. Leverage existing offscreen render support for
MESA_FORMAT_RGBA_FLOAT16 and MESA_FORMAT_RGBX_FLOAT16.
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kevin Strasser [Fri, 25 Jan 2019 00:55:33 +0000 (16:55 -0800)]
egl: Handle dri configs with floating point pixel data
In the case that __DRI_ATTRIB_FLOAT_BIT is set in the dri config, set
EGL_COLOR_COMPONENT_TYPE_FLOAT_EXT in the egl config. Add a field to the
platform driver visual to indicate if it has components that are in floating
point form.
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kevin Strasser [Fri, 25 Jan 2019 00:44:06 +0000 (16:44 -0800)]
dri: Handle configs with floating point pixel data
In order to handle pixel formats that consist of floating point data, enable
floatMode field in the dri config, and set __DRI_ATTRIB_FLOAT_BIT in the
render type attribute.
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kevin Strasser [Fri, 25 Jan 2019 00:36:29 +0000 (16:36 -0800)]
glx: Add fields for color shifts
glx doesn't read the masks from the dri config directly, but for consistency
add shifts to the glxconfig.
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Kevin Strasser [Fri, 25 Jan 2019 00:32:48 +0000 (16:32 -0800)]
egl: Convert configs to use shifts and sizes instead of masks
Change dri2_add_config to take arrays of shifts and sizes, and compare with
those set in the dri config. Convert all platform driver masks
to shifts and sizes.
In order to handle older drivers, where shift attributes aren't available,
we fall back to the mask attributes and compute the shifts with ffs.
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Kevin Strasser [Fri, 14 Jun 2019 21:27:53 +0000 (14:27 -0700)]
util: move bitcount to bitscan.h
bitcount is free from the pipe header dependencies that make u_math.h hard
to include by non-gallium specific code, so move it to bitscan.h. bitscan.h
is included by u_math.h so existing references will continue working.
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Kevin Strasser [Fri, 25 Jan 2019 00:11:11 +0000 (16:11 -0800)]
dri: Add config attributes for color channel shift
The existing mask attributes can only support up to 32 bpp. Introduce
per-channel SHIFT attributes that indicate how many bits, from lsb towards
msb, the bit field is offset. A shift of -1 will indicate that there is no
bit field set for the channel.
As old loaders will still be looking for masks, we set the masks to 0 for
any formats wider than 32 bpp.
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Kevin Strasser [Mon, 15 Jul 2019 20:36:31 +0000 (13:36 -0700)]
gallium: Use consistent approach for config format filtering
rgb10 uses an 'if(allowed) continue' approach, do the same for rgba_ordering.
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Kevin Strasser [Fri, 12 Jul 2019 20:25:14 +0000 (13:25 -0700)]
i965: Add helper function for allowed config formats
The driver checks dri config options and loader caps to filter out certain
formats during config creation. Fold 4 call sites under a single helper
function.
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Kevin Strasser [Fri, 4 Jan 2019 20:12:48 +0000 (12:12 -0800)]
drm-uapi: Update headers for fp16 formats
From drm-next commit
88ab9c76d191ad8645b483f31e2b394b0f3e280e
Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Andres Rodriguez [Wed, 14 Aug 2019 01:49:52 +0000 (21:49 -0400)]
radv: add RADV_DEBUG=allentrypoints
This debug option allows vkGet[Instance/Device]ProcAddr() to succeed
even if the extension associated with the requested entrypoint was not
enabled.
This has come in handy in a few instances when debugging VR
applications, so I thought it would be good to have a cleaned up version
upstreamed.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Alyssa Rosenzweig [Fri, 16 Aug 2019 17:26:03 +0000 (10:26 -0700)]
panfrost: Fix PIPE_BUFFER spacing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 16 Aug 2019 17:25:34 +0000 (10:25 -0700)]
panfrost: Implement depth range clipping
This should fix glDepthRangef issues. Eventually, something similar
should allow implementing the depth bounds test.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 16 Aug 2019 17:25:05 +0000 (10:25 -0700)]
panfrost: Don't bail on PIPE_BUFFER
We can handle some of it.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 19 Aug 2019 15:10:28 +0000 (08:10 -0700)]
pan/midgard: Identify and disassemble indirect texture/sampler
A pair of special flags can turn the texture/sampler handle fields into
register selects. This means code like:
texture(uTextures[hr28.w], ...)
can be compiled to something like:
texture ..., fsampler[hr28.w], texture[hr28.w]
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 19 Aug 2019 15:09:57 +0000 (08:09 -0700)]
pan/midgard: Breakout texture reg select printer
This data structure is shared in other parts of the texture word, so
let's streamline printing.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:41:24 +0000 (09:41 -0700)]
panfrost: Pass stream_output_info by reference
It's a large structure, apparently.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:40:11 +0000 (09:40 -0700)]
panfrost: Guard against NULL rasterizer explicitly
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:39:04 +0000 (09:39 -0700)]
pan/bifrost: Correct file size signedness
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:37:49 +0000 (09:37 -0700)]
panfrost: Fix missing ret assignment in DRM code
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:33:39 +0000 (09:33 -0700)]
panfrost: Hoist bo != NULL check before dereference
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:32:55 +0000 (09:32 -0700)]
panfrost: Hoist job != NULL check
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:30:12 +0000 (09:30 -0700)]
panfrost: Prevent potential integer overflow in instancing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:22:17 +0000 (09:22 -0700)]
panfrost: Clarify intention with PIPE_SWIZZLE_X check
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:21:19 +0000 (09:21 -0700)]
panfrost: Pay attention to framebuffer dimension sign
These are unsigned so the clamp-positive is redundant.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:20:17 +0000 (09:20 -0700)]
pan/midgard: Mark fallthrough explicitly
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:18:55 +0000 (09:18 -0700)]
panfrost: Don't check reads_point_coord
Useless check.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:18:12 +0000 (09:18 -0700)]
pan/midgard: Simplify contradictory check.
Coverity.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:17:03 +0000 (09:17 -0700)]
pan/midgard: Reorder bits check to fix 8-bit masks
Coverity.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:15:56 +0000 (09:15 -0700)]
pan/midgard: Represent unused nodes by ~0
This allows nodes to be unsigned and prevents a class of weird
signedness bugs identified by Coverity.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 16:02:40 +0000 (09:02 -0700)]
pan/bifrost: Avoid buffer overflow in disassembler
This path shouldn't be possible for in-spec shaders, but let's be
defensive. (Because security, right? Mostly because Coverity.)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 15:59:57 +0000 (08:59 -0700)]
pan/decode: Remove all_zero
The checks confuse Coverity, so let's make it explicit what's going on.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 15:55:05 +0000 (08:55 -0700)]
pan/decode: Don't leak FBD pointer
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 15:53:49 +0000 (08:53 -0700)]
pan/midgard: Allocate `dependencies` on stack
It's small; this way we don't leak memory.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 21 Aug 2019 15:50:09 +0000 (08:50 -0700)]
pan/midgard: Free liveness info
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Jason Ekstrand [Wed, 21 Aug 2019 16:47:55 +0000 (11:47 -0500)]
v3d: Use the correct opcodes for signed image min/max
Reviewed-by: Eric Anholt <eric@anholt.net>
Jason Ekstrand [Wed, 21 Aug 2019 04:10:50 +0000 (23:10 -0500)]
intel/nir: Add a helper for getting BRW_AOP from an intrinsic
So many duplicated switch statements....
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Wed, 21 Aug 2019 03:32:50 +0000 (22:32 -0500)]
nir: Add explicit signs to image min/max intrinsics
This better matches all the other atomic intrinsics such as those for
SSBOs and shared variables where the sign is part of the intrinsic
opcode. Both generators (GLSL and SPIR-V) know the sign from the type
of the image variable or handle. In SPIR-V, signed min/max are separate
opcodes from unsigned.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Alyssa Rosenzweig [Wed, 21 Aug 2019 15:05:02 +0000 (08:05 -0700)]
pan/decode: Cleanup mali_attr printing
We can smush this into one-line per record as per usual. We still need
more validation and cleaning this up, especially around instancing. But
for LINEAR records, it works okay already.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 20 Aug 2019 23:02:38 +0000 (16:02 -0700)]
pan/decode: Validate attribute/varying buffer pointer
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 20 Aug 2019 22:59:03 +0000 (15:59 -0700)]
pan/decode: Include address in union mali_attr
No need to break it out into extra lines.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 20 Aug 2019 22:46:39 +0000 (15:46 -0700)]
pan/decode: Use concise texture printing
This consolidates texture format and dimensionality into something simple:
tiled rgba8_unorm.rgb1: 512x512
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 20 Aug 2019 22:36:00 +0000 (15:36 -0700)]
panfrost: Break up usage2 field
This is another bit field describing layout.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 20 Aug 2019 22:24:45 +0000 (15:24 -0700)]
pan/decode: Pretty-print sRGB format
We can just stick an "s" in if it's sRGB.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 20 Aug 2019 22:24:38 +0000 (15:24 -0700)]
panfrost: Remove ancient TODO
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 20 Aug 2019 22:24:18 +0000 (15:24 -0700)]
panfrost: nr_mipmap_levels -> levels
No need to be so verbose.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>