git-blame-ignore-revs: add radv formatting commit

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24583>

git-blame-ignore-revs: repeat instruction on how to enable to avoid having to look for it

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24583>

zink: apply ZINK_DEBUG=noopt to linked separate shaders

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24581>

zink: generated tcs is on the tes, not the vs

not sure how I screwed this up

Fixes: 4c47d830516 ("zink: use EXT_shader_object to implement generic separate shader precompile")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24581>

docs/radv: mark VK_INTEL_shader_integer_functions2 as implemented

Fixes: aa9d2d88935eda7612aa ("radv: Enable VK_INTEL_shader_integer_functions2.")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24582>

docs/radv: mark VK_EXT_tooling_info as implemented

Fixes: 10d1073aa62203d86c1b ("radv: advertise VK_EXT_tooling_info")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24582>

ci: document max image tag length

I've known about this for years and yet I still accidentally wrote a too
long tag.

Document this for myself next time, and for everyone else.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24560>

ci/zink: Add flake seen in the wild

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24577>

ac/nir: handle more special cases in ac_nir_unpack_arg

Foz-DB Navi21:
Totals from 60972 (45.96% of 132657) affected shaders:
CodeSize: 158371336 -> 158127376 (-0.15%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24534>

virgl/video: Enable AV1 decoding

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23386>

virgl/video: Add support for AV1 decoding

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23386>

virgl/video: Add definition of virgl_av1_picture_desc

The virgl_av1_picture_desc references to pipe_av1_picture_desc.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23386>

frontends/va: Add slice_count to AV1 slice_parameter

Save the number of slice in AV1 slice parameter, so that the
underlying driver (such as virgl) can handle the slice parameters
better.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Suggested-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23386>

anv: implement VK_EXT_pipeline_robustness

v2:
 - Use vk_pipeline_robustness_state

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>

anv/hasvk: track robustness per pipeline stage

And split them into UBO and SSBO

v2 (Lionel):
 - Get rid of robustness fields in anv_shader_bin
v3 (Lionel):
 - Do not pass unused parameters around

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>

hasvk: remove descriptor array bounds checking

Same reason as Anv.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>

anv: remove descriptor array bounds checking

We cannot find anything in the Vulkan spec requiring this. D3D12 [1]
says it's undefined as long as it doesn't crash the OS :

   "Out of bounds indexing of any descriptor table from the shader
    results in a largely undefined memory access, including the
    possibility of reading arbitrary in-process memory as if it is a
    hardware state descriptor and living with the consequence of what
    the hardware does with that. This could produce a device reset, but
    will not crash Windows."

[1] : https://learn.microsoft.com/en-us/windows/win32/direct3d12/advanced-use-of-descriptor-tables#out-of-bounds-indexing

Found 2 titles affected by this change

Some pretty good results on Cyberpunk 2077 :

  Totals from 10285 (100.00% of 10285) affected shaders:
  Instrs: 7638709 -> 7517360 (-1.59%); split: -1.64%, +0.05%
  Cycles: 148047414 -> 148470916 (+0.29%); split: -0.83%, +1.12%
  Subgroup size: 112544 -> 112576 (+0.03%); split: +0.04%, -0.01%
  Spill count: 98 -> 90 (-8.16%)
  Fill count: 90 -> 82 (-8.89%)
  Max live registers: 495274 -> 479502 (-3.18%); split: -3.21%, +0.03%
  Max dispatch width: 87824 -> 91168 (+3.81%); split: +4.10%, -0.29%

  Gaining 297 shaders in SIMD16/32, loosing 16 SIMD32 shaders

Some not so good results on Strange Brigade :

  Totals from 4027 (100.00% of 4027) affected shaders:
  Instrs: 2080355 -> 2013880 (-3.20%); split: -3.20%, +0.01%
  Cycles: 25405149 -> 25170579 (-0.92%); split: -1.37%, +0.45%
  Max live registers: 167303 -> 168958 (+0.99%)
  Max dispatch width: 33264 -> 32496 (-2.31%)

  Loosing 96 SIMD16 shaders.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>

hasvk: fix null descriptor handling with A64 messages

This replicates the same fix we did for Anv and null descriptors with
A64 messages from commit efcda1c530 ("anv: fix null descriptor
handling with A64 messages").

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>

svga: use alignas over struct MKSGuestStatInfoEntry

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24571>

v3dv: Use alignas(8) over 64 bit atomic value

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24571>

util/treewide: Use alignas(x) instead __attribute__((aligned(x)))

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24571>

nvk: EXT_conditional_rendering

This reads the buffer value, combines it with the inverted setting
and sets SET_RENDER_ENABLE depending on this.

This works for draw and clear calls, but not for dispatch.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24520>

nvk: add cond render upload buffer.

conditional render has some issues with vram, so we have to use
a gart buffer to put the value into. This is similiar to what
nvidia seem to do.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24520>

nvk: add gart forced cmd pool side buffer.

Currently we put the upload and cmd bos into GART, however in the
future this might change, but for conditional rendering we must have
 a GART space to read the value from. This creates a separate buffer
allocations that are gart forced. This will be used to provide
cond render with a gart location.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24520>

glsl: mark structs containing images as bindless

Structs are not allowed to contain an image in regular glsl. The only time
they are intended to be allowed to be declared in a struct is when
they are bindless.

Unfortunately the bindless spec does not meantion this behaviour
explicitly so there is no spec quote to reference but you can see in
the original commit to allow them in mesa that spec clarification was
provided 48b7882200c5

The spec also states that certain uses are implicitly bindless as per
the following spec quote:

   "When used as shader inputs, outputs, uniform block members,
   or temporaries, the value of the sampler is a 64-bit unsigned
   integer handle and never refers to a texture image unit."

Given images are not allowed in regular glsl for the above types
similair to being forbidden in structs, we can also assume
declarations in structs are implicitly bindless.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24269>

aux/trace: fix winsys handle dumping

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24493>

zink: add VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT

now that there's more locking around pipeline caches this makes sense

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24559>

zink: add more locking for pipeline cache

this ensures the size remains constant for entry updates

fixes #9494

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24559>

zink: use SPV_KHR_workgroup_memory_explicit_layout when available

aliasing shared memory is otherwise questionably legal

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24467>

zink: propagate have_workgroup_memory_explicit_layout to ntv

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24467>

zink: hook up VK_KHR_workgroup_memory_explicit_layout

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24467>

nvk: Enable dynamic line rasterization mode state

Enables extendedDynamicState3LineRasterizationMode feature.
Just moved the state flipping from the pipeline to the dynamic rs state
flush.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24517>

nvk: Support VK_EXT_line_rasterization

- bresenham and smooth lines

These two need to override multisample rasterization to get correct
results on CTS tests.

- stippled lines

The stipple factor needs to be remapped from [1, 256] to [0, 255].

-rectangular and strict lines

Rectangular lines need multisample rasterization rules to get correctly
rasterized even for one sample. That way we get strict lines too for
VK_LINE_RASTERIZATION_MODE_DEFAULT_EXT.

As per the DX rasterization rules:

Rasterization rules for primitives are, in general, unchanged by multisample antialiasing, except:
- For a triangle, a coverage test is performed for each sample location (not for a pixel center).
  If more than one sample location is covered, a pixel shader runs once with attributes interpolated at the pixel center.
  The result is stored (replicated) for each covered sample location in the pixel that passes the depth/stencil test.
- A line is treated as a rectangle made up of two triangles, with a line width of 1.4.
- For a point, a coverage test is performed for each sample location (not for a pixel center).

For single sample rasterization we get the same results for the
triangles and points, but for lines we get the rectangular form instead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24517>

zink: set msrtss depth resolve mode when enabled

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24309>

zink: don't append msrtss to dynamic render if not supported

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24309>

zink: don't add VK_IMAGE_USAGE_ATTACHMENT_FEEDBACK_LOOP_BIT_EXT for transient images

this is illegal

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24309>

zink: fix zs resolve attachment indexing

this has never been tested until now

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24309>

zink: add batch refs for transient images

ensure these don't get deleted while in use

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24309>

radv/winsys: Remove unused struct radv_winsys_bo_list.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24551>

radv/amdgpu: Remove unused bo_list variable from cs_submit.

Handle based bo_list is no longer used since 767a9324b9c ("radv/amdgpu:
remove legacy code path for creating the BO list").

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24551>

freedreno/a5xx: Skip SSBO emit when none are enabled.

There was a weird NUM_UNIT=0 in a crash dump I was looking at, but this
doesn't fix the crash.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

freedreno: Fix crashdec pre-a6xx.

We'd assert fail looking up the REM registers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

ci/freedreno: Add a regression test for decoding a540 blob's compute shaders.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

freedreno/cffdec: Fix decode on pixel 2 blob's COMPUTE_CHECKPOINT

dEQP-GLES31.functional.image_load_store.buffer.image_size.writeonly_7
produces:

t7 opcode: CP_COMPUTE_CHECKPOINT (6e) (8 dwords)
{ ADDR_0_LO = 0x15000 }
{ ADDR_0_HI = 0x5 }
0x18
{ ADDR_1_LEN = 3 }
0xf
{ ADDR_1_LO = 0x2e010 }
{ ADDR_1_HI = 0x5 }

and it was asserting due to sizedwords==7.  Without the assert, we were
dereffing a len past the end of the packet.  This len value we were
loading is also suspiciously not the location of the ADDR_1_LEN field in
the packet's XML.  But then, the command stream at ADDR_1 was clearly 0xf
long, and that puts ADDR_1_LEN at the spot we would expect compared to
SET_RENDER_MODE's ADDR_1.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

freedreno/a5xx: Add private mem support.

A bunch of our piglit fails were due to failing to compile shaders due to
a lack of spilling support.  I used a simple shader with a large local
array with tunable size to determine the MEMSIZEPERITEM increment and the
location of HWSTACKOFFSET (matching a3xx locations).  Unfortunately
fibers_per_sp I had to guess by taking a big spilling shader and cranking
it up until it rendered correctly.  The value I found made HWSTACKOFFSET's
shift value match a6xx's, as a bit of confirmation.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

freedreno/a5xx: Set num_sp_cores and set PC/VFD_POWER_CNTL accordingly.

Based on libwrap tracing of the blob.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

freedreno/a5xx: Refactor SHADER_OBJ emit to a helper function.

This will grow private mem setup shortly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

freedreno/a3xx: Add the shift for MEMSIZEPERITEM according to db410c docs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

freedreno/a6xx: Move pvtmem allocation to ir3_gallium.

This will be the same thing for pre-a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

freedreno/devices: Set num_sp_cores explicitly for pre-gen6.

These are all 0 currently, but will change for a5xx shortly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

freedreno/devices: Move fibers_per_sp to the common info struct.

We'll need it for pvt mem on other GPUs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

ci/freedreno: Add some more db820c xfails.

We do a fractional run so we didn't have them listed.  Adding these helps
me with local baseline testing, and future people doing uprevs or
rebalancing.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

ci/freedreno: Update comments for some a530 xfails.

That assert doesn't exist any more but the test still fails.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

ci/freedreno: Sort another a530 xfail with its friends.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

ci/freedreno: Drop a bunch of stale a530 xfails.

These all pass fairly reliably on my a530 when run on their own.  We've
not noticed this because a530 has some very loose flakes regexes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

freedreno/ir3: Move pvtmem per-fiber size alignment to the compiler.

Instead of having tu and each fd backend do it.  This will help me make
some shared code on freedreno for pre-6xx pvtmem support.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

freedreno/a5xx: Skip emitting unused texture descriptors for images.

In that case, we'd emit it to DST_OFF=255+i, angering the hardware
mightily.  This was missed in the addition of a6xx image support.

Fixes: 2e0ea3f09c79 ("freedreno/ir3: add image/ssbo <-> ibo/tex mapping")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

freedreno/a5xx: Fix border color structure size.

This now matches a6xx.  This major border color flakiness in deqp -- when
a prior test in the caselist bound a VS and it didn't get unbound at the
gallium level, our FS border colors would be up at offset 8 instead of 0,
and the wrong padding would make FS sampler 0 get a junk border color.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24358>

radv/rt: fix capture/replay support

When replaying a RT pipeline, RADEON_FLAG_REPLAYABLE should be set.

The idea is that for capture, RADEON_FLAG_REPLAYABLE should be passed
when allocating a BO (ie. replay_va would be 0), and then for replay
the VA would be non-zero but the flag is also required.

Fixes
dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.multithreaded_compilation.*.

Fixes: 744357477ef ("radv: Add utilities to serialize and deserialize shader allocation info")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24543>

docs: Add INTEL_DEBUG_BKP_BEFORE/AFTER_DRAW_COUNT

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24308>

blorp: Implement blorp hooks to emit breakpoint

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24308>

iris: Add GPU breakpoint before/after draw call

This change allow us to insert the MI_SEMAPHORE_WAIT before/after
specific draw call. With GTX tool, we can always update the memory
address to unblock spinning wait.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24308>

anv: Add GPU breakpoint before/after specific draw call

This change allow us to insert the MI_SEMAPHORE_WAIT before/after
specific draw call. With GTX tool, we can always update the memory
address to unblock spinning wait.

v2:
- Make sure draw_call_count is thread-safe (Lionel)
- Add static inline helper (Lionel)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24308>

intel: Add env variable to add break point on/before draw

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24308>

ci/panfrost: t760-gles is nightly job, test also GLES 3 and 3.1

We don't care about how long it takes since it's nightly.

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24546>

CI: Re-enable G52 Vulkan testing

This gives us coverage back on panvk on Bifrost. There are a lot of
fails since it was last tested though.

[daniels: Updated with new expectations.]

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24546>

ci/panfrost: re-enable t760 and t860 traces as a nightly job

Two crashing jobs documented in: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9473

Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24546>

ci: add perfetto into mesa git-cache

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8821

Fixes: 8aff2281276c ("ci: Enable building the testing drivers with perfetto.")
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23611>

zink: fix setting VkShaderCreateInfoEXT::nextStage

nextStage has some restrictions depending on the current stage.

Fixes: cd6625c6eb9 ("zink: use EXT_shader_object to (re)implement separate shaders")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24558>

nir/print: always group variables by type when printing

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23752>

nir/print: print location names for (some) tess slots

these should be fine to print

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23752>

Gallium: Fix shared memory segment leak

Commit abe6d750e58d371624de75f4bad365c61e0196c1 caused shared memory
segments to be leaked. We need to mark shared memory segments for
deletion upon construction.

Fixes: abe6d750e5 xlib: fix glXDestroyContext in Gallium frontends
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9425
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24556>

radv: Expose VK_EXT_external_memory_acquire_unmodified.

No-op, since we generally don't do anything to revalidate images.

In general on external/foreign queues we prepare on "export" that
it might be used on more queues, but we do pretty much nothing on
"import".

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9348
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24524>

ci: build nvk

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24542>

meson: Export winsys function symbols for target va

Export winsys function symbols of target va, even if the user
links with '-Bsymbolic-functions'.

It refers target vdpau, which commit is:
8c136b53b79e90b9e8f30f891b8bef112fee375d
("fix vdpau interop when using -Bsymbolic-functions in ldflags")

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23177>

vc4/ci: update expected results

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24550>

radv: use vk_query

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24416>

radv: use common vkCmdBegin/EndQuery wrappers

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24416>

radv: use vk_sampler

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24416>

radv: use vk_buffer_view

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24416>

vulkan: add init/finish helpers for vk_buffer_view

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24416>

anv: fake non intel vendorID for Death Stranding

The assumption is the same issue that is plaguing Cyberpunk 2077 is
also at play here. That is the XeSS library is looking for the Windows
driver binary and not finding them in the Wine/Proton distribution.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24237>

radv: update cmdbuf scratch size info when shaders are bound

This will automatically update the scratch size info for shader object.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24502>

radv: update the number of scratch waves for RT prolog at bind time

The compute scratch size is computed later because the RT stack size
can be dynamic, but the number of waves shouldn't change.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24502>

radv: add a helper to get the maximum number of scratch waves per shader

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24502>

radv: use the RT prolog scratch size directly for tracing rays

It should be the same as the pipeline scratch size value.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24502>

intel/genxml: Add filter_engines() to GenXml class

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24547>

intel/genxml: Add GenXml class into intel_genxml module

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24547>

intel/genxml: Convert gen_pack_header to use ElementTree

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24547>

intel/genxml: Convert gen_bits_header to use ElementTree

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24547>

intel/genxml: Split some genxml sorting code into a intel_genxml module

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24547>

intel/genxml: Align "Texture Coordinate Mode" naming

Some older gens used '_' (underscore) while newer gens used a ' '
(space).

$ sed -i 's/Texture_Coordinate_Mode/Texture\ Coordinate\ Mode/' \
      src/intel/genxml/*.xml

The naming needs to be aligned for importing enums later on.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24547>

llvmpipe: fix UAF in lp_scene_is_resource_referenced.

reworked slightly by airlied

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24414>

nvk: Fix assert

Fix defect reported by Coverity Scan.

Assign instead of compare (PW.ASSIGN_WHERE_COMPARE_MEANT)
assign_where_compare_meant: use of "=" where "==" may have been intended

Fixes: e41031d8ffd ("nvk: Enable multiplane images and image views")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24530>

nouveau/mme: fix OOB inside tu104 simulator

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24544>

nouveau/mme: fix OOB access inside while_ine builder test

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24544>

anv: Override vendorID for Hogwarts Legacy

This is another game that makes use of XeSS but works when we fake
the vendorID.

With this temporary hack it works on i915 and Xe KMDs.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24506>

glsl: fix spirv sso validation

The api validation calls will segfault without this as it will
try to fallback to string matching names which are NULL. This
would be incorrect behaviour even if the names weren't NULL so
here we correctly set the explicit location flag.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9483
Fixes: ffdb44d3a0a2 ("nir/linker: Add inputs/outputs to the program resource list")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24529>

zink: turn off threaded cpu access if not visible.

This turns off the threaded cpu access it the resource isn't visible.

Fixes a bunch of crashes with current nvk.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24548>

nvk: Remove plane sources from tex instructions

The plane source is entirely handled by lower_tex() so there's no need
to keep it around.  Codegen currently just ignores these but NAK will
assert if it sees an unknown source type.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24549>