nir/loop_analyze: skip unsupported induction variable early

Instead of fail in trip count calculation, just don't mark such
kind of variable as induction from the beginning.

Don't bother inline uniform to deal with such kind of variable
either.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11950>

nir/loop_analyze: record induction variables for each loop

For being used by uniform inline lowering pass.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11950>

nir/loop_analyze: move nir_is_supported_terminator_condition() to header

To be shared with uniform inline.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11950>

nir/inline_uniforms: support vector uniform

Collect per vector component dependency and lower vector uniform
load to scalar if any component need to be inlined.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11950>

nir/inline_uniforms: add uniforms in condition atomically

Unless all uniforms in the condition can be inlined we can
lower the if/loop. So we rollback added uniforms when one
of uniforms in a if condition fail to be added.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11950>

mesa: don't return errors for gl_* GetFragData* queries

There is nothing in the spec about this. BindFragDataLocation* is
supposed to return an error, but not Get.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5221
Fixes: 59012c3133 ("mesa: Implement glGetFragDataLocation")
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12333>

panfrost: Add unit tests for non-dithered clears

Would have exposed the bug fixed in the previous commit. This is gnarly
stuff, let's not regress it.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12460>

panfrost: Handle non-dithered clear colours

In b9c095cc2c6 ("panfrost: Rewrite the clear colour packing code"),
packing of clear colours was corrected to use the tilebuffer's
fractional bits, fixing dithering of the clear colour with formats like
RGB565. Unfortunately, that commit did so unconditionally. If the
framebuffer is dithered, but dithering is disabled at the time of
the clear, we would incorrectly dither the clear.

This is a regression, as the old (broken) code passed the relevant CTS
test. What's the catch? Depending on dither state, there are two
formulas to pack tilebuffer colours. We need to handle both. Fixes
KHR-GLES31.core.draw_buffers_indexed.color_masks.

Fixes: b9c095cc2c6 ("panfrost: Rewrite the clear colour packing code")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12460>

panfrost: Add dither state to the clear colour tests

There is a dependence on dithering state about which I was previously
unaware. All these test cases were with dithering enabled, so mark that
down.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12460>

broadcom/qpu: use and expand version info at opcode description

Right now opcode_desc struct, used to define data for all the
operations to pack/unpack, include a version field. In theory that
could be used to check if we are retrieving a opcode valid for our hw
version, or to get the correct opcode if a given one changed across hw
versions, or just the same if it didn't change.

In practice that field was not used. So for example, if by mistake we
asked for an opcode defined at version 41, while being on version 33
hardware, we would still get that opcode description.

This commit fixes that, and as we are here we expand the functionality
to allow to define version ranges, just in case a given opcode number
and their description is only valid for a given range.

v2 (from Iago feedback):
   * Fixed some comment typos
   * Simplified filtering opcode method
   * Rename filtering opcode method

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12301>

broadcom/qpu: add new lookup opcode description helper

Right now there is a helper to get the opcode description from a
packed instruction, used on unpack related instructions. This commit
adds a helper that refactors the equivalent that is already in use on
pack related instructions.

Right now the helper is small, but we plan to extend it on following
commits in order to use the opcode description version field.

To avoid any possible confusion we rename the existing lookup helper.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12301>

broadcom/qpu: update/remove comments

   * Remove one about waddr 6 being reserved, when at some point it
     become NOP

   * Fix one comment about reserved signals on v41 map, as 24 and 25
     are in fact defined. This seems a C&P issue (see v40 map).

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12301>

ci/freedreno: Flake the rest of the pbuffer/window dEQP-EGL tests.

I had at least 3 of these in my logs, I see no reason not to fill out the
rest at this point.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12458>

ci/freedreno: Mark a new flaky SSBO length test.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12458>

intel/compiler: Lower 8-bit ops to 16-bit in NIR on all platforms

This fixes the Crucible func.shader.shift.int8_t test on Gen8 and Gen9.
See https://gitlab.freedesktop.org/mesa/crucible/-/merge_requests/76.

With the previous optimizations in place, this change seems to improve
the quality of the generated code.  Comparing a couple Vulkan CTS tests
on Skylake had the following results.

dEQP-VK.spirv_assembly.type.vec3.i8.bitwise_xor_frag:
SIMD8 shader: 36 instructions. 1 loops. 3822 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 27 instructions. 1 loops. 2742 cycles. 0:0 spills:fills, 5 sends

dEQP-VK.spirv_assembly.type.vec3.i8.max_frag:
SIMD8 shader: 39 instructions. 1 loops. 3922 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 37 instructions. 1 loops. 3682 cycles. 0:0 spills:fills, 5 sends

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>

nir: intel/compiler: Add and use nir_op_pack_32_4x8_split

A lot of CTS tests write a u8vec4 or an i8vec4 to an SSBO.  This results
in a lot of shifts and MOVs.  When that pattern can be recognized, the
individual 8-bit components can be packed much more efficiently.

v2: Rebase on b4369de27fc ("nir/lower_packing: use
shader_instructions_pass")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>

nir/algebraic: Remove spurious conversions from inside logic ops

Not only does this eliminate a bunch of unnecessary type converting
MOVs, but it can also enable some SWAR.  The
dEQP-VK.spirv_assembly.type.vec3.i8.bitwise_xor_frag test does
something about like:

    c = a.x ^ b.x;
    d = a.y ^ b.y;
    e = a.z ^ b.z;

After this change, it looks more like:

    uint t = i8vec3AsUint(a) ^ i8vec3AsUint(b);
    c = extract_u8(t, 0);
    d = extract_u8(t, 1);
    e = extract_u8(t, 2);

On Ice Lake, this results in:

SIMD8 shader: 41 instructions. 1 loops. 3804 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 31 instructions. 1 loops. 2844 cycles. 0:0 spills:fills, 5 sends

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>

intel/fs: Emit better code for u2u of extract

Emitting the instructions one by one results in two MOV instructions
that won't be propagated.  By handling both instructions at once, a
single MOV is emitted.  For example, on Ice Lake this helps
dEQP-VK.spirv_assembly.type.vec3.i8.bitwise_xor_frag:

SIMD8 shader: 49 instructions. 1 loops. 4044 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 41 instructions. 1 loops. 3804 cycles. 0:0 spills:fills, 5 sends

Without "intel/fs: Allow copy propagation between MOVs of mixed sizes,"
the improvement is still 8 instructions, but there are more instructions
to begin with:

SIMD8 shader: 52 instructions. 1 loops. 4164 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 44 instructions. 1 loops. 3944 cycles. 0:0 spills:fills, 5 sends

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>

intel/fs: Allow copy propagation between MOVs of mixed sizes

This eliminates some spurious, size-converting moves.  For example, on
Ice Lake this helps dEQP-VK.spirv_assembly.type.vec3.i8.bitwise_xor_frag:

SIMD8 shader: 52 instructions. 1 loops. 4164 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 49 instructions. 1 loops. 4044 cycles. 0:0 spills:fills, 5 sends

Unfortunately, this doesn't clean everything up.  Here's a subset of the
"before" assembly:

send(8)         g11<1>UW        g2<0,1,0>UD     0x02106e02
                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
mov(8)          g7<4>UB         g11<8,8,1>UD                    { align1 1Q };
mov(8)          g12<1>UB        g7<32,8,4>UB                    { align1 1Q };
send(8)         g13<1>UW        g2<0,1,0>UD     0x02106e03
                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
mov(8)          g15<1>UW        g12<8,8,1>UB                    { align1 1Q };
mov(8)          g8<4>UB         g13<8,8,1>UD                    { align1 1Q };
mov(8)          g14<1>UB        g8<32,8,4>UB                    { align1 1Q };
mov(8)          g16<1>UW        g14<8,8,1>UB                    { align1 1Q };
xor(8)          g17<1>UW        g15<8,8,1>UW    g16<8,8,1>UW    { align1 1Q };

And here's the same subset of the "after" assembly:

send(8)         g11<1>UW        g2<0,1,0>UD     0x02106e02
                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
mov(8)          g7<4>UB         g11<8,8,1>UD                    { align1 1Q };
send(8)         g13<1>UW        g2<0,1,0>UD     0x02106e03
                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
mov(8)          g15<1>UW        g7<32,8,4>UB                    { align1 1Q };
mov(8)          g8<4>UB         g13<8,8,1>UD                    { align1 1Q };
mov(8)          g16<1>UW        g8<32,8,4>UB                    { align1 1Q };
xor(8)          g17<1>UW        g15<8,8,1>UW    g16<8,8,1>UW    { align1 1Q };

There are a lot of regioning and type restrictions in
fs_visitor::try_copy_propagate, and I'm a little nervious about messing
with them too much.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>

nir/algebraic: Optimize some extract forms resulting from 8-bit lowering

This eliminates some spurious, size-converting moves.  For example, on
Ice Lake this helps dEQP-VK.spirv_assembly.type.vec3.i8.bitwise_xor_frag:

SIMD8 shader: 56 instructions. 1 loops. 4444 cycles. 0:0 spills:fills, 5 sends
SIMD8 shader: 52 instructions. 1 loops. 4164 cycles. 0:0 spills:fills, 5 sends

v2: Condition two of the patterns on !options->lower_extract_byte.
Suggested by Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>

intel/compiler: Document and assert some aspects of 8-bit integer lowering

In the vec4 compiler, 8-bit types should never exist.

In the scalar compiler, 8-bit types should only ever be able to exist on
Gfx ver 8 and 9.

Some instructions are handled in non-obvious ways.

Hopefully this will save the next person some time.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9025>

glx: Simplify context API profile computation

GLX_ARB_create_context_profile has some clever language that sets the
default to core profile but silently degrades back to compat for pre-3.2
GLs. We can just do that, rather than track whether the user specified a
profile.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>

glx/dri: Collect the GLX context attributes in a struct

dri2_convert_glx_attribs had way too many arguments, let's fix that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>

glx/drisw: Remove some misplaced error checks

If the driver doesn't like these attributes it can reject them, it's not
libGL's job to verify them here.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>

glx/dri2: Require the driver to support v4 of __DRI_DRI2

Mesa has supported this unconditionally since 10.1.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>

glx: Store the context vtable on the glx screen

Again this is rewriting part of driX_create_context_attribs to be
caller-agnostic, so that we can eventually unify it among the DRI
backends.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>

glx: Fix and simplify the share context compatibility check

We only end up with one DRI provider per screen, so the only way the
context vtable can differ is if they're not the same directness. Rewrite
the test in those terms to help us unify some of this code away in the
future. Also apply the same logic to the indirect context creation path.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>

dri: Reformat DRI context attribute #defines

These were confusingly sorted before.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12456>

zink: clear current gfx/compute program upon unbinding its shaders

this simplifies a lot of code

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12428>

zink: do compute shader change on bind

we can do this update earlier to optimize the actual compute path

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12428>

zink: flag the gfx pipeline dirty and unset pipeline shader module on shader change

there's no need to leave this until the module updating when the info
is known much earlier

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12428>

zink: remove repeated lazy batch dd casts

these all have an ergonomic cost

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12427>

zink: remove redundant asserts from lazy descriptor set populate

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12427>

zink: simplify get_descriptor_set_lazy params

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12427>

radeon/vcn: check frame size change for vp9 header flags

Beside show_frame and error_resilient_mode, also need to check if frame size
changes. FRAME_HDR_INFO_VP9_USE_PREV_IN_FIND_MV_REFS flag should be OFF if
frame size changes.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12368>

radeon/vcn: track width and height of the last frame

Adding last width/height to keep tracking the size of the last frame.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12368>

radeon/vcn: initilize num_temporal_layers for hevc

Fixes: 51935d59

num_temporal_layers has not been initialized for hevc, which will cause hevc
encode failure.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12434>

intel/pci-ids: Re-enable DG1 and add SG1

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11584>

anv: Fix VK_EXT_memory_budget to consider VRAM if available

Instead of calling the OS query, re-run anv_update_meminfo to get the
latest from either the kernel memory info API or the OS as appropriate.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5173
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12433>

anv: compute available memory in anv_init_meminfo

We can now detect EXT_memory_budget support based on whether or not we
have non-zero available system memory.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12433>

anv: Rework init_meminfo

Instead of making LMEM the special case, unify the two paths by setting
up a fake drm_i915_query_memory_regions struct and filling it out based
on OS queries.  The important functional change here is that we now pass
system memory through the same GTT size and 3/4 filter that we were
using with the OS queries.  This should make behavior consistent on
integrated GPUs regardless of whether or not we have the memory region
query API.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12433>

anv: Move compute_heap_size lower in the file

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12433>

softpipe: fix ci rule ordering to avoid unnecessarily running jobs

fixes #5242

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12445>

anv: warn if system memory is used

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12318>

anv: Allocate workaround buffer in local memory if present

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12318>

anv: Use local memory for block pool BO

Allocating block pool BO into local memory means indirectly it allows us to
push our aux map table into local memory too.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12318>

nir/lower_vectorize_tess_levels: set num_components for vectorized loads

this otherwise explodes when rewriting e.g., a single array component load to a vec4

Fixes: f5adf27fb92 ("nir,radv: add and use nir_vectorize_tess_levels()")

fixes zmike/mesa#94

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12419>

gallivm: fix texture-mapping with 16-bit result

16bit integer support also implies using 16-bit results when sampling
textures.

Because we're returning the results in float SSA values instead of int,
we need to bitcast back to integers before truncating the values.

Fixes: 00ff60f799c ("gallivm: add 16-bit integer support")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12413>

iris: declare padding for iris_vue_prog_key

Otherwise with some compilers/environments (Android) padding
may contain garbage and memcmp of the key will fail.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12438>

radv: fix fast clearing depth images with mips on GFX10+

Found by inspection.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12325>

freedreno/a5xx: Reduce packet emits for SSBO state.

This is what I see happening in
dEQP-VK.spirv_assembly.instruction.compute.opatomic_storage_buffer.load on
pixel 2 (also where I found a buffer big enough to show how to encode the
size).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258>

freedreno/a5xx: Use ST4_ constants for SSBO/image state types.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258>

freedreno/a6xx: Skip setting up image dims constants.

We just use resinfo anyway.  Notably, a6xx was only doing its setup in the
FS case and not CS.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258>

freedreno/ir3: Move a6xx's get_ssbo_size shl to NIR.

Just cleaning up a TODO.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258>

freedreno/ir3: Use the resinfo path for ssbo sizes on GL, too.

Less state walking at draw time, in exchange for a SHL in the lookup.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258>

freedreno/ir3: Only lower cube image sizes once.

shader variants can cause ir3_nir_finalize() to run more than once, which
would make us keep dividing the size by 6.

Fixes: a48fc88571f9 ("freedreno/a6xx: Apply the cube image size lowering to GL, too.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12258>

freedreno: Add a680 support

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12041>

meson: Check that bin/meson_get_version.py ran without an error

According to https://mesonbuild.com/Reference-manual.html, the check
parameter is supported since meson 0.47.0.

This could have helped to catch the issue fixed by:

221871fb6da ("meson: Search for python3 before python for bin/meson_get_version.py")

as it would have caused the build to fail immediately.

It's still a good idea to check the result even though that issue is
now fixed.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12404>

panfrost: drm-shim support

Reviewed-and-tested-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12431>

zink: ci updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12423>

zink: enable compat contexts

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12423>

anv,vulkan: Add a vk_image::wsi_legacy_scanout bit

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

anv,vulkan: Move drm_format_mod to vk_image

Even though we can't really do the parsing on behalf of the driver (it's
too complicated), storing it in the vk_image lets us provide a common
implementation of vkGetImageDrmFormatModifierPropertiesEXT().  It'll
also be useful in the next few commits for swapchain images.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

anv,vulkan: Move ANV image layout helpers to common code

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

anv: Make anv_image_view derive from vk_image_view

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

vulkan: Add a vk_image_view struct

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

vulkan,radv: Move vk_format_depth/stencil_only to common code

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

radv: Add asserts to vk_format_depth/stencil_only

It doesn't make sense to ask for the depth-only or stencil-only format
if there is no depth or stencil.  One bit of radv_image.c did seem to
take advantage of the default case in vk_format_depth_only so throw an
`if (vk_format_has_depth(format))` around it.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

radv: Check format before calling depth_only/stencil_only.

Breaks when we drop the fallback in those functions.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

vulkan: Refactor and better document vk_image_expand_aspect_mask

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

anv,vulkan: Move VkImageSubresource* helpers from ANV

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

anv,vulkan: Move anv_image_expand_aspects to common code

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

anv: Make anv_image derive from vk_image

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

vulkan: Add a vk_image struct

Currently, this is optional for drivers to carry around but it scrapes
up most of VkImageCreateInfo for you and parses a couple of extension
structs.  We also add a few useful little helpers copied over from ANV.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

anv: Delete anv_image::format

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

anv/image: Use planes[i]->primary_surface.isl.format in check_drm_format_mod

In theory, with linear vs. tiled differences, it could be different
(RGBA vs. RGB etc.) but it won't matter for the two checks we do with
it.  Also, we probably want to be checking the real format here anyway.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>

zink: handle map failures more effectively

the transfer object needs to be destroyed

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12422>

zink: break out transfer map destroy

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12422>

zink: remove unused variable from image map

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12422>

zink: split buffer and image map functions

this is a bit nicer to read

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12422>

zink: split out zink_transfer allocation

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12422>

zink: remove duplicated zink_resource_object::mem member

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12421>

zink: collapse 'dedicated' allocation into zink_bo

this simplifies all the map and memory management code

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12421>

zink: flake out some tests for now

I can't repro these on any branch, so I'll just disable them and see if they get fixed
by some upcoming refactors

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12424>

freedreno/a6xx: Apply the cube image size lowering to GL, too.

Fixes KHR-GLES31.core.texture_cube_map_array.texture_size_compute_sh.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12256>

ci/freedreno: Move freedreno's deqp testing to suite support.

Using suites makes load-balancing our jobs much easier, keeps the CPU busy
handling the a630_gles_others.sh test sets (and improves the output and
baseline handling for them), and makes it trivial to add in more short
test sets.

a306: still 5 jobs, and we add KHR-GLES2 (KHR-GLES3 is unstable)
a530: still 5 jobs, added KHR-GLES*
a630_gl: 5 jobs becomes 4, and we add KHR-GLES*
a630_vk: still 3 jobs, now 1/3 of all VK instead of 1/4.
a630_vk_full: still 2 jobs, now includes full bypass testing, partial
              no-force testing, and testing of pre-merge-skipped tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12256>

ci/turnip: Add a new flake from running more of the CTS.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12256>

zink: rejigger PIPE_MAP_ONCE for internal qbo reads

DONTBLOCK is only used internally for this case, and promoting it over
the staging buffer case ensures that it's always reached when it should be

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12410>

zink: remove PIPE_MAP_ONCE from subdata

subdata calls that happen once for a buffer are likely to happen again,
so just leave them mapped

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12410>

zink: make map_count useful for dedicated image allocations

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12410>

zink: split mem unmap logic for images and buffers

buffers should only be unmapped if they're explicitly marked for unmap,
but images should only be unmapped when running in 32bit, in which case
they need to always be unmapped

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12410>

zink: split transfer_unmap for images and buffers

these should be separate

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12410>

zink: stop zeroing structs during resource allocation

some of these show up in profiling

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12410>

zink: repack zink_resource_object struct

this makes better use of cachelines and eliminates holes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12410>

turnip: provide dummy CmdSetLogicOpEXT and CmdSetPatchControlPointsEXT

Fixes: fd62e0b7996afde22447fd929a55b0cc89e9ab36 "tu: enable VK_EXT_extended_dynamic_state2"

Fixes dEQP-VK.api.version_check.entry_points

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5243

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12417>

tu: Consider depth/stencil for implicit dependencies

Noticed by inspection.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12386>

tu: Fix logic errors with subpass implicit dependencies

We were adding them if there was an external dep instead of if there
wasn't, and we were skipping the entire subpass which would've resulted
in attachments not getting marked as used.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12386>

util: Replace recursive DFS with iterative implementation

Doesn't fix, but improves the situation in issue #5163. The
VK.spirv_assembly.instruction.graphics.spirv_ids_abuse.lots_ids_* tests
emit about 160k instructions. ir3_sched blows out the stack after
dag_traverse_bottom_up_node reaches a depth of about 130k frames.

This patch replaces the recursively-implemented post-order traversal
with an iterative implementation using a stack, allowing us to process
DAGs as large as memory can hold.

Definitely makes you appreciate the elegance of recursion...

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12232>

util: Add unit tests for dag

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12232>

freedreno: Decode a650+ CP_START_BIN/CP_END_BIN packets

The blob uses them for GMEM renderpasses.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12184>