isl: remove ffs function that conflicts with system headers

Remove a wrapper around __builtin_ffs that conflicts with system
headers on OpenBSD and perhaps elsewhere:

isl_priv.h:44: error: conflicting types for 'ffs'

v2: include strings.h to ensure prototype is found

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

gallium: use unreachable instead of asserts

Avoids warnings in release builds.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

anv: fix warnings in release build

Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings
in release build.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

isl: fix warnings in release build

Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings
in release build.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

spirv: fix warning in release build

Mark variable MAYBE_UNUSED to avoid unused-but-set-variable warning in
release build.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

gallium: fix warnings in release build

Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings
in release build.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

glsl: fix warning in release build

Mark variable MAYBE_UNUSED to avoid unused-but-set-variable warning in
release build.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

util: add MAYBE_UNUSED for config dependent variables

This is mostly for variables that are only used in asserts and cause
unused-but-set-variable warnings in release builds. Could just use
UNUSED directly, but MAYBE_UNUSED should be less confusing and is
similar to what the Linux kernel has.

And yes __attribute__((unused)) can be used on variables on both GCC 4.2
(oldest supported by mesa) and clang 3.0 (just some random old version,
not sure what's the minimum for mesa).

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

nouveau: codegen: combineLd/St do not combine indirect loads

combineLd/St would combine, i.e. :

st  u32 # g[$r2+0x0] $r2
st  u32 # g[$r2+0x4] $r3

into:

st  u64 # g[$r2+0x0] $r2d

But this is only valid if r2 contains an 8 byte aligned address,
which is not guaranteed for compute shaders

This commit checks for src0 dim 0 not being indirect when combining
loads / stores as combining indirect loads / stores may break alignment
rules.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/ir3: relax restriction in grouping

Currently we were two restrictive, and would insert an output move in
cases like: MOV OUT[0], IN[0].xyzw

Loosen the restriction to allow the current instruction to appear in the
neighbor list but only at it's current possition.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: fix small memory leak

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: fix small RA bug

Normally the offset in the group would be the same, but not always.  For
example, in a sam(w) which only writes the 4th component.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: better workaround for astc+srgb

This *seems* like a hw bug, and maybe only applies to certain a4xx
variants/revisions.  But setting the SRGB bit in sampler view state
(texconst0) causes invalid alpha for ASTC textures.  Work around this
setting up a second texture state and using that to sample alpha
separately.

This way, srgb->linear conversion happens in hw *prior* to
interpolation.

This fixes 546 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb*

Signed-off-by: Rob Clark <robclark@freedesktop.org>

Revert "freedreno/a4xx: lower srgb in shader for astc textures"

Better workaround in the following patch.

This reverts commit 899bd63acefd49a668e11c42d2ad92fa55aa157d.

freedreno/a4xx: blend state no longer depends on fb state

Signed-off-by: Rob Clark <robclark@freedesktop.org>

Revert "st/dri: add 32-bit RGBX/RGBA formats"

This reverts commit ccdcf91104a5f07127b5b8d8570b5c4bbcf86647.

It breaks most KDE apps, because DRI doesn't support the RGBA component
ordering.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95071

genxml: use PYTHON3

Allows the build to work when the python3 binary is not "python3".

v2: remove x bit from the script at Emil's suggestion

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/tex_image: Flush certain subnormal ASTC channel values

When uploading a linear, void-extent, ASTC LDR block on Skylake, we are
required to flush to zero the UNORM16 channel values that would be
denormalized. This is specifically required for the values: 1, 2, and 3.

Fixes the 14 failing tests in:
   dEQP-GLES3.functional.texture.compressed.astc.void_extent_ldr.*

v2: Split out flushing function (Kristian Høgsberg)
v3: Map with READ instead of INVALIDATE (Kenneth Graunke)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

configure.ac: search for and set PYTHON3

src/intel/genxml/gen_pack_header.py requires python3.

v2: check for python3.5 as well

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp: Enable for buffer resolves

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94181

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp: Enable for normal color clears

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp: Fix clear code for ignoring colormask for XRGB formats on Gen9+

This is equivalent of 73b01e2711ff45a1f313d5372d6c8fa4fe55d4d2
for blorp.

v2 (Ken): No need to call _mesa_format_has_color_component() now
          that the number of components is gotten from
          _mesa_base_format_component_count().

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa/formats: Take luminance into account in component count

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965/blorp: Do not trigger re-emission of base state address

In case blorp needs to configure it will be just as if render or
compute pipeline had configured it.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp: Reconfigure base state address only if needed

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp: Use BRW_NEW_BLORP instead of trashing all state bits

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Make all atoms to track BRW_NEW_BLORP by default

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com

i965: Introduce state flag for blorp

In the past, BLORP has clobbered all BRW_NEW_* state flags, to trigger
re-emission of the entire 3D pipeline on the next draw.  However, there
are some packets BLORP simply leaves alone, so there's no need to
re-emit them.  Trying to reduce the set of dirty bits flagged after
BLORP runs is tricky.

Instead, we introduce a BRW_NEW_BLORP flag.  This should be set on any
atom which emits a packet that BLORP also emits.  When BLORP runs, it
will flag BRW_NEW_BLORP, causing those packets to get re-emitted.

This also makes it easy to avoid re-emitting specific atoms - we can
simply drop the BRW_NEW_BLORP flag on those.

To start, we assume that all packets need to be re-emitted.  This is the
safest approach and closest to the existing code's behavior.  Many of
these are obviously not required, and can be dropped in subsequent
patches.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp/gen6: Use normal base state address setup

This is identical to the blorp version which only differs in case
fragment shader isn't used. In that case blorp would reset batch
buffer address to zero.
This is not really needed, and having blorp to use base state
address setup that is compatible with normal upload allows one to
skip resetting it.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Remove pointers to non-existing atoms

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: Implement ddx/ddy on VI using ds_bpermute

The ds_bpermute instruction allows threads to transfer data directly
to or from the vgprs of other threads.  These instructions use the LDS
hardware to transfer data, but do not read or write LDS memory.

DDX BEFORE:                        |  DDX AFTER:
                                   |
v_mbcnt_lo_u32_b32_e64 v2, -1, 0   |  v_mbcnt_lo_u32_b32_e64 v2, -1, 0
v_mbcnt_hi_u32_b32_e64 v2, -1, v2  |  v_mbcnt_hi_u32_b32_e64 v2, -1, v2
v_lshlrev_b32_e32 v4, 2, v2        |  v_and_b32_e32 v2, 60, v2
v_and_b32_e32 v2, 60, v2           |  v_lshlrev_b32_e32 v2, 2, v2
v_lshlrev_b32_e32 v3, 2, v2        |  ds_bpermute_b32 v3, v2, v0
s_mov_b32 m0, -1                   |  ds_bpermute_b32 v0, v2, v0 offset:4
ds_write_b32 v4, v0                |  s_waitcnt lgkmcnt(0)
s_waitcnt lgkmcnt(0)               |
v_or_b32_e32 v0, 1, v2             |
v_lshlrev_b32_e32 v0, 2, v0        |
ds_read_b32 v1, v3                 |
ds_read_b32 v0, v0                 |
s_waitcnt lgkmcnt(0)               |
                                   |
LDS: 1 blocks                      |  LDS: 0 blocks

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: Use llvm.amdgcn.mbcnt.* intrinsics instead of llvm.SI.tid

We're trying to move to more of the new style intrinsics with include
the correct target name, and map directly to ISA instructions.

v2:
  - Only do this with LLVM 3.8 and newer.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: Set range metadata on calls to llvm.SI.tid

The range metadata tells LLVM the range of expected values for this intrinsic,
so it can do some additional optimizations on the result.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: Create a helper function for computing the thread id

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965: Disable KHR_texture_compression_astc_hdr on Gen9

Although Gen9 samples from most HDR ASTC surfaces of correctly,
there currently are no software workarounds to fix the incorrect
sampling that occurs in others of certain color endpoint modes.

With this change, we are no longer failing the 14 tests from:
   dEQP-GLES3.functional.texture.compressed.astc.endpoint_value_hdr_cem_15.*

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

swr: [rasterizer memory] Constify load tiles

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] CompleteDrawContext changes for gcc

Add explicit inline and non-inline versions of CompleteDrawContext
to make gcc happy.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer] Small cleanups

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer scripts] Knob scripts tweaks

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer] Interpolation utility functions

v2: use _mm_cmpunord_ps for vIsNaN

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] TemplateArgUnroller

Switch boolean template arguments to typename template arguments of type
std::integral_constant<bool, VALUE>.

This allows the template argument unroller to easily be extended to enums.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] Arena: make most allocated blocks the same size

Reduces sorting cost

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] Fix global arena allocator bug

- Plus some minor code refactoring

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] Fix thread binding for 32-bit windows

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer fetch] Add support for fetching non-uniform component formats

For example, R10G10B10A2_UNORM.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer core] Use CS spill/fill size in core

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: fix memory leaks from vs/fs compilation

v2: varient -> variant

Reviewed by: George Kyriazis <George.Kyriazis@intel.com>

swr: fix clang warnings

v2: use alternate logic version in swr_check_render_cond

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

freedreno/a4xx: fix encoding of blend color state

Fixes a whole bunch of dEQP-GLES3.functional.fragment_ops.random.* (now
they all pass)

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: update generated headers

Pull in RB_BLEND_* fixes.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

vc4: Make sure we recompile when sample_mask changes.

Part of fixing piglit EXT_framebuffer_multisample/sample-coverage inverted
(there is also a bug with RCL tiled blits)

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>

vc4: Fix validation of full res tile offset if used for non-MSAA.

There's no reason we couldn't do non-MSAA full resolution tile buffer
load/stores, but we would have claimed buffer overflow was being
attempted.  Nothing does this currently.

vc4: Only do MSAA FB operations if the FB is MSAA.

I noticed this as a problem with ET:QW traces emitting coverage code when
the framebuffer was supposed to be single sampled.

vc4: Fix tests for format supported with nr_samples == 1.

This was a bug from the MSAA enabling.  Tests for surfaces with
nr_samples==1 instead of 0 (generally GL renderbuffers) would incorrectly
fail out.

Fixes the ARB_framebuffer_sRGB piglit tests other than srgb_conformance.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>

vc4: Don't try to blit from MSAA surfaces with mismatched width to dst.

I had made the previous blit fix non-MSAA only because I was thinking
about how the hardware infers stride from the RENDERING_CONFIG packet.
However, I'm also inferring the stride for both MSAA src and dst in
vc4_render_cl.c from the width argument in the ioctl.

Fixes 15 EXT_framebuffer_multisample piglit tests.

i965: Disable channel expressions for scalar GS, TCS, TES.

On Broadwell, I get the following shader-db statistics:

Tessellation Control Shaders:

   total instructions in shared programs: 57327 -> 57012 (-0.55%)
   instructions in affected programs: 27334 -> 27019 (-1.15%)
   helped: 45
   HURT: 0

   total cycles in shared programs: 265692 -> 255188 (-3.95%)
   cycles in affected programs: 263122 -> 252618 (-3.99%)
   helped: 184
   HURT: 26

Tessellation Evaluation Shaders:

   total instructions in shared programs: 23236 -> 23157 (-0.34%)
   instructions in affected programs: 2791 -> 2712 (-2.83%)
   helped: 27
   HURT: 0

   total cycles in shared programs: 151858 -> 149704 (-1.42%)
   cycles in affected programs: 151858 -> 149704 (-1.42%)
   helped: 101
   HURT: 114

Geometry Shaders:

   Orbital Explorer goes from 6442 -> 6356 instructions.
   Two Shadow of Mordor shaders increase by a single instruction.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/blorp: Add support for 2x msaa

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/blorp: Add support for encoding/decoding interleaved 2x msaa

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: don't lower mod() in glsl ir

NIR will lower it in nir_opt_algebraic.

No change in shader-db.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: fix cross validation for explicit locations on structs and arrays

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: implement TGSI_SEMANTIC_HELPER_INVOCATION

Depends on LLVM support introduced in r267102.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

swr: ignore generated files in rasterizer

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

nvc0: fix retrieving query results into buffer for timestamps

The timestamps are stored in a funny place, and even though they are a
64-bit result, are not stored with is64bit. Account for that when
retrieving the query result into a resource.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.2" <mesa-stable@lists.freedesktop.org>

i965/surface_state: Use libisl functions for image format lowering

This lets us delete some redundant code and keep all of the
image_load_store format lowering logic in one place: libisl.

Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/fs_surface_builder: Use isl instead of mesa for format info

Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/fs_surface_builder: Add a helper for converting GL to ISL formats

Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/fs_surface_builder: Explicitly handle FORMAT_NONE in num_image_coordinates

Previously, we were relying on has_matching_typed_format returning true for
MESA_FORMAT_NONE which, in turn, relied on _mesa_get_format_bytes returning
1 for MESA_FORMAT_NONE.  When we switch to ISL, this behaviour will no
longer be something we can rely on.

Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/fs_surface_builder: Take a GL format enum instead of mesa_format

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl/format: Add a get_num_channels helper

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl/format: Add more isl_format_has_type_channel functions

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl/format: Break the guts of has_[us]int_channel into a helper

Reviewed-by: Chad Versace <chad.versace@intel.com>

anv/image: Use the has_matching_typed_storage_image_format helper from isl

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Add a helper for determining when a typed load/store can be used

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Take a devinfo in lower_storage_image_format instead of an isl_device

We want to call this function from the shader compiler and having a full
isl_device available at that point isn't practical.

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Don't use designated initializers in the header

C++ doesn't support designated initializers and g++ in particular doesn't
handle them when the struct gets complicated, i.e. has a union.

Reviewed-by: Chad Versace <chad.versace@intel.com>

isl: Include c99_compat.h

We need the restrict keyword in isl.h

Reviewed-by: Chad Versace <chad.versace@intel.com>

i965: Add a dependency on libisl

To avoid build issues, ensure that you're running `make' at the top level
and/or you've executed `make clean' beforehand.

Reviewed-by: Chad Versace <chad.versace@intel.com>

radeon: handle query buffer allocation and mapping failures

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94984
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeon: wire end_query return value to sw/hw_end

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: check return value of begin/end_query

They can only indicate out of memory conditions, since the other error
conditions are caught earlier.

v2: fix error message in EndQuery

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

gallium: add bool return to pipe_context::end_query

Even when begin_query succeeds, there can still be failures in query handling.
For example for radeon, additional buffers may have to be allocated when
queries span multiple command buffers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965: Always use Y-tiled buffers on SKL+

Starting with Skylake, the display engine is capable of scanning out from
Y-tiled buffers. As such, we can and should use Y-tiling for better efficiency.
This also has the added benefit of being able to fast clear the winsys buffer.

Note that the buffer allocation done for mipmaps will already never allocate an
X-tiled buffer for GEN9.

This has an almost universal positive impact on benchmarks, some improving by as
much as 20%.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

softpipe: fix a warning due to an incorrect enum comparison

no change in behavior, because both are defined the same

Acked-by: Jose Fonseca <jfonseca@vmware.com>

gallium: remove helpers converting to/from TGSI_PROCESSOR_*

Acked-by: Jose Fonseca <jfonseca@vmware.com>

gallium: use PIPE_SHADER_* everywhere, remove TGSI_PROCESSOR_*

Acked-by: Jose Fonseca <jfonseca@vmware.com>

gallium: merge PIPE_SWIZZLE_* and UTIL_FORMAT_SWIZZLE_*

Use PIPE_SWIZZLE_* everywhere.
Use X/Y/Z/W/0/1 instead of RED, GREEN, BLUE, ALPHA, ZERO, ONE.
The new enum is called pipe_swizzle.

Acked-by: Jose Fonseca <jfonseca@vmware.com>

gallium: use enums in p_shader_tokens.h (v2)

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> (v1)
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
Acked-by: Jose Fonseca <jfonseca@vmware.com> (v1)
v2: name enums

gallium: use enums in p_defines.h (v2)

and remove number assignments which are consecutive

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> (v1)
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
Acked-by: Jose Fonseca <jfonseca@vmware.com> (v1)
v2: name enums

radeonsi: remove the shader parameter from si_set_ring_buffer

not used anymore

this is a follow-up to the RW buffer cleanup.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radeonsi: decrease GS copy shader user SGPRs to 2

const buffers are no longer used since the clip plane const buffer was
moved to RW buffers

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: shorten slot masks to 32 bits

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: clean up shader resource limit definitions

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move default tess level constant buffer to RW buffers

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move sample positions constant buffer to RW buffers

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move clip plane constant buffer to RW buffers

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: rework polygon stippling to use constant buffer instead of texture

add it to the RW_BUFFERS descriptor array

now the slot masks don't have to have 64 bits

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: generalize si_set_constant_buffer

this will be used in the next commit

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: make RW buffer descriptor array global, not per shader stage

v2: also simplify invalidation of RW buffer bindings (squashed)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: rename and rearrange RW buffer slots

- use an enum
- use a unique slot number regardless of the shader stage
  (the per-stage slots will go away for RW buffers)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallivm: fix bogus argument order to lp_build_sample_mipmap function

Screwed up since 0753b135f6e83b171d8a1b08aea967374f3542bc.

(Only an issue with different min/mag filters, and then only in some cases,
which is probably why it went unnoticed for quite a while.
The effect should have simply been nearest mip filter instead of linear, iff
min was nearest, mag was linear, and all pixels hit the mignifying path.)

Fixes a bunch of dEQP failures.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>