zink: require maintenance5 for shobj

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25289>

zink: delete injected pointsize during shader creation

maintenance5 is best maintenance.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25289>

lavapipe/ci: Fix asan expectations

Those failures were fixed in b2f6de8f0d86b8143084212f970af072780fc201.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25309>

nir/deref: Layer rematerialization helpers

nir_rematerialize_derefs_in_use_blocks_impl can be implemented on top of
nir_rematerialize_deref_in_use_blocks.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23712>

nir/lcssa: Fix rematerializing derefs

This would pull derefs out of loops by emitting the pattern
`deref(phi(deref))` which is not allowed by nir_validate.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23712>

nir: Add nir_rematerialize_deref_in_use_blocks

nir_rematerialize_deref_in_use_blocks can be used in passes that don't
run on the whole function.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23712>

nir/deref: remove rematerialize_deref_in_block cache

Nothing was ever inserted into this.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23712>

nir: Add nir_foreach_block_in_cf_node_reverse

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23712>

nir: Add nir_cf_node_cf_tree_prev

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23712>

ci/zink+radv: bump the timeout of zink-radv-navi10-valve by 10 minutes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25342>

ci/zink+radv: specify that zink-radv-navi10-valve should run in the mupuf farm

Fixes: 8c98ee6f3addb1d1b41d ("radv/ci: move vkcts-navi10 testing to KWS")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25342>

virgl: Cover all the formats defined in the virgl definition

Add all the formats currently defined in u_formats.h

Also make sure that no format on virgl protocol has the same number as another one.
Make so that the virgl_formats_conv_table is following the same order as virgl_formats

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25295>

aco/spill: Make sure that offset stays in bounds

If a shader spills a lot, the offset can be above the HW limit.

cc: mesa-stable

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24652>

freedreno/fence: Hold a strong ref to batch

We don't want a unflushed fence to outlive it's batch, otherwise we run
into trouble when it comes time to wait on the fence.  For ex:

1. Create a fence before framebuffer state is set, with the
   PIPE_FLUSH_DEFERRED flags.  This creates a new batch, to which the
   ctx holds the only reference (unless the fence also holds a ref)
2. set_framebuffer_state() creates a new batch and drops the ctx->batch
   reference.
3. Later something tries to wait on the fence

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8621
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25337>

freedreno: Add reformatting commits to .git-blame-ignore-revs

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25337>

glsl: remove unused validate_first_and_last_interface_explicit_locations()

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>

glsl: switch to nir validate_first_and_last_interface_explicit_locations()

Use the new nir version. The glsl ir version will be removed in the
following patch.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>

glsl: add nir version of validate_first_and_last_interface_explicit_locations()

The glsl ir version will be removed in a following commit.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>

glsl: move get_varying_type() declaration earlier

Required for the following patch to keep this file somewhat organised.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>

intel/isl: Build for Xe2

This is only *build* support in isl for Xe2. Before adding LNL PCI
IDs, subsequent patches will fill in ISL updates for Xe2.

Rework:
 * Rohan: Update isl_genX_declare_get_func

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25253>

intel/genxml: Build with gen20.xml

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25253>

radv/ci: add more tests to the navi10 vkcts flake list

Since I had to aggregate the results of a lot of run, this commit also
ends up ordering some of the flakes to fit the alphabetical order.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25324>

radv/ci: move vkcts-navi10 testing to KWS

We now have 2 more navi10 DUTs at KWS, so let's use them to speed
up vkcts testing!

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25324>

nir/rematerialize: Rematerialize ALUs used only by compares with zero

This was 4th on the list of things to try in 3ee2e84c608 ("nir:
Rematerialize compare instructions"). This is implemented as a separate
subpass that tries to find ALU instructions (with restrictions) that are
only used by comparisons with zero that are in turn only used as
conditions for bcsel or if-statements.

There are two restrictions implemented. One of the sources must be a
constant. This is done in an attempt to prevent increasing register
pressure. Additionally, the opcode of the instruction must be one that
has a high probablility of getting a conditional modifier on Intel
GPUs. Not all instructions can have a conditional modifiers (e.g., min
and max), so I don't think there is any benefit to moving these
instructions.

v2: Rebase on many, many recent NIR infrastructure changes.

v3: Make data in commit message more clear. Suggested by Matt. Rebase on
b5d6b7c402a ("nir: Drop most uses if nir_instr_rewrite_src()").

All of the affected shaders on ILK and G45 are in CS:GO. There is some
brief analysis of the changes in the MR.

Reviewed-by: Matt Tuner <mattst88@gmail.com>
Shader-db results:

DG2
total instructions in shared programs: 22824637 -> 22824258 (<.01%)
instructions in affected programs: 365742 -> 365363 (-0.10%)
helped: 190 / HURT: 97

total cycles in shared programs: 832186193 -> 832157290 (<.01%)
cycles in affected programs: 41245259 -> 41216356 (-0.07%)
helped: 208 / HURT: 117

total spills in shared programs: 4072 -> 4060 (-0.29%)
spills in affected programs: 366 -> 354 (-3.28%)
helped: 4 / HURT: 2

total fills in shared programs: 3601 -> 3607 (0.17%)
fills in affected programs: 708 -> 714 (0.85%)
helped: 4 / HURT: 2

LOST:   0
GAINED: 1

Tiger Lake and Ice Lake had similar results. (Ice Lake shown)
total instructions in shared programs: 20320934 -> 20320689 (<.01%)
instructions in affected programs: 236592 -> 236347 (-0.10%)
helped: 176 / HURT: 29

total cycles in shared programs: 849846341 -> 849843856 (<.01%)
cycles in affected programs: 41277336 -> 41274851 (<.01%)
helped: 195 / HURT: 110

LOST:   0
GAINED: 1

Skylake
total instructions in shared programs: 18550811 -> 18550470 (<.01%)
instructions in affected programs: 233908 -> 233567 (-0.15%)
helped: 182 / HURT: 25

total cycles in shared programs: 835910983 -> 835889167 (<.01%)
cycles in affected programs: 38764359 -> 38742543 (-0.06%)
helped: 207/ HURT: 94

total spills in shared programs: 4522 -> 4506 (-0.35%)
spills in affected programs: 324 -> 308 (-4.94%)
helped: 4 / HURT: 0

total fills in shared programs: 5296 -> 5280 (-0.30%)
fills in affected programs: 324 -> 308 (-4.94%)
helped: 4 / HURT: 0

LOST:   0
GAINED: 1

Broadwell
total instructions in shared programs: 18199130 -> 18197920 (<.01%)
instructions in affected programs: 214664 -> 213454 (-0.56%)
helped: 191 / HURT: 0

total cycles in shared programs: 935131908 -> 934870248 (-0.03%)
cycles in affected programs: 75770568 -> 75508908 (-0.35%)
helped: 203 / HURT: 84

total spills in shared programs: 13896 -> 13734 (-1.17%)
spills in affected programs: 162 -> 0
helped: 3 / HURT: 0

total fills in shared programs: 16989 -> 16761 (-1.34%)
fills in affected programs: 228 -> 0
helped: 3 / HURT: 0

Haswell
total instructions in shared programs: 16969502 -> 16969085 (<.01%)
instructions in affected programs: 185498 -> 185081 (-0.22%)
helped: 121 / HURT: 1

total cycles in shared programs: 925290863 -> 924806827 (-0.05%)
cycles in affected programs: 30200863 -> 29716827 (-1.60%)
helped: 100 / HURT: 85

total spills in shared programs: 13565 -> 13533 (-0.24%)
spills in affected programs: 736 -> 704 (-4.35%)
helped: 8 / HURT: 0

total fills in shared programs: 15468 -> 15436 (-0.21%)
fills in affected programs: 740 -> 708 (-4.32%)
helped: 8 / HURT: 0

LOST:   0
GAINED: 1

Ivy Bridge
total instructions in shared programs: 15839127 -> 15838947 (<.01%)
instructions in affected programs: 77776 -> 77596 (-0.23%)
helped: 58 / HURT: 0

total cycles in shared programs: 459852774 -> 459739770 (-0.02%)
cycles in affected programs: 11970210 -> 11857206 (-0.94%)
helped: 79 / HURT: 53

Sandy Bridge
total instructions in shared programs: 14106847 -> 14106831 (<.01%)
instructions in affected programs: 1611 -> 1595 (-0.99%)
helped: 10 / HURT: 0

total cycles in shared programs: 775004024 -> 775007516 (<.01%)
cycles in affected programs: 2530686 -> 2534178 (0.14%)
helped: 55 / HURT: 48

Iron Lake
total cycles in shared programs: 257753356 -> 257754900 (<.01%)
cycles in affected programs: 2977374 -> 2978918 (0.05%)
helped: 12 / HURT: 106

GM45
total cycles in shared programs: 169711382 -> 169712816 (<.01%)
cycles in affected programs: 2402070 -> 2403504 (0.06%)
helped: 12 / HURT: 57

Fossil-db results:

All Intel platforms had similar results. (DG2 shown)
Totals:
Instrs: 193884596 -> 193465896 (-0.22%); split: -0.25%, +0.03%
Cycles: 14050193354 -> 14048194826 (-0.01%); split: -0.34%, +0.33%
Spill count: 114944 -> 100449 (-12.61%); split: -13.59%, +0.98%
Fill count: 201525 -> 179534 (-10.91%); split: -11.22%, +0.31%
Scratch Memory Size: 10028032 -> 8468480 (-15.55%)

Totals from 16912 (2.59% of 653124) affected shaders:
Instrs: 34173709 -> 33755009 (-1.23%); split: -1.41%, +0.19%
Cycles: 2945969110 -> 2943970582 (-0.07%); split: -1.62%, +1.55%
Spill count: 97753 -> 83258 (-14.83%); split: -15.98%, +1.15%
Fill count: 176355 -> 154364 (-12.47%); split: -12.82%, +0.35%
Scratch Memory Size: 8619008 -> 7059456 (-18.09%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20176>

radeonsi: emit framebuffer state after allocating cmask

tex->cmask_base_address_reg and tex->cb_color_info are used in
si_emit_framebuffer_state so we have to re-emit the state when
they're modified.

It's not done in si_alloc_separate_cmask because it cannot
update framebuffer.dirty_cbufs.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9830
Cc: mesa-stable
Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25317>

ci/fastboot: Use a case insensitive match for a fastboot line.

Newer boards like the RB5 have a capital F, so this will make the script
more reusable for drm ci.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25311>

radeonsi/vcn: Implement destroy_fence vfunc

Now that fences are correctly cleaned up in frontend, we can store
the fence reference in picture->fence again.

The encoder also needs to implement this vfunc because if a surface
from decoder is used directly as encode input it's now up to encoder
to destroy the fence.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9834

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25296>

frontends/va: Destroy fences when destroying surface or context

It is valid to destroy VASurface after destroying VAContext, so we need
to destroy fences of all surfaces that are currently being tracked by a
context when deleting this context.

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25296>

frontends/va: Track surfaces in context

This will be needed to correctly cleanup fences.

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25296>

u_gralloc: Add a function that returns gralloc type

This is needed by some drivers to reject the fallback gralloc.

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>

Revert "util: Add NONNULL macro"

We agreed in [1] not to use it since it has little value,
but making a code less readable.

[1]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256

This reverts commit 21dcde096f351f83a2df7aa9f42a7276b5454c81.

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>

u_gralloc: Remove usage of NONNULL macro

We agreed in [1] not to use it since it has little value,
but making a code less readable.

[1]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>

u_gralloc: Remove inline modifiers from the functions

Suggested-by: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>

docs: drop outdated and redundant note about the minimum meson version

The documentation we've been keeping up to date is in `docs/meson.rst`.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25322>

aco: simplify masked swizzle dpp selection by removing or_mask first

and_mask and xor_mask alone can represent all patterns without or_mask

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25115>

ci: limit build jobs to 30min so that they can retry when they go wrong

Build jobs should never take more than 1-3 minutes.

These jobs are never slow, either they finish within reasonable time or
something has gone wrong and the job will never terminate, so we should
instead timeout and retry.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24995>

rusticl/kernel: skip adding global id offsets if not used

This allows us to shrink the kernel input buffer quite significantly as
the offset is a vec aligned size_t3 value.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25303>

rusticl/mesa: fix `set_constant_buffer` when passing an empty buffer

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25303>

intel/fs: Update SSBO & shared uniform block loads for Xe2

Note: lower_lsc_block_logical_send() most likely stills needs some
related updates.

Ref: a358b97c586 ("intel/fs: optimize uniform SSBO & shared loads")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler: Update RT stack_id access for Xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler: Update ray-tracing intrinsic lowering for Xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler: Update lower_trace_ray_logical_send() for Xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler: Update emit_rt_lsc_fence() for Xe2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler: Update opt_split_sends() for Xe2 reg size

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler/fs: Support Xe2 reg size in assign_curb_setup

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/xe2+: Round up size to reg_unit() in fs_reg_alloc::alloc_spill_reg().

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Fix calculation of spill message width for Xe2 regs.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Fix execution width of SHADER_OPCODE_GET_BUFFER_SIZE for SIMD16 EU.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Update regioning lowering offset alignment checks for Xe2 regs.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs: Lower unsupported regioning with non-trivial 2D regions on FIXED_GRFs.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Update TASK/MESH payload setup for Xe2 reg size.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Update BS payload setup for Xe2 reg size.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Update TES payload setup for Xe2 reg size.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Update TCS payload setup for Xe2 reg size.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Update GS payload setup for Xe2 reg size.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler/xe2: Account for reg_unit() in TES intrinsics

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler/xe2: Account for reg_unit() in TCS intrinsics

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Fix payload layout of sampler messages for Xe2 reg size

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler/xe2: TXD is lowered to SIMD16 in SIMD32 mode

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler/xe2: Use SIMD16 for nir_intrinsic_image_size

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler/xe2: Update fs_visitor::setup_vs_payload to account for Xe2 reg size

[ Francisco Jerez: Simplify. ]

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler: Adjust barrier emission for Xe2+

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Scale BRW_MAX_MSG_LENGTH by native register size.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler: Adjust fence message lengths for new register width on Xe2+

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler: Adjust CS payload registers for new register width on Xe2+

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Round up fs_builder::vgrf() size calculation to HW register unit.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Update encoding of FB write message payload.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler/xe2+: Represent dispatch_grf_start_reg in native GRF units.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Allow increased SIMD width for various get_fpu_lowered_simd_width() restrictions.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/eu/xe2+: Update validation of GRF region size to account for Xe2 reg size

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Scale MAX_SAMPLER_MESSAGE_SIZE by native register size.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Fixes for increased accumulator register width.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Fix grf_count in post-RA scheduling for updated register file size.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/xe2+: Fix payload node live range calculations for change in register size.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs: Fix signedness of payload_node_count argument of calculate_payload_ranges().

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/eu/xe2+: Fix encoding of various message descriptors for change in register size.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/ra/xe2: Scale up register allocation granularity by 2x on Xe2+ platforms.

v2: Fix spill register allocation.  Switch to brw_reg::nr
    representation in fake 256b units.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/compiler: Make MAX_VGRF_SIZE macro depend on devinfo and update it for Xe2.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/vec4/ra: Define REG_CLASS_COUNT constant specifying the number of register classes.

Rework:
 * Jordan: 16=>20 following d33aff783d9 ("intel/fs: add support for
   sparse accesses")

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

intel/fs/ra: Define REG_CLASS_COUNT constant specifying the number of register classes.

Rework:
 * Jordan: 16=>20 following d33aff783d9 ("intel/fs: add support for
   sparse accesses")

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>

docs: add another 23.1.x

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25310>

docs: update calendar for 23.1.8

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25310>

docs: add sha256sum for 23.1.8

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25310>

docs: add release notes for 23.1.8

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25310>

amd: Use inverse ballot intrinsic if available

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25123>

nir/spirv: Add inverse_ballot intrinsic

This is actually a no-op on AMD, so we really don't want to lower it to
something more complicated.  There may be a more efficient way to do
this on Intel too. In addition, in the future we'll want to use this for
lowering boolean reduce operations, where the inverse ballot will
operate on the backend's "natural" ballot type as indicated by
options->ballot_bit_size, instead of uvec4 as produced by SPIR-V. In
total, there are now three possible lowerings we may have to perform:

- inverse_ballot with source type of uvec4 from SPIR-V to inverse_ballot
with natural source type, when the backend supports inverse_ballot
natively.
- inverse_ballot with source type of uvec4 from SPIR-V to arithmetic,
when the backend doesn't support inverse_ballot.
- inverse_ballot with natural source type from reduce operation, when
the backend doesn't support inverse_ballot.

Previously we just did the second lowering unconditionally in vtn, but
it's just a combination of the first and third. We add support here for
the first and third lowerings in nir_lower_subgroups, instead of simply
moving the second lowering, to avoid unnecessary churn.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25123>

nir/lower_subgroups: Don't do multiple lowerings at once

Since using nir_shader_lower_instructions(), instructions get revisited
before proceeding with the next one. This already guarantees that any
subsequent lowerings of those instructions happen during the same pass
of nir_lower_subgroups().

v2: use nir_shader_lower_instructions() instead of setting the cursor.

Co-authored-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25123>

zink: Store zink_vertex_elements_hw_state::b.strides by binding id

Currently, we store strides by vertex buffer id, which means that we have
to map the binding index to the vertex buffer index every time we want to
get a stride for a given binding. This also creates an order mismatch when
we pass strides directly to CmdBindVertexBuffers2EXT. Instead of converting
strides for CmdBindVertexBuffers2EXT too, we can just store strides by
binding id, and drop the mapping in other places.

Fixes: 76725452 ("gallium: move vertex stride to CSO")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9817
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25305>

radv/rt: Skip cull_mask handling if it is FF

Totals from 9 (1.32% of 680) affected shaders:
Instrs: 609329 -> 609057 (-0.04%)
CodeSize: 3267328 -> 3265664 (-0.05%)
Latency: 8289582 -> 8275874 (-0.17%)
InvThroughput: 2166498 -> 2163147 (-0.15%)
VClause: 23581 -> 23583 (+0.01%)
Copies: 51076 -> 51028 (-0.09%)
Branches: 24637 -> 24603 (-0.14%)
PreVGPRs: 996 -> 986 (-1.00%)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25268>

radv/ray_queries: Skip cull_mask handling if it is FF

Stats for Metro Exodus:

Totals from 26 (0.99% of 2627) affected shaders:
Instrs: 14586 -> 14232 (-2.43%)
CodeSize: 77024 -> 75192 (-2.38%)
VGPRs: 1408 -> 1208 (-14.20%)
Latency: 315076 -> 309898 (-1.64%)
InvThroughput: 42345 -> 41677 (-1.58%)
VClause: 366 -> 374 (+2.19%)
Copies: 2840 -> 2800 (-1.41%); split: -1.48%, +0.07%
Branches: 587 -> 561 (-4.43%)
PreSGPRs: 897 -> 853 (-4.91%)
PreVGPRs: 1290 -> 1122 (-13.02%)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25268>

radv/bvh: Treat instances with mask == 0 as inactive

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25268>

anv: refactor to fix pipe control debugging

While earlier changes to pipe control emission allowed debug dump of
each pipe control, they also changed debug output to almost always print
same reason/function for each pc. These changes fix the output so that
we print the original function name where pc is emitted.

As example:

pc: emit PC=( +depth_flush +rt_flush +pb_stall +depth_stall ) reason: gfx11_batch_emit_pipe_control_write
pc: emit PC=( ) reason: gfx11_batch_emit_pipe_control_write

changes back to:

pc: emit PC=( +depth_flush +rt_flush +pb_stall +depth_stall ) reason: gfx11_emit_apply_pipe_flushes
pc: emit PC=( ) reason: cmd_buffer_emit_depth_stencil

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25282>

v3dv: we can sample from 1D array too

Fixes: 95f881ad ('v3dv: add support for sampling simple 2D linear textures')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25286>

freedreno/a6xx: Add L8_SRGB

Avoids a tragic slow-path with CS:GO

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25298>

ci/zink: Add a few updates for anv/tgl from the nightly runs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25301>

ci/virgl: Disable virgl-iris-traces.

It's been failing with "No virgl contexts available on hostlibEGL warning:
egl: failed to create dri2 screen" for ages, and nobody seems to care.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25301>

ci/intel: Add various updates from our nightly runs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25301>

vc4: mark buffers as initialized at vc4_texture_subdata

This fixes several tests when the initially uploaded buffer
from CPU was being ignored because vc4_texture_subdata was not
marking the resource as written/initialized.

The usage flags management available at vc4_resource_transfer_map
is generalized into vc4_map_usage_prep and reused at
vc4_resource_transfer_map. This makes vc4 implementation more similar
to v3d.

This fixes 7 text in the following subgroups:
  -dEQP-GLES2.functional.fbo.render.texsubimage.*
  -dEQP-GLES2.functional.texture.specification.basic_copytexsubimage2d.*
  -spec@arb_clear_texture@arb_clear_texture-*

Cc: mesa-stable
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25297>

iris: assert(bo->deps) after realloc()

Iris in general doesn't really like checking the return value of its
allocations, but in some places it does assert that those pointers are
non-NULL. We've recently investigated a bug that could have been
coming from a failed bo->deps realloc(), so add the assert() here to
help give us more confidence over things the next time we're debugging
issues.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25236>

iris: avoid stack overflow in iris_bo_wait_syncobj()

Keep most cases using the stack as it's cheaper, but fall back to the
heap when the size gets too big.

This should fix a stack overflow reported by @rhezashan for a case
where we had lots of iris_screens.

Credits to Matt Turner and José Roberto de Souza for their work on
this issue, which led us to find its root cause.

Cc: mesa-stable
Reported-by: rheza shandikri (@rhezashan in gitlab)
Credits-to: José Roberto de Souza <jose.souza@intel.com>
Credits-to: Matt Turner <mattst88@gmail.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25236>