etnaviv: abort() instead of assert(0) on compiler error

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>

amd/registers: use gfx9 packet definitions for gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

amd/registers: update gfx940.json

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

amd/registers: fix the parser to include CP_COHER registers for gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

amd/registers: simplify integer division by 0x1000 in the parser

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi: don't set registers that don't exist on gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: enable RGBA/ARGB formats on gfx940 jpeg

enable RGBA/ARGB format on gfx940 to aid RGBA/ARGB conversion after decode

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

frontends/va: support crop region in jpeg decode

propogate region of interest co-ordinates for crop region decode

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: reset to default value when ROI/FC is not used

when decoding without ROI/FC feature reset the registers to default value.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: Add decode support for gfx940

Add VCN decode for gfx940

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: Add video capabilities support for gfx940

Add VCN codec caps support for gfx940

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

amd/common: Add gfx940 codec query support

Add support for GFX940 VCN query

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: set jpeg reg version for gfx940

select appropriate jpeg register version for gfx940

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: support ARGB/RGBA conversion on JPEG 4.0.3

enable ARGB/RGBA conversion feature on JPEG 4.0.3

v2: fix regression caused due to uninitialized variable

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: add support for picture crop on JPEG 4.0.3

set the crop region and enable the feature if requested

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: use register versions for jpeg

update the register version and select appropriate registers during decoder create

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: add register definitions for JPEG 4.0.3

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

ac/nir: fix CDNA image lowering for array textures

The x,y coordinates were not added.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

ac/nir: implement image opcode emulation for CDNA, enable it in radeonsi

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi: add an emulated image descriptor for gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

ac/surface: force linear image layout for chips not supporting image opcodes

Image opcodes will be emulated.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi: always use ffma32 on gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi: use COMPUTE_DISPATCH_SCRATCH_BASE on gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

amd: add initial code for gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

amd: add gfx940 register definitions

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

Revert "broadcom/ci: run gl jobs on arm64, just like vk"

This reverts commit ba4eeaf435f050dfec5472c7919b9b70e38d1bb8.

Looks like we have a lot of memory issues on arm64; revert the pre-merge
CI to armhf until we've been able to figure out the problem and fix it.

Closes https://gitlab.freedesktop.org/mesa/mesa/-/issues/8788

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22335>

nv50,nvc0: Use u_pipe_screen_get_param_defaults

Other than nouveau, every single Gallium driver relies on
u_pipe_screen_get_param_defaults to get the default values of CAPs.

For the driver, this is much more concise. Unsupported new features -- or
supported features that virtually all Gallium drivers support -- do not need to
written out explicitly. Their absence (or presence) is implied as the default.
If there's any doubt over whether the CAP is exposed, it's easy to check in
u_pipe_screen_get_param_defaults.

For the Gallium tree in general, this brings a number of benefits:

* Unused CAPs are easy to delete, because there is only a single place
  (u_pipe_screen_get_param_defaults) where they are referenced and need to be
  deleted from.

* New CAPs are easy to introduce, for the same reason.

* It's straightforward to audit which drivers support (or don't support) a given
  CAP by grepping for the name (for example, when determining whether a CAP is
  unused and can be garbage collected, or a CAP is so widely supported that it
  can be made default.). You still need to check the source code in case it's
  conditionally exposed (common for layered drivers) but the search space is
  limited to drivers that reference the CAP by name.

Unfortunately, all of these benefits rely on all Gallium drivers cooperating.
The status quo is much less nice:

* Unused CAPs need to be deleted both from common code, and also specially from
  nouveau. Why is nouveau special?

* New CAPs need to be added both to common code, and also specially to nouveau.
  Again, why is nouveau special?

* When grepping for CAPs, nouveau (only) needs to be ignored, since it's
  spurious.  Unless sometimes it's not, in which case you need to open nouveau
  source code anyway to check.

Compounding on the fun, you have to do the special nouveau step twice, once for
nvc0 and once for nv50.

Why might it be benefical to list CAPs explicitly instead of relying on the
defaults?

* Maybe easier auditing nouveau driver for CAP correctness? In practice this has
  not been an issue for any of the drivers I've worked on, especially because
  the defaults are quite reasonable.

* Maybe forcing people adding CAPs to think about nouveau specially? This isn't
  fair to the tree in general, why should nouveau get this special
  treatment? Instead, CAPs are generally added to gate functionality that may
  not be supported on all drivers, and the default is disabling the new
  functionality until a developer for a given driver can wire it up. There's
  already no expectation that the person adding CAPs needs to also add the
  functionality to nouveau (if that's even possible) -- unless the CAP is being
  added for the particular nouveau's benefit of course -- so this isn't helpful.

* Maybe forcing people removing CAPs to think about nouveau specially? Similar
  issues apply here, and it's not clear how this would even work.

* Maybe keeping novueau developers aware of CAP churn? Again nouveau should not
  be special here and it isn't sustainable to do this for every driver. So, if
  this is something that nouveau developers want to do -- and they choose not to
  follow Gallium-tagged merge requests -- then the git log of
  src/gallium/include/pipe/p_defines.h or indeed
  src/gallium/auxiliary/util/u_screen.c may be consulted.

So, without an excellent reason why nouveau should be treated specially, and
with several reasons why it should not, let's bring nouveau in line with the
rest of Gallium and rely on the defaults.

I've left in CAPs with attached comments even when they are returning the
default value to preserve information from before the commit. Otherwise, this
commit aims to remove explicit cases that match the default value, as other
drivers generally aim to do.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22245>

Revert "ci: disable Collabora's LAVA lab for maintance"

This reverts commit 86ad0356b6a8cc5f8b338cf7b92149b6e81f08e2.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22329>

intel/common: limit the amount of SLM with Wa_14017341140

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22307>

anv,blorp,iris: Set PreferredSLMAllocationSize on gfx125+

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22307>

intel/genxml: Add the preferred slm size enum for gen125

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22307>

intel/genxml/125: Add preferred SLM allocation size field

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22307>

CI/windows: Increase timeout for build container job

These jobs can take upwards of 40 minutes just to upload
the built container images...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22320>

CI/windows: Update headers and Agility redist to 1.710.0-preview

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22320>

glsl: move some GL ES checks to the NIR linker

Eventually we should aim to remove the GLSL IR linker.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22305>

mesa: add _mesa_is_api_gles2() helper

The glsl compiler has been reworked to avoid passing gl_context around
so that we can avoid expensive recompiles across the code base for
minor changes. This helper will help us avoid passing gl_context around
where its otherwise unrequired.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22305>

ci: disable Collabora's LAVA lab for maintance

This is to inform you of some planned downtime in the LAVA lab as follows:

    Start: 2023-04-06 07:30 GMT
    End: 2023-04-06 09:00 GMT

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22185>

radv: disable tc_compatible_cmask on GFX9 in some cases

There seems to be issues when sample count > 2 on GFX9.  More precisely,
CTS has issues when sample count > 2.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21615>

radv: add RADV_FMASK_COMPRESSION_PARTIAL

RADV_FMASK_COMPRESSION_PARTIAL means the fmask is decompressed but not
expanded.  It is desired for sampling when the cmask is not
TC-compatible.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21615>

radv: rework radv_layout_fmask_compressed

Rename radv_layout_fmask_compressed and make it return an enum.  We will
add partial compression (fmask decompressed and not expanded) in a
following commit.

Drop the check for VK_IMAGE_USAGE_STORAGE_BIT and
VK_IMAGE_USAGE_TRANSFER_DST_BIT.  When transitioning to
VK_IMAGE_LAYOUT_GENERAL, we should decompress and expand FMASK even when
those usage bits are not set.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21615>

ci/zink: Disable a630 portal-2-v2 due to kernel OOMs.

It's been popular for flakes due to oomkilling or kernel kmalloc failure
recently.  Is it ultimately the source of running out of memory?  Who
knows, but hopefully it's at least a big part of the problem.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

tgsi: Drop TGSI_OPCODE_DFRACEXP.

This is no longer emitted by nir_to_tgsi, so let's drop it.  This unlocks
some more TGSI DCE, since now all instructions have a single dest, but
that's a project for another day.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

glsl: Drop PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED.

All drivers should now be using the appropriate NIR lowering, so we can
drop this pile of code.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

glsl: Drop frontend lowering of 32-bit frexp.

All the users should now be calling the appropriate NIR lowering function.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

nir_to_tgsi: Always lower frexp_exp/sig.

The GLSL frontend was already lowering 32-bit frexp, so only 64-bit frexp
is possible as an op in the incoming NIR.  However, svga and nouveau don't
set PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED, leaving just r600's
non-default TGSI mode potentially using it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

panfrost/midgard: Enable nir_lower_frexp.

Needed for dropping the GLSL frontend lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

agx: Enable nir_lower_frexp.

Needed for Vulkan, and for dropping GLSL frontend lowering for the deqp
coverage override case.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

v3d: Lower frexp in the GL compiler like we do in Vulkan.

Needed for dropping GLSL's frontend lowering.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

zink: Enable nir_lower_frexp.

This will enable GLSL to drop its frexp lowering in the frontend.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

nouveau: Enable frexp lowering in the backend.

This would be desired for NVK using this backend, but also for getting
lowering out of the GLSL frontend.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

nouveau: Add missing nir_opt_algebraic_late.

This was needed for nir_lower_frexp, but it's a win anyway.  shader-db
results:

total gpr in shared programs: 1143621 -> 1143502 (-0.01%)
gpr in affected programs: 33918 -> 33799 (-0.35%)

total instructions in shared programs: 7829415 -> 7820124 (-0.12%)
instructions in affected programs: 1204967 -> 1195676 (-0.77%)

total bytes in shared programs: 71802760 -> 71717352 (-0.12%)
bytes in affected programs: 11031888 -> 10946480 (-0.77%)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

ir3: Move turnip's nir_lower_frexp to the shared compiler.

We had NIR lowering for Vulkan, and rely on GLSL's lowering in the
frontend, but this will let us drop the GLSL lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

intel: Always call nir_lower_frexp.

We have NIR lowering for Vulkan, and rely on GLSL's lowering in the
frontend, but this will let us drop the GLSL lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

state_tracker: Lower frexp before lowering doubles.

We don't have softfp64 for frexp, it has been lowered in GLSL up until
now.  I didn't bother splitting out 32 from 64 because it's not worth any
effort.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

glsl/softfp64: Add fisfinite lowering.

This is generated by nir_lower_frexp, and if we leave fisfinite in place
then the late algebraic pass lowering it to this pattern will cause an
un-lowered fabs64 to be emitted.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

glsl/softfp64: GC the temp vars after we lower them to SSA.

They don't serve any purpose other than taking up memory and cluttering
your compiler output at this point.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

glsl: Retire ldexp lowering in favor of the nir lowering flag.

Compilers need to set the nir flag anyway for vulkan, so just pass ldexp
through to NIR and let that handle it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

zink: Add mapping for nir_op_ldexp, but disable it for 64-bit's sake.

We previously had GLSL do ldexp lowering to bitops, but NIR can do it
instead.  It's tempting to just pass the NIR op through to the host Vulkan
driver, but to do that we'd need to split up NIR's flag between 32 and
64-bit support, and that's not worth anyone's time for an op we've never
seen used.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

glsl: Move ForceGLSLAbsSqrt handling to glsl-to-nir.

Cutting more GLSL lowering pass in favor of nir builder.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

radv: fix leak of nir from retained shaders

if shaders are found in the app cache above, execution will goto done:
and the nir must still be freed

Fixes: 03d2bd6042d ("radv: ensure to retain NIR shaders for GPL libs found in the cache")

fixes #8786

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22317>

panfrost: assign the correct create_for_resource from the start

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22322>

util/disk_cache: Move blob_put_cb to the async queue

Move deflate and put to the queue for the blob cache case.  This moves
the overhead out of the app thread when storing new shaders.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22248>

util/disk_cache: Use queue state to skip put

If we move the blob-cache path into the async queue, then
path_init_failed is no longer a good way to check if puts
should be a no-op.  But fortunately checking if the queue
is initialized is, and is a more obvious check because
what it is guarding is a util_queue_add_job().

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22248>

util/disk_cache: Add NONE type

Add an explicit enum for the DISK_CACHE_NONE type so that we don't
confuse with the MULTI_FILE case on android when the blob-cache is
used.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22248>

util/disk_cache: Split out queue initialization

Split out a helper to initialize the queue, as we'll want to re-use this
for the blob-cache case.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22248>

intel/compiler: Support fmul_fsign opt for fp64 when int64 isn't supported

MTL support fp64, but not int64. The fsign(double(x))*FOO optimization
would try to use a 64-bit int xor operation to conditionally toggle
the sign bit off the result.

Since this only affects high bit of the result, we can do a 32-bit
move of the low dword, and a 32-bit xor on the high dword.

Fixes dEQP-VK.spirv_assembly.instruction.compute.float_controls.fp64.input_args.modf_denorm_flush_to_zero
on MTL.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22259>

radv/amdgpu: Remove can_patch and chained submit code path.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv: Chain cmd buffers in queue code when possible, not in winsys.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv/amdgpu: Unchain CS array in queue code not in winsys.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv/amdgpu: Walk chained CS objects for BO list.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv/amdgpu: Remember which CS the current one is chained to.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv/amdgpu: Extract radv_amdgpu_add_cs_to_bo_list function.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv/amdgpu: Expose CS chain and unchain on the winsys.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

radv/amdgpu: Extract CS chain and unchain functions.

Also add a comment that explains what chaining means
and add a check to make sure the HW IP type supports it.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22220>

ci: implement sections for cuttlefish

Reviewed-by: Helen Koike <helen.koike@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22005>

radv: emit the PS epilog after the graphics pipeline

Otherwise, SPI_SHADER_PGM_RSRC1_PS is overwritten when the graphics
pipeline is emitted.

Fixes: 5c362cde33b ("radv: update PS num_vgprs in case of epilogs rather than overallocating VGPRs")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22310>

vc4/ci: add another sync flake

https://gitlab.freedesktop.org/mesa/mesa/-/jobs/39377396

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22312>

glthread: use id 0 for internal buffer objects

-1 is an invalid buffer index which breaks app expectations, specifically
apitrace, which checks for return value of 0 from checking buffer bindings
to determine whether to inject user vertex buffer bindings and create functional
traces

this should fix capturing traces with drivers using glthread

fixes #8383

cc: mesa-stable

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22293>

intel/fs: also allow vec8+ vectorization of load_global_const_block_intel

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

intel/fs: optimize uniform SSBO & shared loads

Using divergence analysis, figure out when SSBO & shared memory loads
are uniform and carry the data only once in register space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

nir: add 2 new intel intrinsics for uniform ssbo/shared loads

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

nir: reuse nir_component_mask() where it makes sense

Avoiding local bit field manipulations.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

intel/fs: factor out lsc surface descriptor settings

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

intel/fs: copy instruction sources in logical send lowering

Having references to inst->src[X] when you're also modifying
inst->src[X] is a receipe for disaster. Making changes to the lowering
code I've been bitten quite a few times by this take copies of all
sources to do the lowering.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

intel/fs: UNDEF fixup_nomask_control_flow temp register

Ensure that the register's liveness is not expanded to loops.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

intel/fs: don't consider fixup_nomask_control_flow SENDs predicate

Those SENDs are still doing a full register write. We just inserted
some predication for a workaround.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

intel/fs: run VGRF compaction just before max live register accounting

There are a number of instances of the dead code elimination pass that
could reduce the count. For some reason this also seems to affect
register allocation itself.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21853>

anv: ignore structure types handled in vk_device_memory_create

Without that we get warning from anv_debug_ignored_stype, called in
the default case.

Fixes: 4b0b75c27a7 ("anv: Use the new vk_device_memory base struct")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22295>

broadcom/ci: run gl jobs on arm64, just like vk

These were running on armhf because that's the default in the custom
distro that Raspberry Pi provides, but arm64 is ~20% faster, and we
already run weekly tests on both arm64 & armhf, so let's keep only the
faster one in the pre-merge path.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22272>

r600/sfn: fix container allocators

This fixes leaks in TexInstr and in Shader.

Thanks to Patrick Lerda for pointing out the bug.

Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
    r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22300>

radv: fix VS prologs with GPL and static binding stride

When a graphics pipeline library is created with only the vertex input
state, the driver binds this state at pipeline bind time. Though the
vertex binding stride is not necessarily dynamic, in this case the
pipeline stride should be used.

This fixes GPU hangs with recent
dEQP-VK.pipeline.fast_linked_library.vertex_input.*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22285>

v3d,v3dv: stop trying to force 16-bit TMU output for shadow comparisons

In V3D we were doing this incorrectly by peeking into the sampler state
unconditionally, which is not correct if the TMU operations don't use
sampler state at all (like PBOs). This was causing us to fail the second
test in this sequence when both tests run back back to back in the same
process:

dEQP-GLES3.functional.texture.shadow.2d.linear.greater_or_equal_depth_component32f
dEQP-GLES3.functional.texture.specification.teximage2d_pbo.rg32f_cube

Here, the first test would setup sampler state for shadow comparisons and
the second test would setup a PBO upload, which would incorrectly pick
up the sampler state to decide about the TMU output size for the PBO
operation.

In V3DV we were doing this right looking through each texture/sampler
instruction and checking if they all involved shadow comparisons or had
relaxed precission, defaulting to 32-bit otherwise.

This special-casing for shadow comparisons also leaks from drivers
into the compiler where we are forced to emit some pieces of sampler
state for 32-bit outputs, so we had to special-case shadow instructions
there as well and we also had a fix for CS textures not having correct
sampler state representing shadow operations too. Finally,
we also had  at least a couple of bugs where forcing 32-bit TMU output
through V3D_DEBUG wasn't correctly forcing shadow comparisons to actually
be 32-bit in all the right places, leading to visual bugs with the
option enabled (Sponza being one example of this). This change eliminates
all of these issues.

Finally, the performance improvement observed from special casing shadow
comparison is negligible, and in specific scenarios it can even be
detrimental to performance due to increased register pressure (Sponza with
PCF filtering set to 4 is an example of this again).

Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8684
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22284>

vulkan/wsi/display: set pDisplay to NULL on error

the spec for vkGetDrmDisplayEXT says:

  "If there is no VkDisplayKHR corresponding to the connectorId on the
   physicalDevice, the returning display must be set to VK_NULL_HANDLE.
   The provided drmFd must correspond to the one owned by the physicalDevice.
   If not, the error code VK_ERROR_UNKNOWN must be returned. (...)
   The given connectorId must be a resource owned by the provided drmFd.
   If not, the error code VK_ERROR_UNKNOWN must be returned"

We were only setting the display pointer to VK_NULL_HANDLE if the provided
drmFd was valid, however, there are CTS tests checking that it is also set
to NULL when it is not.

Fixes the following test on all drivers exposing EXT_acquire_drm_display
(tested with Intel and V3DV):
dEQP-VK.wsi.acquire_drm_display.acquire_drm_display_invalid_fd

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22283>

v3dv: always acquire display device before checking if we can present

Usually, we postpone acquisition until a swapchain is created, but there are
some cases with display extensions (at least with EXT_acquire_drm_display)
where we need to acquire before a swapchain is ever created.

Fixes various tests in:
dEQP-VK.wsi.acquire_drm_display.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22283>

v3dv: drop unused parameter

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22283>

llvmpipe: clean-up llvmpipe_get_query_result()

Get rid of the uint64 result pointer which was used by some query
types.  Handle each switch case with self-contained code.  Remove
unneeded casts.  Use MIN2/MAX2 macros.

Signed-off-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22281>

llvmpipe: s/unsigned/enum pipe_query_type/

Note we should do the same for pipe_context::create_query()'s
query_type parameter.  That would touch quite a few files.

Signed-off-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22281>

llvmpipe: s/tabs/spaces/

Signed-off-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22281>

llvmpipe: rename some vars related to occlusion query and ps invocations

More consistent naming.

Signed-off-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22281>

llvmpipe: fix ps invocations query bug

We were not initializing the PS invocation count to zero before
computing the sum of the per-thread results.

This fixes an issue where querying the result of the query more
than once would cause the result to grow larger each time.

Signed-off-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22281>