Phoebe Wang [Tue, 16 May 2023 15:39:05 +0000 (23:39 +0800)]
[Driver] Support multi /guard: options
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D150645
Valentin Clement [Tue, 16 May 2023 15:43:17 +0000 (08:43 -0700)]
[mlir][openacc] Add ReturnLike trait to acc.yield operation
Just add the trait as acc.yield is a return like op.
Reviewed By: razvanlupusoru, jeanPerier
Differential Revision: https://reviews.llvm.org/D150617
Juan Manuel MARTINEZ CAAMAÑO [Wed, 10 May 2023 09:26:44 +0000 (11:26 +0200)]
[AMDGPU][InferAddressSpaces] Only rewrite address-spaces that can be trivially casted to flat for llvm.amdgcn.flat.atomic.{fadd,fmax,fmin}
The intrinsic @llvm.amdgcn.flat.atomic.{fadd,fmax,fmin} can only be
selected for flat address spaces (constant, flat and global).
This patch restricts the cases over which GCNTTIImpl::rewriteIntrinsicWithAddressSpace
rewrites the intrinsic.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D149938
Matt Arsenault [Thu, 20 Apr 2023 11:39:40 +0000 (07:39 -0400)]
LangRef: Clarify behavior of minnum/maxnum
Make it clearer minnum(+0, +0) cannot return -0. Also remove
a note about the result always being quiet which is directly
contradicted by the following paragraph.
Matt Arsenault [Sat, 29 Apr 2023 20:50:48 +0000 (16:50 -0400)]
GlobalOpt: Improve addrspacecast handling
Handle addrspacecast when looking at uses.
Matt Arsenault [Sat, 29 Apr 2023 20:41:54 +0000 (16:41 -0400)]
GlobalOpt: Add a test for addrspacecast coverage with alloc functions
AllUsesOfValueWillTrapIfNull could handle addrspacecast, but currently
doesn't.
Timm Bäder [Tue, 16 May 2023 15:26:19 +0000 (17:26 +0200)]
Revert "[clang] Show line numbers in diagnostic code snippets"
This reverts commit
e2917311f026cc445fa8aeefa0457b0c7a60824a.
This caused some problems with lldb testing the diagnostic output:
https://lab.llvm.org/buildbot/#/builders/68/builds/52754
Timm Bäder [Tue, 16 May 2023 15:20:40 +0000 (17:20 +0200)]
[clang][docs] Fix sphinx bot
Breakage:
https://lab.llvm.org/buildbot/#/builders/92/builds/44222
Timm Bäder [Sun, 9 Apr 2023 08:16:17 +0000 (10:16 +0200)]
[clang] Show line numbers in diagnostic code snippets
Show line numbers to the left of diagnostic code snippets and increase
the numbers of lines shown from 1 to 16.
Differential Revision: https://reviews.llvm.org/D147875
Phoebe Wang [Tue, 16 May 2023 15:10:51 +0000 (23:10 +0800)]
[LLD] Do not assume /guard:cf always set together with /guard:ehcont
MS link accepts *.obj with ehcont bit set only. LLD should match this
behavoir too.
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D150508
Alexey Lapshin [Thu, 11 May 2023 17:09:47 +0000 (19:09 +0200)]
[DWARFLinker][DWARFv5] Add support for .debug_line_str table.
This patch adds support for DWARFv5 .debug_line_str table.
It replaces code generating line table. Instead of copying original
table and patching certain places this patch implements full line table
generation.
Differential Revision: https://reviews.llvm.org/D150554
Bjorn Pettersson [Thu, 11 May 2023 09:40:45 +0000 (11:40 +0200)]
[MemCpyOpt] Fix up debug loc for simplified memset in processMemSetMemCpyDependence
Make sure the code comments in processMemSetMemCpyDependence match
with the actual transform. They indicated that the memset being
rewritten was sunk to after a memcpy, while it actually is inserted
just before the memcpy.
Also make sure we use the debug location of the original memset
when creating the new simplified memset. In the past we've been
using the debug location for the memcpy which could be a bit
confusing.
Differential Revision: https://reviews.llvm.org/D135574
Jay Foad [Mon, 15 May 2023 13:42:14 +0000 (14:42 +0100)]
[AMDGPU] Avoid RegScavenger::forward in copyPhysReg/indirectCopyToAGPR
RegScavenger::backward is preferred because it does not rely on accurate
kill flags.
Differential Revision: https://reviews.llvm.org/D150571
Bjorn Pettersson [Tue, 16 May 2023 14:33:46 +0000 (16:33 +0200)]
Revert "[GlobalIsel][X86] Legalize G_BSWAP"
This reverts commit
5cafecf9f952818400fa32645695e79838f1bc2c.
Buildbots are not happy with the patch.
Lots of crashes and assertion failures such as
llvm::LegalizeRuleSet &llvm::LegalizerInfo::getActionDefinitionsBuilder(
std::initializer_list<unsigned int>): Assertion `Opcodes.size() >= 2 &&
"Initializer list must have at least two opcodes"' failed.
Jon Roelofs [Tue, 16 May 2023 14:25:21 +0000 (07:25 -0700)]
tsan-rt: silence a -Wunused-const-variable
Jon Roelofs [Tue, 16 May 2023 14:24:54 +0000 (07:24 -0700)]
lsan-rt: silence a -Wformat-pedantic
Jon Roelofs [Tue, 16 May 2023 14:19:59 +0000 (07:19 -0700)]
asan-rt: silence some more -Wformat-pedantic's
zhijian [Tue, 16 May 2023 14:13:57 +0000 (10:13 -0400)]
[AIX] Fixed malformed big archive when total archive file size is large than 4Gbytes
Summary:
1. we use the unsigned type for NextOffset,PrevOffset ,GlobalSymbolOffset , MemberTableSize, it will caused a malform big archive when the archive file size is large than 4G.
2. also fix a NFC comment on https://reviews.llvm.org/D142479#inline-1443927
Reviewers: James Henderson
Differential Revision: https://reviews.llvm.org/D150462
Bjorn Pettersson [Mon, 24 Apr 2023 08:48:04 +0000 (10:48 +0200)]
Remove some includes that shouldn't be needed any longer
This remove a bunch of #include statements in Scalar.cpp. I do not
think those should be needed any longer (assuming that they once
upon a time possibly were needed for legacy PM C bindings, but
that is not supported any longer).
Also removing some other #include statements not needed any longer
due to deprecation of legacy PM.
Differential Revision: https://reviews.llvm.org/D149438
Sander de Smalen [Tue, 16 May 2023 12:53:37 +0000 (12:53 +0000)]
[AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for pext (multi)
These intrinsics are used to implement the pext intrinsics that extract
two predicates (mask) from a predicate-as-counter value, e.g.
__attribute__((arm_streaming))
svboolx2_t svpext_lane_c8_x2(svcount_t pnn, uint64_t imm);
As described in https://github.com/ARM-software/acle/pull/217
Reviewed By: kmclaughlin
Differential Revision: https://reviews.llvm.org/D150442
Sander de Smalen [Tue, 16 May 2023 12:53:23 +0000 (12:53 +0000)]
[AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for pext (single)
These intrinsics are used to implement the pext intrinsics that extract
a predicate (mask) from a predicate-as-counter value, e.g.
__attribute__((arm_streaming))
svbool_t svpext_lane_c8(svcount_t pnn, uint64_t imm);
As described in https://github.com/ARM-software/acle/pull/217
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D150441
Thorsten Schütt [Tue, 16 May 2023 13:45:30 +0000 (15:45 +0200)]
[GlobalIsel][X86] Legalize G_BSWAP
remark: unable to legalize instruction: %95:_(s16) = G_BSWAP %94:_ (in function: _ZNK4llvm13DataExtractor6getU16EPyPtj) [-Rpass-missed=gisel-legalize]
check plan: ninja check-llvm-codegen-x86
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D150667
Qiongsi Wu [Tue, 16 May 2023 13:41:00 +0000 (09:41 -0400)]
[clang][AIX] Adding Revised xcoff-roptr CodeGen Test Case
https://reviews.llvm.org/D150586 removed a problematic test cases that caused failures on non-ppc buildbots. This patch revises the test case and adds it back.
Reviewed By: hubert.reinterpretcast
Differential Revision: https://reviews.llvm.org/D150597
Michael Klein [Tue, 16 May 2023 13:34:48 +0000 (15:34 +0200)]
[analyzer] Fix QTimer::singleShot NewDeleteLeaks false positive
Fixes #39713
fferential Revision: https://reviews.llvm.org/D150552
Matt Arsenault [Wed, 26 Apr 2023 14:02:54 +0000 (10:02 -0400)]
ValueTracking: Restore ordered negative handling for frem
In D148674, the negative condition was weakened to only
checking isKnownNever(fcNegative), instead of cannotBeOrderedLessThanZero().
This avoids a regression when CannotBeOrderedLessThanZero is
replaced with computeKnownFPClass.
Timm Bäder [Sun, 14 May 2023 07:45:51 +0000 (09:45 +0200)]
[clang][NFC] Use llvm::count_if instead of manual loop
Matt Arsenault [Thu, 13 Apr 2023 14:07:13 +0000 (10:07 -0400)]
ValueTracking: fadd/fsub +0 cannot return -0
Copied from CannotBeNegativeZero and extended to cover fsub.
Sergei Barannikov [Tue, 16 May 2023 13:10:31 +0000 (16:10 +0300)]
[clang] Regenerate checks in OpenMP tests with opaque-pointers enabled
LLVM GN Syncbot [Tue, 16 May 2023 13:22:38 +0000 (13:22 +0000)]
[gn build] Port
7158fd381a0b
Jun Zhang [Tue, 16 May 2023 13:21:52 +0000 (21:21 +0800)]
Revert "[clang-repl] Introduce Value to capture expression results"
This reverts commit
a423b7f1d7ca8b263af85944f57a69aa08fc942c.
See https://lab.llvm.org/buildbot/#/changes/95083
David Candler [Tue, 16 May 2023 13:13:04 +0000 (14:13 +0100)]
[builtins][test] Use architecture specific float16 check
The COMPILER_RT_HAS_FLOAT16 cmake check is now set per architecture,
which needs to be reflected when building the tests.
Additionally added armhf to the architecture list.
Reviewed By: dim
Differential Revision: https://reviews.llvm.org/D150281
Tobias Gysi [Tue, 16 May 2023 13:06:12 +0000 (13:06 +0000)]
[mlir][llvm] Add is constant intrinsic.
The revision adds LLVM's is constant intrinsic.
Depends on D150643
Reviewed By: Dinistro
Differential Revision: https://reviews.llvm.org/D150660
Weining Lu [Tue, 16 May 2023 09:43:59 +0000 (17:43 +0800)]
[Clang][LoongArch] Pass the -mabi and -target-abi options to as and cc1as respectively
This change is necessary to set correct EFlags according to the
options (-m*-float and -mabi=) passed to clang when input is assembly.
Note: `-mabi=` is not documented by `as`.
```
$ as --version
GNU assembler (GNU Binutils) 2.40.50.
20230316
...
$ as --target-help
LARCH options:
```
But we can see gcc invokes `as` and passes the `-mabi=` option when compiling C or assembly.
```
$ gcc -c a.c -v 2>&1 -msoft-float | grep "as -v"
as -v -mabi=lp64s -o a.o /tmp/ccFrxzZi.s
$ gcc -c a.s -v 2>&1 -msoft-float | grep "as -v"
as -v -mabi=lp64s -o a.o a.s
```
Reviewed By: xen0n
Differential Revision: https://reviews.llvm.org/D150537
Weining Lu [Tue, 16 May 2023 09:43:41 +0000 (17:43 +0800)]
[LoongArch] Move lp64s out of the unimplemented calling conv list
lp64s is same as lp64d execpt that floating point arguments and return
values are always passed via GPRs or stack which means `UseGPRForFloat`
is always `true` in `CC_LoongArch` for lp64s.
One motivation of this change is to build linux which uses
`-msoft-float` and `-mabi=lp64s` [1].
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/Makefile?h=v6.4-rc1#n49
Reviewed By: xen0n, hev
Differential Revision: https://reviews.llvm.org/D150417
Sam McCall [Thu, 4 May 2023 22:18:38 +0000 (00:18 +0200)]
[clangd] downgrade missing-includes diagnostic to Information level
In practice, a Warning on every occurrence is very unpopular, even on a codebase
with clear rules about direct inclusion & moderately good compliance.
This change has various practical effects (in vscode for concreteness):
- makes the diagnostic decoration less striking (blue vs yellow)
- makes these diagnostics visually distinct from others when reading
- causes these diagnostics to sort last in the "problems" view
- allows these diagnostics to be easily filtered from the "problems" view
Differential Revision: https://reviews.llvm.org/D149912
David Green [Tue, 16 May 2023 13:03:15 +0000 (14:03 +0100)]
[AArch64] Change the type of i64 neon shifts to v1i64
This alters the lowering of shifts by a constant, so that the type is lowered
to a v1i64 instead of a i64. This helps communicate that the type will live in
a neon register, and can help clean up surrounding code. Note this is only
currently for the scalar shifts of a constant that go through the nodes in
tryCombineShiftImm.
ssra instructions are no longer being recognized in places, but that can be
cleaned up in a followup patch that combines the i64 add into a v1i64 add.
Differential Revision: https://reviews.llvm.org/D148309
Nico Weber [Tue, 16 May 2023 13:00:48 +0000 (09:00 -0400)]
[gn build] Port
a423b7f1d7ca (ClangReplInterpreterTests -rdynamic)
Sergei Barannikov [Mon, 15 May 2023 23:15:06 +0000 (02:15 +0300)]
[clang] Convert a few OpenMP tests to opaque pointers
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D150652
Takuya Shimizu [Tue, 16 May 2023 12:37:08 +0000 (21:37 +0900)]
[clang][AST] Print name instead of type when diagnosing uninitialized subobject in constexpr variables
This patch improves the diagnostic on uninitialized subobjects in constexpr variables by modifying the diagnostic message to display the subobject's name instead of its type.
Fixes https://github.com/llvm/llvm-project/issues/58601
Differential Revision: https://reviews.llvm.org/D146358
Thorsten Schütt [Tue, 16 May 2023 12:35:38 +0000 (14:35 +0200)]
[GlobalIsel][x86] Legalize G_AND, G_OR, and G_XOR for AVX2
check plan: ninja check-llvm-codegen-x86
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D150658
Matthias Springer [Tue, 16 May 2023 10:53:14 +0000 (12:53 +0200)]
[mlir][GPU] Rename MLIRGPUOps CMake target to MLIRGPUDialect
This is for consistency with other dialects.
Differential Revision: https://reviews.llvm.org/D150659
David Green [Tue, 16 May 2023 12:16:42 +0000 (13:16 +0100)]
[AArch64] Additional testing for uqshl and regenerate arm64-vshift.ll. NFC
This tries to fill in some missing testing for neon shift intrinsics, and
regenerates the existing tests. See D148309 and D148311.
Jun Zhang [Tue, 16 May 2023 12:10:49 +0000 (20:10 +0800)]
[clang-repl] Introduce Value to capture expression results
This is the second part of the below RFC:
https://discourse.llvm.org/t/rfc-handle-execution-results-in-clang-repl/68493
This patch implements a Value class that can be used to carry expression
results in clang-repl. In other words, when we see a top expression
without semi, it will be captured and stored to a Value object. You can
explicitly specify where you want to store the object, like:
```
Value V;
llvm::cantFail(Interp->ParseAndExecute("int x = 42;"));
llvm::cantFail(Interp->ParseAndExecute("x", &V));
```
`V` now stores some useful infomation about `x`, you can get its real
value (42), it's `clang::QualType` or anything interesting.
However, if you don't specify the optional argument, it will be captured
to a local variable, and automatically called `Value::dump`, which is
not implemented yet in this patch.
Signed-off-by: Jun Zhang <jun@junz.org>
Jun Zhang [Tue, 16 May 2023 12:10:43 +0000 (20:10 +0800)]
[clang] Add a new annotation token: annot_repl_input_end
This patch is the first part of the below RFC:
https://discourse.llvm.org/t/rfc-handle-execution-results-in-clang-repl/68493
It adds an annotation token which will replace the original EOF token
when we are in the incremental C++ mode. In addition, when we're
parsing an ExprStmt and there's a missing semicolon after the
expression, we set a marker in the annotation token and continue
parsing.
Eventually, we propogate this info in ParseTopLevelStmtDecl and are able
to mark this Decl as something we want to do value printing. Below is a
example:
clang-repl> int x = 42;
clang-repl> x
// `x` is a TopLevelStmtDecl and without a semicolon, we should set
// it's IsSemiMissing bit so we can do something interesting in
// ASTConsumer::HandleTopLevelDecl.
The idea about annotation toke is proposed by Richard Smith, thanks!
Signed-off-by: Jun Zhang <jun@junz.org>
Differential Revision: https://reviews.llvm.org/D148997
Wang, Xin10 [Tue, 16 May 2023 12:04:35 +0000 (13:04 +0100)]
Fix regression after D150436
llvm-clang-x86_64-expensive-checks-debian will fail after D150436 merged.
The fail occurred in X86, I changed the sort rule in AsmMatcher in Patch D150436, so x86 code will arrive line 633 first(will not affect other targets).
The logic here want to use the order record written in source file to make AsmMatcher to first use AVX instructions, it used field HasPositionOrder.
But the condition here just makes sure one of the compared record is subclass of Instruction and has field HasPositionOrder true, and didn't check another.
(Committing on behalf of @XinWang10 to unblock broken expensive-cjhecks builds)
Differential Revision: https://reviews.llvm.org/D150651
Corentin Jabot [Tue, 16 May 2023 11:55:40 +0000 (13:55 +0200)]
Revert "[Clang] Fix parsing of `(auto(x))`."
This reverts commit
ef47318ec3615e83c328b07341046dfb9d869414.
This patch breaks valid code https://reviews.llvm.org/D149276#4345620
Alvin Wong [Thu, 6 Apr 2023 13:24:06 +0000 (21:24 +0800)]
[asan][test][win] Move MSVC-specific tests into a subdir
This moves all but one remaining tests which use clang-cl and test
MSVC-specific behaviour into its own subdirectory. `dll_host.cpp` test
is excluded from the move because other tests also depend on its source
file, making it not MSVC-specific.
Differential Revision: https://reviews.llvm.org/D150271
Alvin Wong [Tue, 9 May 2023 16:45:45 +0000 (00:45 +0800)]
[asan][test][win] Remove `REQUIRES: asan-rtl-heap-interception`
This appears to be a leftover from when these tests were first added in
D62927. Because of this, these tests had never run with `check-asan` or
`check-asan-dynamic`.
I've tested locally that these tests do pass on both i686 MSVC and MinGW
targets. They are disabled for 64-bit though, and I believe no LLVM
buildbots are testing for 32-bit Windows targets.
Differential Revision: https://reviews.llvm.org/D150270
Alvin Wong [Tue, 9 May 2023 21:41:06 +0000 (05:41 +0800)]
[asan][test][win] Port more tests to not use clang-cl on MinGW (4)
This ports some tests that requires dead stripping or ICF.
Differential Revision: https://reviews.llvm.org/D150269
Alvin Wong [Sun, 2 Apr 2023 11:45:57 +0000 (19:45 +0800)]
[asan][test][win] Port more tests to not use clang-cl on MinGW (3)
This ports tests which requires additional link flags.
Differential Revision: https://reviews.llvm.org/D150268
Alvin Wong [Sun, 2 Apr 2023 11:45:57 +0000 (19:45 +0800)]
[asan][test][win] Port more tests to not use clang-cl on MinGW (2)
Continuation of D147432 and D147444.
Differential Revision: https://reviews.llvm.org/D150267
Alvin Wong [Thu, 11 May 2023 09:26:03 +0000 (17:26 +0800)]
[asan][win][test] Disable interception_failure_test.cpp for static asan
This test checks that asan does not intercept user-provided libc
functions, but on Windows the static asan runtime does intercept static
copies of libc functions, so this test is invalid for said environment.
It used to fail from a different linker error, but this no longer
happens with newer WinSDK. Refer to comments on
https://reviews.llvm.org/D149549.
Differential Revision: https://reviews.llvm.org/D150349
Matt Arsenault [Sun, 9 Apr 2023 02:33:35 +0000 (22:33 -0400)]
ValueTracking: Implement computeKnownFPClass for sqrt
Could be slightly smarter in cases that are probably uninteresting.
Alex Zinenko [Tue, 16 May 2023 11:31:21 +0000 (11:31 +0000)]
[mlir] drop spurious PDL include
Jun Zhang [Tue, 16 May 2023 11:11:40 +0000 (19:11 +0800)]
[Instsimplfy] X == Y ? 0 : X - Y --> X - Y
Alive2: https://alive2.llvm.org/ce/z/rPN1GB
Fixes: https://github.com/llvm/llvm-project/issues/62238
Depends on D150377
Signed-off-by: Jun Zhang <jun@junz.org>
Differential Revision: https://reviews.llvm.org/D150378
Jun Zhang [Tue, 16 May 2023 11:11:34 +0000 (19:11 +0800)]
Add baseline tests for PR62238
Differential Revision: https://reviews.llvm.org/D150377
Signed-off-by: Jun Zhang <jun@junz.org>
Tobias Gysi [Tue, 16 May 2023 11:06:36 +0000 (11:06 +0000)]
[mlir][llvm] Add expect intrinsics.
The revision adds the LLVM expect and expect.with.probability
intrinsics.
Reviewed By: Dinistro, ftynse
Differential Revision: https://reviews.llvm.org/D150643
Tung D. Le [Tue, 16 May 2023 10:24:39 +0000 (10:24 +0000)]
[mlir] Fix memory explosion when converting global variable bodies in ModuleTranslation
There is memory explosion when converting the body or initializer region of a large global variable, e.g. a constant array.
For example, when translating a constant array of 100000 strings:
```
llvm.mlir.global internal constant @cats_strings() {addr_space = 0 : i32, alignment = 16 : i64} : !llvm.array<100000 x ptr<i8>> {
%0 = llvm.mlir.undef : !llvm.array<100000 x ptr<i8>>
%1 = llvm.mlir.addressof @om_1 : !llvm.ptr<array<1 x i8>>
%2 = llvm.getelementptr %1[0, 0] : (!llvm.ptr<array<1 x i8>>) -> !llvm.ptr<i8>
%3 = llvm.insertvalue %2, %0[0] : !llvm.array<100000 x ptr<i8>>
%4 = llvm.mlir.addressof @om_2 : !llvm.ptr<array<1 x i8>>
%5 = llvm.getelementptr %4[0, 0] : (!llvm.ptr<array<1 x i8>>) -> !llvm.ptr<i8>
%6 = llvm.insertvalue %5, %3[1] : !llvm.array<100000 x ptr<i8>>
%7 = llvm.mlir.addressof @om_3 : !llvm.ptr<array<1 x i8>>
%8 = llvm.getelementptr %7[0, 0] : (!llvm.ptr<array<1 x i8>>) -> !llvm.ptr<i8>
%9 = llvm.insertvalue %8, %6[2] : !llvm.array<100000 x ptr<i8>>
%10 = llvm.mlir.addressof @om_4 : !llvm.ptr<array<1 x i8>>
%11 = llvm.getelementptr %10[0, 0] : (!llvm.ptr<array<1 x i8>>) -> !llvm.ptr<i8>
%12 = llvm.insertvalue %11, %9[3] : !llvm.array<100000 x ptr<i8>>
... (ignore the remaining part)
}
```
where `@om_1`, `@om_2`, ... are string global constants.
Each time an operation is converted to LLVM, a new constant is created.
When it comes to `llvm.insertvalue`, a new constant array of 100000 elements is created and the old constant array (input) is not destroyed.
This causes memory explosion. We observed that, on a system with 128 GB memory, the translation of 100000 elements got killed due to using up all the memory.
On a system with 64 GB, 65536 elements was enough to cause the translation killed.
This patch fixes the issue by checking generated constants and destroyed them if there is no use.
By the fix, the translation of 100000 elements only takes about 1.6 GB memory, and finishes without any error.
Reviewed By: ftynse, kiranchandramohan
Differential Revision: https://reviews.llvm.org/D148487
Sergei Barannikov [Mon, 15 May 2023 18:53:28 +0000 (21:53 +0300)]
[clang] Convert several OpenMP tests to opaque pointers
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D150608
Michael Buch [Mon, 15 May 2023 16:37:46 +0000 (17:37 +0100)]
[lldb][DWARFASTParserClang] Don't create unnamed bitfields to account for vtable pointer
**Summary**
When filling out the LayoutInfo for a structure with the offsets
from DWARF, LLDB fills gaps in the layout by creating unnamed
bitfields and adding them to the AST. If we don't do this correctly
and our layout has overlapping fields, we will hat an assertion
in `clang::CGRecordLowering::lower()`. Specifically, if we have
a derived class with a VTable and a bitfield immediately following
the vtable pointer, we create a layout with overlapping fields.
This is an oversight in some of the previous cleanups done around this
area.
In `D76808`, we prevented LLDB from creating unnamed bitfields if there
was a gap between the last field of a base class and the start of a bitfield
in the derived class.
In `D112697`, we started accounting for the vtable pointer. The intention
there was to make sure the offset bookkeeping accounted for the
existence of a vtable pointer (but we didn't actually want to create
any AST nodes for it). Now that `last_field_info.bit_size` was being
set even for artifical fields, the previous fix `D76808` broke
specifically for cases where the bitfield was the first member of a
derived class with a vtable (this scenario wasn't tested so we didn't
notice it). I.e., we started creating redundant unnamed bitfields for
where the vtable pointer usually sits. This confused the lowering logic
in clang.
This patch adds a condition to `ShouldCreateUnnamedBitfield` which
checks whether the first field in the derived class is a vtable ptr.
**Testing**
* Added API test case
Differential Revision: https://reviews.llvm.org/D150591
Michael Buch [Mon, 15 May 2023 14:31:14 +0000 (15:31 +0100)]
[lldb][DWARFASTParserClang][NFC] Extract condition for unnamed bitfield creation into helper function
This patch adds a new private helper
`DWARFASTParserClang::ShouldCreateUnnamedBitfield` which
`ParseSingleMember` whether we should fill the current gap
in a structure layout with unnamed bitfields.
Extracting this logic will allow us to add additional
conditions in upcoming patches without jeoperdizing readability
of `ParseSingleMember`.
We also store some of the boolean conditions in local variables
to make the intent more obvious.
Differential Revision: https://reviews.llvm.org/D150590
Michael Buch [Mon, 15 May 2023 14:04:07 +0000 (15:04 +0100)]
[lldb][DWARFASTParserClang][NFC] Simplify unnamed bitfield condition
Minor cleanup of redundant variable initialization and
if-condition. These are leftovers/oversights from previous
cleanup in this area:
* https://reviews.llvm.org/D72953
* https://reviews.llvm.org/D76808
Differential Revision: https://reviews.llvm.org/D150589
Andrzej Warzynski [Tue, 16 May 2023 09:51:45 +0000 (10:51 +0100)]
[mlir][nfc] Remove unnecessary `-split-input-file`
Nikita Popov [Tue, 16 May 2023 09:50:29 +0000 (11:50 +0200)]
[InstSimplify] Clarify simplifyWithOpReplaced() refinement requirement (NFC)
In order to justify some of the special cases we have, we need to
assume that Op/RepOp are non-poison. For the places where this
function is used, if one of these is poison, then the select result
is poison anyway.
Nikita Popov [Tue, 16 May 2023 09:33:21 +0000 (11:33 +0200)]
[SCEV] Regenerate test checks (NFC)
Nikita Popov [Tue, 16 May 2023 09:23:40 +0000 (11:23 +0200)]
[KnownBits] Handle shifts over wide types
Do not assert if the bit width is larger than 64 bits. This case
is currently hidden from the IR layer by other checks, but gets
exposed with future changes.
Quentin Colombet [Tue, 16 May 2023 08:54:25 +0000 (10:54 +0200)]
[MemRefToLLVM][NFC] Use early exit for the getter of the buffer ptr
Address review comment from https://reviews.llvm.org/D148947
Théo Degioanni [Tue, 16 May 2023 08:35:00 +0000 (08:35 +0000)]
[mlir] [mem2reg] Adapt to be pattern-friendly.
This revision modifies the mem2reg interfaces and algorithm to be more
omfortable to use as a pattern. The motivation behind this is that
currently the pattern needs to be applied to the scope op of the region
in which allocators should be promoted. However, a more natural way to
apply the pattern would be to apply it on the allocator directly. This
is not only clearer but easier to parallelize.
This revision changes the mem2reg pattern to operate this way. This
required restraining the interfaces to only mutate IR using
RewriterBase, as the previously used escape hatch is not granular enough
to match on the region that is modified only. This has the unfortunate
cost of preventing batching allocator promotion and making the block
argument adding logic more complex. Because batching no longer made any
sense, I made the internal analyzer/promoter decoupling private again.
This also adds statistics to the mem2reg infrastructure.
Reviewed By: gysit
Differential Revision: https://reviews.llvm.org/D150432
Nikita Popov [Tue, 16 May 2023 08:29:15 +0000 (10:29 +0200)]
[AArch64] Regenerate test checks (NFC)
Jay Foad [Wed, 10 May 2023 15:50:33 +0000 (16:50 +0100)]
[KnownBits] Define and use intersectWith and unionWith
Define intersectWith and unionWith as two complementary ways of
combining KnownBits. The names are chosen for consistency with
ConstantRange.
Deprecate commonBits as a synonym for intersectWith.
Differential Revision: https://reviews.llvm.org/D150443
Jay Foad [Tue, 16 May 2023 08:19:43 +0000 (09:19 +0100)]
[KnownBits] Make use of KnownBits.isUnknown. NFC.
Alex Zinenko [Mon, 15 May 2023 17:07:53 +0000 (17:07 +0000)]
[mlir] update types in remaining Linalg TransformOps test
All ops now support explicit type specification, update types to use
`!transform.any_op` instead of `!pdl.operation` for consistency.
Depends On D144515
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D150592
Alex Zinenko [Tue, 21 Feb 2023 21:04:00 +0000 (21:04 +0000)]
[mlir] make structured transform ops use types
Types have been introduced a while ago and provide for better
readability and transform-time verification. Use them in the ops from
the structured transform dialect extension.
In most cases, the types are appended as trailing functional types or a
derived format of the functional type that allows for an empty right
hand size without the annoying `-> ()` syntax (similarly to `func.func`
declaration that may omit the arrow). When handles are used inside mixed
static/dynamic lists, such as tile sizes, types of those handles follow
them immediately as in `sizes [%0 : !transform.any_value, 42]`. This
allows for better readability than matching the trailing type.
Update code to remove hardcoded PDL dependencies and expunge PDL from
structured transform op code.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D144515
Jay Foad [Mon, 15 May 2023 13:25:39 +0000 (14:25 +0100)]
[AMDGPU] Add implicit uses to AGPR copy MIR tests
Some tests were using liveins or IMPLICIT_DEFs to add fake live
registers, but that only works if you track liveness forwards. Add some
implicit uses too, so that it also works if you track liveness
backwards.
Some of these tests were using the regmask amdgpu_allvgprs but that is a
clobber not a use.
Differential Revision: https://reviews.llvm.org/D150570
Jay Foad [Mon, 15 May 2023 12:46:16 +0000 (13:46 +0100)]
[RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt
RegScavenger::backward is preferred because it does not rely on accurate
kill flags.
Differential Revision: https://reviews.llvm.org/D150562
Jonas Paulsson [Fri, 12 May 2023 13:12:46 +0000 (15:12 +0200)]
[MachineSink] Don't reject sinking because of dead def in isProfitableToSinkTo().
An instruction should be sunk (if otherwise legal and profitable) regardless
of if it has a dead def of a physreg or not. Physreg defs are checked in other
places and sinking is only done with dead defs of regs that are not live into
the target MBB.
Differential Revision: https://reviews.llvm.org/D150447
Reviewed By: sebastian-ne, arsenm
Jonas Paulsson [Tue, 16 May 2023 07:27:30 +0000 (09:27 +0200)]
Precommit test for D150447.
Gaëtan Bossu [Tue, 16 May 2023 07:22:22 +0000 (09:22 +0200)]
FastRegAlloc: Fix implicit operands not rewritten
This patch fixes a potential crash due to RegAllocFast not rewriting virtual
registers. This essentially happens because of a call to
MachineInstr::addRegisterKilled() in the process of allocating a "killed" vreg.
The former can eventually delete implicit operands without RegAllocFast
noticing, leading to some operands being "skipped" and not rewritten to use
physical registers.
Note that I noticed this crash when working on a solution for tying a register
with one/multiple of its sub-registers within an instruction. (See problem
description here:
https://discourse.llvm.org/t/pass-to-tie-an-output-operand-to-a-subregister-of-an-input-operand/67184).
Aside from this fix, I believe there could be further improvements to the
RegAllocFast when it comes to instructions with multiple uses of a same virtual
register. You can see it in the added test where the implicit uses have been
re-written in a somewhat surprising way because of phase ordering. Ultimately,
when allocating vregs for an instruction, I believe we should iterate on the
vregs it uses (and then process all the operands that use this vregs), instead
of directly iterating on operands and somewhat assuming each operand uses a
different vreg. This would in the end be quite close to what
greedy+virtregrewriter does. If that makes sense, I would probably spin off
another patch (after I get more familiar with RegAllocFast).
Differential Revision: https://reviews.llvm.org/D145169
Andrzej Warzynski [Fri, 12 May 2023 16:35:53 +0000 (17:35 +0100)]
[mlir][linalg] Add a test for linalg.matmul --> vector.outerproduct
Representing matmuls as a sum of outer products is central to various
matrix extensions (e.g. Arm's SME). This test demonstrates how to use
Linalg's vectoriser and Vector's lowerings to represent `linalg.matmul`
as a chain of `vector.outerproduct` Ops.
Differential Revision: https://reviews.llvm.org/D150457
Nikita Popov [Mon, 15 May 2023 15:38:49 +0000 (17:38 +0200)]
[KnownBits] Make shl/lshr/ashr implementations optimal
The implementations for shifts were suboptimal in the case where
the max shift amount was >= bitwidth. In that case we should still
use the usual code clamped to BitWidth-1 rather than just giving up
entirely.
Additionally, there was an implementation bug where the known zero
bits for the individual shift amounts were not set in the shl/lshr
implementations. I think after these changes, we'll be able to drop
some of the code in ValueTracking which *also* evaluates all possible
shift amounts and has been papering over this issue.
For the "all poison" case I've opted to return an unknown value for
now. It would be better to return zero, but this has fairly
substantial test fallout, so I figured it's best to not mix it into
this change. (The "correct" return value would be a conflict, but
given that a lot of our APIs assert conflict-freedom, that's probably
not the best idea to actually return.)
Differential Revision: https://reviews.llvm.org/D150587
Martin Storsjö [Wed, 3 May 2023 06:57:22 +0000 (09:57 +0300)]
[OpenMP] Use CMAKE_CXX_STANDARD for setting the C++ version
Previously, we tried to check whether the -std=c++17 option was
supported and manually add the flag. That doesn't work for compilers
that do support C++17 but use a different option syntax, like
clang-cl.
OpenMP itself probably doesn't specifically require C++17, therefore
CXX_STANDARD_REQUIRED is left off, but in some cases, we may
have code that only works in C++17 mode.
In particular,
46262cab24312c71717ca70a9d0700481aa59152 made a
refactoring that works when built with Clang in C++17 mode, but not
in C++14 mode. MSVC accepts the construct in both language modes.
For libomptarget, we've had specific checks that require C++17
(or the -std=c++17 option) to be supported. It's doubtful that
libomptarget has got any code which more specifically requires C++17;
this seems to be a remnant from when libomptarget was added
originally in
2467df6e4f04e3d0e8e78d662473ba1b87c0a885 / D14031.
At that point, the rest of OpenMP didn't require C++11, while
libomptarget did require it. Now, it's unlikely that anyone attempts
building it with a toolchain that doesn't support C++11.
At this point, we could also probably just set CXX_STANDARD_REQUIRED
to true, requiring C++17 as baseline for all the OpenMP libraries.
This fixes building OpenMP with clang-cl after
46262cab24312c71717ca70a9d0700481aa59152.
Differential Revision: https://reviews.llvm.org/D149726
Martin Storsjö [Fri, 5 May 2023 10:58:47 +0000 (10:58 +0000)]
Reapply [clang] [test] Narrow down MSVC specific behaviours from "any windows" to only MSVC/clang-cl
This fixes running tests with a toolchain that defaults to a MinGW
target.
After the previous attempt with this patch, this is now changed to
use !defined(__MINGW32__) instead of defined(_MSC_VER) to distinguish
between MSVC and MinGW mode; Clang doesn't define _MSC_VER when invoked
with "clang -cc1" as some of those tests do.
Differential Revision: https://reviews.llvm.org/D149997
Martin Storsjö [Fri, 5 May 2023 11:05:26 +0000 (11:05 +0000)]
Reapply [test] [llvm-config] Assume unix style lib names on mingw targets
Assume the MSVC style naming only for "windows-msvc" targets.
After the previous attempt, this was changed to use the host triple
instead of the target.
Differential Revision: https://reviews.llvm.org/D149998
Tobias Gysi [Tue, 16 May 2023 07:21:22 +0000 (07:21 +0000)]
[mlir] Add mlir translate flag to print errors only.
The revision adds a flag to mlir translate that suppresses
any non-error diagnostics. The flag is useful when importing
LLVM IR to LLVM dialect, which produces a lot of
warnings due to dropped metadata and debug intrinsics.
Reviewed By: Dinistro
Differential Revision: https://reviews.llvm.org/D150547
Balázs Kéri [Tue, 16 May 2023 07:05:44 +0000 (09:05 +0200)]
[clang][analyzer] Handle special value AT_FDCWD in affected standard functions
Some file and directory related functions have an integer file descriptor argument
that can be a valid file descriptor or a special value AT_FDCWD. This value is
relatively often used in open source projects and is usually defined as a negative
number, and the checker reports false warnings (a valid file descriptor is not
negative) if this fix is not included.
Reviewed By: steakhal
Differential Revision: https://reviews.llvm.org/D149160
Job Noorman [Tue, 16 May 2023 07:24:31 +0000 (09:24 +0200)]
[JITLink] Process null symbols
Some relocations (e.g., R_RISCV_ALIGN) don't have a target symbol and
use a null symbol as a placeholder. These symbols were not processed
before making it impossible to create edges for them.
This patch tries to detect these null symbols and create absolute
symbols for them. Note that technically, these null symbols are UND in
the ELF file, not ABS, so it might make more consistent to create a new
symbol type for this (local undefined or so). However, since these
symbols are only used as placeholders (i.e., their values are never
used), I don't think it's worth the effort of doing this.
Also note that in the binaries that I have inspected, this null symbol
always has index 0. Could it make sense to add that to the test to avoid
accidentally adding unnecessary symbols? The reason I didn't do this
yet, is that I couldn't find any references in the specs that actually
guarantee this.
Reviewed By: lhames
Differential Revision: https://reviews.llvm.org/D149541
Job Noorman [Tue, 16 May 2023 07:23:26 +0000 (09:23 +0200)]
[BOLT][Wrapper] Fix off-by-one in find_section upper limit
find_section used to match offsets equal to file_offset + size causing
offsets to sometimes be attributed to the wrong section.
Reviewed By: Amir
Differential Revision: https://reviews.llvm.org/D149047
esmeyi [Tue, 16 May 2023 07:02:00 +0000 (03:02 -0400)]
[XCOFF][DWARF] XCOFF64 should be able to select the dwarf format in intergrated-as mode.
Summary: DWARF32 is not supported for XCOFF64 under non-integrated-as mode on AIX, because system assembler will fill the debug section lengths according to DWARF64 format. While in intergrated-as mode, XCOFF64 should be able to select the DWARF format.
Reviewed By: shchenz
Differential Revision: https://reviews.llvm.org/D150181
Corentin Jabot [Tue, 16 May 2023 06:52:25 +0000 (08:52 +0200)]
[Clang][NFC] Present language version in descending publication date
Kadir Cetinkaya [Tue, 16 May 2023 06:41:56 +0000 (08:41 +0200)]
[clangd] Fix builds after
4ddae8b941398a6579d3
Wang, Xin10 [Tue, 16 May 2023 06:43:27 +0000 (02:43 -0400)]
Correct the sort logic in AsmMatcherEmmitter.cpp
The logic from line 633 to 640 is specific for ARM as the comments said, it will make all the targets will prefer to using instruction with more predicates when compiler do AsmMatching.
And for code from line 642 to 649, X86 want to use the order records written in source file to sort the instructions. So X86 could be affected by this logic. (These code could be arrived only by X86)
After change this, seems AVX instructions have not be affected but it exposed some other errors for instruction push and call.
CALLpcrel16 could not be used in 64 bit mode, we need add Predicate for it. And for push instruction, previously because pushi32 has predicates = [Not64bitmode], so it precede pushi16, which is incorrect here, we should get pushw here and it also align with gcc.
Reviewed By: skan
Differential Revision: https://reviews.llvm.org/D150436
Craig Topper [Tue, 16 May 2023 06:15:30 +0000 (23:15 -0700)]
[RISCV] Use mask agnostic policy for masked RISCVISD::VFMADD_VL patterns.
These aren't currently created from anything that has a passthru
operand. If we need to support this in the future, we should add
a policy operand to the ISD node definition.
Corentin Jabot [Wed, 26 Apr 2023 18:09:13 +0000 (20:09 +0200)]
[Clang] Fix parsing of `(auto(x))`.
Allow auto(x) to appear in a parenthesis
expression.
The pattern (auto( can appear as part of a declarator,
so the parser is modified to avoid the ambiguity,
in a way consistent with the proposed resolution to CWG1223.
Reviewed By: aaron.ballman, #clang-language-wg
Differential Revision: https://reviews.llvm.org/D149276
Muhammad Omair Javaid [Tue, 16 May 2023 06:09:53 +0000 (10:09 +0400)]
[LLDB] Fix typo in TestDataFormatterSynthVal.py
This is follow up to
039b28e14e6d to fix a typo to make sure skipped
part of test is only skipped for AArch64 Windows platform.
Timm Bäder [Thu, 11 May 2023 07:22:21 +0000 (09:22 +0200)]
[clang][NFC] Fix a doc comment mixup
These are regular comments, use double slashes.
Craig Topper [Tue, 16 May 2023 05:47:30 +0000 (22:47 -0700)]
[RISCV] Update RISCVISD::VFWMADD_VLL isel patterns to allow a mask that isn't all ones.
Fixes an isel crash after
6e6bed575777be7be55482090414e153ed6f7557.
Add more tests so we have coverage for this.
Christudasan Devadasan [Thu, 11 May 2023 16:13:18 +0000 (21:43 +0530)]
[AMDGPU] Add optional tied-op for wwm-register's epilog spill restore
The COPY inserted in the epilog block before return instruction as part
of ABI lowering, can get optimized during machine copy propagation if
the same register is used earlier in a wwm operation that demands the
prolog/epilog wwm-spill store/restore to preserve its inactive lanes.
With the spill restore in the epilog, the preceding COPY appears to be
dead during machine-cp. To avoid it, mark the same register as a tied-op
in the spill restore instruction to ensure a usage for the COPY.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D150381
Jonas Devlieghere [Tue, 16 May 2023 05:14:35 +0000 (22:14 -0700)]
[lldb] Fix lldb_assert -> lldbassert in docs
Update the documentation to reference lldbassert rather than
lldb_assert. The latter is the implementation, which shouldn't be used
directly. Instead, users should use lldbassert which is the macro that
expands to assert or lldb_assert depending on the build type.
Sameer Sahasrabuddhe [Tue, 16 May 2023 04:07:04 +0000 (09:37 +0530)]
[LLVM][Uniformity] Improve detection of uniform registers
The MachineUA now queries the target to determine if a given register holds a
uniform value. This is determined using the corresponding register bank if
available, or by a combination of the register class and value type. This
assumes that the target is optimizing for performance by choosing registers, and
the target is responsible for any mismatch with the inferred uniformity.
For example, on AMDGPU, an SGPR is now treated as uniform, except if the
register bank is VCC (i.e., the register holds a wave-wide vector of 1-bit
values) or equivalently if it has a value type of s1.
- This does not always work with inline asm, where the register bank or the
value type might not be present. We assume that the SGPR is uniform, because
it is not expected to be s1 in the vast majority of cases.
- The pseudo branch instruction SI_LOOP is now hard-coded to be always
divergent, although its condition is an SGPR.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D150438
Joshua Cao [Tue, 16 May 2023 03:28:40 +0000 (20:28 -0700)]
[SimpleLoopUnswitch] Skip trivial select conds for selects
Fixes https://github.com/llvm/llvm-project/issues/62715
If a select's condition is a trivial select:
```
%s = select %cond, i1 true, i1 false
```
Unswitch on %cond, rather than %s. This fixes crashes where there is a
disparity in finding candidates and and the transformation logic.