Marcin Kościelnicki [Fri, 3 Jun 2016 14:39:15 +0000 (16:39 +0200)]
bfd/s390: Misc minor fixes.
The only non-comment fix here is in the code writing out the 3 fixed
.got.plt entries - it mistakenly put a 64-bit 0 at offsets 8 and 12
instead of 8 and 16.
bfd/ChangeLog:
* elf32-s390.c (elf_s390_finish_dynamic_symbol): Fix comment.
* elf64-s390.c (elf_s390x_plt_entry): Fix comment.
(elf_s390_relocate_section): Fix comment.
(elf_s390_finish_dynamic_sections): Fix initialization of fixed
.got.plt entries.
Simon Marchi [Tue, 7 Jun 2016 14:02:42 +0000 (10:02 -0400)]
mi/mi-interp.c: Add missing braces
gdb/ChangeLog:
* mi/mi-interp.c (mi_record_changed): Add missing braces.
Maciej W. Rozycki [Fri, 27 May 2016 16:53:01 +0000 (17:53 +0100)]
ld/testsuite/ld-elf/init-fini-arrays.d: Remove `ft32-*-*' xfail
Revert the addition of `ft32-*-*' to this test case made with commit
d1f70bdcab6c ("Fix lots of linker testsuite failures for the FT32
target.") as this case scores an XPASS now.
ld/
* testsuite/ld-elf/init-fini-arrays.d: Remove `ft32-*-*' xfail.
Andreas Krebbel [Tue, 7 Jun 2016 14:45:15 +0000 (16:45 +0200)]
Fix PLT first entry GOT operand calculation.
Embedding the .plt section in another revealed a bug in the way the
larl operand of the first magic plt entry is being calculated. Fixed
with the attached patch.
bfd/ChangeLog:
* elf64-s390.c (elf_s390_finish_dynamic_sections): Subtract plt
section offset when calculation the larl operand in the first PLT
entry.
ld/ChangeLog:
* testsuite/ld-s390/pltoffset-1.dd: New test.
* testsuite/ld-s390/pltoffset-1.ld: New test.
* testsuite/ld-s390/pltoffset-1.s: New test.
* testsuite/ld-s390/s390.exp: Run new test.
Alan Modra [Tue, 7 Jun 2016 12:34:38 +0000 (22:04 +0930)]
PowerPC VLE
VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE. For
example
{"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe. Also, we don't check
user assembly against the processor type as well as we could.
Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31. Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.
This patch fixes those problems in the opcode table, and removes
PPCNONE. I find a plain 0 distracts less from other values.
In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects. It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.
include/
* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
PPC_APUINFO_VLE: Define.
opcodes/
* ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
cpu for "vle" to e500.
* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
(PPCNONE): Delete, substitute throughout.
(powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
except for major opcode 4 and 31.
(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
to match other 32-bit archs.
* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
(ppc_elf_object_p): Call it.
(ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix
overlong line.
(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
_bfd_elf_ppc_at_tprel_transform): Move to..
* elf-bfd.h: ..here.
(_bfd_elf_ppc_set_arch): Declare.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
by vle_opcodes, and that vle flag doesn't enable opcodes. Don't
add vle_opcodes twice.
(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
* testsuite/ld-powerpc/apuinfo-vle2.s: New.
* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
Bernhard Heckel [Tue, 7 Jun 2016 11:36:05 +0000 (13:36 +0200)]
Frame static link: Handle null pointer.
2016-06-07 Bernhard Heckel <bernhard.heckel@intel.com>
gdb/Changelog:
* findvar.c (follow_static_link): Check for valid pointer.
Matthew Wahab [Tue, 7 Jun 2016 08:56:42 +0000 (09:56 +0100)]
[ARM] Add command line option for RAS extension.
This patch adds the architecture extension "+ras" to enable RAS
support. It is enabled by default for -march=armv8.2-a and available but
disabled by default for armv8-a and armv8.1-a.
gas/
* config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras.
(arm_ext_ras): Renamed from arm_ext_v8_2.
(insns): Update for arm_ext_v8_2 renaming.
(arm_extensions): Add "ras".
* doc/c-arm.texi (ARM Options): Add an entry for "ras".
* testsuite/gas/arm/armv8-a+ras.d: New.
* testsuite/gas/arm/armv8_2-a.d: Add explicit command line
options.
include/
* opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding
entries.
(ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
opcodes/
* arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
ARM_EXT_RAS in relevant entries.
GDB Administrator [Tue, 7 Jun 2016 00:00:16 +0000 (00:00 +0000)]
Automatic date update in version.in
Simon Marchi [Mon, 30 May 2016 21:29:39 +0000 (17:29 -0400)]
Add method/format information to =record-started
Eclipse CDT now supports enabling execution recording using two methods
(full and btrace) and both formats for btrace (bts and pt). In the
event that recording is enabled behind the back of the GUI (by the user
on the command line, or a script), we need to know which method/format
are being used, so it can be correctly reflected in the interface. This
patch adds this information to the =record-started async record.
Before:
=record-started,thread-group="i1"
After:
=record-started,thread-group="i1",method="btrace",format="bts"
=record-started,thread-group="i1",method="btrace",format="pt"
=record-started,thread-group="i1",method="full"
The "format" field is only present when the current method supports
multiple formats (only the btrace method as of now).
gdb/ChangeLog:
* NEWS: Mention the new fields in =record-started.
* common/btrace-common.h (btrace_format_short_string): New function
declaration.
* common/btrace-common.c (btrace_format_short_string): New
function.
* mi/mi-interp.c (mi_record_changed): Output method and format
fields in the =record-started record.
* record-btrace.c (record_btrace_open): Adapt record_changed
notification.
* record-full.c (record_full_open): Likewise.
* record.c (cmd_record_stop): Likewise.
gdb/doc/ChangeLog:
* gdb.texinfo (GDB/MI Async Records): Document method and
format fields in =record-started.
* observer.texi (record_changed): Add method and format
parameters.
gdb/testsuite/ChangeLog:
* gdb.mi/mi-record-changed.exp: Adjust =record-started output
matching.
H.J. Lu [Mon, 6 Jun 2016 18:06:55 +0000 (11:06 -0700)]
Support x86-64 TLS code sequences without PLT
We can generate x86-64 TLS code sequences for general and local dynamic
models without PLT, which uses indirect call via GOT:
call *__tls_get_addr@GOTPCREL(%rip)
instead of direct call:
call __tls_get_addr[@PLT]
Since direct call is 4-byte long and indirect call, is 5-byte long, the
extra one byte must be handled properly.
For general dynamic model, one 0x66 prefix before call instruction is
removed to make room for indirect call. For local dynamic model, we
simply use 5-byte indirect call.
TLS linker optimization is updated to recognize new instruction patterns.
For local dynamic model to local exec model transition, we generate
4 0x66 prefixes, instead of 3, before mov instruction in 64-bit and
generate a 5-byte nop, instead of 4-byte, before mov instruction in
32-bit. Since linker may convert
call *__tls_get_addr@GOTPCREL(%rip)
to
addr32 call __tls_get_addr
when producing static executable, both patterns are recognized.
bfd/
* elf64-x86-64.c (elf_x86_64_link_hash_entry): Add tls_get_addr.
(elf_x86_64_link_hash_newfunc): Initialize tls_get_addr to 2.
(elf_x86_64_check_tls_transition): Check indirect call and
direct call with the addr32 prefix for general and local dynamic
models. Set the tls_get_addr feild.
(elf_x86_64_convert_load_reloc): Always use addr32 prefix for
indirect __tls_get_addr call via GOT.
(elf_x86_64_relocate_section): Handle GD->LE, GD->IE and LD->LE
transitions with indirect call and direct call with the addr32
prefix.
ld/
* testsuite/ld-x86-64/pass.out: New file.
* testsuite/ld-x86-64/tls-def1.c: Likewise.
* testsuite/ld-x86-64/tls-gd1.S: Likewise.
* testsuite/ld-x86-64/tls-ld1.S: Likewise.
* testsuite/ld-x86-64/tls-main1.c: Likewise.
* testsuite/ld-x86-64/tls.exp: Likewise.
* testsuite/ld-x86-64/tlsbin2-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlsbin2.dd: Likewise.
* testsuite/ld-x86-64/tlsbin2.rd: Likewise.
* testsuite/ld-x86-64/tlsbin2.sd: Likewise.
* testsuite/ld-x86-64/tlsbin2.td: Likewise.
* testsuite/ld-x86-64/tlsbinpic2.s: Likewise.
* testsuite/ld-x86-64/tlsgd10.dd: Likewise.
* testsuite/ld-x86-64/tlsgd10.s: Likewise.
* testsuite/ld-x86-64/tlsgd11.dd: Likewise.
* testsuite/ld-x86-64/tlsgd11.s: Likewise.
* testsuite/ld-x86-64/tlsgd12.d: Likewise.
* testsuite/ld-x86-64/tlsgd12.s: Likewise.
* testsuite/ld-x86-64/tlsgd13.d: Likewise.
* testsuite/ld-x86-64/tlsgd13.s: Likewise.
* testsuite/ld-x86-64/tlsgd14.dd: Likewise.
* testsuite/ld-x86-64/tlsgd14.s: Likewise.
* testsuite/ld-x86-64/tlsgd5c.s: Likewise.
* testsuite/ld-x86-64/tlsgd6c.s: Likewise.
* testsuite/ld-x86-64/tlsgd9.dd: Likewise.
* testsuite/ld-x86-64/tlsgd9.s: Likewise.
* testsuite/ld-x86-64/tlsld4.dd: Likewise.
* testsuite/ld-x86-64/tlsld4.s: Likewise.
* testsuite/ld-x86-64/tlsld5.dd: Likewise.
* testsuite/ld-x86-64/tlsld5.s: Likewise.
* testsuite/ld-x86-64/tlsld6.dd: Likewise.
* testsuite/ld-x86-64/tlsld6.s: Likewise.
* testsuite/ld-x86-64/tlspic2-nacl.rd: Likewise.
* testsuite/ld-x86-64/tlspic2.dd: Likewise.
* testsuite/ld-x86-64/tlspic2.rd: Likewise.
* testsuite/ld-x86-64/tlspic2.sd: Likewise.
* testsuite/ld-x86-64/tlspic2.td: Likewise.
* testsuite/ld-x86-64/tlspic3.s: Likewise.
* testsuite/ld-x86-64/tlspie2.s: Likewise.
* testsuite/ld-x86-64/tlspie2a.d: Likewise.
* testsuite/ld-x86-64/tlspie2b.d: Likewise.
* testsuite/ld-x86-64/tlspie2c.d: Likewise.
* testsuite/ld-x86-64/tlsgd5.dd: Updated.
* testsuite/ld-x86-64/tlsgd6.dd: Likewise.
* testsuite/ld-x86-64/x86-64.exp: Run libtlspic2.so, tlsbin2,
tlsgd5b, tlsgd6b, tlsld4, tlsld5, tlsld6, tlsgd9, tlsgd10,
tlsgd11, tlsgd14, tlsgd12, tlsgd13, tlspie2a, tlspie2b and
tlspie2c.
Christian Groessler [Mon, 6 Jun 2016 07:47:25 +0000 (09:47 +0200)]
2016-06-06 Christian Groessler <chris@groessler.org>
* ChangeLog: Fix entry from 2016-06-04.
Trevor Saunders [Tue, 24 May 2016 12:59:35 +0000 (08:59 -0400)]
fixup another old style function definition
gas/ChangeLog:
2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* itbl-parse.y (yyerror): Use modern argument declaration style.
Trevor Saunders [Sun, 29 May 2016 02:31:07 +0000 (22:31 -0400)]
sh{,64}: make arg type enum
The values are always members of the enum, except the two places -1 is assigned
only to playcate -Wuninitialized because gcc isn't or at least didn't used to
be smart enough to figure out its only used if it was set.
gas/ChangeLog:
2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-sh.c (parse_reg): Change type of mode argument to
sh_arg_type.
(get_operand): Adjust.
(insert): Change type of how to bfd_reloc_code_real_type.
(insert4): Likewise.
* config/tc-sh64.c (shmedia_get_operand): Adjust.
(shmedia_parse_reg): Change type of mode to shmedia_arg_type.
GDB Administrator [Mon, 6 Jun 2016 00:00:15 +0000 (00:00 +0000)]
Automatic date update in version.in
Trevor Saunders [Sat, 28 May 2016 21:57:44 +0000 (17:57 -0400)]
nds32: constify ptr_arg
it points to the result of strchr on a const char *, so it aliases
something that is const. Further its only passed to a function that expects a
const char *, so there's no reason for it to not be const.
gas/ChangeLog:
2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nds32.c (nds32_parse_option): Make the type of ptr_arg
const char *.
GDB Administrator [Sun, 5 Jun 2016 00:00:19 +0000 (00:00 +0000)]
Automatic date update in version.in
Christian Groessler [Sat, 4 Jun 2016 20:39:46 +0000 (22:39 +0200)]
ld/testsuite/ld-z8k/test-ld.sh: Remove. Checked in by mistake.
Christian Groessler [Sat, 4 Jun 2016 20:15:52 +0000 (22:15 +0200)]
Add z8k ld testsuite and fix range check in coff-z8k.c
bfd/
* coff-z8k.c (extra_case): Fix range check for R_JR relocation.
ld/
* ld/testsuite/ld-z8k/0filler.s: New file.
* ld/testsuite/ld-z8k/branch-target.s: New file.
* ld/testsuite/ld-z8k/branch-target2.s: New file.
* ld/testsuite/ld-z8k/calr-back-8001.d: New file.
* ld/testsuite/ld-z8k/calr-back-8002.d: New file.
* ld/testsuite/ld-z8k/calr-back-fail-8001.d: New file.
* ld/testsuite/ld-z8k/calr-back-fail-8002.d: New file.
* ld/testsuite/ld-z8k/calr-forw-8001.d: New file.
* ld/testsuite/ld-z8k/calr-forw-8002.d: New file.
* ld/testsuite/ld-z8k/calr-forw-fail-8001.d: New file.
* ld/testsuite/ld-z8k/calr-forw-fail-8002.d: New file.
* ld/testsuite/ld-z8k/calr-opcode.s: New file.
* ld/testsuite/ld-z8k/dbjnz-forw-8001.d: New file.
* ld/testsuite/ld-z8k/dbjnz-forw-8002.d: New file.
* ld/testsuite/ld-z8k/dbjnz-forw-fail-8001.d: New file.
* ld/testsuite/ld-z8k/dbjnz-forw-fail-8002.d: New file.
* ld/testsuite/ld-z8k/dbjnz-opcode.s: New file.
* ld/testsuite/ld-z8k/djnz-back-8001.d: New file.
* ld/testsuite/ld-z8k/djnz-back-8002.d: New file.
* ld/testsuite/ld-z8k/djnz-back-fail-8001.d: New file.
* ld/testsuite/ld-z8k/djnz-back-fail-8002.d: New file.
* ld/testsuite/ld-z8k/djnz-forw-8001.d: New file.
* ld/testsuite/ld-z8k/djnz-forw-8002.d: New file.
* ld/testsuite/ld-z8k/djnz-forw-fail-8001.d: New file.
* ld/testsuite/ld-z8k/djnz-forw-fail-8002.d: New file.
* ld/testsuite/ld-z8k/djnz-opcode.s: New file.
* ld/testsuite/ld-z8k/filler.s: New file.
* ld/testsuite/ld-z8k/jr-back-8001.d: New file.
* ld/testsuite/ld-z8k/jr-back-8002.d: New file.
* ld/testsuite/ld-z8k/jr-back-fail-8001.d: New file.
* ld/testsuite/ld-z8k/jr-back-fail-8002.d: New file.
* ld/testsuite/ld-z8k/jr-forw-8001.d: New file.
* ld/testsuite/ld-z8k/jr-forw-8002.d: New file.
* ld/testsuite/ld-z8k/jr-forw-fail-8001.d: New file.
* ld/testsuite/ld-z8k/jr-forw-fail-8002.d: New file.
* ld/testsuite/ld-z8k/jr-opcode.s: New file.
* ld/testsuite/ld-z8k/ldr-back-8001.d: New file.
* ld/testsuite/ld-z8k/ldr-back-8002.d: New file.
* ld/testsuite/ld-z8k/ldr-back-fail-8001.d: New file.
* ld/testsuite/ld-z8k/ldr-back-fail-8002.d: New file.
* ld/testsuite/ld-z8k/ldr-forw-8001.d: New file.
* ld/testsuite/ld-z8k/ldr-forw-8002.d: New file.
* ld/testsuite/ld-z8k/ldr-forw-fail-8001.d: New file.
* ld/testsuite/ld-z8k/ldr-forw-fail-8002.d: New file.
* ld/testsuite/ld-z8k/ldr-opcode.s: New file.
* ld/testsuite/ld-z8k/ldrb-forw-8001.d: New file.
* ld/testsuite/ld-z8k/ldrb-forw-8002.d: New file.
* ld/testsuite/ld-z8k/ldrb-forw-fail-8001.d: New file.
* ld/testsuite/ld-z8k/ldrb-forw-fail-8002.d: New file.
* ld/testsuite/ld-z8k/ldrb-opcode.s: New file.
* ld/testsuite/ld-z8k/ldrb-opcode2.s: New file.
* ld/testsuite/ld-z8k/other-file.s: New file.
* ld/testsuite/ld-z8k/reloc.dd: New file.
* ld/testsuite/ld-z8k/reloc.ld: New file.
* ld/testsuite/ld-z8k/relocseg.dd: New file.
* ld/testsuite/ld-z8k/relocseg.ld: New file.
* ld/testsuite/ld-z8k/relocseg1.dd: New file.
* ld/testsuite/ld-z8k/test-ld.sh: New file.
* ld/testsuite/ld-z8k/this-file.s: New file.
* ld/testsuite/ld-z8k/z8k.exp: New file.
GDB Administrator [Sat, 4 Jun 2016 00:00:18 +0000 (00:00 +0000)]
Automatic date update in version.in
Peter Bergner [Fri, 3 Jun 2016 23:38:02 +0000 (18:38 -0500)]
Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.
opcodes/
PR binutils/20196
* ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
opcodes for E6500.
gas/
PR binutils/20196
* gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx,
stbcx., sthcx., stwcx., stdcx.>: Add tests.
* gas/testsuite/gas/ppc/e6500.d: Likewise.
* gas/testsuite/gas/ppc/power8.s: Likewise.
* gas/testsuite/gas/ppc/power8.d: Likewise.
* gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx.,
stdcx.>: Add tests.
* gas/testsuite/gas/ppc/power4.d: Likewise.
H.J. Lu [Fri, 3 Jun 2016 22:55:29 +0000 (15:55 -0700)]
Handle indirect branches for AMD64 and Intel64
AMD64 spec and Intel64 spec differ in indirect branches in 64-bit mode.
AMD64 supports indirect branches with 16-bit address via the data size
prefix while the data size prefix is ignored by Intel64.
gas/
PR binutis/18386
* testsuite/gas/i386/i386.exp: Run x86-64-branch-4.
* testsuite/gas/i386/x86-64-branch.d: Updated.
* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
* testsuite/gas/i386/x86-64-branch-4.l: New file.
* testsuite/gas/i386/x86-64-branch-4.s: Likewise.
opcodes/
PR binutis/18386
* i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
(indir_v_mode): New.
Add comments for '&'.
(reg_table): Replace "{T|}" with "{&|}" on call and jmp.
(putop): Handle '&'.
(intel_operand_size): Handle indir_v_mode.
(OP_E_register): Likewise.
* i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
64-bit indirect call/jmp for AMD64.
* i386-tbl.h: Regenerated
Kyrylo Tkachov [Fri, 3 Jun 2016 15:59:24 +0000 (16:59 +0100)]
[AArch64][gas] Add support for Cortex-A73
* config/tc-aarch64.c (aarch64_cpus): Add cortex-a73 entry.
* doc/c-aarch64.texi (-mcpu): Document cortex-a73 value.
Kyrylo Tkachov [Fri, 3 Jun 2016 15:58:21 +0000 (16:58 +0100)]
[ARM][gas] Add support for Cortex-A73
* config/tc-arm.c (arm_cpus): Add cortex-a73 entry.
* doc/c-arm.texi (-mcpu=): Document cortex-a73 value.
Jon Turney [Thu, 2 Jun 2016 13:34:10 +0000 (13:34 +0000)]
Fix C++ build for Cygwin
gdb/ChangeLog:
2016-06-02 Jon Turney <jon.turney@dronecode.org.uk>
* windows-nat.c (handle_output_debug_string): Return type of
gdb_signal_from_host() is gdb_signal, not an int.
(windows_get_exec_module_filename): Add pointer casts for C++.
gdb/gdbserver/ChangeLog:
2016-06-02 Jon Turney <jon.turney@dronecode.org.uk>
* win32-low.c (win32_create_inferior): Add pointer casts for C++.
H.J. Lu [Fri, 3 Jun 2016 11:10:11 +0000 (04:10 -0700)]
Update x86 linker tests for --disable-x86-relax-relocations
Pass -mrelax-relocations=yes to x86 linker tests, which require relax
relocations, to support --disable-x86-relax-relocations.
* testsuite/ld-i386/i386.exp: Assemble gotpc1.o and pr19319b.o
with -mrelax-relocations=yes.
* testsuite/ld-i386/lea1a.d (as): Add -mrelax-relocations=yes.
* testsuite/ld-i386/lea1b.d (as): Likewise.
* testsuite/ld-i386/lea1d.d (as): Likewise.
* testsuite/ld-i386/lea1e.d (as): Likewise.
* testsuite/ld-i386/lea1f.d (as): Likewise.
* testsuite/ld-i386/load7.d (as): Likewise.
* testsuite/ld-i386/mov1b.d (as): Likewise.
* testsuite/ld-i386/pr19175.d (as): Likewise.
* testsuite/ld-ifunc/ifunc-13-i386.d (as): Likewise.
* testsuite/ld-ifunc/ifunc-21-i386.d (as): Likewise.
* testsuite/ld-ifunc/ifunc-22-i386.d (as): Likewise.
* testsuite/ld-x86-64/x86-64.exp: Assemble gotpcrel1a.o,
gotpcrel1b.o and gotpcrel1c.o with -mrelax-relocations=yes.
GDB Administrator [Fri, 3 Jun 2016 00:00:18 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom Tromey [Sat, 19 Sep 2015 23:45:47 +0000 (17:45 -0600)]
Fix PR python/18984
This fixes PR python/18984.
The bug is that gdbpy_solib_name uses GDB_PY_LL_ARG, whereas it should
use GDB_PY_LLU_ARG to avoid overflow.
Built and tested on x86-64 Fedora 23.
2016-06-02 Tom Tromey <tom@tromey.com>
PR python/18984:
* python/python.c (gdbpy_solib_name): Use GDB_PY_LLU_ARG.
2016-06-02 Tom Tromey <tom@tromey.com>
PR python/18984:
* gdb.python/py-shared.exp: Add solib_name test.
Nick Clifton [Thu, 2 Jun 2016 16:17:03 +0000 (17:17 +0100)]
Add "arm_any" architecture type to allow -m option to various binutils to match any ARM architecture.
PR target/20088
* cpu-arm.c (processors): Add "arm_any" type to match any ARM
architecture.
(arch_info_struct): Likewise.
(architectures): Likewise.
Nick Clifton [Thu, 2 Jun 2016 15:32:45 +0000 (16:32 +0100)]
Also check that the group header's sh_info field is valid.
PR 20089
* objcopy.c (group_signature): Fail if the input symbol table has
not been loaded, or if the sh_info field of the group header is 0.
Nick Clifton [Thu, 2 Jun 2016 15:20:27 +0000 (16:20 +0100)]
Fix a seg-fault when stripping a corrupt binary.
PR 20089
* objcopy.c (group_signature): Fail if the input symbol table has
not been loaded.
Simon Marchi [Thu, 2 Jun 2016 14:05:59 +0000 (10:05 -0400)]
mi-memory-changed.exp: Fix filename passed to untested
gdb/testsuite/ChangeLog:
* gdb.mi/mi-memory-changed.exp: Fix filename passed to untested.
Vineet Gupta [Thu, 2 Jun 2016 14:03:47 +0000 (15:03 +0100)]
Allow ARC Linux targets that do not use uclibc.
bfd * config.bfd: Replace -uclibc with *.
gas * configure.tgt: Replace -uclibc with *.
ld * configure.tgt: Replace -uclibc with *.
H.J. Lu [Thu, 2 Jun 2016 13:50:45 +0000 (06:50 -0700)]
Replace data32 with data16 in comments
The 0x66 prefix is data16, not data32 in 64-bit.
* elf64-x86-64.c: Replace data32 with data16 in comments.
Andrew Burgess [Thu, 2 Jun 2016 13:03:23 +0000 (14:03 +0100)]
Add support for 48 and 64 bit ARC instructions.
gas * config/tc-arc.c (parse_opcode_flags): New function.
(find_opcode_match): Move flag parsing code out to new function.
Ignore operands marked IGNORE.
(build_fake_opcode_hash_entry): New function.
(find_special_case_long_opcode): New function.
(find_special_case): Lookup long opcodes.
* testsuite/gas/arc/nps400-7.d: New file.
* testsuite/gas/arc/nps400-7.s: New file.
include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
(struct arc_long_opcode): New structure.
(arc_long_opcodes): Declare.
(arc_num_long_opcodes): Declare.
opcodes * arc-dis.c (struct arc_operand_iterator): New structure.
(find_format_from_table): All the old content from find_format,
with some minor adjustments, and parameter renaming.
(find_format_long_instructions): New function.
(find_format): Rewritten.
(arc_insn_length): Add LSB parameter.
(extract_operand_value): New function.
(operand_iterator_next): New function.
(print_insn_arc): Use new functions to find opcode, and iterator
over operands.
* arc-opc.c (insert_nps_3bit_dst_short): New function.
(extract_nps_3bit_dst_short): New function.
(insert_nps_3bit_src2_short): New function.
(extract_nps_3bit_src2_short): New function.
(insert_nps_bitop1_size): New function.
(extract_nps_bitop1_size): New function.
(insert_nps_bitop2_size): New function.
(extract_nps_bitop2_size): New function.
(insert_nps_bitop_mod4_msb): New function.
(extract_nps_bitop_mod4_msb): New function.
(insert_nps_bitop_mod4_lsb): New function.
(extract_nps_bitop_mod4_lsb): New function.
(insert_nps_bitop_dst_pos3_pos4): New function.
(extract_nps_bitop_dst_pos3_pos4): New function.
(insert_nps_bitop_ins_ext): New function.
(extract_nps_bitop_ins_ext): New function.
(arc_operands): Add new operands.
(arc_long_opcodes): New global array.
(arc_num_long_opcodes): New global.
* arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
Nick Clifton [Thu, 2 Jun 2016 10:34:49 +0000 (11:34 +0100)]
Fix a bug displaying the interpretation of a CFA block that just contains DW_CFA_NOP instructions.
* dwarf.c (display_debug_frames): Do not display any
interpretation if the block consists solely of DW__CFA_NOPs.
Alan Modra [Mon, 30 May 2016 00:13:44 +0000 (09:43 +0930)]
Revert PR16467 change
This reverts the pr16467 change, which was incorrect due to faulty
analysis of the pr16467 testcase. The failure was not due to a
mismatch in symbol type (ifunc/non-ifunc) but due to a symbol loop
being set up.
See https://sourceware.org/ml/binutils/2016-06/msg00013.html for some
rambling on versioned symbols and ELF shared library symbol overriding
that explain this patch.
bfd/
PR ld/20159
PR ld/16467
* elflink.c (_bfd_elf_merge_symbol): Revert PR16467 change.
(_bfd_elf_add_default_symbol): Don't indirect to/from defined
symbol given a version by a script different to the version
of the symbol being added.
(elf_link_add_object_symbols): Use _bfd_elf_strtab_save and
_bfd_elf_strtab_restore. Don't fudge dynstr references.
* elf-strtab.c (_bfd_elf_strtab_restore_size): Delete.
(struct strtab_save): New.
(_bfd_elf_strtab_save, _bfd_elf_strtab_restore): New functions.
* elf-bfd.h (_bfd_elf_strtab_restore_size): Delete.
(_bfd_elf_strtab_save, _bfd_elf_strtab_restore): Declare.
Trevor Saunders [Sun, 29 May 2016 05:04:01 +0000 (01:04 -0400)]
ns32k: remove dupplicate definition of input_line_pointer
gas/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ns32k.c: Remove definition of input_line_pointer.
Trevor Saunders [Sun, 29 May 2016 08:29:22 +0000 (04:29 -0400)]
add more extern C
opcodes/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* nds32-asm.h: Add extern "C".
* sh-opc.h: Likewise.
bfd/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* elf32-hppa.h: Add extern "C".
* elf32-nds32.h: Likewise.
* elf32-tic6x.h: Likewise.
include/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* elf/mips.h: Likewise.
* elf/sh.h: Likewise.
* opcode/d10v.h: Likewise.
* opcode/d30v.h: Likewise.
* opcode/ia64.h: Likewise.
* opcode/mips.h: Likewise.
* opcode/ppc.h: Likewise.
* opcode/sparc.h: Likewise.
* opcode/tic6x.h: Likewise.
* opcode/v850.h: Likewise.
Trevor Saunders [Fri, 13 May 2016 06:51:41 +0000 (02:51 -0400)]
avr: replace sentinal with iteration from 0 to ARRAY_SIZE
This seems a little easier to understand than using a sentinal, and will
hopefully let the compiler optimize the loop better. It also has the effect
that we stop initializing a field of the sentinal that is an enum with zero.
gas/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-avr.c (avr_parse_cons_expression): Replace iteration to
sentinal with iteration to array size.
Trevor Saunders [Mon, 28 Mar 2016 09:42:02 +0000 (05:42 -0400)]
xtensa: typedef enums when defining them
I think this is the more typical way to do this. Its also slightly shorter and
less repeditive.
gas/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/xtensa-relax.h: Move typedefs of enums to the enums
definition.
Trevor Saunders [Sun, 29 May 2016 05:04:15 +0000 (01:04 -0400)]
ns32k: use XOBNEW in another spot
gas/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ns32k.c (bit_fix_new): Replace obstack-alloc with XOBNEW
macro.
GDB Administrator [Thu, 2 Jun 2016 00:00:19 +0000 (00:00 +0000)]
Automatic date update in version.in
Nick Clifton [Wed, 1 Jun 2016 15:51:55 +0000 (16:51 +0100)]
Add new Serbian translation for the bfd library.
* po/sr.po: New Serbian translation.
* configure.ac (ALL_LINGUAS): Add sr.
* configure: Regenerate.
Pedro Alves [Wed, 1 Jun 2016 15:34:49 +0000 (16:34 +0100)]
gdb/remote-fileio.c: Eliminate custom SIGINT signal handler
... and fix Ctrl-C races.
The current remote-fileio.c SIGINT/EINTR code can lose Ctrl-C --
there's a period where SIG_IGN is installed as signal handler, for
example.
Since:
- remote.c no longer installs a custom SIGINT handler;
- The current remote-fileio.c SIGINT handler is basically the same as
the default SIGINT handler (event-top.c:handle_sigint), in
principle, except that instead of setting the quit flag, it sets a
separate flag.
I think we should be able to completely remove the remote-fileio.c
SIGINT handler, and centralize on the quit flag, thus fixing the
Ctrl-C race.
gdb/ChangeLog:
yyyy-mm-dd Pedro Alves <palves@redhat.com>
* remote-fileio.c (remote_fio_ctrl_c_flag, remote_fio_sa)
(remote_fio_osa)
(remote_fio_ofunc, remote_fileio_sig_init, remote_fileio_sig_set)
(remote_fileio_sig_exit, remote_fileio_ctrl_c_signal_handler):
Delete.
(remote_fileio_o_quit_handler): New global.
(remote_fileio_quit_handler): New function.
(remote_fileio_reply): Check the quit flag instead of the custom
'remote_fio_ctrl_c_flag' flag. Restore the quit handler instead
of changing the SIGINT handler.
(do_remote_fileio_request): Override the quit handler instead of
changing the SIGINT handler.
Graham Markall [Wed, 1 Jun 2016 15:29:27 +0000 (16:29 +0100)]
Add support for some variants of the ARC nps400 rflt instruction.
gas * testsuite/gas/arc/nps-400-1.s: Add rflt variants with
operands of types a,b,u6, 0,b,u6, and 0,b,limm.
* testsuite/gas/arc/nps-400-1.d: Likewise.
opcodes * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
0,b,limm to the rflt instruction.
Nick Clifton [Wed, 1 Jun 2016 10:44:08 +0000 (11:44 +0100)]
Add xmalloc_failed() function to common-utils.c in to avoid the need to link in libiberty's xmalloc code.
Markus Metzger [Tue, 31 May 2016 07:03:15 +0000 (09:03 +0200)]
infcmd, btrace: fix crash in 'finish' for tailcall-only frames
Patch
7eb895307f53 Skip unwritable frames in command "finish"
skips non-writable frames in addition to tailcall frames.
If skip_tailcall_frames already returns NULL, skip_unwritable_frames
will be called with a NULL frame and crash in get_frame_arch. This is
caught by gdb.btrace/tailcall-only.exp.
Further, if we ever end up with a mixture of tailcall and non-writable
frames, we may not skip all of them, as intended.
Loop over skip_tailcall_frames and skip_unwritable_frames as long as at least
one of them makes progress.
gdb/
* infcmd.c (skip_finish_frames): New.
(finish_command): Call skip_finish_frames.
Yao Qi [Wed, 1 Jun 2016 08:33:40 +0000 (09:33 +0100)]
Wake up interruptible_select in remote_fileio ctrl-c handler
As reported in PR 19998, after type ctrl-c, GDB hang there and does
not send interrupt. It causes a fail in gdb.base/interrupt.exp.
All targets support remote fileio should be affected.
When we type ctrc-c, SIGINT is handled by remote_fileio_sig_set,
as shown below,
#0 remote_fileio_sig_set (sigint_func=0x4495d0 <remote_fileio_ctrl_c_signal_handler(int)>) at /home/yao/SourceCode/gnu/gdb/git/gdb/remote-fileio.c:325
#1 0x00000000004495de in remote_fileio_ctrl_c_signal_handler (signo=<optimised out>) at /home/yao/SourceCode/gnu/gdb/git/gdb/remote-fileio.c:349
#2 <signal handler called>
#3 0x00007ffff647ed83 in __select_nocancel () at ../sysdeps/unix/syscall-template.S:81
#4 0x00000000005530ce in interruptible_select (n=10, readfds=readfds@entry=0x7fffffffd730, writefds=writefds@entry=0x0, exceptfds=exceptfds@entry=0x0,
timeout=timeout@entry=0x0) at /home/yao/SourceCode/gnu/gdb/git/gdb/event-top.c:1017
#5 0x000000000061ab20 in stdio_file_read (file=<optimised out>, buf=0x12d02e0 "\n\022-\001", length_buf=16383)
at /home/yao/SourceCode/gnu/gdb/git/gdb/ui-file.c:577
#6 0x000000000044a4dc in remote_fileio_func_read (buf=0x12c0360 "") at /home/yao/SourceCode/gnu/gdb/git/gdb/remote-fileio.c:583
#7 0x0000000000449598 in do_remote_fileio_request (uiout=<optimised out>, buf_arg=buf_arg@entry=0x12c0340)
at /home/yao/SourceCode/gnu/gdb/git/gdb/remote-fileio.c:1179
we don't set quit_serial_event,
do
{
res = gdb_select (n, readfds, writefds, exceptfds, timeout);
}
while (res == -1 && errno == EINTR);
if (res == 1 && FD_ISSET (fd, readfds))
{
errno = EINTR;
return -1;
}
return res;
we can't go out of the loop above, and that is why GDB can't send
interrupt.
Recently, we stop throwing exception from SIGINT handler
(remote_fileio_ctrl_c_signal_handler)
https://sourceware.org/ml/gdb-patches/2016-03/msg00372.html, which
is correct, because gdb_select is interruptible. However, in the
same patch series, we add interruptible_select later as a wrapper
to gdb_select, https://sourceware.org/ml/gdb-patches/2016-03/msg00375.html
and it is not interruptible (because of the loop in it) unless
select/poll-able file descriptors are marked.
This fix in this patch is to call quit_serial_event_set, so that we can
go out of the loop above, return -1 and set errno to EINTR.
2016-06-01 Yao Qi <yao.qi@linaro.org>
PR remote/19998
* remote-fileio.c (remote_fileio_ctrl_c_signal_handler): Call
quit_serial_event_set.
Trevor Saunders [Sun, 29 May 2016 00:29:54 +0000 (20:29 -0400)]
sh: make constant unsigned to avoid narrowing
Shifting into the sign bit of a 32 bit int and then converting to a unsigned
type is less straight forward than just shifting an unsigned value.
opcodes/ChangeLog:
2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
constant.
Joel Brobecker [Wed, 1 Jun 2016 00:49:49 +0000 (17:49 -0700)]
Document the GDB 7.11.1 release in gdb/ChangeLog
gdb/ChangeLog:
GDB 7.11.1 released.
GDB Administrator [Wed, 1 Jun 2016 00:00:18 +0000 (00:00 +0000)]
Automatic date update in version.in
Martin Galvan [Tue, 31 May 2016 18:54:01 +0000 (15:54 -0300)]
[PR gdb/19893] Fix handling of synthetic C++ references
https://sourceware.org/bugzilla/show_bug.cgi?id=19893
I've traced the main source of the problem to pieced_value_funcs.coerce_ref not being
implemented. Since gdb always assumes references are implemented as pointers, this
causes it to think that it's dealing with a NULL pointer, thus breaking any operations
involving synthetic references.
What I did here was implementing pieced_value_funcs.coerce_ref using some of the synthetic
pointer handling code from indirect_pieced_value, as Pedro suggested. I also made a few
adjustments to the reference printing code so that it correctly shows either the address
of the referenced value or (if it's non-addressable) the "<synthetic pointer>" string.
I also wrote some unit tests based on Dwarf::assemble; these took a while to make
because in most cases I needed a synthetic reference to a physical variable. Additionally,
I started working on a unit test for classes that have a vtable, but ran into a few issues
so that'll probably go in a future patch. One thing that should definitely be fixed is that
proc function_range (called for MACRO_AT_func) will always try to compile/link using gcc
with the default options instead of g++, thus breaking C++ compilations that require e.g. libstdc++.
gdb/ChangeLog:
* dwarf2loc.c (coerce_pieced_ref, indirect_synthetic_pointer,
fetch_const_value_from_synthetic_pointer): New functions.
(indirect_pieced_value): Move lower half to indirect_synthetic_pointer.
(pieced_value_funcs): Implement coerce_ref.
* valops.c (value_addr): Call coerce_ref for synthetic references.
* valprint.c (valprint_check_validity): Return true for synthetic
references. Also, don't show "<synthetic pointer>" if they reference
addressable values.
(generic_val_print_ref): Handle synthetic references. Also move some
code to print_ref_address.
(print_ref_address, get_value_addr_contents): New functions.
gdb/testsuite/ChangeLog:
* gdb.dwarf2/implref.exp: Rename to...
* gdb.dwarf2/implref-const.exp: ...this. Also add more test statements.
* gdb.dwarf2/implref-array.c: New file.
* gdb.dwarf2/implref-array.exp: Likewise.
* gdb.dwarf2/implref-global.c: Likewise.
* gdb.dwarf2/implref-global.exp: Likewise.
* gdb.dwarf2/implref-struct.c: Likewise.
* gdb.dwarf2/implref-struct.exp: Likewise.
Alan Modra [Tue, 31 May 2016 10:51:09 +0000 (20:21 +0930)]
objcopy add-symbol uninitialised struct
* objcopy.c: Formatting, whitespace throughout.
(copy_main): Init newsym->othersym.
(parse_symflags): Make len a size_t. Adjust uses.
Alan Modra [Tue, 31 May 2016 11:04:47 +0000 (20:34 +0930)]
Don't needlessly clear xmemdup allocated memory.
* xmemdup.c (xmemdup): Use xmalloc rather than xcalloc.
GDB Administrator [Tue, 31 May 2016 00:00:16 +0000 (00:00 +0000)]
Automatic date update in version.in
Marcin Kościelnicki [Fri, 6 May 2016 21:02:43 +0000 (23:02 +0200)]
gold/s390: Fix compilation on gcc 4.4
gold/ChangeLog:
PR/19960
* s390.cc (Target_s390::ss_code_st_r14): Removed.
(Target_s390::ss_code_l_r14): Removed.
(Target_s390::ss_code_ear): Removed.
(Target_s390::ss_code_c): Removed.
(Target_s390::ss_match_st_r14): New function.
(Target_s390::ss_match_l_r14): New function.
(Target_s390::ss_match_mcount): Call ss_match_{l,st}_r14 instead
of matching code directly.
(Target_s390::ss_match_ear): New function.
(Target_s390::ss_match_c): New function.
(Target_s390::do_calls_non_split): Call ss_match_{ear,c} instead
of matching code directly.
Antoine Tremblay [Mon, 30 May 2016 15:24:44 +0000 (11:24 -0400)]
Add tests for 64bit values in trace-condition.exp
This patch adds tests for emit operations with 64 bit values. It takes
special care to avoid mistakes that one could make on a 32bit architecture
using 64bit values.
gdb/testsuite/ChangeLog:
* gdb.trace/trace-condition.exp: Add 64bit tests.
Antoine Tremblay [Mon, 30 May 2016 15:24:44 +0000 (11:24 -0400)]
Add variable length tests for emit_ref in trace-condition.exp
This patch add variable length tests for emit_ref by reading the variable
passed as argument of 8 to 64 bit.
gdb/testsuite/ChangeLog:
* gdb.trace/trace-condition.c (marker): Adapt signature to 8 to 64
bits types.
(main): Adapt to 8 to 64 bits types.
* gdb.trace/trace-condition.exp: Add new tests.
Antoine Tremblay [Mon, 30 May 2016 15:24:44 +0000 (11:24 -0400)]
Add emit_less_unsigned test in trace-condition.exp
This patch adds coverage for emit_less_unsigned.
gdb/testsuite/ChangeLog:
* gdb.trace/trace-condition.exp: Add emit_less_unsigned test.
Antoine Tremblay [Mon, 30 May 2016 15:24:44 +0000 (11:24 -0400)]
Move trace conditions tests from ftrace.exp to trace-condition.exp
This patch moves conditional tests that were done in ftrace.exp to
trace-condition.exp.
Note that emit_ref is now tested by the anarg local variable there is no
need to test the register directly.
All emit calls have been tested using asserts before / after the move, to
ensure that the tests cover the same functions.
Note that these function were not covered before and are still not:
emit_gt_goto, emit_lt_goto, emit_pop, emit_unsigned_less.
gdb/testsuite/ChangeLog:
* gdb.trace/ftrace.exp (test_ftrace_condition): Remove.
Move condition tests...
* gdb.trace/trace-condition.exp: Here.
Antoine Tremblay [Mon, 30 May 2016 15:24:44 +0000 (11:24 -0400)]
Add counter-cases for trace-condition.exp tests
In trace-condition.exp, tests are done by doing a conditional tracepoint
and validating that the trace contains all the frames that could be
collected if that condition is true.
E.g. test_tracepoints $trace_command "21 + 21 == 42" 10
This will always return true and collect the 10 frames possible to collect
with the test program.
However, if the condition evaluation is broken such that the condition is
unconditional we will not notice this problem.
This patch adds counter-cases to such conditions like so:
$trace_command "21 + 11 == 42" 0
This way such a problem would be noticed.
gdb/testsuite/ChangeLog:
* gdb.trace/trace-condition.exp: Add counter-case tests.
Jan Kratochvil [Mon, 30 May 2016 12:14:43 +0000 (14:14 +0200)]
PR 15231: import bare DW_TAG_lexical_block
Local variables in lambdas are not accessible
https://sourceware.org/bugzilla/show_bug.cgi?id=15231
GDB: read_lexical_block_scope
/* Ignore blocks with missing or invalid low and high pc attributes. */
[...]
if (!dwarf2_get_pc_bounds (die, &lowpc, &highpc, cu, NULL))
return;
But sometimes there is:
FAIL: gcc-5.3.1-6.fc23.x86_64
<2><92>: Abbrev Number: 11 (DW_TAG_lexical_block)
<3><9c>: Abbrev Number: 13 (DW_TAG_structure_type)
<9d> DW_AT_name : (indirect string, offset: 0x3c): <lambda()>
[...]
Where DW_TAG_lexical_block has no attributes. Such whole subtree is currently
dropped by GDB while I think it should just import all its children DIEs.
It even XFAIL->XPASSes gdb.ada/out_of_line_in_inlined.exp:
commit
0fa7fe506c242b459c4c05d331e7c7d66fb52390
Author: Joel Brobecker <brobecker@adacore.com>
out of line functions nested inside inline functions.
So I have removed that xfail.
gdb/ChangeLog
2016-05-30 Jan Kratochvil <jan.kratochvil@redhat.com>
PR c++/15231
* dwarf2read.c (enum pc_bounds_kind): Add PC_BOUNDS_INVALID.
(process_psymtab_comp_unit_reader, read_func_scope): Adjust callers.
(read_lexical_block_scope): Import DIEs from bare DW_TAG_lexical_block.
(read_call_site_scope): Adjust callers.
(dwarf2_get_pc_bounds): Implement pc_bounds_invalid.
(dwarf2_get_subprogram_pc_bounds, get_scope_pc_bounds): Adjust callers.
gdb/testsuite/ChangeLog
2016-05-30 Jan Kratochvil <jan.kratochvil@redhat.com>
PR c++/15231
* gdb.ada/out_of_line_in_inlined.exp: Remove xfails.
* gdb.dwarf2/dw2-lexical-block-bare.exp: New file.
Jan Kratochvil [Mon, 30 May 2016 12:11:43 +0000 (14:11 +0200)]
Code cleanup: dwarf2_get_pc_bounds: -1/0/+1 -> enum
Make the code (maybe) more readable + primarily prepare it for [patch 2/2]
enum extension.
This change should have no code change impact.
gdb/ChangeLog
2016-05-30 Jan Kratochvil <jan.kratochvil@redhat.com>
Code cleanup: dwarf2_get_pc_bounds: -1/0/+1 -> enum
* dwarf2read.c (enum pc_bounds_kind) New.
(dwarf2_get_pc_bounds): Use it in the declaration.
(process_psymtab_comp_unit_reader): Adjust caller. Rename has_pc_info
to cu_bounds_kind.
(read_func_scope, read_lexical_block_scope, read_call_site_scope):
Adjust callers.
(dwarf2_get_pc_bounds): Use enum pc_bounds_kind in the definition.
(dwarf2_get_subprogram_pc_bounds, get_scope_pc_bounds): Adjust callers.
GDB Administrator [Mon, 30 May 2016 00:00:15 +0000 (00:00 +0000)]
Automatic date update in version.in
Jan Kratochvil [Sun, 29 May 2016 18:45:42 +0000 (20:45 +0200)]
NEWS: QCatchSyscalls: simplify
Standardize the QCatchSyscalls NEWS entry.
gdb/ChangeLog
2016-05-29 Jan Kratochvil <jan.kratochvil@redhat.com>
* NEWS (QCatchSyscalls): Remove the parameter. Include ...
(QCatchSyscalls:1 in qSupported) ... this separate entry which got
deleted.
Jan Kratochvil [Sun, 29 May 2016 16:40:32 +0000 (18:40 +0200)]
NEWS: Remove empty line.
gdb/ChangeLog
2016-05-29 Jan Kratochvil <jan.kratochvil@redhat.com>
* NEWS (N stop reply): Remove empty line.
H.J. Lu [Sun, 29 May 2016 15:26:43 +0000 (08:26 -0700)]
Add missing ChangeLog entries
H.J. Lu [Fri, 27 May 2016 22:41:45 +0000 (15:41 -0700)]
Add .noavx512XX directives to x86 assembler
Add .noavx512f, .noavx512cd, .noavx512er, .noavx512pf, .noavx512dq,
.noavx512bw, .noavx512vl, .noavx512ifma, .noavx512vbmi directives to x86
assembler.
gas/
PR gas/20145
* config/tc-i386.c (cpu_noarch): Add noavx512f, noavx512cd,
noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl,
noavx512ifma and noavx512vbmi.
* doc/c-i386.texi: Mention noavx512f, noavx512cd, noavx512er,
noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma
and noavx512vbmi.
* testsuite/gas/i386/i386.exp: Run noavx512-1 and noavx512-2.
* testsuite/gas/i386/noavx512-1.l: New file.
* testsuite/gas/i386/noavx512-1.s: Likewise.
* testsuite/gas/i386/noavx512-2.l: Likewise.
* testsuite/gas/i386/noavx512-2.s: Likewise.
opcodes/
PR gas/20145
* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
* i386-init.h: Regenerated.
GDB Administrator [Sun, 29 May 2016 00:00:19 +0000 (00:00 +0000)]
Automatic date update in version.in
Alan Modra [Sat, 28 May 2016 13:06:04 +0000 (22:36 +0930)]
Add dependencies to configure rule
* Makefile.tpl (configure): Depend on m4 files included.
* Makefile.in: Regenerate.
Maciej W. Rozycki [Sat, 28 May 2016 09:57:58 +0000 (10:57 +0100)]
MIPS/BFD: Correctly handle `bfd_reloc_outofrange' with branches
Fix internal errors like:
ld: BFD (GNU Binutils) 2.26.51.
20160526 internal error, aborting at .../bfd/elfxx-mips.c:10278 in _bfd_mips_elf_relocate_section
ld: Please report this bug.
triggered by the `bfd_reloc_outofrange' condition on branch relocations.
bfd/
* elfxx-mips.c (b_reloc_p): New function.
(_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Handle
branch relocations.
ld/
* testsuite/ld-mips-elf/unaligned-branch.d: New test.
* testsuite/ld-mips-elf/unaligned-branch.s: New test source.
* testsuite/ld-mips-elf/unaligned-text.s: New test source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
Maciej W. Rozycki [Sat, 28 May 2016 09:28:05 +0000 (10:28 +0100)]
MIPS/LD/testsuite: Rename `unaligned-syms' to `unaligned-data'
ld/
* testsuite/ld-mips-elf/unaligned-syms.s: Rename to...
* testsuite/ld-mips-elf/unaligned-data.s: ... this.
* testsuite/ld-mips-elf/unaligned-ldpc-0.d: Adjust accordingly.
* testsuite/ld-mips-elf/unaligned-ldpc-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-lwpc-0.d: Likewise.
* testsuite/ld-mips-elf/unaligned-lwpc-1.d: Likewise.
Maciej W. Rozycki [Sat, 28 May 2016 09:30:22 +0000 (10:30 +0100)]
MIPS/BFD: Enable local R_MIPS_26 overflow detection
The original MIPS SVR4 psABI defines the calculation for the R_MIPS_26
relocation in a complex way, as follows[1]:
Name Value Field Symbol Calculation
R_MIPS_26 4 T-targ26 local (((A << 2) | \
(P & 0xf0000000)) + S) >> 2
4 T-targ26 external (sign-extend(A << 2) + S) >> 2
This is further clarified, by correcting typos (already applied in the
excerpt above) in the 64-bit psABI extension[2]. A note is included in
both documents to specify that for the purpose of relocation processing
a local symbol is one with binding STB_LOCAL and type STT_SECTION, and
otherwise, a symbol is external.
We have both calculations implemented for the R_MIPS_26 relocation, and
by extension also for the R_MIPS16_26 and R_MICROMIPS_26_S1 relocations,
from now on collectively called jump relocations. However our code uses
a different condition to tell local and external symbols apart, that is
it only checks for the STB_LOCAL binding and ignores the symbol type,
however for REL relocations only. The external calculation is used for
all RELA jump relocations.
In reality the difference matters for jump relocations referring local
MIPS16 and, as from recent commit
44d3da233815 ("MIPS/GAS: Treat local
jump relocs the same no matter if REL or RELA"), also local microMIPS
symbols. Such relocations are not converted to refer to corresponding
section symbols instead and retain the original local symbol reference.
It can be inferred from the relocation calculation definitions that the
addend is effectively unsigned for the local case and explicitly signed
for the external case. With the REL relocation format it makes sense
given the limited range provided for by the field being relocated: the
use of an unsigned addend expands the range by one bit for the local
case, because a negative offset from a section symbol makes no sense,
and any usable negative offset from the original local symbol will have
worked out positive if converted to a section-relative reference. In
the external case a signed addend gives more flexibility as offsets both
negative and positive can be used with a symbol. Any such offsets will
typically have a small value.
The inclusion of the (P & 0xf0000000) component, ORed in the calculation
in the local case, seems questionable as bits 31:28 are not included in
the relocatable field and are masked out as the relocation is applied.
Their value is therefore irrelevant for output processing, the relocated
field ends up the same regardless of their value. They could be used
for overflow detection, however this is precluded by adding them to bits
31:28 of the symbol referred, as the sum will not correspond to the
value calculated by the processor at run time whenever bits 31:28 of the
symbol referred are not all zeros, even though it is valid as long they
are the same as bits 31:28 of P.
We deal with this problem by ignoring any overflow resulting from the
local calculation. This however makes us miss genuine overflow cases,
where 31:28 of the symbol referred are different from bits 31:28 of P,
and non-functional code is produced.
Given the situation, for the purpose of overflow detection we can change
our code to follow the original psABI and only treat the in-place addend
as unsigned in the section symbol case, permitting jumps to offsets
128MiB and above into section. Sections so large may be uncommon, but
still a reasonable use case. On the other hand such large offsets from
regular local symbols are not expected and it makes sense to support
(possibly small) negative offsets instead, also in consistency with what
we do for global symbols.
Drop the (P & 0xf0000000) component then, treat the addend as signed
with local non-section symbols and also detect an overflow in the result
of such calculation with local symbols. NB it does not affect the value
computed for the relocatable field, it only affects overflow detection.
References:
[1] "SYSTEM V APPLICATION BINARY INTERFACE, MIPS RISC Processor
Supplement, 3rd Edition", Figure 4-11: "Relocation Types", p. 4-19
<http://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf>
[2] "64-bit ELF Object File Specification, Draft Version 2.5", Table 32
"Relocation Types", p. 45
<http://techpubs.sgi.com/library/manuals/4000/007-4658-001/pdf/007-4658-001.pdf>
bfd/
* elfxx-mips.c (mips_elf_calculate_relocation): <R_MIPS16_26>
<R_MIPS_26, R_MICROMIPS_26_S1>: Drop the region bits of the
reloc location from calculation, treat the addend as signed with
local non-section symbols and enable overflow detection.
ld/
* testsuite/ld-mips-elf/jal-global-overflow-0.d: New test.
* testsuite/ld-mips-elf/jal-global-overflow-1.d: New test.
* testsuite/ld-mips-elf/jal-local-overflow-0.d: New test.
* testsuite/ld-mips-elf/jal-local-overflow-1.d: New test.
* testsuite/ld-mips-elf/jal-global-overflow.s: New test source.
* testsuite/ld-mips-elf/jal-local-overflow.s: New test source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Alan Modra [Fri, 27 May 2016 07:50:55 +0000 (17:20 +0930)]
Return void from linker callbacks
The ldmain.c implementation of these linker callback functions always
return true, so any code handling a false return is dead. What's
more, some of the bfd backends abort if ever a false return is seen,
and there seems to be some confusion in gdb's compile-object-load.c.
The return value was never meant to be "oh yes, a multiple_definition
error occurred", but rather "out of memory or other catastrophic
failure".
This patch removes the status return on the callbacks that always
return true. I kept the return status for "notice" because that one
does happen to need to return "out of memory".
include/
* bfdlink.h (struct bfd_link_callbacks): Update comments.
Return void from multiple_definition, multiple_common,
add_to_set, constructor, warning, undefined_symbol,
reloc_overflow, reloc_dangerous and unattached_reloc.
bfd/
* aoutx.h: Adjust linker callback calls throughout file,
removing dead code.
* bout.c: Likewise.
* coff-alpha.c: Likewise.
* coff-arm.c: Likewise.
* coff-h8300.c: Likewise.
* coff-h8500.c: Likewise.
* coff-i960.c: Likewise.
* coff-mcore.c: Likewise.
* coff-mips.c: Likewise.
* coff-ppc.c: Likewise.
* coff-rs6000.c: Likewise.
* coff-sh.c: Likewise.
* coff-tic80.c: Likewise.
* coff-w65.c: Likewise.
* coff-z80.c: Likewise.
* coff-z8k.c: Likewise.
* coff64-rs6000.c: Likewise.
* cofflink.c: Likewise.
* ecoff.c: Likewise.
* elf-bfd.h: Likewise.
* elf-m10200.c: Likewise.
* elf-m10300.c: Likewise.
* elf32-arc.c: Likewise.
* elf32-arm.c: Likewise.
* elf32-avr.c: Likewise.
* elf32-bfin.c: Likewise.
* elf32-cr16.c: Likewise.
* elf32-cr16c.c: Likewise.
* elf32-cris.c: Likewise.
* elf32-crx.c: Likewise.
* elf32-d10v.c: Likewise.
* elf32-epiphany.c: Likewise.
* elf32-fr30.c: Likewise.
* elf32-frv.c: Likewise.
* elf32-ft32.c: Likewise.
* elf32-h8300.c: Likewise.
* elf32-hppa.c: Likewise.
* elf32-i370.c: Likewise.
* elf32-i386.c: Likewise.
* elf32-i860.c: Likewise.
* elf32-ip2k.c: Likewise.
* elf32-iq2000.c: Likewise.
* elf32-lm32.c: Likewise.
* elf32-m32c.c: Likewise.
* elf32-m32r.c: Likewise.
* elf32-m68hc1x.c: Likewise.
* elf32-m68k.c: Likewise.
* elf32-mep.c: Likewise.
* elf32-metag.c: Likewise.
* elf32-microblaze.c: Likewise.
* elf32-moxie.c: Likewise.
* elf32-msp430.c: Likewise.
* elf32-mt.c: Likewise.
* elf32-nds32.c: Likewise.
* elf32-nios2.c: Likewise.
* elf32-or1k.c: Likewise.
* elf32-ppc.c: Likewise.
* elf32-s390.c: Likewise.
* elf32-score.c: Likewise.
* elf32-score7.c: Likewise.
* elf32-sh.c: Likewise.
* elf32-sh64.c: Likewise.
* elf32-spu.c: Likewise.
* elf32-tic6x.c: Likewise.
* elf32-tilepro.c: Likewise.
* elf32-v850.c: Likewise.
* elf32-vax.c: Likewise.
* elf32-visium.c: Likewise.
* elf32-xstormy16.c: Likewise.
* elf32-xtensa.c: Likewise.
* elf64-alpha.c: Likewise.
* elf64-hppa.c: Likewise.
* elf64-ia64-vms.c: Likewise.
* elf64-mmix.c: Likewise.
* elf64-ppc.c: Likewise.
* elf64-s390.c: Likewise.
* elf64-sh64.c: Likewise.
* elf64-x86-64.c: Likewise.
* elflink.c: Likewise.
* elfnn-aarch64.c: Likewise.
* elfnn-ia64.c: Likewise.
* elfxx-mips.c: Likewise.
* elfxx-sparc.c: Likewise.
* elfxx-tilegx.c: Likewise.
* linker.c: Likewise.
* pdp11.c: Likewise.
* pe-mips.c: Likewise.
* reloc.c: Likewise.
* reloc16.c: Likewise.
* simple.c: Likewise.
* vms-alpha.c: Likewise.
* xcofflink.c: Likewise.
* elf32-rl78.c (get_symbol_value, get_romstart, get_ramstart): Delete
status param. Adjust calls to these and linker callbacks throughout.
* elf32-rx.c: (get_symbol_value, get_gp, get_romstart,
get_ramstart): Delete status param. Adjust calls to these and
linker callbacks throughout.
ld/
* ldmain.c (multiple_definition, multiple_common, add_to_set,
constructor_callback, warning_callback, undefined_symbol,
reloc_overflow, reloc_dangerous, unattached_reloc): Return void.
* emultempl/elf32.em: Adjust callback calls.
gdb/
* compile/compile-object-load.c (link_callbacks_multiple_definition,
link_callbacks_warning, link_callbacks_undefined_symbol,
link_callbacks_undefined_symbol, link_callbacks_reloc_overflow,
link_callbacks_reloc_dangerous,
link_callbacks_unattached_reloc): Return void.
GDB Administrator [Sat, 28 May 2016 00:00:19 +0000 (00:00 +0000)]
Automatic date update in version.in
Maciej W. Rozycki [Fri, 27 May 2016 19:43:05 +0000 (20:43 +0100)]
MIPS/BFD: Include the addend in JALX's target alignment verification
On RELA targets the addend can affect JALX target's alignment, so only
verify it once the whole relocation calculation has completed.
bfd/
* elfxx-mips.c (mips_elf_calculate_relocation) <R_MIPS16_26>
<R_MIPS_26, R_MICROMIPS_26_S1>: Include the addend in JALX's
target alignment verification.
ld/
* testsuite/ld-mips-elf/unaligned-jalx-addend-0.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-0.d: New
test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d: New
test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-0.d: New
test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d: New
test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-0.s: New test
source.
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.s: New test
source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Maciej W. Rozycki [Fri, 27 May 2016 19:41:40 +0000 (20:41 +0100)]
MIPS/BFD: Fix section symbol name fetching in relocation
Symbol table entries for section symbols are different between IRIX and
traditional MIPS ELF targets in that IRIX entries have their `st_name'
member pointing at the section's name in the string table section, while
traditional entries have 0 there and the section header string table has
to be referred via the relevant section header's `shn_name' member
instead.
This is chosen with the `elf_backend_name_local_section_symbols' backend
and can be observed with `readelf -s' output for an IRIX object:
Symbol table '.symtab' contains 12 entries:
Num: Value Size Type Bind Vis Ndx Name
0:
00000000 0 NOTYPE LOCAL DEFAULT UND
1:
00000000 0 SECTION LOCAL DEFAULT 1 .text
2:
00000000 0 SECTION LOCAL DEFAULT 3 .data
3:
00000000 0 SECTION LOCAL DEFAULT 4 .bss
4:
00000000 0 SECTION LOCAL DEFAULT 5 .reginfo
5:
00000000 0 SECTION LOCAL DEFAULT 6 .MIPS.abiflags
6:
00000000 0 SECTION LOCAL DEFAULT 7 .pdr
7:
00000000 0 SECTION LOCAL DEFAULT 9 .gnu.attributes
8:
00002000 16 FUNC GLOBAL DEFAULT 1 foo
9:
00004008 0 FUNC LOCAL DEFAULT 1 abar
10:
00002008 0 FUNC LOCAL DEFAULT 1 afoo
11:
00004000 16 FUNC GLOBAL DEFAULT 1 bar
and a corresponding traditional object:
Symbol table '.symtab' contains 12 entries:
Num: Value Size Type Bind Vis Ndx Name
0:
00000000 0 NOTYPE LOCAL DEFAULT UND
1:
00000000 0 SECTION LOCAL DEFAULT 1
2:
00000000 0 SECTION LOCAL DEFAULT 3
3:
00000000 0 SECTION LOCAL DEFAULT 4
4:
00004008 0 FUNC LOCAL DEFAULT 1 abar
5:
00002008 0 FUNC LOCAL DEFAULT 1 afoo
6:
00000000 0 SECTION LOCAL DEFAULT 5
7:
00000000 0 SECTION LOCAL DEFAULT 6
8:
00000000 0 SECTION LOCAL DEFAULT 7
9:
00000000 0 SECTION LOCAL DEFAULT 9
10:
00002000 16 FUNC GLOBAL DEFAULT 1 foo
11:
00004000 16 FUNC GLOBAL DEFAULT 1 bar
respectively. Consequently the right way to retrieve a section symbol's
name has to be chosen in `mips_elf_calculate_relocation' for the purpose
of error reporting.
Originally we produced symbol tables in the traditional object format
only and we handled it correctly until it was lost in a rewrite with:
commit
7403cb6305f5660fccc8869d3333a731102ae978
Author: Mark Mitchell <mark@codesourcery.com>
Date: Wed Jun 30 20:13:43 1999 +0000
probably because of the extra pointer indirection added which made the
same expression have a different meaning.
With the addition of IRIX symbol table format with:
commit
174fd7f9556183397625dbfa99ef68ecd325c74b
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Mon Feb 9 08:04:00 2004 +0000
the bug has been partially covered and now when a relocation error is
triggered with an IRIX object the offending section symbol is correctly
reported:
tmpdir/dump0.o: In function `foo':
(.text+0x2000): relocation truncated to fit: R_MIPS_26 against `.text'
tmpdir/dump0.o: In function `bar':
(.text+0x4000): relocation truncated to fit: R_MIPS_26 against `.text'
because `bfd_elf_string_from_elf_section' retrieves the name from the
string table section. With a traditional object however the function
returns an empty string and consequently `no symbol' is printed instead:
tmpdir/dump0.o: In function `foo':
(.text+0x2000): relocation truncated to fit: R_MIPS_26 against `no symbol'
tmpdir/dump0.o: In function `bar':
(.text+0x4000): relocation truncated to fit: R_MIPS_26 against `no symbol'
Restore the original semantics so that the section name is always
correctly retrieved.
bfd/
* elfxx-mips.c (mips_elf_calculate_relocation): Also use the
section name if `bfd_elf_string_from_elf_section' returns an
empty string.
ld/
* testsuite/ld-mips-elf/reloc-local-overflow.d: New test.
* testsuite/ld-mips-elf/reloc-local-overflow.s: Source for the
new test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
H.J. Lu [Fri, 27 May 2016 17:05:39 +0000 (10:05 -0700)]
Update x86 CPU_XXX_FLAGS handling
Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS. Update
CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL. Don't enable
MMX when enabling SSE, AVX or AVX512. Don't disable AVX nor AVX512 when
disabling SSE. Don't disable AVX512 when disabling AVX. Disable F16C,
FMA, FMA4 and XOP when disabling AVX. Add 87, no287, no387, no687,
nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives
to x86 assembler.
TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler.
gas/
PR gas/20145
* config/tc-i386.c (cpu_arch): Add 687.
(cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3,
nosse4.1, nosse4.2, nosse4 and noavx2.
(parse_real_register): Check cpuregmmx instead of cpummx for MMX
register. Check cpuregxmm instead of cpusse for XMM register.
Check cpuregymm instead of cpuavx for YMM register. Check
cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register.
* doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2,
nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2.
* testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx.
* testsuite/gas/i386/arch-10.d (as): Likewise.
* testsuite/gas/i386/arch-11.s: Add ".arch .mmx".
* testsuite/gas/i386/i386.exp: Pass mmx to assembler for
arch-10-3 and arch-10-4. Run no87-3, nosse-4, nosse-5, noavx-3
and noavx-4.
* testsuite/gas/i386/no87-3.l: New file.
* testsuite/gas/i386/no87-3.s: Likewise.
* testsuite/gas/i386/noavx-3.l: Likewise.
* testsuite/gas/i386/noavx-3.s: Likewise.
* testsuite/gas/i386/noavx-4.d: Likewise.
* testsuite/gas/i386/noavx-4.s: Likewise.
* testsuite/gas/i386/nosse-4.l: Likewise.
* testsuite/gas/i386/nosse-4.s: Likewise.
* testsuite/gas/i386/nosse-5.d: Likewise.
* testsuite/gas/i386/nosse-5.s: Likewise.
opcodes/
PR gas/20145
* i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
CpuRegMask for AVX512.
(cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
and CpuRegMask.
(set_bitfield_from_cpu_flag_init): New function.
(set_bitfield): Remove const on f. Call
set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
* i386-opc.h (CpuRegMMX): New.
(CpuRegXMM): Likewise.
(CpuRegYMM): Likewise.
(CpuRegZMM): Likewise.
(CpuRegMask): Likewise.
(i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
and cpuregmask.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
Pedro Alves [Fri, 27 May 2016 15:18:28 +0000 (16:18 +0100)]
Skip attach-many-short-lived-threads.exp on known-broken DejaGnu versions
If the testsuite is run with a DejaGnu version that predates the fix
from last year:
[PATCH] DejaGnu kills the wrong process due to PID-reuse races
http://lists.gnu.org/archive/html/dejagnu/2015-07/msg00005.html
... gdb.threads/attach-many-short-lived-threads.exp fails randomly,
often. Other tests randomly fail due to that issue too, but this one
is _much_ more exposed.
DejaGnu 1.6 was released meanwhile, which includes that DejaGnu fix,
and also some distros backported the fix too.
So skip the test when run with older/broken DejaGnus.
gdb/testsuite/ChangeLog:
2016-05-27 Pedro Alves <palves@redhat.com>
* gdb.threads/attach-many-short-lived-threads.exp (bad_dejagnu):
New procedure.
(top level): Call it, and bail out of DejaGnu is known to be bad.
H.J. Lu [Fri, 27 May 2016 15:02:56 +0000 (08:02 -0700)]
Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
AMD64 vs CpuIntel64 ISA should be handled similar as AT&T vs Intel
syntax. Since cpu_flags isn't sorted by position, we need to check
the whole cpu_flags array for the maximum position when verifying
CpuMax.
gas/
PR gas/20154
* config/tc-i386.c (cpu_flags_match): Don't set cpuamd64 nor
cpuintel64.
(match_template): Check Intel64/AMD64 ISA.
opcodes/
PR gas/20154
* i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
(opcode_modifiers): Add AMD64 and Intel64.
(main): Properly verify CpuMax.
* i386-opc.h (CpuAMD64): Removed.
(CpuIntel64): Likewise.
(CpuMax): Set to CpuNo64.
(i386_cpu_flags): Remove cpuamd64 and cpuintel64.
(AMD64): New.
(Intel64): Likewise.
(i386_opcode_modifier): Add amd64 and intel64.
(i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
on call and jmp.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
Eli Zaretskii [Fri, 27 May 2016 13:59:22 +0000 (16:59 +0300)]
Improve documentation of general query packets
gdb/doc/ChangeLog:
* gdb.texinfo (General Query Packets): Move the description of the
response before the long list of the specific 'read' and 'write'
requests.
H.J. Lu [Fri, 27 May 2016 13:55:42 +0000 (06:55 -0700)]
Correct CpuMax in i386-opc.h
CpuMax should be CpuIntel64, not CpuNo64. i386-gen.c is updated to
verify that CpuMax is correct. X86 assembler is updated to properly
set cpuamd64 and cpuintel64.
gas/
PR gas/20154
* config/tc-i386.c (intel64): New.
(cpu_flags_match): Set cpuamd64 and cpuintel64.
(md_parse_option): Set intel64 instead of cpuamd64 and
cpuintel64.
opcodes/
PR gas/20154
* i386-gen.c (main): Fail if CpuMax is incorrect.
* i386-opc.h (CpuMax): Set to CpuIntel64.
* i386-tbl.h: Regenerated.
Nick Clifton [Fri, 27 May 2016 13:34:06 +0000 (14:34 +0100)]
Fix typo introduced during the most recent synchronization update.
Nick Clifton [Fri, 27 May 2016 12:49:58 +0000 (13:49 +0100)]
Improve the MSP430 disassembler's handling of memory read errors.
PR target/20150
* msp430-dis.c (msp430dis_read_two_bytes): New function.
(msp430dis_opcode_unsigned): New function.
(msp430dis_opcode_signed): New function.
(msp430_singleoperand): Use the new opcode reading functions.
Only disassenmble bytes if they were successfully read.
(msp430_doubleoperand): Likewise.
(msp430_branchinstr): Likewise.
(msp430x_callx_instr): Likewise.
(print_insn_msp430): Check that it is safe to read bytes before
attempting disassembly. Use the new opcode reading functions.
Andrew Burgess [Tue, 24 May 2016 15:53:58 +0000 (16:53 +0100)]
gdb: Forward VALUE_LVAL when avoiding side effects for STRUCTOP_STRUCT
When evaluating an expression with EVAL_AVOID_SIDE_EFFECTS if the value
we return is forced to be of type not_lval then GDB will be unable to
take the address of the returned value.
Instead, we should properly initialise the LVAL of the returned value.
This commit builds on two previous commits
2520f728b710 (Forward
VALUE_LVAL when avoiding side effects for STRUCTOP_STRUCT) and
ac775bf4d35b (gdb: Forward VALUE_LVAL when avoiding side effects for
STRUCTOP_PTR), which in turn build on
ac1ca910d74d (Fixes for PR
exp/15364).
This commit is currently untested due to my lack of access to an OpenCL
compiler, however, if follows the same pattern as the first two commits
mentioned above and so I believe that it is correct.
gdb/ChangeLog:
* opencl-lang.c (evaluate_subexp_opencl): If
EVAL_AVOID_SIDE_EFFECTS mode, forward the VALUE_LVAL attribute to
the returned value in the STRUCTOP_STRUCT case.
Andrew Burgess [Tue, 24 May 2016 15:17:52 +0000 (16:17 +0100)]
gdb: Forward VALUE_LVAL when avoiding side effects for STRUCTOP_PTR
Assume that we have a C program like this:
struct foo_type
{
int var;
} foo;
struct foo_type *foo_ptr = &foo;
int
main ()
{
return foo_ptr->var;
}
Then GDB should be able to evaluate the following, however, it currently
does not:
(gdb) start
...
(gdb) whatis &(foo_ptr->var)
Attempt to take address of value not located in memory.
The problem is that in EVAL_AVOID_SIDE_EFFECTS mode,
eval.c:evaluate_subexp_standard always returns a not_lval value as the
result for a STRUCTOP_PTR operation. As a consequence, the rest of
the code believes that one cannot take the address of the returned
value.
This patch fixes STRUCTOP_PTR handling so that the VALUE_LVAL
attribute for the returned value is properly initialized. After this
change, the above session becomes:
(gdb) start
...
(gdb) whatis &(foo_ptr->var)
type = int *
This commit is largely the same as commit
2520f728b710 (Forward
VALUE_LVAL when avoiding side effects for STRUCTOP_STRUCT) but applied
to STRUCTOP_PTR rather than STRUCTOP_STRUCT. Both of these commits are
building on top of commit
ac1ca910d74d (Fixes for PR exp/15364).
gdb/ChangeLog:
* eval.c (evaluate_subexp_standard): If EVAL_AVOID_SIDE_EFFECTS
mode, forward the VALUE_LVAL attribute to the returned value in
the STRUCTOP_PTR case.
gdb/testsuite/ChangeLog:
* gdb.base/whatis.c: Extend the test case.
* gdb.base/whatis.exp: Add additional tests.
H.J. Lu [Fri, 27 May 2016 11:56:05 +0000 (04:56 -0700)]
Don't clear cpu64 nor cpuno64
No need to clear cpu64 nor cpuno64 since they will be cleared by
cpu_flags_and.
* config/tc-i386.c (cpu_flags_match): Don't clear cpu64 nor
cpuno64.
Peter Bergner [Fri, 27 May 2016 00:06:51 +0000 (19:06 -0500)]
Add support for new POWER ISA 3.0 instructions.
opcodes/
* ppc-opc.c (CY): New define. Document it.
(powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
gas/
* testsuite/gas/ppc/altivec3.d <vmsumudm>: Add test.
* testsuite/gas/ppc/altivec3.s: Likewise.
* testsuite/gas/ppc/power9.d <addex[.], lwzmx, vmsumudm>: Add tests.
* testsuite/gas/ppc/power9.s: Likewise.
GDB Administrator [Fri, 27 May 2016 00:00:20 +0000 (00:00 +0000)]
Automatic date update in version.in
H.J. Lu [Thu, 26 May 2016 14:55:38 +0000 (07:55 -0700)]
Append ".p2align 4" to some x86 directive tests
Append ".p2align 4" to some x86 directive tests for explicit paddings
for section alignment to avoid implicit section alignment in assembler
listings.
* testsuite/gas/i386/avx512vl-2.l: Append "#pass".
* testsuite/gas/i386/noavx-1.l: Likewise.
* testsuite/gas/i386/nommx-1.l: Likewise.
* testsuite/gas/i386/nosse-1.l: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
* testsuite/gas/i386/avx512vl-2.s: Append ".p2align 4".
* testsuite/gas/i386/noavx-1.s: Likewise.
* testsuite/gas/i386/nommx-1.s: Likewise.
* testsuite/gas/i386/nosse-1.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
Trevor Saunders [Mon, 23 May 2016 11:42:14 +0000 (07:42 -0400)]
metag: make an array's type unsigned char[]
It contains values between 128 and 256 which fit in an unsigned char, but not a
signed char, so we should explicitly use unsigned char to not rely on how these
values are converted to signed char.
gas/ChangeLog:
2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-metag.c (metag_handle_align): Make the type of noop
unsigned char.
Trevor Saunders [Sun, 22 May 2016 02:24:24 +0000 (22:24 -0400)]
rx: make the type of a variable bfd_reloc_code_real_type
gas/ChangeLog:
2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-rx.c (md_convert_frag): Make the type of reloc_type
bfd_reloc_code_real_type.
Maciej W. Rozycki [Thu, 26 May 2016 11:24:45 +0000 (12:24 +0100)]
MIPS/BFD: Don't stop processing on `bfd_reloc_outofrange'
Upon a `bfd_reloc_outofrange' error continue processing so that any
further issues are also reported, similarly to how `bfd_reloc_overflow'
is handled. Adjust message formatting accordingly, using `%X' to abort
processing at conclusion.
Reduce the number of test cases by grouping relocations the handling of
which can now be verified together with a single source and dump.
bfd/
* elfxx-mips.c (_bfd_mips_elf_relocate_section)
<bfd_reloc_outofrange>: Use the `%X%H' rather than `%C' format
for message. Continue processing rather than returning failure.
ld/
* testsuite/ld-mips-elf/unaligned-jalx-0.d: Fold
`unaligned-jalx-2' here.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-0.d: Fold
`unaligned-jalx-mips16-2' here.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-0.d: Fold
`unaligned-jalx-micromips-2' here.
* testsuite/ld-mips-elf/unaligned-jalx-0.s: Update accordingly.
* testsuite/ld-mips-elf/unaligned-jalx-1.d: Update error
message.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-2.d: Remove test.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-2.d: Remove test.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-2.d: Remove
test.
* testsuite/ld-mips-elf/unaligned-jalx-2.s: Remove test source.
* testsuite/ld-mips-elf/unaligned-lwpc-0.d: Fold
`unaligned-lwpc-3' here.
* testsuite/ld-mips-elf/unaligned-lwpc-0.s: Update accordingly.
* testsuite/ld-mips-elf/unaligned-lwpc-1.d: Fold
`unaligned-lwpc-2' here.
* testsuite/ld-mips-elf/unaligned-lwpc-1.s: Update accordingly.
* testsuite/ld-mips-elf/unaligned-lwpc-2.d: Remove test.
* testsuite/ld-mips-elf/unaligned-lwpc-2.s: Remove test source.
* testsuite/ld-mips-elf/unaligned-lwpc-3.d: Remove test.
* testsuite/ld-mips-elf/unaligned-lwpc-3.s: Remove test source.
* testsuite/ld-mips-elf/unaligned-ldpc-0.d: Fold
`unaligned-ldpc-4' here.
* testsuite/ld-mips-elf/unaligned-ldpc-0.s: Update accordingly.
* testsuite/ld-mips-elf/unaligned-ldpc-1.d: Update error
message. Fold `unaligned-ldpc-2' and `unaligned-ldpc-3' here.
* testsuite/ld-mips-elf/unaligned-ldpc-1.s: Update accordingly.
* testsuite/ld-mips-elf/unaligned-ldpc-2.d: Remove test.
* testsuite/ld-mips-elf/unaligned-ldpc-2.s: Remove test source.
* testsuite/ld-mips-elf/unaligned-ldpc-3.d: Remove test.
* testsuite/ld-mips-elf/unaligned-ldpc-3.s: Remove test source.
* testsuite/ld-mips-elf/unaligned-ldpc-4.d: Remove test.
* testsuite/ld-mips-elf/unaligned-ldpc-4.s: Remove test source.
* testsuite/ld-mips-elf/mips-elf.exp: Delete removed tests.
Nick Clifton [Thu, 26 May 2016 10:43:38 +0000 (11:43 +0100)]
Provide the __bssstart and __bsssize symbols needed by the MSP430's crt0.o code.
PR target/20134
* scripttempl/elf32msp430.sc (.bss): Provide __bssstart and
__bsssize.
* scripttempl/elf32msp430_3.sc (.bss): Likewise.
Trevor Saunders [Mon, 23 May 2016 11:54:24 +0000 (07:54 -0400)]
metag: add extern C to header
include/ChangeLog:
2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* opcode/metag.h: wrap declarations in extern "C".
GDB Administrator [Thu, 26 May 2016 00:00:20 +0000 (00:00 +0000)]
Automatic date update in version.in
H.J. Lu [Wed, 25 May 2016 21:59:05 +0000 (14:59 -0700)]
Require another match for AVX512VL
The AVX512VL bit alone isn't sufficient to select a 128-bit or 256-bit
AVX512 instruction. We must match another AVX512 bit.
PR gas/20140
* config/tc-i386.c (cpu_flags_match): Require another match
for AVX512VL.
* testsuite/gas/i386/i386.exp: Run avx512vl-1, avx512vl-2,
x86-64-avx512vl-1 and x86-64-avx512vl-2.
* testsuite/gas/i386/avx512vl-1.l: New file.
* testsuite/gas/i386/avx512vl-1.s: Likewise.
* testsuite/gas/i386/avx512vl-2.l: Likewise.
* testsuite/gas/i386/avx512vl-2.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-1.l: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-1.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
Maciej W. Rozycki [Wed, 25 May 2016 19:59:37 +0000 (20:59 +0100)]
MIPS/BFD: Report `bfd_reloc_outofrange' errors as such
A `bfd_reloc_outofrange' condition from `mips_elf_calculate_relocation'
currently triggers the warning callback, which in the case of LD prints
messages like:
foo.o: In function `foo':
(.text+0x0): warning: JALX to a non-word-aligned address
or:
foo.o: In function `foo':
(.text+0x0): warning: PC-relative load from unaligned address
and nothing else, which suggests this is a benign condition and link has
otherwise successfully run to completion. This is however not the case,
the link terminates right away with no further messages and no output
produced.
Use the general error or warning info callback then, preserving the
message format. Also set a BFD error condition so that a failure is
unambiguously reported. Complement the change with a set of suitable
test suite additions.
bfd/
* elfxx-mips.c (_bfd_mips_elf_relocate_section)
<bfd_reloc_outofrange>: Call `->einfo' rather than `->warning'.
Call `bfd_set_error'.
ld/
* testsuite/ld-mips-elf/unaligned-jalx-0.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-1.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-2.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-0.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-2.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-0.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-2.d: New test.
* testsuite/ld-mips-elf/unaligned-lwpc-0.d: New test.
* testsuite/ld-mips-elf/unaligned-lwpc-1.d: New test.
* testsuite/ld-mips-elf/unaligned-lwpc-2.d: New test.
* testsuite/ld-mips-elf/unaligned-lwpc-3.d: New test.
* testsuite/ld-mips-elf/unaligned-ldpc-0.d: New test.
* testsuite/ld-mips-elf/unaligned-ldpc-1.d: New test.
* testsuite/ld-mips-elf/unaligned-ldpc-2.d: New test.
* testsuite/ld-mips-elf/unaligned-ldpc-3.d: New test.
* testsuite/ld-mips-elf/unaligned-ldpc-4.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-0.s: New test source.
* testsuite/ld-mips-elf/unaligned-jalx-1.s: New test source.
* testsuite/ld-mips-elf/unaligned-jalx-2.s: New test source.
* testsuite/ld-mips-elf/unaligned-insn.s: New test source.
* testsuite/ld-mips-elf/unaligned-lwpc-0.s: New test source.
* testsuite/ld-mips-elf/unaligned-lwpc-1.s: New test source.
* testsuite/ld-mips-elf/unaligned-lwpc-2.s: New test source.
* testsuite/ld-mips-elf/unaligned-lwpc-3.s: New test source.
* testsuite/ld-mips-elf/unaligned-ldpc-0.s: New test source.
* testsuite/ld-mips-elf/unaligned-ldpc-1.s: New test source.
* testsuite/ld-mips-elf/unaligned-ldpc-2.s: New test source.
* testsuite/ld-mips-elf/unaligned-ldpc-3.s: New test source.
* testsuite/ld-mips-elf/unaligned-ldpc-4.s: New test source.
* testsuite/ld-mips-elf/unaligned-syms.s: New test source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
H.J. Lu [Wed, 25 May 2016 18:23:40 +0000 (11:23 -0700)]
Enable VREX for all AVX512 directives
Add all AVX512 bits to CPU_ANY_AVX_FLAGS.
* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
CPU_ANY_AVX_FLAGS.
* i386-init.h: Regenerated.
H.J. Lu [Wed, 25 May 2016 17:49:25 +0000 (10:49 -0700)]
Enable VREX for AVX512 directives
Enable VREX for AVX512 instructions with upper 16 vector registers.
gas/
PR gas/20141
* testsuite/gas/i386/i386.exp: Run x86-64-pr20141.
* testsuite/gas/i386/x86-64-pr20141.d: New file.
* testsuite/gas/i386/x86-64-pr20141.s: Likewise.
opcodes/
PR gas/20141
* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
* i386-init.h: Regenerated.
projects / external / binutils.git / log