Alyssa Rosenzweig [Sat, 13 Nov 2021 19:26:57 +0000 (14:26 -0500)]
asahi: Remove obnoxious workaround
Now that we're not hardcoded any magic BO IDs, there is no minimum
number of allocations needed. Remove the unneeded -- and obnoxious --
workaround of allocating unused BOs on startup.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
Alyssa Rosenzweig [Sat, 13 Nov 2021 19:25:47 +0000 (14:25 -0500)]
asahi: Remove silly magic numbers
These are unnecessary now that the structure of agx_map_* is better
understood.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
Alyssa Rosenzweig [Sat, 13 Nov 2021 19:24:01 +0000 (14:24 -0500)]
asahi: Fix agx_map_* structures
Dougall Johnson observed these structures make more sense with indices[]
first in the entries and indices[] absent from the header. Then the
sentinel entry disappears, nr_entries makes more sense, and a few magic
numbers pop out. Many thanks to Dougall's astute eyes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
Alyssa Rosenzweig [Sat, 13 Nov 2021 18:53:43 +0000 (13:53 -0500)]
asahi: Allocate special scratch buffers
Seem to be used for preemption.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
Alyssa Rosenzweig [Sat, 13 Nov 2021 18:53:34 +0000 (13:53 -0500)]
asahi: Deflake addresses
Reported by Dougall.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
Alyssa Rosenzweig [Sun, 31 Oct 2021 15:13:58 +0000 (11:13 -0400)]
asahi: Rename PANDECODE->AGXDECODE
Fix remnant of the Panfrost decoder fork.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13784>
Alyssa Rosenzweig [Mon, 8 Nov 2021 00:51:19 +0000 (19:51 -0500)]
pan/bi: Add XML for LD_BUFFER
Encoded like LOAD.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Mon, 15 Nov 2021 23:15:42 +0000 (18:15 -0500)]
pan/bi: Suppress uniform validation for LD_BUFFER
Seems to be ok and used by the DDK...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Mon, 8 Nov 2021 00:50:51 +0000 (19:50 -0500)]
pan/bi: Confirm IDP unit on Valhall
Based on Anandtech which gives 8-bit dot product throughput on Valhall
under FMA and not consistent with SFU.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Thu, 4 Nov 2021 23:08:36 +0000 (19:08 -0400)]
pan/bi: Forbid unaligned staging registers on Valhall
Would've saved me some debugging with the computerator. I keep
forgetting about this nuance. Enforce it in the assembler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Thu, 4 Nov 2021 00:22:26 +0000 (20:22 -0400)]
pan/bi: Add XML for assembling Valhall image stores
Not complete yet but let's get some tests in early. Document the new
instructions.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Mon, 15 Nov 2021 23:19:57 +0000 (18:19 -0500)]
pan/bi: Add Valhall's special FMA_RSCALE instructions
Like Bifrost, but exposed as separate physical instructions.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Mon, 15 Nov 2021 23:19:08 +0000 (18:19 -0500)]
pan/bi: Add sqrt form of Valhall FREXPM
Like Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Mon, 15 Nov 2021 23:18:55 +0000 (18:18 -0500)]
pan/bi: Add full form of Valhall MUX instruction
Like Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Alyssa Rosenzweig [Mon, 15 Nov 2021 23:18:23 +0000 (18:18 -0500)]
pan/bi: Annotate Valhall instructions with units
Based on analyzing the cycle counts reported by the Mali offline
compiler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>
Mike Blumenkrantz [Thu, 5 Aug 2021 15:32:52 +0000 (11:32 -0400)]
zink: enable PIPE_TEXTURE_TRANSFER_COMPUTE on non-cpu drivers
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13859>
Mike Blumenkrantz [Wed, 17 Nov 2021 21:45:20 +0000 (16:45 -0500)]
zink: use pb_slab_alloc_reclaimed(reclaim_all) for BAR heap sometimes
this forces a full slab reclaim any time the device is known to have a
too-small BAR in order to keep memory usage at a minimum when it might otherwise
balloon out and crash us
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13850>
Mike Blumenkrantz [Wed, 17 Nov 2021 21:43:55 +0000 (16:43 -0500)]
aux/pb: add a new slab alloc function for reclaiming all bo objects
sometimes a driver might want to always reclaim all bo objects in the course
of allocating a new bo. this is useful when it's known that a given memory
heap is very small and will likely need to keep its usage minimized
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13850>
Roland Scheidegger [Mon, 15 Nov 2021 17:27:44 +0000 (18:27 +0100)]
llvmpipe: adjust rounding for viewport scissoring
Some apps may try to use a viewport adjusted by 0.5 pixels (among other
things) to emulate d3d9 pixel center, and in this case we would end up
with incorrect "fake scissor" box (shifted by 1 pixel), hence pixels
being incorrectly scissored away when permit_linear_rasterizer is set
(this happens even if the linear rasterizer is not used in the end).
So adjust the offset so that the half-way points get rounded down instead
of up.
(This is all a bit iffy I think since we don't use fractional
boxes (with 8 subpixel bits) anywhere yet, but at least without msaa
it should work out.)
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13794>
Eric Engestrom [Wed, 17 Nov 2021 20:30:43 +0000 (20:30 +0000)]
docs: add 22.0 branchpoint date for perspective
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13848>
Eric Engestrom [Wed, 17 Nov 2021 20:28:17 +0000 (20:28 +0000)]
docs: add 21.3.x release schedule
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13848>
Eric Engestrom [Wed, 17 Nov 2021 20:22:05 +0000 (20:22 +0000)]
docs: update calendar and link releases notes for 21.3.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13848>
Eric Engestrom [Wed, 17 Nov 2021 20:10:19 +0000 (20:10 +0000)]
docs: add release notes for 21.3.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13848>
Samuel Pitoiset [Tue, 16 Nov 2021 10:08:15 +0000 (11:08 +0100)]
radv: disable HTILE for D32S8 format and mipmaps on GFX10
Stencil texturing with HTILE doesn't work with mipmapping on Navi10-14,
it's a hw bug. RadeonSI and PAL have a workaround too.
This fixes 35 piglit failures with Zink on Navi10.
Cc: 21.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13814>
Tomeu Vizoso [Fri, 29 Oct 2021 09:00:32 +0000 (11:00 +0200)]
ci: Uprev Crosvm
And use my fork while we upstream some improvements to Crosvm that make
it more appropriate for using in CI.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12828>
Tomeu Vizoso [Wed, 8 Sep 2021 05:52:58 +0000 (07:52 +0200)]
virgl/ci: Run each dEQP instance in its own VM
Currently we run deqp-runner inside a single VM, which makes very poor
use of the available CPUs because Virgl has a bottleneck in the VMM that
serializes everything.
With this change, we can run several Crosvm instances in a runner and
make full use of the CPUs. Getting the same coverage with 3 runners
instead of 6.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12828>
Tomeu Vizoso [Wed, 17 Nov 2021 07:33:46 +0000 (08:33 +0100)]
ci: Remove syslogd
Crosvm doesn't need it any more.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12828>
Tomeu Vizoso [Wed, 8 Sep 2021 05:42:49 +0000 (07:42 +0200)]
virgl/ci: Set GALLIVM_PERF=nopt,no_quad_lod
nopt will disable some shader optimizations that slow down test runs for
no gain.
no_quad_lod will disable some speed hacks that can cause inaccurate
results.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12828>
Tomeu Vizoso [Wed, 8 Sep 2021 05:40:23 +0000 (07:40 +0200)]
ci: Don't set GALLIVM_PERF in the scripts
Instead, let gitlab-ci.yml files define it.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12828>
Tomeu Vizoso [Wed, 8 Sep 2021 05:38:59 +0000 (07:38 +0200)]
ci: Create symlink to /install early
So we can use well-known absolute paths in configuration files.
Otherwise, the install dir is within $CI_PROJECT_DIR, which changes
between jobs.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12828>
Mike Blumenkrantz [Thu, 5 Aug 2021 19:28:52 +0000 (15:28 -0400)]
gallium: implement compute pbo download
this reworks PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER into an
enum as PIPE_CAP_TEXTURE_TRANSFER_MODES, enabling drivers to choose
a (sometimes) faster, compute-based download mechanism based on a new
pipe_screen hook
compute pbo download is implemented using shaders with a prolog to convert
the input format to generic rgb float values, then an epilog to convert
to the output value. the prolog and epilog are determined based on a vec4
of packed ubo data which is dynamically updated based on the API usage
currently, the only known limitations are:
* GL_ARB_texture_cube_map_array is broken somehow (and disabled)
* AMD hardware somehow can't do depth readback?
otherwise it should work for every possible case
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11984>
Mike Blumenkrantz [Wed, 17 Nov 2021 23:16:14 +0000 (18:16 -0500)]
mesa/st: make some pbo functions public
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11984>
Mike Blumenkrantz [Tue, 16 Nov 2021 15:14:37 +0000 (10:14 -0500)]
mesa/st: make sampler_type_for_target public
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11984>
Mike Blumenkrantz [Mon, 8 Nov 2021 17:33:57 +0000 (12:33 -0500)]
gallium: rename PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
this is now a bitfield enum for more functionality
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11984>
Mike Blumenkrantz [Mon, 8 Nov 2021 17:30:26 +0000 (12:30 -0500)]
gallium: add pipe_screen::is_compute_copy_faster hook
this can be used to query whether a driver expects a given texture
copy to be faster as a compute shader or using cpu/gfx transfers
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11984>
Dylan Baker [Thu, 18 Nov 2021 01:03:49 +0000 (17:03 -0800)]
turnip: don't use mesa/macros.h to get utils/rounding.h
For hopefully obvious reasons.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13853>
Pierre-Eric Pelloux-Prayer [Wed, 17 Nov 2021 14:45:19 +0000 (15:45 +0100)]
radeonsi/sqtt: increase the default buffer size to 32MB
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13838>
Pierre-Eric Pelloux-Prayer [Wed, 17 Nov 2021 14:40:31 +0000 (15:40 +0100)]
radeonsi: unreference framebuffer state after use
util_copy_framebuffer_state increases refcounts, so we have
to decrement them afterwards.
Fixes:
b1b491cdbba ("radeonsi: add a faster clear path for glClearTexImage")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5631
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13838>
Iago Toral Quiroga [Wed, 17 Nov 2021 12:55:48 +0000 (13:55 +0100)]
broadcom/compiler: fix early fragment tests setup
When early fragment tests are mandated by the shader, we must use
the Z value produced by the FEP even if there are elements that
would typically require late fragment tests (such as discards,
sample to coverage, etc).
This change means we also need to be a bit more careful when
we promote shaders to use early fragment tests so we don't
promote anything with discards for example.
Fixes:
dEQP-VK.fragment_operations.early_fragment.discard_early_fragment_tests_depth
dEQP-VK.fragment_operations.early_fragment.discard_early_fragment_tests_stencil
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13837>
Joshua Ashton [Tue, 6 Jul 2021 14:01:10 +0000 (15:01 +0100)]
radv: Implement VK_EXT_image_view_min_lod
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13820>
Joshua Ashton [Tue, 16 Nov 2021 15:03:42 +0000 (15:03 +0000)]
vulkan: Update the XML and headers to 1.2.199
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13820>
Joshua Ashton [Tue, 6 Jul 2021 13:19:46 +0000 (14:19 +0100)]
radv: Expose min_lod in *_make_texture_descriptor
We'll need this going forward for VK_EXT_image_view_min_lod.
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13820>
Joshua Ashton [Tue, 6 Jul 2021 13:28:20 +0000 (14:28 +0100)]
radv: Refactor S_FIXED to radv_float_to_{s,u}fixed
We'll need to use this in radv_image for VK_EXT_image_view_min_lod.
Additionally, creates signed/unsigned variants to avoid sign-extending where we don't need to.
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13820>
Mike Blumenkrantz [Wed, 17 Nov 2021 19:15:18 +0000 (14:15 -0500)]
zink: clamp to 500 max batch states on nvidia
I've been advised that leaving this unclamped will use up all the fds
allotted to a process
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13844>
Mike Blumenkrantz [Tue, 16 Nov 2021 22:45:58 +0000 (17:45 -0500)]
zink: fail context creation more gracefully
handle some cases where context creation fails earlier than expected
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13844>
Mike Blumenkrantz [Wed, 17 Nov 2021 21:48:28 +0000 (16:48 -0500)]
zink: fix memory availability reporting
this shouldn't report the budgeted available memory, it should return
the total memory, as that's what this api expects
Fixes:
ff4ba3d4a77 ("zink: support PIPE_CAP_QUERY_MEMORY_INFO")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13849>
Mike Blumenkrantz [Wed, 17 Nov 2021 21:46:49 +0000 (16:46 -0500)]
zink: use IMMUTABLE for dummy xfb buffer
this is never getting read back or anything so don't waste BAR allocation
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13849>
Mike Blumenkrantz [Wed, 17 Nov 2021 21:42:50 +0000 (16:42 -0500)]
zink: demote BAR allocations to device-local on oom
ideally this shouldn't happen, but it's better than crashing even if
it may crash later from attempting to map
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13849>
Mike Blumenkrantz [Wed, 17 Nov 2021 21:47:16 +0000 (16:47 -0500)]
zink: set zink_resource_object::host_visible based on actual bo placement
the properties determined before allocation may not be the same as what gets
allocated
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13849>
Mike Blumenkrantz [Wed, 17 Nov 2021 21:41:34 +0000 (16:41 -0500)]
zink: always use slab allocation placement for domains
this allows the actual bo to have its memory type changed if necessary
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13849>
Mike Blumenkrantz [Wed, 17 Nov 2021 18:22:39 +0000 (13:22 -0500)]
zink: add error for bo allocation failure
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13849>
Marek Olšák [Sun, 31 Oct 2021 05:02:02 +0000 (01:02 -0400)]
glx: add a workaround to glXDestroyWindow for Viewperf2020/Sw
This fixes:
X Error of failed request: GLXBadWindow
Major opcode of failed request: 152 (GLX)
Minor opcode of failed request: 32 (X_GLXDestroyWindow)
Serial number of failed request: 9667
Current serial number in output stream: 9674
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13611>
Iván Briano [Wed, 17 Nov 2021 19:02:26 +0000 (11:02 -0800)]
intel/nir: also allow unknown format for getting the size of a storage image
Fixes:
fa251cf111df ("intel/nir: allow unknown format in lowering of storage images")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13847>
Ian Romanick [Wed, 17 Nov 2021 01:02:50 +0000 (17:02 -0800)]
glsl/nir: Don't build soft float64 when it cannot be used
Fixes:
82d9a37a59c ("glsl/nir: Add a shared helper for building float64 shaders")
Closes: #5556
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13828>
Mike Blumenkrantz [Thu, 11 Nov 2021 16:57:49 +0000 (11:57 -0500)]
zink: implement multiplanar modifier handling
it turns out this is trivial as long as dri gives usable resource templates
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13799>
Mike Blumenkrantz [Thu, 11 Nov 2021 20:10:45 +0000 (15:10 -0500)]
dri2: set dimensions on dmabuf import planes
this is unusable for some drivers without the plane size attached
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13799>
Mike Blumenkrantz [Thu, 11 Nov 2021 17:23:29 +0000 (12:23 -0500)]
zink: always set matching resource export type for dmabuf creation
both of these need to be set if one is
cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13799>
Mike Blumenkrantz [Thu, 11 Nov 2021 17:11:33 +0000 (12:11 -0500)]
zink: stop using VK_IMAGE_LAYOUT_PREINITIALIZED for dmabuf
this is illegal
cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13799>
Jason Ekstrand [Wed, 17 Nov 2021 15:24:40 +0000 (09:24 -0600)]
vulkan/sync: Rework asserts a bit
ANV currently smashes off the TIMELINE bit depending on whether or not
the i915 interface supports them, triggering assert(!type->get_value).
Instead of requiring ANV to smash off function pointers, let the extra
function pointers through and then assert on the feature bits before the
function pointers get used. This should give us roughly the same amount
of assert protection while side-stepping the feature disabling problem.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13839>
Filip Gawin [Tue, 16 Nov 2021 23:46:19 +0000 (00:46 +0100)]
glsl: fix trivial strict aliasing warning
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13827>
Omar Akkila [Fri, 12 Nov 2021 17:51:26 +0000 (12:51 -0500)]
llvmpipe: page-align memory allocations
Allows memory allocated by llvmpipe_allocate_memory_fd to be
mappable to guests in virtualized environments like KVM which
requires page-aligned memory.
llvmpipe_allocate_memory is updated similarly for consistency.
Signed-off-by: Omar Akkila <omar.akkila@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13793>
Connor Abbott [Mon, 8 Nov 2021 18:36:36 +0000 (19:36 +0100)]
ir3: Stop inserting nops during scheduling
Not necessary since nothing uses it anymore. This might have a slight
effect on spilling with multiple blocks, but no shader-db difference
because nothing spills.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13722>
Connor Abbott [Mon, 8 Nov 2021 18:13:38 +0000 (19:13 +0100)]
ir3/postsched: Only prefer tex/sfu if they are soft-ready
Otherwise we schedule an SFU depending on a tex as soon as the tex is
scheduled, which is very much not what we want.
Note that sstall is helped more than nops are hurt, and the shaders with
the largest nop regressions also have sstall helped. However (sy) is
also very much helped.
total nops in shared programs: 345482 -> 345986 (0.15%)
nops in affected programs: 5731 -> 6235 (8.79%)
helped: 15
HURT: 81
helped stats (abs) min: 1 max: 9 x̄: 3.27 x̃: 3
helped stats (rel) min: 0.50% max: 16.00% x̄: 8.55% x̃: 10.26%
HURT stats (abs) min: 1 max: 72 x̄: 6.83 x̃: 4
HURT stats (rel) min: 0.57% max: 400.00% x̄: 32.50% x̃: 13.16%
95% mean confidence interval for nops value: 3.34 7.16
95% mean confidence interval for nops %-change: 13.07% 39.10%
Nops are HURT.
total sstall in shared programs: 133804 -> 132381 (-1.06%)
sstall in affected programs: 4743 -> 3320 (-30.00%)
helped: 68
HURT: 24
helped stats (abs) min: 1 max: 153 x̄: 21.88 x̃: 8
helped stats (rel) min: 1.79% max: 100.00% x̄: 33.20% x̃: 28.00%
HURT stats (abs) min: 1 max: 11 x̄: 2.71 x̃: 2
HURT stats (rel) min: 1.02% max: 200.00% x̄: 17.73% x̃: 5.59%
95% mean confidence interval for sstall value: -22.05 -8.89
95% mean confidence interval for sstall %-change: -27.60% -12.22%
Sstall are helped.
total (ss) in shared programs: 35471 -> 35481 (0.03%)
(ss) in affected programs: 462 -> 472 (2.16%)
helped: 9
HURT: 15
helped stats (abs) min: 1 max: 2 x̄: 1.11 x̃: 1
helped stats (rel) min: 4.17% max: 33.33% x̄: 14.00% x̃: 7.69%
HURT stats (abs) min: 1 max: 3 x̄: 1.33 x̃: 1
HURT stats (rel) min: 1.19% max: 50.00% x̄: 12.27% x̃: 8.33%
95% mean confidence interval for (ss) value: -0.14 0.97
95% mean confidence interval for (ss) %-change: -5.11% 9.94%
Inconclusive result (value mean confidence interval includes 0).
total (sy) in shared programs: 13522 -> 13288 (-1.73%)
(sy) in affected programs: 422 -> 188 (-55.45%)
helped: 22
HURT: 1
helped stats (abs) min: 1 max: 21 x̄: 10.68 x̃: 10
helped stats (rel) min: 8.00% max: 94.44% x̄: 56.58% x̃: 56.94%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 25.00% max: 25.00% x̄: 25.00% x̃: 25.00%
95% mean confidence interval for (sy) value: -13.18 -7.17
95% mean confidence interval for (sy) %-change: -65.48% -40.59%
(sy) are helped.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13722>
Connor Abbott [Wed, 3 Nov 2021 17:06:17 +0000 (18:06 +0100)]
ir3/postsched: Rewrite delay handling
Analogous to the pre-RA scheduler. Unfortunately this time it's a bit
more involved because we have to correctly handle (rptN), which is
already relevant for swz. This means we need the index of the
destination register that conflicts with the source register, to handle
swz, and we need to expose that part of ir3_delay. But once that's done,
we can delete ir3_delay_calc_postra.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13722>
Connor Abbott [Mon, 8 Nov 2021 16:20:39 +0000 (17:20 +0100)]
ir3/delay: Ignore earlier definitions to the same register
We have a situation in some skia shaders like:
add.f r0.x, ...
(rpt2)nop
mul.f ..., r0.x
sam (xyzw) r0.x, ...
rcp ..., r0.x
Notice that rcp uses the result of the sam instruction, not the add.f,
but we didn't keep track of which instructions kill the sources in
ir3_delay, so we'd add an extra nop, resulting in a disagreement betwen
ir3_delay and the scheduling graph. Since postsched is correct, fix
ir3_delay. This only results in some very slight shader-db changes but
keeps the next commit from changing things.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13722>
Connor Abbott [Wed, 3 Nov 2021 17:00:51 +0000 (18:00 +0100)]
ir3/postsched: Handle sync dependencies better
We want to model soft dependencies, but because of how there's only a
single bit to wait on all of them, there may be unnecessary delays
inserted when a (sy)-consumer follows an unrelated (sy)-producer.
Previously there was some code to try to work around this, but we can
just model it directly using the sfu_delay and tex_delay cycle counts
that we have to maintain anyway and delete it.
This also gets rid of the calls to ir3_delay_postra with soft=true which
would be more complicated to handle in the next commit.
There is a functional change here: the idea of preferring less nop's
over critical path length (max_delay) up to 3 nops is kept (and we
delete the TODO which is already sort-of resolved by it), but delays due
to (ss)/(sy) and nops are now treated equally, rather than always
preferring nops over syncs. So if our estimate indicates that scheduling
an (ss) consumer will result in a wait of one cycle and there's another
instruction that will require one nop, we will treat them otherwise
equal and choose based on max_delay instead. This results in more
sstall, but the decrease in nops is much greater.
total nops in shared programs: 376613 -> 345482 (-8.27%)
nops in affected programs: 275483 -> 244352 (-11.30%)
helped: 3226
HURT: 110
helped stats (abs) min: 1 max: 78 x̄: 9.73 x̃: 7
helped stats (rel) min: 0.19% max: 100.00% x̄: 19.48% x̃: 13.68%
HURT stats (abs) min: 1 max: 16 x̄: 2.43 x̃: 2
HURT stats (rel) min: 0.00% max: 150.00% x̄: 13.34% x̃: 4.36%
95% mean confidence interval for nops value: -9.61 -9.06
95% mean confidence interval for nops %-change: -19.01% -17.78%
Nops are helped.
total sstall in shared programs: 126195 -> 133806 (6.03%)
sstall in affected programs: 79440 -> 87051 (9.58%)
helped: 300
HURT: 1922
helped stats (abs) min: 1 max: 15 x̄: 4.72 x̃: 4
helped stats (rel) min: 1.05% max: 100.00% x̄: 17.15% x̃: 14.55%
HURT stats (abs) min: 1 max: 29 x̄: 4.70 x̃: 4
HURT stats (rel) min: 0.00% max: 900.00% x̄: 25.38% x̃: 10.53%
95% mean confidence interval for sstall value: 3.22 3.63
95% mean confidence interval for sstall %-change: 17.50% 21.78%
Sstall are HURT.
total (ss) in shared programs: 35190 -> 35472 (0.80%)
(ss) in affected programs: 6433 -> 6715 (4.38%)
helped: 163
HURT: 401
helped stats (abs) min: 1 max: 2 x̄: 1.06 x̃: 1
helped stats (rel) min: 1.92% max: 33.33% x̄: 11.53% x̃: 10.00%
HURT stats (abs) min: 1 max: 3 x̄: 1.13 x̃: 1
HURT stats (rel) min: 1.56% max: 100.00% x̄: 15.33% x̃: 12.50%
95% mean confidence interval for (ss) value: 0.41 0.59
95% mean confidence interval for (ss) %-change: 6.22% 8.93%
(ss) are HURT.
total (sy) in shared programs: 13476 -> 13521 (0.33%)
(sy) in affected programs: 669 -> 714 (6.73%)
helped: 30
HURT: 78
helped stats (abs) min: 1 max: 2 x̄: 1.13 x̃: 1
helped stats (rel) min: 4.00% max: 50.00% x̄: 21.22% x̃: 21.11%
HURT stats (abs) min: 1 max: 2 x̄: 1.01 x̃: 1
HURT stats (rel) min: 3.45% max: 100.00% x̄: 31.93% x̃: 25.00%
95% mean confidence interval for (sy) value: 0.23 0.60
95% mean confidence interval for (sy) %-change: 11.19% 23.15%
(sy) are HURT.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13722>
Connor Abbott [Fri, 5 Nov 2021 14:43:13 +0000 (15:43 +0100)]
ir3/postsched: Fix copy-paste mistake
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13722>
Connor Abbott [Fri, 29 Oct 2021 20:56:05 +0000 (22:56 +0200)]
ir3/sched: Rewrite delay handling
The old code walked the instructions between each ready instruction and
each of its parents for every instruction, which can quickly become
accidentally quadratic. Instead we keep track of the current
"instruction pointer" of the to-be-scheduled instruction, and for each
ready instruction calculate an "earliest possible IP" which is the IP
that needs to be reached before we can schedule it. Because this stays
constant as soon as an instruction becomes ready, we never have to
recompute it and each call to ir3_delay_calc_prera() becomes a simple
comparison and subtract. We only need to iterate over the children and
update their earliest_ip when scheduling an instruction, and we already
do that in util_day_prune_head() so it should be cheap.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13722>
Connor Abbott [Mon, 8 Nov 2021 14:31:29 +0000 (15:31 +0100)]
util/dag: Add dag_add_edge_max_data
This will be useful for when the edge data represents a delay of some
sort, like it will with ir3.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13722>
Connor Abbott [Mon, 8 Nov 2021 14:06:33 +0000 (15:06 +0100)]
util/dag: Make edge data a uintptr_t
Nobody was actually using it as a pointer, and I'm going to introduce a
shared function which relies on it not being a pointer so let's fix this
once and for all.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13722>
Erico Nunes [Wed, 17 Nov 2021 11:01:03 +0000 (12:01 +0100)]
ci: temporarily disable lima CI
The lima board farm will be unavailable for a few days, so disable it
to avoid CI failures.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13595>
Kenneth Graunke [Tue, 16 Nov 2021 03:14:01 +0000 (19:14 -0800)]
iris: Tidy code in iris_use_pinned_bo a bit
Now that we aren't short-circuiting most of the code, we should probably
reorganize it a little bit. Tagged with fixes just so we pull all the
refactors together as one group.
Fixes:
b21e916a628 ("iris: Combine iris_use_pinned_bo and add_exec_bo")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13808>
Kenneth Graunke [Tue, 16 Nov 2021 03:08:55 +0000 (19:08 -0800)]
iris: Check for cross-batch flushing whenever a buffer is newly written.
We need to perform cross-batch flushing if any batch writes to a BO
while others refer to it. We checked this case when recording a new
BO in the list which we'd never seen before. However, we neglected to
handle the case when we already read from a BO, but then began writing
to it. That new write may provoke a conflict between existing reads
in other batches, so we need to re-check the cross-batch flushing.
Caught by Piglit's copyteximage when forcing blits and copies to use
a new IRIS_BATCH_BLITTER that isn't upstream yet. But this bug could
be provoked by render/compute work today...we just hadn't noticed it.
Fixes:
b21e916a628 ("iris: Combine iris_use_pinned_bo and add_exec_bo")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13808>
Kenneth Graunke [Tue, 16 Nov 2021 03:02:31 +0000 (19:02 -0800)]
iris: Make a helper function for cross-batch dependency flushing
This should have no functional change, but it's tagged with Fixes
anyway because it's needed for the bug fix in the next patch.
Fixes:
b21e916a628 ("iris: Combine iris_use_pinned_bo and add_exec_bo")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13808>
Alejandro Piñeiro [Wed, 17 Nov 2021 09:44:49 +0000 (10:44 +0100)]
v3d,v3dv: move TFU register definition to a common header
We are using the same definitions for both OpenGL and Vulkan, so let's
move it to common.
As we are here we are also adding versioning on the TFU register
definition. Those are basically register bit places, so really likely
to change between versions.
Adding 33 as it is the first version they got defined.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13832>
Samuel Pitoiset [Tue, 16 Nov 2021 18:07:55 +0000 (19:07 +0100)]
radv: simplify re-using cache entries in radv_pipeline_cache_insert_shaders()
If entry->shaders[i] is NULL, shaders[i] should be also NULL, so the
else condition is a no-op.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13823>
Iago Toral Quiroga [Tue, 16 Nov 2021 11:46:29 +0000 (12:46 +0100)]
v3dv: fix internal bpp of D/S formats
Depth/stencil formats can, at worse (d32/d24s8), be exactly 32bpp,
which is the minimum we can program for the internal format.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13816>
Pavel Asyutchenko [Sat, 11 Sep 2021 17:08:20 +0000 (20:08 +0300)]
llvmpipe: enable PIPE_CAP_FBFETCH_COHERENT
llvmpipe's fragment shaders are always run sequentially and
in API order for a single tile, so it's impossible to have
out of order render target writes requiring fetch barriers.
Issues fixed in previous commits were actually breaking most
piglit/deqp tests for coherent extension variant.
Signed-off-by: Pavel Asyutchenko <sventeam@yandex.ru>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13252>
Pavel Asyutchenko [Thu, 7 Oct 2021 18:49:21 +0000 (21:49 +0300)]
llvmpipe: remove dead args from load_unswizzled_block
They were only used in fs_fb_fetch.
Signed-off-by: Pavel Asyutchenko <sventeam@yandex.ru>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13252>
Pavel Asyutchenko [Thu, 7 Oct 2021 18:39:00 +0000 (21:39 +0300)]
llvmpipe: fix FB fetch with non 32-bit render target formats
Use lp_build_fetch_rgba_soa instead of lp_build_unpack_rgba_soa.
This one was failing most of deqp *framebuffer_fetch* tests.
Signed-off-by: Pavel Asyutchenko <sventeam@yandex.ru>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13252>
Pavel Asyutchenko [Thu, 7 Oct 2021 17:57:16 +0000 (20:57 +0300)]
llvmpipe: protect from doing FB fetch of missing buffers
Signed-off-by: Pavel Asyutchenko <sventeam@yandex.ru>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13252>
Pavel Asyutchenko [Wed, 6 Oct 2021 20:27:50 +0000 (23:27 +0300)]
llvmpipe: fix gl_FragColor and gl_LastFragData[0] combination
Signed-off-by: Pavel Asyutchenko <sventeam@yandex.ru>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13252>
Pavel Asyutchenko [Wed, 8 Sep 2021 20:21:18 +0000 (23:21 +0300)]
llvmpipe: fix wrong assumption on FB fetch shader opacity
In certain cases variant->opaque could be set to true, which
reset command list for tiles fully covered by a triangle
with this shader. This is obviously wrong in presence of
framebuffer fetch.
Signed-off-by: Pavel Asyutchenko <sventeam@yandex.ru>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13252>
Mike Blumenkrantz [Fri, 5 Nov 2021 16:00:25 +0000 (12:00 -0400)]
zink: implement pipe_context::draw_vertex_state
rough implementation, but it should be a decent start
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13692>
Vasily Khoruzhick [Wed, 6 Oct 2021 14:16:33 +0000 (07:16 -0700)]
lima: add more wrap modes
Using 1 bit per wrap mode looked very suspicious and after some
experiments it turns out it's 3-bit enum.
Border color is also here, it sits right after depth field. For
some reason it uses 16 bit per channel just like for clear color in RSW
GL_CLAMP mode is broken for nearest filter just as on Midgard, so add
the same workaround - use GL_CLAMP_TO_EDGE for nearest filter.
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13213>
Vasily Khoruzhick [Wed, 6 Oct 2021 14:01:18 +0000 (07:01 -0700)]
lima: handle 1D samplers
It's just a matter of changing number of dimensions in texture
descriptor.
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13213>
Vasily Khoruzhick [Wed, 6 Oct 2021 06:12:28 +0000 (23:12 -0700)]
lima: add support for 3D textures
It looks like MBS format used by blob doesn't distinguish sampler2D from
sampler3D, so load texture instruction is the same for 2D and 3D
textures.
So all we need to RE is texture descriptor for 3D textures, but blob
doesn't implement it, so we need to do some guesswork:
- unknown_3_1 looks like a depth since it sits after height/width and
always set to 1
- unknown_2_2 is exactly 3 bits and it follows wrap_t, so it must be
wrap_r
- missing part is texture type for 3D textures. By trial and error it
seems to be 4. First bit is only set for cubemap, so it's likely a
separate flag, and rest 2 bits look like number of tex dimensions akin
to midgard and later (thanks, panfrost!) with 0 for 1D, 1 for 2D
and 2 for 3D.
Put it all together and we have working 3D textures on lima!
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13213>
Mike Blumenkrantz [Tue, 16 Nov 2021 22:19:43 +0000 (17:19 -0500)]
zink: set suballocator bo size to aligned allocation size
this is the actual memory size
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13824>
Mike Blumenkrantz [Tue, 16 Nov 2021 21:27:59 +0000 (16:27 -0500)]
zink: block suballocator caching for swapchain/dmabuf images
these have pNext pointers which makes their memory uncacheable
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13824>
Marek Olšák [Sat, 6 Nov 2021 18:08:53 +0000 (14:08 -0400)]
radeonsi: don't use GS SGPR6 for the small prim cull info
use a user SGPR instead. This will be needed in the future.
Also don't upload small_prim_precision because it's passed via
VS_STATE_BITS.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13811>
Marek Olšák [Sun, 7 Nov 2021 15:46:04 +0000 (10:46 -0500)]
radeonsi: inline declare_vs_specific_input_sgprs
I think it was getting a little hard to follow.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13811>
Marek Olšák [Sun, 7 Nov 2021 21:43:13 +0000 (16:43 -0500)]
radeonsi: cull against clip planes, clipvertex, clip/cull distances in shader
The downside is that this duplicates shader code for clip/cull distances
in both the position and parameter portions of the shader.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13811>
Marek Olšák [Sun, 7 Nov 2021 20:49:19 +0000 (15:49 -0500)]
radeonsi: unify how ngg_cull_flags are set
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13811>
Jesse Natalie [Tue, 16 Nov 2021 15:05:45 +0000 (07:05 -0800)]
d3d12: Fix incorrect hash table usage
I'd assumed that since insert didn't take a deleter, it was
find-or-insert, not insert-or-replace. This caused a bo reference
leak if the same bo was used more than once in a batch.
Fixes:
fde36d79920 ("d3d12: Don't wait for GPU reads to do CPU reads")
Reviewed By: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13819>
Vasily Khoruzhick [Thu, 30 Sep 2021 04:34:01 +0000 (21:34 -0700)]
lima: add native txp support
Currently lima uses generic TXP lowering that results in downgrading
coords precision to FP16 since we have to do some calculations with
coords instead of loading them directly from varying.
Mali4x0 has native TXP support, however coords and projector have to
come from a single source.
Add NIR lowering pass that combines coords and projector into a single
backend-specific source and use it instead of generic lowering.
Unfortunately this change regresses one test, but it also fails in blob and
disassembly is now identical.
shader-db diff:
total instructions in shared programs: 15623 -> 15603 (-0.13%)
instructions in affected programs: 877 -> 857 (-2.28%)
helped: 7
HURT: 0
helped stats (abs) min: 2 max: 8 x̄: 2.86 x̃: 2
helped stats (rel) min: 0.87% max: 10.53% x̄: 4.93% x̃: 1.85%
95% mean confidence interval for instructions value: -4.95 -0.76
95% mean confidence interval for instructions %-change: -9.31% -0.55%
Instructions are helped.
total loops in shared programs: 3 -> 3 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total spills in shared programs: 136 -> 137 (0.74%)
spills in affected programs: 0 -> 1
helped: 0
HURT: 1
total fills in shared programs: 598 -> 602 (0.67%)
fills in affected programs: 0 -> 4
helped: 0
HURT: 1
Tested-by: Denis Pauk <pauk.denis@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13111>
Rob Clark [Sun, 14 Nov 2021 20:00:07 +0000 (12:00 -0800)]
isaspec: Add prototypes for expr evaluators
Add function prototypes for generated expr evaluators, to avoid a use-
before-declaration issue if an expression references a derived field.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13787>
Ilia Mirkin [Tue, 16 Nov 2021 04:41:59 +0000 (23:41 -0500)]
freedreno/ir3: adjust condition for when to use ldib
We have to use it any time that the image is writable. Otherwise writes
from the same invocation won't have posted into the texture cache.
See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5629
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13807>
Samuel Pitoiset [Mon, 15 Nov 2021 13:37:41 +0000 (14:37 +0100)]
nir: fix constant expression of ibitfield_extract
This fixes dEQP-VK.graphicsfuzz.cov-condition-bitfield-extract-integer.
For example, nir_ibitfield_extract(3, 1, 2) should return 1.
Cc: 21.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13791>
Jason Ekstrand [Mon, 15 Nov 2021 22:41:52 +0000 (16:41 -0600)]
vulkan: Add a dummy sync type
This is useful in WSI scenarios where you want to trivially signal a
fence or semaphore.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13427>
Jason Ekstrand [Fri, 12 Nov 2021 15:51:59 +0000 (09:51 -0600)]
vulkan,anv: Auto-detect syncobj features
Instead of having a bunch of const vk_sync_type for each permutation of
vk_drm_syncobj capabilities, have a vk_drm_syncobj_get_type helper which
auto-detects features. If a driver can't support a feature for some
reason (i915 got timeline support very late, for instance), they can
always mask off feature bits they don't want.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13427>
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