Richard Smith [Wed, 12 May 2021 00:34:14 +0000 (17:34 -0700)]
Add test for PR50039.
I believe Clang's behavior is correct according to the standard here,
but this is an unusual situation for which we had no test coverage, so
I'm adding some.
Richard Smith [Thu, 6 May 2021 01:56:58 +0000 (18:56 -0700)]
Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope.
This implements the direction proposed in
https://github.com/itanium-cxx-abi/cxx-abi/pull/126.
Differential Revision: https://reviews.llvm.org/D101968
Matt Arsenault [Thu, 6 May 2021 00:25:31 +0000 (20:25 -0400)]
GlobalISel: Don't hardcode varargs=false in resultsCompatible
Matt Arsenault [Tue, 11 May 2021 21:12:33 +0000 (17:12 -0400)]
AMDGPU: Fix assert on constant load from addrspacecasted pointer
This was trying to create a bitcast between different address spaces.
Matt Arsenault [Wed, 12 May 2021 00:10:55 +0000 (20:10 -0400)]
GlobalISel: Make constant fields const
Matt Arsenault [Tue, 4 May 2021 22:12:38 +0000 (18:12 -0400)]
GlobalISel: Split ValueHandler into assignment and emission classes
Currently the ValueHandler handles both selecting the type and
location for arguments, as well as inserting instructions needed to
handle them. Split this so that the determination of the argument
handling is independent of the function state. Currently the checks
for tail call compatibility do not follow the full assignment logic,
so it misses cases where arguments require nontrivial legalization.
This should help avoid targets ending up in a buggy state where the
argument evaluation may change in different contexts.
Matt Arsenault [Tue, 4 May 2021 21:32:09 +0000 (17:32 -0400)]
GlobalISel: Move AArch64 AssignFnVarArg to base class
We can handle the distinction easily enough in the generic code, and
this makes it easier to abstract the selection of type/location from
the code to insert code.
Jordan Rupprecht [Tue, 11 May 2021 23:08:53 +0000 (16:08 -0700)]
Revert "[GVN] Clobber partially aliased loads."
This reverts commit
6c570442318e2d3b8b13e95c2f2f588d71491acb.
It causes assertion errors due to widening atomic loads, and potentially causes miscompile elsewhere too. Repro, also posted to D95543:
```
$ cat repro.ll
; ModuleID = 'repro.ll'
source_filename = "repro.ll"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
%struct.widget = type { i32 }
%struct.baz = type { i32, %struct.snork }
%struct.snork = type { %struct.spam }
%struct.spam = type { i32, i32 }
@global = external local_unnamed_addr global %struct.widget, align 4
@global.1 = external local_unnamed_addr global i8, align 1
@global.2 = external local_unnamed_addr global i32, align 4
define void @zot(%struct.baz* %arg) local_unnamed_addr align 2 {
bb:
%tmp = getelementptr inbounds %struct.baz, %struct.baz* %arg, i64 0, i32 1
%tmp1 = bitcast %struct.snork* %tmp to i64*
%tmp2 = load i64, i64* %tmp1, align 4
%tmp3 = getelementptr inbounds %struct.baz, %struct.baz* %arg, i64 0, i32 1, i32 0, i32 1
%tmp4 = icmp ugt i64 %tmp2,
4294967295
br label %bb5
bb5: ; preds = %bb14, %bb
%tmp6 = load i32, i32* %tmp3, align 4
%tmp7 = icmp ne i32 %tmp6, 0
%tmp8 = select i1 %tmp7, i1 %tmp4, i1 false
%tmp9 = zext i1 %tmp8 to i8
store i8 %tmp9, i8* @global.1, align 1
%tmp10 = load i32, i32* @global.2, align 4
switch i32 %tmp10, label %bb11 [
i32 1, label %bb12
i32 2, label %bb12
]
bb11: ; preds = %bb5
br label %bb14
bb12: ; preds = %bb5, %bb5
%tmp13 = load atomic i32, i32* getelementptr inbounds (%struct.widget, %struct.widget* @global, i64 0, i32 0) acquire, align 4
br label %bb14
bb14: ; preds = %bb12, %bb11
br label %bb5
}
$ opt -O2 repro.ll -disable-output
opt: /home/rupprecht/src/llvm-project/llvm/lib/Transforms/Utils/VNCoercion.cpp:496: llvm::Value *llvm::VNCoercion::getLoadValueForLoad(llvm::LoadInst *, unsigned int, llvm::Type *, llvm::Instruction *, const llvm::DataLayout &): Assertion `SrcVal->isSimple() && "Cannot widen volatile/atomic load!"' failed.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0. Program arguments: /home/rupprecht/dev/opt -O2 repro.ll -disable-output
...
```
Lang Hames [Tue, 11 May 2021 23:04:00 +0000 (16:04 -0700)]
[JITLink] Fix bogus format string.
Leonard Chan [Thu, 6 May 2021 22:54:28 +0000 (15:54 -0700)]
[clang][Fuchsia] Introduce compat multilibs
These are GCC-compatible multilibs that use the generic Itanium C++ ABI
instead of the Fuchsia C++ ABI.
Differential Revision: https://reviews.llvm.org/D102030
Congzhe Cao [Tue, 11 May 2021 22:34:32 +0000 (18:34 -0400)]
[LoopInterchange] Fix legality for triangular loops
This is a bug fix in legality check.
When we encounter triangular loops such as the following form:
for (int i = 0; i < m; i++)
for (int j = 0; j < i; j++), or
for (int i = 0; i < m; i++)
for (int j = 0; j*i < n; j++),
we should not perform interchange since the number of executions
of the loop body will be different before and after interchange,
resulting in incorrect results.
Reviewed By: bmahjour
Differential Revision: https://reviews.llvm.org/D101305
Petr Hosek [Fri, 9 Apr 2021 18:53:59 +0000 (11:53 -0700)]
[Coverage] Support overriding compilation directory
When making compilation relocatable, for example in distributed
compilation scenarios, we want to set compilation dir to a relative
value like `.` but this presents a problem when generating reports
because if the file path is relative as well, for example `..`, you
may end up writing files outside of the output directory.
This change introduces a flag that allows overriding the compilation
directory that's stored inside the profile with a different value that
is absolute.
Differential Revision: https://reviews.llvm.org/D100232
Lang Hames [Tue, 11 May 2021 21:47:40 +0000 (14:47 -0700)]
[JITLink][MachO/x86_64] Expose API for creating eh-frame fixing passes.
These can be used to create eh-frame section fixing passes outside the usual
linker pipeline, which can be useful for tests and tools that just want to
verify or dump graphs.
Lang Hames [Tue, 11 May 2021 21:45:14 +0000 (14:45 -0700)]
[JITLink][x86-64] Add an x86_64 PointerSize constexpr.
This can be used in place of magic '8' values in generic x86-64 utilities.
Lang Hames [Tue, 11 May 2021 21:09:49 +0000 (14:09 -0700)]
[JITLink] Make LinkGraph debug dumps more readable.
This commit reorders some fields and fixes the width of others to try to
maintain more consistent columns. It also switches to long-hand scope
and linkage names, since LinkGraph dumps aren't read often enough for
single-character codes to be memorable.
Victor Huang [Tue, 11 May 2021 21:35:13 +0000 (16:35 -0500)]
[AIX][TLS] Diagnose use of unimplemented TLS models
Add front end diagnostics to report error for unimplemented TLS models set by
- compiler option `-ftls-model`
- attributes like `__thread int __attribute__((tls_model("local-exec"))) var_name;`
Reviewed by: aaron.ballman, nemanjai, PowerPC
Differential Revision: https://reviews.llvm.org/D102070
Congzhe Cao [Tue, 11 May 2021 22:06:41 +0000 (18:06 -0400)]
Revert "[LoopInterchange] Fix legality for triangular loops"
This reverts commit
29342291d25b83da97e74d75004b177ba41114fc.
The test case requires an assert build. Will add REQUIRES and re-commit.
Petr Hosek [Thu, 15 Apr 2021 08:22:04 +0000 (01:22 -0700)]
[llvm-cov] Support for v4 format in convert-for-testing
v4 moves function records to a dedicated section so we need to write
and read it separately.
https://reviews.llvm.org/D100535
Evandro Menezes [Tue, 11 May 2021 17:17:26 +0000 (12:17 -0500)]
[RISCV] Move instruction information into the RISCVII namespace (NFC)
Move instruction attributes into the `RISCVII` namespace and add associated helper functions.
Differential Revision: https://reviews.llvm.org/D102268
Nikita Popov [Tue, 11 May 2021 20:51:16 +0000 (22:51 +0200)]
[InstCombine] Clean up one-hot merge optimization (NFC)
Remove the requirement that the instruction is a BinaryOperator,
make the predicate check more compact and use slightly more
meaningful naming for the and operands.
Rob Suderman [Tue, 11 May 2021 20:40:03 +0000 (13:40 -0700)]
[mlir][tosa] Tosa elementwise broadcasting had some minor bugs
Updated tests to include broadcast of left and right. Includes
bypass if in-type and out-type match shape (no broadcasting).
Differential Revision: https://reviews.llvm.org/D102276
River Riddle [Tue, 11 May 2021 19:40:27 +0000 (12:40 -0700)]
[mlir] Elide large elements attrs when printing Operations in diagnostics
Diagnostics are intended to be read by users, and in most cases displayed in a terminal. When not eliding huge element attributes, in some cases we end up dumping hundreds of megabytes(gigabytes) to the terminal (or logs), completely obfuscating the main diagnostic being shown.
Differential Revision: https://reviews.llvm.org/D102272
Alex Orlov [Tue, 11 May 2021 20:46:00 +0000 (00:46 +0400)]
Removed unnecessary introduction of semi-colons.
Austin Kerbow [Tue, 11 May 2021 16:29:48 +0000 (09:29 -0700)]
[AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2
The waitcnt pass would increment the number of vmem events for some buffer
invalidates that were not handled by the pass.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D102252
Evgenii Stepanov [Wed, 5 May 2021 18:56:52 +0000 (11:56 -0700)]
[hwasan] Stress test for thread creation.
This test has two modes - testing reused threads with multiple loops of
batch create/join, and testing new threads with a single loop of
create/join per fork.
The non-reuse variant catches the problem that was fixed in D101881 with
a high probability.
Differential Revision: https://reviews.llvm.org/D101936
Craig Topper [Tue, 11 May 2021 19:24:56 +0000 (12:24 -0700)]
[RISCV] Regenerate stepvector.ll. NFC
It looks like the RV32 and RV64 prefixes were removed from the
RUN lines while another patch was in review that added check
lines that used them.
Christopher Pulido [Tue, 11 May 2021 20:03:04 +0000 (23:03 +0300)]
[OpenMP] Changes to enable MSVC ARM64 build of libomp
This is the first in a series of changes to the OpenMP runtime
that have been done internally by Microsoft. This patch makes
the necessary changes to enable libomp.dll to build with
the MSVC compiler targeting ARM64.
Differential Revision: https://reviews.llvm.org/D101173
Albion Fung [Tue, 11 May 2021 19:56:24 +0000 (14:56 -0500)]
[PowerPC] Improve codegen for int-to-fp conversion of subword vector extract
When an integer is converted into floating point in subword vector extract,
it can be done in 2 instructions instead of the 3+ instructions it generates
right now. This patch removes the uncessary generation.
Differential: https://reviews.llvm.org/D100604
Amara Emerson [Tue, 11 May 2021 00:57:47 +0000 (17:57 -0700)]
[AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects.
One test needed updating because the newly side-effect-free instructions were
now being DCE'd.
Vitaly Buka [Tue, 11 May 2021 07:15:17 +0000 (00:15 -0700)]
[NFC][LSAN] Limit the number of concurrent threads is the test
Test still fails with D88184 reverted.
The test was flaky on https://bugs.chromium.org/p/chromium/issues/detail?id=1206745 and
https://lab.llvm.org/buildbot/#/builders/sanitizer-x86_64-linux
Reviewed By: morehouse
Differential Revision: https://reviews.llvm.org/D102218
River Riddle [Tue, 11 May 2021 19:09:17 +0000 (12:09 -0700)]
[mlir] Move move capture in SparseElementsAttr::getValues
This was a TODO for the move to C++14. Now that the move has been completed, we can resolve it.
Sam Clegg [Tue, 11 May 2021 18:08:14 +0000 (11:08 -0700)]
[lld][WebAssembly] Remove relocation target verification
We have this extra step in wasm-ld that doesn't exist in other lld
backend which verifies the existing contents of the relocation targets.
This was originally intended as an extra form of double checking and an
aid to compiler developers. However it has always been somewhat
controversial and there have been suggestions in the past the we simply
remove it.
My motivation for removing it now is that its causing me a headache
when trying to fix an issue with negative addends. In the case of
negative addends that final result can be wrapped/negative but this
checking code would require significant modification to be able to deal
with that case. For example with some test cases I'm looking at I'm
seeing error like this:
```
wasm-ld: warning: /usr/local/google/home/sbc/dev/wasm/llvm-build/tools/lld/test/wasm/Output/merge-string.s.tmp.o:(.rodata_relocs): unexpected existing value for R_WASM_MEMORY_ADDR_I32: existing=
FFFFFFFA expected=
FFFFFFFFFFFFFFFA
```
Rather than try to refactor `calcExpectedValue` to somehow return two
different types of results (32 and 64-bit) depending on the relocation
type, I think we can just remove this code.
Differential Revision: https://reviews.llvm.org/D102265
Jim Ingham [Thu, 6 May 2021 21:14:35 +0000 (14:14 -0700)]
Add an "interrupt timeout" to Process, and pipe that through the
ProcessGDBRemote plugin layers.
Also fix a bug where if we tried to interrupt, but the ReadPacket
wakeup timer woke us up just after the timeout, we would break out
the switch, but then since we immediately check if the response is
empty & fail if it is, we could end up actually only giving a
small interval to the interrupt.
Differential Revision: https://reviews.llvm.org/D102085
Vladimir Vereschaka [Tue, 11 May 2021 18:39:15 +0000 (11:39 -0700)]
[libc++] Run `substitutes-in-compile-flags.sh.cpp` test on Windows.
Fix for substitutes-in-compile-flags.sh.cpp to run it properly on Windows platform.
Differential Revision: https://reviews.llvm.org/D102048
Mike Rice [Sat, 20 Mar 2021 00:39:04 +0000 (17:39 -0700)]
[OpenMP] Use compound operators for reduction combiner if available.
The OpenMP spec seems to require the compound operators be used for
+, *, &, |, and ^ reduction. So use these if a class has those operators.
If not try the simple operators as we did previously to limit the impact
to existing code.
Fixes: https://bugs.llvm.org/show_bug.cgi?id=48584
Differential Revision: https://reviews.llvm.org/D101941
Fangrui Song [Tue, 11 May 2021 18:38:32 +0000 (11:38 -0700)]
[clang] Support -fpic -fno-semantic-interposition for RISCV
-fno-semantic-interposition (only effective with -fpic) can optimize default
visibility external linkage (non-ifunc-non-COMDAT) variable access and function
calls to avoid GOT/PLT, by using local aliases, e.g.
```
int var;
__attribute__((optnone)) int fun(int x) { return x * x; }
int test() { return fun(var); }
```
-fpic (var and fun are dso_preemptable)
```
test:
.LBB1_1:
auipc a0, %got_pcrel_hi(var)
ld a0, %pcrel_lo(.LBB1_1)(a0)
lw a0, 0(a0)
// fun is preemptible by default in ld -shared mode. ld will create a PLT.
tail fun@plt
```
vs -fpic -fno-semantic-interposition (var and fun are dso_local)
```
test:
.Ltest$local:
.LBB1_1:
auipc a0, %pcrel_hi(.Lvar$local)
addi a0, a0, %pcrel_lo(.LBB1_1)
lw a0, 0(a0)
// The assembler either resolves .Lfun$local at assembly time (-mno-relax
// -fno-function-sections), or produces a relocation referencing a non-preemptible
// local symbol (which can avoid PLT).
tail .Lfun$local
```
Note: Clang's default -fpic is more aggressive than GCC -fpic: interprocedural
optimizations (including inlining) are available but local aliases are not used.
-fpic -fsemantic-interposition can disable interprocedural optimizations.
Depends on D101875
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D101876
Sam Clegg [Tue, 11 May 2021 18:15:45 +0000 (11:15 -0700)]
[lld][WebAssembly] Convert test to assembly. NFC.
Differential Revision: https://reviews.llvm.org/D102264
Roman Lebedev [Tue, 11 May 2021 18:19:41 +0000 (21:19 +0300)]
[X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): canonicalize to integer type
This way we don't have to duplicate i32/f32 and i64/f64 entries,
which was already forgotten to be done for a few tuples.
Fangrui Song [Tue, 11 May 2021 18:34:37 +0000 (11:34 -0700)]
[GlobalOpt] Remove heap SROA
GlobalOpt implements a heap SROA (SROA for an malloc allocatated struct or array
of structs) which is largely undertested (heap-sra-[1234].ll are basically the
same test with very little difference) and does not trigger at all when
bootstrapping clang (it only supports the case of one single store).
The heap SROA implementation causes PR50027 (GEP is not properly handled; crash or miscompile).
Just drop the implementation. I have deleted some obviously duplicated tests
but kept `heap-sra-[12]{,-no-nullopt}.ll`.
Reviewed By: aeubanks
Differential Revision: https://reviews.llvm.org/D102257
Amara Emerson [Sun, 24 Jan 2021 08:35:15 +0000 (00:35 -0800)]
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs.
This needs some tablegen changes so that we can actually import the patterns properly.
Differential Revision: https://reviews.llvm.org/D102204
Fangrui Song [Tue, 11 May 2021 18:29:45 +0000 (11:29 -0700)]
[RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
Similar to X86 D73230 and AArch64 D101872
With this change, we can set dso_local in clang's -fpic -fno-semantic-interposition mode,
for default visibility external linkage non-ifunc-non-COMDAT definitions.
For such dso_local definitions, variable access/taking the address of a
function/calling a function will go through a local alias to avoid GOT/PLT.
Reviewed By: jrtc27, luismarques
Differential Revision: https://reviews.llvm.org/D101875
Eli Friedman [Tue, 20 Oct 2020 20:08:07 +0000 (13:08 -0700)]
[ArgumentPromotion] Fix byval alignment handling.
Make sure the alignment of the generated operations matches the
alignment of the byval argument. Previously, we were just ignoring
alignment and getting lucky.
While I'm here, also delete the unnecessary "tail" handling.
Passing a pointer to a byval argument to a "tail" call is UB, so
rewriting to an alloca doesn't require any special handling.
Differential Revision: https://reviews.llvm.org/D89819
Sean Silva [Mon, 10 May 2021 21:30:22 +0000 (14:30 -0700)]
[mlir][ODS]: Add per-op cppNamespace.
This is useful for dialects that have logical subparts.
Differential Revision: https://reviews.llvm.org/D102200
Martin Storsjö [Fri, 26 Feb 2021 12:37:26 +0000 (14:37 +0200)]
[libcxx] [test] Fix filesystem permission tests for windows
On Windows, the permission bits are mapped down to essentially only
two possible states; readonly or readwrite. Normalize the checked
permission bitmask to match what the implementation will return.
Differential Revision: https://reviews.llvm.org/D101728
Pirama Arumuga Nainar [Wed, 5 May 2021 00:41:40 +0000 (17:41 -0700)]
[git-clang-format] Do not apply clang-format to symlinks
This fixes PR46992.
Git stores symlinks as text files and we should not format them even if
they have one of the requested extensions.
(Move the call to `cd_to_toplevel()` up a few lines so we can also print
the skipped symlinks during verbose output.)
Differential Revision: https://reviews.llvm.org/D101878
Nico Weber [Tue, 11 May 2021 15:43:48 +0000 (11:43 -0400)]
[lld/mac] Implement -sectalign
clang sometimes passes this flag along (see D68351), so we should implement it.
Differential Revision: https://reviews.llvm.org/D102247
Lang Hames [Tue, 11 May 2021 17:13:52 +0000 (10:13 -0700)]
Re-apply "[ORC-RT] Add unit test infrastructure, extensible_rtti..."
This reapplies
6d263b6f1c9 (which was reverted in
1c7c6f2b106) with a fix for a
CMake issue.
Peter Steinfeld [Tue, 11 May 2021 02:39:05 +0000 (19:39 -0700)]
[flang] Allow large and erroneous ac-implied-do's
We sometimes unroll an ac-implied-do of an array constructor into a flat list
of values. We then re-analyze the array constructor that contains the
resulting list of expressions. Such a list may or may not contain errors.
But when processing an array constructor with an unrolled ac-implied-do, the
compiler was building an expression to represent the extent of the resulting
array constructor containing the list of values. The number of operands
in this extent expression was based on the number of elements in the
unrolled list of values. For very large lists, this created an
expression so large that it could not be evaluated by the compiler
without overflowing the stack.
I fixed this by continuously folding the extent expression as each operand is
added to it. I added the test .../flang/test/Semantics/array-constr-big.f90
that will cause the compiler to seg fault without this change.
Also, when the unrolled ac-implied-do expression contains errors, we were
repeating the same error message referencing the same source line for every
instance of the erroneous expression in the unrolled list. This potentially
resulted in a very long list of messages for a single error in the source code.
I fixed this by comparing the message being emitted to the previously emitted
message. If they are the same, I do not emit the message. This change is also
tested by the new test array-constr-big.f90.
Several of the existing tests had duplicate error messages for the same source
line, and this change caused differences in their output. So I adjusted the
tests to match the new message emitting behavior.
Differential Revision: https://reviews.llvm.org/D102210
Sam Powell [Tue, 11 May 2021 16:57:52 +0000 (09:57 -0700)]
[TextAPI] Reformat llvm_unreachable message
Change llvm_unreachable message from "Unknown llvm.MachO.PlatformKind
enum" to "Unknown llvm::MachO::PlatformKind enum".
Differential revision: https://reviews.llvm.org/D102250
Lang Hames [Tue, 11 May 2021 16:51:12 +0000 (09:51 -0700)]
Revert "[ORC-RT] Add unit test infrastructure, extensible_rtti..."
This reverts commit
6d263b6f1c9 while I investigate the CMake failures that it
causes in some configurations.
Alan Phipps [Tue, 11 May 2021 16:40:11 +0000 (11:40 -0500)]
Reland "[Coverage] Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation""
Originally landed in:
6400905a615282c83a2fc6e49e57ff716aa8b4de
Reverted in:
668dccc396da4f593ac87c92dc0eb7bc983b5762
Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation
groups.
This change corrects the implementation for the branch coverage summary to do
the same thing for branches that is done for lines and regions. That is,
across function instantiations in an instantiation group, the maximum branch
coverage found in any of those instantiations is returned, with the total
number of branches being the same across instantiations.
Differential Revision: https://reviews.llvm.org/D102193
Simon Pilgrim [Tue, 11 May 2021 16:30:31 +0000 (17:30 +0100)]
[X86][SSE] Add tests for permute(phaddw(phaddw(x,y),phaddw(z,w))) -> phaddw(phaddw(),phaddw()) folds.
We currently only fold if NumEltsPerLane == 4
zoecarver [Tue, 11 May 2021 16:43:14 +0000 (09:43 -0700)]
[libcxx][tests] Fix incomplte.verify tests by disabling them on clang-10.
For some reason clang-10 can't match the expected errors produced by
passing icomplete arrays to range access functions. Disabling the tests
is a stop-gap solution to fix the bots.
Craig Topper [Tue, 11 May 2021 16:32:19 +0000 (09:32 -0700)]
[RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.
My thought process is that if v2i64 is an LMUL=1 type then v2i32
should be an LMUL=1/2 type. We limit the fractional LMUL so that
SEW=64 clips to LMUL=1, SEW=32 clips to LMUL=1/2, etc. This
ensures there's always a fractional LMUL available to truncate a type.
This does reduce the number of vsetvlis in some cases.
Some tests increase vsetvlis because the best container type for a
mask type is dependent on the LMUL+SEW that the mask was produced
from, but you can't tell that from the type. I think this is
something we need to solve this in the machine IR when optimizing
vsetvlis.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D101215
Roman Lebedev [Tue, 11 May 2021 16:35:41 +0000 (19:35 +0300)]
[X86][Codegen] Shift amount mod: sh? i64 x, (32-y) --> sh? i64 x, -(y+32)
I've seen this in the RawSpeed's BitPumpMSB*::push() hotpath,
after fixing the buffer abstraction to a more sane one,
when looking into a +5% runtime regression.
I was hoping that this would fix it, but it does not look it does.
This seems to be at least not worse than the original pattern.
But i'm actually mainly interested in the case where we already
compute `(y+32)` (see last test),
https://alive2.llvm.org/ce/z/ZCzJio
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D101944
Craig Topper [Mon, 10 May 2021 19:12:16 +0000 (12:12 -0700)]
[RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl.
Limited to splats because we would need to truncate the shift
amount vector otherwise.
I tried to do this with new ISD nodes and a DAG combine to
avoid such a large pattern, but we don't form the splat until
LegalizeDAG and need DAG combine to remove a scalable->fixed->scalable
cast before it becomes visible to the shift node. By the time that
happens we've already visited the truncate node and won't revisit it.
I think I have an idea how to improve i64 on RV32 I'll save for a
follow up.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D102019
Alan Phipps [Tue, 11 May 2021 16:26:19 +0000 (11:26 -0500)]
Revert "Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation"
This reverts commit
6400905a615282c83a2fc6e49e57ff716aa8b4de.
Arthur O'Dwyer [Mon, 10 May 2021 17:13:04 +0000 (13:13 -0400)]
[libc++] Remove more unnecessary _VSTD:: from type names. NFCI.
Differential Revision: https://reviews.llvm.org/D102181
Arthur O'Dwyer [Mon, 10 May 2021 19:32:38 +0000 (15:32 -0400)]
[libc++] s/_VSTD::is_unsigned/is_unsigned/ in <random>. NFCI.
Arthur O'Dwyer [Mon, 10 May 2021 17:19:07 +0000 (13:19 -0400)]
[libc++] s/_VSTD::chrono/chrono/g. NFCI.
Arthur O'Dwyer [Mon, 10 May 2021 17:07:00 +0000 (13:07 -0400)]
[libc++] s/std::size_t/size_t/g. NFCI.
Arthur O'Dwyer [Mon, 10 May 2021 17:04:16 +0000 (13:04 -0400)]
[libc++] s/_VSTD::declval/declval/g. NFCI.
Jon Chesterfield [Tue, 11 May 2021 16:23:08 +0000 (17:23 +0100)]
[libomptarget][nfc] Add hook to easily disable building amdgcn bclib
[libomptarget][nfc] Add hook to easily disable building amdgcn bclib
This is useful when building LLVM with a toolchain that can't emit code
for amdgcn, e.g. because it overrides the include search path with headers
from another architecture, or the clang compiler is missing builtins.
Reviewed By: tianshilei1992
Differential Revision: https://reviews.llvm.org/D102229
Benjamin Kramer [Tue, 11 May 2021 12:14:54 +0000 (14:14 +0200)]
[mlir] Use static shape knowledge when lowering memref.reshape
This is actually necessary for correctness, as memref.reinterpret_cast
doesn't verify if the output shape doesn't match the static sizes.
Differential Revision: https://reviews.llvm.org/D102232
Augusto Noronha [Tue, 11 May 2021 16:15:03 +0000 (13:15 -0300)]
Add null-pointer checks when accessing a TypeSystem's SymbolFile
A type system is not guaranteed to have a symbol file. This patch adds null-pointer checks so we don't crash when trying to access a type system's symbol file.
Reviewed By: aprantl, teemperor
Differential Revision: https://reviews.llvm.org/D101539
Augusto Noronha [Tue, 11 May 2021 16:07:02 +0000 (13:07 -0300)]
Change Target::ReadMemory to ensure the amount of memory read from the file-cache is the amount requested.
This change ensures that if for whatever reason we read less bytes than expected (for example, when trying to read memory that spans multiple sections), we try reading from the live process as well.
Reviewed By: jasonmolenda
Differential Revision: https://reviews.llvm.org/D101390
Alan Phipps [Mon, 10 May 2021 20:15:26 +0000 (15:15 -0500)]
Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation
groups.
This change corrects the implementation for the branch coverage
summary to do the same thing for branches that is done for lines and regions.
That is, across function instantiations in an instantiation group, the maximum
branch coverage found in any of those instantiations is returned, with the
total number of branches being the same across instantiations.
Differential Revision: https://reviews.llvm.org/D102193
Roman Lebedev [Tue, 11 May 2021 15:34:14 +0000 (18:34 +0300)]
[NFC][X86] Precommit another testcase for D101944
Jamie Schmeiser [Tue, 11 May 2021 15:29:50 +0000 (11:29 -0400)]
Produce warning for performing pointer arithmetic on a null pointer.
Summary:
Test and produce warning for subtracting a pointer from null or subtracting
null from a pointer. Reuse existing warning that this is undefined
behaviour. Also add unit test for both warnings.
Reformat to satisfy clang-format.
Respond to review comments: add additional test.
Respond to review comments: Do not issue warning for nullptr - nullptr
in C++.
Fix indenting to satisfy clang-format.
Respond to review comments: Add C++ tests.
Author: Jamie Schmeiser <schmeise@ca.ibm.com>
Reviewed By: efriedma (Eli Friedman), nickdesaulniers (Nick Desaulniers)
Differential Revision: https://reviews.llvm.org/D98798
Steven Wu [Tue, 11 May 2021 15:23:08 +0000 (08:23 -0700)]
[IR][AutoUpgrade] Drop align attribute from void return types
Since D87304, `align` become an invalid attribute on none pointer types and
verifier will reject bitcode that has invalid `align` attribute.
The problem is before the change, DeadArgumentElimination can easily
turn a pointer return type into a void return type without removing
`align` attribute. Teach Autograde to remove invalid `align` attribute
from return types to maintain bitcode compatibility.
rdar://
77022993
Reviewed By: dexonsmith
Differential Revision: https://reviews.llvm.org/D102201
Tony Tye [Tue, 11 May 2021 02:24:30 +0000 (02:24 +0000)]
[NFC][AMDGPU] Correct product name for gfx908
The product name for gfx908 is "AMD Instinct MI100 Accelerator".
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D102209
Pushpinder Singh [Tue, 11 May 2021 11:45:09 +0000 (06:45 -0500)]
Revert "[AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S"
This reverts commit
7f78e409d0280c62209e1a7dc8c6d1409acc9184.
Congzhe Cao [Tue, 11 May 2021 14:59:50 +0000 (10:59 -0400)]
[LoopInterchange] Fix legality for triangular loops
This is a bug fix in legality check.
When we encounter triangular loops such as the following form:
for (int i = 0; i < m; i++)
for (int j = 0; j < i; j++), or
for (int i = 0; i < m; i++)
for (int j = 0; j*i < n; j++),
we should not perform interchange since the number of executions of the loop body
will be different before and after interchange, resulting in incorrect results.
Reviewed By: bmahjour
Differential Revision: https://reviews.llvm.org/D101305
Aakanksha Patil [Tue, 4 May 2021 22:36:32 +0000 (18:36 -0400)]
Fix typo "Execpt" in comments
Differential Revision: https://reviews.llvm.org/D101858
Paul C. Anagnostopoulos [Tue, 11 May 2021 14:41:17 +0000 (10:41 -0400)]
Revert "[TableGen] Make the NUL character invalid in .td files"
At least one build uses a 'sed' that does not understand \x00.
This reverts commit
cf9647011c4f05e1eb4423c6637d84e2f26b2042.
Peyton, Jonathan L [Mon, 10 May 2021 15:03:23 +0000 (10:03 -0500)]
[OpenMP] Fix hidden helper + affinity
When KMP_AFFINITY is set, each worker thread's gtid value is used as an
index into the place list to determine the thread's placement. With hidden
helpers enabled, this gtid value is shifted down leading to unexpected
shifted thread placement. This patch restores the previous behavior by
adjusting the mask index to take the number of hidden helper threads
into account.
Hidden helper threads are given the full initial mask and do not
participate in any of the other affinity mechanisms (place partitioning,
balanced affinity). Their affinity is only printed for debug builds.
Differential Revision: https://reviews.llvm.org/D101882
Florian Hahn [Tue, 11 May 2021 13:29:21 +0000 (14:29 +0100)]
[VPlan] Register recipe for instr if the simplified value is recipe.
If the simplified VPValue is a recipe, we need to register it for Instr,
in case it needs to be recorded. The way this is handled in general may
change soon, following some post-commit comments.
This fixes PR50298.
Roman Lebedev [Tue, 11 May 2021 13:09:10 +0000 (16:09 +0300)]
[X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): use getMemoryOpCost()
Now that getMemoryOpCost() correctly handles all the vector variants,
we should no longer hand-roll our own version of it, but use it directly.
The AVX512 variant probably needs a similar change,
but there it is less obvious.
Paul C. Anagnostopoulos [Wed, 5 May 2021 16:03:50 +0000 (12:03 -0400)]
[TableGen] Make the NUL character invalid in .td files
Differential Revision: https://reviews.llvm.org/D101923
Simon Pilgrim [Tue, 11 May 2021 13:18:29 +0000 (14:18 +0100)]
[X86] Replace repeated isa/cast<ConstantSDNode> calls with single single dyn_cast<>. NFCI.
Noticed while looking at D101944
Simon Pilgrim [Tue, 11 May 2021 11:26:14 +0000 (12:26 +0100)]
[X86][SSE] Replace foldShuffleOfHorizOp with generalized version in canonicalizeShuffleMaskWithHorizOp
foldShuffleOfHorizOp only handled basic shufps(hop(x,y),hop(z,w)) folds - by moving this to canonicalizeShuffleMaskWithHorizOp we can work with more general/combined v4x32 shuffles masks, float/integer domains and support shuffle-of-packs as well.
The next step will be to support 256/512-bit vector cases.
Matt Arsenault [Tue, 11 May 2021 00:56:24 +0000 (20:56 -0400)]
CodeGen: Fix null dereference before null check
Roman Lebedev [Tue, 11 May 2021 13:02:11 +0000 (16:02 +0300)]
[X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again
Instead of handling power-of-two sized vector chunks,
try handling the large vector in a stream mode,
decreasing the operational vector size
once it no longer works for the elements left to process.
Notably, this improves costs for overaligned loads - loading padding is fine.
This more directly tracks when we need to insert/extract the YMM/XMM subvector,
some costs fluctuate because of that.
Reviewed By: RKSimon, ABataev
Differential Revision: https://reviews.llvm.org/D100684
Sanjay Patel [Tue, 11 May 2021 12:45:20 +0000 (08:45 -0400)]
[SLP] restrict matching of load combine candidates
The test example from https://llvm.org/PR50256 (and reduced here)
shows that we can match a load combine candidate even when there
are no "or" instructions. We can avoid that by confirming that we
do see an "or". This doesn't apply when matching an or-reduction
because that match begins from the operands of the reduction.
Differential Revision: https://reviews.llvm.org/D102074
Piotr Sobczak [Tue, 11 May 2021 10:45:04 +0000 (12:45 +0200)]
[AMDGPU] Move code sinking before structurizer
Moving code sinking pass before structurizer creates more sinking
opportunities.
The extra flow edges introduced by the structurizer can have adverse
effects on sinking, because the sinking pass prefers moving instructions
to blocks with unique predecessors and the structurizer destroys that
property in some cases.
A notable example is moving high-latency image instructions across kills.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D101115
Anastasia Stulova [Tue, 11 May 2021 09:36:19 +0000 (10:36 +0100)]
[OpenCL] Allow use of double type without extension pragma.
Simply use of extensions by allowing the use of supported
double types without the pragma. Since earlier standards
instructed that the pragma is used explicitly a new warning
is introduced in pedantic mode to indicate that use of
type without extension pragma enable can be non-portable.
This patch does not break backward compatibility since the
extension pragma is still supported and it makes the behavior
of the compiler less strict by accepting code without extra
pragma statements.
Differential Revision: https://reviews.llvm.org/D100980
Jon Chesterfield [Tue, 11 May 2021 11:19:55 +0000 (12:19 +0100)]
[libomptarget][nfc] Drop stringify in macro
[libomptarget][nfc] Drop stringify in macro
A step towards deleting the macros entirely.
Differential Revision: https://reviews.llvm.org/D102228
Martin Storsjö [Wed, 5 May 2021 10:26:56 +0000 (13:26 +0300)]
[LLDB] Don't use the local python to set a default for LLDB_PYTHON_RELATIVE_PATH when cross compiling.
Differential Revision: https://reviews.llvm.org/D101903
Stefan Pintilie [Tue, 11 May 2021 10:32:32 +0000 (05:32 -0500)]
[PowerPC][Bug] Fix Bug in Stack Frame Update Code
The stack frame update code does not take into consideration spilling
to registers for callee saved registers. The option -ppc-enable-pe-vector-spills
turns on spilling to registers for callee saved registers and may expose a bug
in the code that moves a stack frame pointer update instruction.
Reviewed By: nemanjai, #powerpc
Differential Revision: https://reviews.llvm.org/D101366
Denis Antrushin [Wed, 24 Mar 2021 15:48:11 +0000 (22:48 +0700)]
[RegAllocFast] properly handle STATEPOINT instruction.
STATEPOINT is a fancy and complex pseudo instruction which
has both tied defs and regmask operand.
Basic FastRA algorithm is as follows:
1. Mark registers used by defs as free
2. If instruction has regmask operand displace clobbered registers
according to regmask.
3. Assign registers for use operands.
In case of tied defs step 1 is replaced with allocation of registers
for them. But regmask is still processed, which may displace already
allocated registers. As a result, tied use and def will get assigned
to different registers.
This patch makes FastRA to process instruction's RegMask (if any) when
checking for physical registers interference.
That way tied operands won't get registers clobbered by regmask.
Reviewed By: arsenm, skatkov
Differential Revision: https://reviews.llvm.org/D99284
Jay Foad [Tue, 11 May 2021 10:21:03 +0000 (11:21 +0100)]
[AMDGPU] Add some GFX10.3 testing. NFC.
Uday Bondhugula [Tue, 11 May 2021 09:48:42 +0000 (15:18 +0530)]
[MLIR] Switch llvm.noalias to a unit attribute
Switch llvm.noalias attribute from a boolean attribute to a unit
attribute.
Differential Revision: https://reviews.llvm.org/D102225
Martin Storsjö [Fri, 7 May 2021 21:21:49 +0000 (00:21 +0300)]
[LLD] [COFF] Add an assert regarding the RVA of exported symbols. NFC.
As this isn't handled as a regular relocation, the normal handling of
maybeReportRelocationToDiscarded in Chunks.cpp doesn't apply here.
This would have caught the issue fixed by
82de4e075339f5ad8d68cfe31eb45b771d4750ae.
Differential Revision: https://reviews.llvm.org/D102115
Andy Wingo [Wed, 5 May 2021 12:59:30 +0000 (14:59 +0200)]
[CodeGen][WebAssembly] Better lowering for WASM_SYMBOL_TYPE_GLOBAL symbols
As we have been missing support for WebAssembly globals on the IR level,
the lowering of WASM_SYMBOL_TYPE_GLOBAL to IR was incomplete. This
commit fleshes out the lowering support, lowering references to and
definitions of addrspace(1) values to correctly typed
WASM_SYMBOL_TYPE_GLOBAL symbols.
Depends on D101608.
Differential Revision: https://reviews.llvm.org/D101913
Simon Moll [Tue, 11 May 2021 07:09:48 +0000 (09:09 +0200)]
[VP] Improve the VP intrinsic unittests
Test that all VP intrinsics are tested.
Test intrinsic id -> opcode -> intrinsic id round tripping.
Test property scopes in the include/llvm/IR/VPIntrinsics.def file.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D93534
Paulo Matos [Tue, 4 May 2021 12:13:08 +0000 (14:13 +0200)]
[WebAssembly] Support for WebAssembly globals in LLVM IR
This patch adds support for WebAssembly globals in LLVM IR, representing
them as pointers to global values, in a non-default, non-integral
address space. Instruction selection legalizes loads and stores to
these pointers to new WebAssemblyISD nodes GLOBAL_GET and GLOBAL_SET.
Once the lowering creates the new nodes, tablegen pattern matches those
and converts them to Wasm global.get/set of the appropriate type.
Based on work by Paulo Matos in https://reviews.llvm.org/D95425.
Reviewed By: pmatos
Differential Revision: https://reviews.llvm.org/D101608
Andrzej Warzynski [Tue, 4 May 2021 15:52:15 +0000 (15:52 +0000)]
[flang][cmake] Enable the new driver by default
With this patch, `FLANG_BUILD_NEW_DRIVER` is set to `On` by default
(i.e. the new driver is enabled). Note that the new driver depends on
Clang and hence with this change you will need to add `clang` to
`LLVM_ENABLE_PROJECTS`.
If you don't want to build the new driver, set `FLANG_BUILD_NEW_DRIVER`
to `Off`. This way you won't be required to include `clang` in
`LLVM_ENABLE_PROJECTS`.
Differential Revision: https://reviews.llvm.org/D101842
Alex Orlov [Tue, 11 May 2021 09:10:54 +0000 (13:10 +0400)]
* Add support for JSON output style to llvm-symbolizer
This patch adds JSON output style to llvm-symbolizer to better support CLI automation by providing a machine readable output.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D96883
Simon Pilgrim [Tue, 11 May 2021 08:20:55 +0000 (09:20 +0100)]
Fix -Wdocumentation warnings. NFCI.
Ole Strohm [Tue, 11 May 2021 08:45:28 +0000 (09:45 +0100)]
[OpenCL] [NFC] Fixed underline being too short in rst