Hou Zhiqiang [Fri, 29 Jul 2016 10:26:35 +0000 (18:26 +0800)]
arm/PSCI: Removed unused code
Identify the PSCI node only by its name, so removed the code finding
it by compatible string.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
York Sun [Fri, 29 Jul 2016 16:02:29 +0000 (09:02 -0700)]
driver/ddr/fsl: Fix timing_cfg_2
Commit
5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the
change was wrong. wr_lat has 5 bits with MSB at [13] and lower
4 bits at [9:12], in big-endian convention.
Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>
York Sun [Fri, 29 Jul 2016 15:46:49 +0000 (08:46 -0700)]
board/freescale: Update MAINTAINERS files
Update maintainers for secure boot targets.
Signed-off-by: York Sun <york.sun@nxp.com>
Wenbin Song [Fri, 15 Jul 2016 09:17:46 +0000 (17:17 +0800)]
armv8: ls1043a: enable pxe commands
Enable pxe command for ls1043ardb and ls1043aqds.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Prabhakar Kushwaha [Tue, 19 Jul 2016 10:24:33 +0000 (15:54 +0530)]
armv8: ls1012a: Update Refresh cycle for DDR
Refresh cycle value must be selected based on the frequency
of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT]
should be based on round up (tREFI/tCK) formula. For 500MHz, mdref
value should be 0x0f3c8000.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Prabhakar Kushwaha [Tue, 19 Jul 2016 10:24:22 +0000 (15:54 +0530)]
armv8: ls1012a: Enable DDR row-bank-column decoding
Enable DDR row-bank-column decoding to decode DDR address as
row-bank-column instead of bank-row-column for improving
performance of serial data transfers.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Prabhakar Kushwaha [Tue, 19 Jul 2016 08:35:47 +0000 (14:05 +0530)]
board: ls1012aqds: Update LBMAP_MASK and RST_CTL_RESET
qixis_reset altbank usagge ~QIXIS_LBMAP_MASK in code. So define
inverse value QIXIS_LBMAP_MASK.
Also, update QIXIS_RST_CTL_RESET value to keep RST_CTL[REQ_MOD]
as 0b11 i.e. PORESET during qixis_reset
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Thu, 14 Jul 2016 17:27:50 +0000 (13:27 -0400)]
crypto/fsl: Update blob cmd to accept 64bit addresses
Update blob cmd to accept 64bit source, key modifier and destination
addresses. Also correct output result print format for fsl specific
implementation of blob cmd.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Yunhui Cui [Wed, 13 Jul 2016 02:46:27 +0000 (10:46 +0800)]
driver: spi: fsl-qspi: remove compile Warnings
Warnins log:
drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
York Sun [Mon, 1 Aug 2016 16:00:13 +0000 (09:00 -0700)]
powerpc/mpc85xx: Update erratum workaround for
A006379
Update erratum workaround for
A006379 to set register CPCHDBCR0
with value 0x001e0000, replacing the old value 0x003c0000.
Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Dave Liu <dave.liu@nxp.com>
Tom Rini [Mon, 1 Aug 2016 00:31:13 +0000 (20:31 -0400)]
Merge git://git.denx.de/u-boot-rockchip
Hans de Goede [Wed, 27 Jul 2016 16:06:35 +0000 (18:06 +0200)]
sunxi: Re-enable h3 emac support
With the recent bug fixes for the sun8i_emac driver all known issues
are resolved, so we can re-enable the driver.
While at it, also enable the emac on the Orange Pi One.
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Jagan Teki <jteki@openedev.com>
Hans de Goede [Wed, 27 Jul 2016 15:31:17 +0000 (17:31 +0200)]
net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffers
This fixes the following CACHE warnings when using sun8i_emac:
=> dhcp
BOOTP broadcast 1
BOOTP broadcast 2
CACHE: Misaligned operation at range [
7bf594a8,
7bf59628]
BOOTP broadcast 3
CACHE: Misaligned operation at range [
7bf59c90,
7bf59e10]
CACHE: Misaligned operation at range [
7bf5a478,
7bf5a5f8]
DHCP client bound to address 10.42.43.80 (1009 ms)
Note this commit also changes the max rx size from 2024 to 2044,
matching what the kernel driver uses.
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Fri, 29 Jul 2016 09:47:03 +0000 (11:47 +0200)]
sunxi: On newer SoCs use words 1-3 instead of just word 3 from the SID
It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the SID
are always 0 on H3 making it a poor candidate to use as source for the
serialnr / mac-address, and the other non constant words (1 and 2) also
have quite a few bits which are the same for some boards,
This commits switches to using the crc32 of words 1 - 3 to get a
more unique value for the mac-address / serialnr.
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Wed, 27 Jul 2016 15:58:06 +0000 (17:58 +0200)]
sunxi: Ensure that the NIC specific bytes of the mac are not all 0
On 2 of my H3 boards bytes 13-15 of the SID are all 0 leading to
the NIC specific bytes of the mac all being 0, which leads to the
boards not getting an ipv6 address from the dhcp server.
This commits adds a check to ensure this does not happen.
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Chen-Yu Tsai [Fri, 22 Jul 2016 08:13:00 +0000 (16:13 +0800)]
sunxi: Hummingbird_A31_defconfig: Drop MACPWR option
MACPWR was used to bring the Ethernet PHY out of reset. The designware
driver now supports the phy reset gpio binding, so this is no longer
needed. In fact in requesting the same GPIO, it makes the designware
driver fail to probe.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Fri, 22 Jul 2016 08:12:59 +0000 (16:12 +0800)]
sunxi: gpio: Add .xlate function for gpio phandle resolution
sunxi uses a 2 cell phandle for gpio bindings. Also there are no
seperate nodes for each pin bank.
Add a custom .xlate function to map gpio phandles to the correct
pin bank device. This fixes gpio_request_by_name usage.
Fixes: 7aa974858422 ("dm: sunxi: Modify the GPIO driver to support driver
model")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:30 +0000 (18:28 +0800)]
rockchip: add support for rk3288 PopMetal board
PopMetal is a rockchip rk3288 based board made by ChipSpark, which has
many interface such as HDMI, VGA, USB, micro-SD card, WiFi, Audio and
Gigabit Ethernet.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:29 +0000 (18:28 +0800)]
rockchip: add basic support for fennec-rk3288 board
Fennec is a RK3288-based development board with 2 USB ports, HDMI,
micro-SD card, audio and WiFi and Gigabit Ethernet. It also includes
on-board 8GB eMMC and 2GB of SDRAM. Expansion connectors provides access
to display pins, I2C, SPI, UART and GPIOs.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:27 +0000 (18:28 +0800)]
rockchip: rk3288: move evb board to rockchip folder
The 'evb-rk3288' is not a vendor name, change it to 'rockchip' which is
the real vendor name.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:26 +0000 (18:28 +0800)]
rockchip: rk3288: revise CONFIG_FASTBOOT_BUF_ADDR
CONFIG_SYS_LOAD_ADDR is absolutely safe to store image for
fastboot.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:25 +0000 (18:28 +0800)]
rockchip: remove the duplicated macro config
CONFIG_DOS_PARTITION and CONFIG_EFI_PARTITION are already included in
config_distro_defaults.h, and we don't need them in SPL stage.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:24 +0000 (18:28 +0800)]
rockchip: rk3288: disable fastboot in SPL stage
Reduce compilation time for SPL.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:23 +0000 (18:28 +0800)]
Revert "rockchip: Move the MMC setup check earlier"
Boot Rom wouldn't initialize sdmmc while booting from eMMC. We need to
setup sdmmc gpio, otherwise we will hit an error below:
=>mmc info
blk_get_device: if_type=6, devnum=0: dwmmc@
ff0c0000.blk, 6, 0
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
- -1 -1
- -1 0
- found
uclass_find_device_by_seq: 0 1
- -1 -1
- -1 0
- not found
fdtdec_get_int_array: interrupts
get_prop_check_min_len: interrupts
Buswidth = 1, clock: 0
Buswidth = 1, clock: 400000
Sending CMD0
dwmci_send_cmd: Timeout on data busy
dwmci_send_cmd: Timeout on data busy
dwmci_send_cmd: Timeout on data busy
dwmci_send_cmd: Timeout on data busy
This reverts commit
6efeeea79c880d3dd262e0dca9da2687f0ab68c9.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:22 +0000 (18:28 +0800)]
cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming
Revise config to CONFIG_ROCKCHIP_RK3288_PINCTRL.
Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
jk.kernel@gmail.com [Tue, 26 Jul 2016 10:28:21 +0000 (18:28 +0800)]
rockchip: add a dummy byte for the sdram-channel property
Add an extra byte so that this data is not byteswapped.
Signed-off-by: Ziyuan Xu <jk.kernel@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
John Keeping [Mon, 25 Jul 2016 09:02:05 +0000 (10:02 +0100)]
rockchip: rk3288: Fix pinctrl for GPIO bank 0
Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers
rather than the GRF registers. In the GRF the top half of the register
is used as a mask so that some bits can be updated without affecting the
others, but in the PMU this feature is not provided and the top half of
the register is reserved.
Take the same approach as the Linux driver to update the value via
read-modify-write but setting the mask for only the bits that have
changed. The PMU registers ignore the top 16 bits so this works for
both GRF and PMU iomux registers.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Mon, 25 Jul 2016 03:45:54 +0000 (11:45 +0800)]
rk3399: Reserve space for ARM Trust Firmware
RK3399 needs reserve 0x200000 at the beginning of DRAM, for ATF bl31.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Sat, 23 Jul 2016 07:09:28 +0000 (15:09 +0800)]
rockchip: rk3036: update MAINTAINER file
Update MAINTAINER files for kylin_rk3036, evb_rk3036.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 22 Jul 2016 09:41:37 +0000 (17:41 +0800)]
configs: rockchip: remove no use MACRO
The CONFIG_ROCKCHIP_COMMON and CONFIG_SPL_ROCKCHIP_COMMON are no use now,
remove them.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 22 Jul 2016 09:22:50 +0000 (17:22 +0800)]
mmc-uclass: correct the device number
Not like the mmc-legacy which the devnum starts from 1, it starts from 0
in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num().
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Angelo Dureghello [Sat, 21 May 2016 22:14:29 +0000 (00:14 +0200)]
m68k: code reformatting for all start.S files
This patch is style-related only, to reformat all the start.S code,
actually not following a coherent style inside single files and
between different cpu start.S files.
Linux format has been respected, as
- max line width at 80 columns
- one 8 cols tab between asm instructions and operands
- inline comments, where any, fixed at col 41
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
Vignesh R [Fri, 29 Jul 2016 08:52:30 +0000 (14:22 +0530)]
ARM: am57xx_evm: Enable QSPI support
AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
board connected to TI QSPI IP over CS0. Therefore enable QSPI support.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Fri, 29 Jul 2016 08:52:31 +0000 (14:22 +0530)]
ARM: dts: am57xx-idk-common: Enable support for QSPI
AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board
connected to TI QSPI over CS0. Hence, add QSPI and flash slave
DT nodes.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Thu, 28 Jul 2016 11:57:57 +0000 (17:27 +0530)]
configs: am43xx_evm_defconfig: Enable CONFIG_SPI_FLASH_BAR
AM437x SK and AM437x IDK EVMs have 64MB flash, therefore enable
CONFIG_SPI_FLASH_BAR to access flash regions above 16MB.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Mon, 25 Jul 2016 10:15:47 +0000 (15:45 +0530)]
ARM: dts: dra7xx: Update spi-max-frequency for QSPI
According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
Therefore update the spi-max-frequency value of QSPI node for DRA74 and
DRA72 evm. This increase flash read speed by ~2MB/s.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Vignesh R [Mon, 25 Jul 2016 10:15:46 +0000 (15:45 +0530)]
configs: dra7xx: Update QSPI speed to 76.8MHz
Now that QSPI driver can support 76.8MHz, update the
CONFIG_SF_DEFAULT_SPEED to the same value.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Vignesh R [Mon, 25 Jul 2016 10:15:45 +0000 (15:45 +0530)]
spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
the driver to use the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Lokesh Vutla [Mon, 25 Jul 2016 10:15:44 +0000 (15:45 +0530)]
ARM: dra7xx: Change DPLL_PER_HS13 divider value
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
clock, so that driver can use the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Wenyou Yang [Tue, 5 Jul 2016 05:17:12 +0000 (13:17 +0800)]
sf: sf_params: Add AT25DF321 flash support
Add AT25DF321 flash support.
Fix AT25DF321A device name.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Fri, 22 Jul 2016 05:25:50 +0000 (10:55 +0530)]
spi: ti_qspi: Remove delay in read path for dra7xx
As per commit
b545a98f5dc563 ("spi: ti_qspi: Add delay
for successful bulk erase) says its added to meet bulk erase timing
constraints. But bulk erase is a cmd to flash and delay in read path
does not make sense. Morever, testing on DRA74/DRA72 evm has shown that
this delay is no longer required.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Vignesh R [Fri, 22 Jul 2016 05:25:49 +0000 (10:55 +0530)]
spi: ti_qspi: Fix compiler warning when DEBUG macro is set
clk_div is uninitialized at the beginning of ti_spi_set_speed(), move
debug() print after clk_div calculation to avoid compiler warning and to
have proper value of clk_div printed during debugging.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Vignesh R [Fri, 22 Jul 2016 05:25:48 +0000 (10:55 +0530)]
spi: ti_qspi: Fix failure on multiple READ_ID cmd
Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value
QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in
ti_qspi_cs_deactivate(). Therefore CS is never deactivated between
successive READ ID which results in sf probe to fail.
Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih
priv->cmd as required (similar to the convention followed in the
driver).
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Moritz Fischer [Thu, 14 Jul 2016 23:22:39 +0000 (16:22 -0700)]
spi: Add support for N25Q016A
This commit adds support in the spi-nor driver for the
N25Q016A, a 16Mbit SPI NOR flash from Micron.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Tom Rini [Thu, 28 Jul 2016 12:45:00 +0000 (08:45 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-imx
Fabio Estevam [Wed, 27 Jul 2016 00:27:49 +0000 (21:27 -0300)]
MAINTAINERS: i.MX: Add board/freescale/*mx* path
Pass the board/freescale/*mx*/ path as files maintained by Stefano
Babic.
While this is not ideal and does not cover all the i.MX board cases,
it gives at least a better hint for the /scripts/get_maintainer.pl
tool.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam [Wed, 27 Jul 2016 00:08:58 +0000 (21:08 -0300)]
mx7dsabresd: MAINTAINERS: Add mx7dsabresd_secure_defconfig
Add an entry for the mx7dsabresd_secure_defconfig target.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Stefan Agner [Tue, 26 Jul 2016 05:57:47 +0000 (22:57 -0700)]
mx7_common: initialize generic timer on all CPU's
Use CONFIG_TIMER_CLK_FREQ to let the non-secure init code initialize
the generic timer on all CPU's. This allows to make use of the timer
freuquency register also on other CPU than the start CPU which is
important for KVM.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Diego Dorta [Mon, 25 Jul 2016 16:45:30 +0000 (13:45 -0300)]
mx6ul_14x14_evk: Remove unused define
Remove unused define constant.
Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam [Sat, 23 Jul 2016 16:23:42 +0000 (13:23 -0300)]
cgtqmx6eval: Remove uneeded PHYS_SDRAM_SIZE
cgtqmx6eval uses the imx_ddr_size() function to calculate the DDR size in
runtime, so there is no need to define PHYS_SDRAM_SIZE.
Remove the unneeded definition.
Cc: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Fabio Estevam [Sat, 23 Jul 2016 16:23:41 +0000 (13:23 -0300)]
novena: Remove uneeded PHYS_SDRAM_SIZE
novena uses the imx_ddr_size() function to calculate the DDR size in
runtime, so there is no need to define PHYS_SDRAM_SIZE.
Remove the unneeded definition.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Marek Vasut <marex@denx.de>
Fabio Estevam [Sat, 23 Jul 2016 16:23:40 +0000 (13:23 -0300)]
bx50v3: Use imx_ddr_size() for calculating the DDR size
imx_ddr_size() can be used to calculate the DDR size in runtime.
By using this function we no longer need to define PHYS_SDRAM_SIZE.
Cc: Martin Donnelly <martin.donnelly@ge.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam [Sat, 23 Jul 2016 16:23:39 +0000 (13:23 -0300)]
aristainetos: Use imx_ddr_size() for calculating the DDR size
imx_ddr_size() can be used to calculate the DDR size in runtime.
By using this function we no longer need to define PHYS_SDRAM_SIZE.
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Heiko Schocher <hs@denx.de>
Fabio Estevam [Sat, 23 Jul 2016 16:23:38 +0000 (13:23 -0300)]
warp: Use imx_ddr_size() for calculating the DDR size
imx_ddr_size() can be used to calculate the DDR size in runtime.
By using this function we no longer need to define PHYS_SDRAM_SIZE.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Breno Lima [Fri, 22 Jul 2016 18:29:30 +0000 (15:29 -0300)]
warp7: Move some USB configuration options to defconfig
Currently it's recommended to move some configuration options to the
defconfig file.
Move some USB related options to the defconfig file.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Stefan Agner [Thu, 21 Jul 2016 04:27:49 +0000 (21:27 -0700)]
colibri_imx7: add Colibri iMX7S/iMX7D module support
This commit adds support for the Toradex Computer on Modules
Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence
can be easily supported by one board. The board code detects RAM
size at runtime which is one of the differences between the two
boards. The board also uses the UART's in DTE mode, hence making
use of the new DTE support via serial DM.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Breno Lima [Fri, 22 Jul 2016 12:12:12 +0000 (09:12 -0300)]
cgtqmx6eval: Replace is_mx6q() for macro
It's not necessary to implement the is_mx6q function, there is a macro in
sys_proto.h already implemented.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Breno Lima [Fri, 22 Jul 2016 12:11:30 +0000 (09:11 -0300)]
mx6cuboxi: Replace is_mx6q() for macro
It's not necessary to implement the is_mx6q function, there is a macro in
sys_proto.h already implemented.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Breno Lima [Fri, 22 Jul 2016 12:11:02 +0000 (09:11 -0300)]
wandboard: Replace is_cpu_type() for macro
It's not necessary to use the is_cpu_type function, there is a macro in
sys_proto.h already implemented.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Tim Harvey [Fri, 15 Jul 2016 14:16:29 +0000 (07:16 -0700)]
imx: ventana: add dt fixup for watchdog external reset
Added removal of the fsl,ext-reset-output property in the wdog node for board
revisions that pre-date the addition of the external watchdog reset signal.
This property is a recent addition to mainline linux kernel in order to
specify that the IMX watchdog external reset should be used instead of the
internal chip-level reset.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Fri, 15 Jul 2016 14:16:28 +0000 (07:16 -0700)]
imx: ventana: refactor board-specific dt fixups (no functional change)
Re-factor the board-specific dt fixups so that they are easier to follow
and extend in the future:
- use defines for DT paths
- use switch/case per board
- order models numerically
There is no functional change in the code
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Fri, 15 Jul 2016 14:14:25 +0000 (07:14 -0700)]
imx: ventana: make hwconfig initialize based on board configuration
The hwconfig env var allows user to control hardware specific configuration
of board specific features but not all Ventana boards have the same features.
We will use the magic default value of "_UNKNOWN_" to signify that the
bootloader should create this based on detected board model.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Fri, 15 Jul 2016 14:14:24 +0000 (07:14 -0700)]
imx: ventana: add extra DIO's for GW5520
The GW5520 has 10 DIO's instead of the typical 4 found on the Ventana
product family.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Fri, 15 Jul 2016 14:14:23 +0000 (07:14 -0700)]
imx: ventana: make number of digital I/O's dynamic
Replace the static list of board-specific digital I/O's with a dynamic list.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Fri, 15 Jul 2016 14:14:22 +0000 (07:14 -0700)]
imx: ventana: make RS232 enable board specific
Not all Ventana boards have an RS232 transceiver, make it board specific.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Wed, 29 Jun 2016 15:58:00 +0000 (08:58 -0700)]
imx: ventana: re-enable late board info display
3b1f681131149b5f62602f582a7e60b0185a2a49 caused a regression that removes
board info dispaly for Gateworks Ventana boards because it made the invalid
assumption that CONFIG_DISPLAY_BOARDINFO_LATE was the same thing as
CONFIG_DISPLAY_BOARDINFO.
Ventana needs to call show_board_info in late init because we need to have
the i2c eeprom based model info. Re-define CONFIG_DISPLAY_BOARDINFO_LATE
to allow that to happen.
Cc: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Fri, 17 Jun 2016 13:20:26 +0000 (06:20 -0700)]
imx: ventana: default pci to disabled
The IMX6 PCIe host controller does not have a proper reset and as such there
are several issues that can arise if PCI is enabled in the bootloader follwed
by Linux trying to re-configure LTSSM and/or toggling PERST# to the devices.
For now, the best approach seems to default to disabling PCI by defaulting
pciedisable=1. This can be overridden by the user if they need PCI in the
bootloader, for example:
- GW552x needing ethernet access in bootloader
- GW16082 expansion board needing a device-tree fixup for irq mapping
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Fri, 17 Jun 2016 13:20:25 +0000 (06:20 -0700)]
pci: allow disabling of pci init/enum via env
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Fri, 17 Jun 2016 13:10:42 +0000 (06:10 -0700)]
imx: ventana: add dt fixup for eth1 mac-address
Ventana boards with a PCI Marvell Sky2 GigE MAC require the MAC address to
be placed in a DT node in order for the mainline linux driver to obtain it.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Fri, 17 Jun 2016 13:10:41 +0000 (06:10 -0700)]
imx: ventana: add dt fixup for GW16082 irq mapping
The GW16082 mini-PCI expansion mezzanine uses a TI XIO2001 PCIe-to-PCI
bridge with legacy INTA/B/C/D interrupts. These interrupts are assigned
in the reverse order according to the PCI spec.
If the TI bridge is found on the Ventana PCI bus, add device-tree nodes
according to bus enumeration explicitly defining the interrupt mapping
to override the default PCI mapping in the Linux kernel. This allows
the GW16082 to work with upstream kernels that support device-tree
irq parsing.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Fabio Estevam [Fri, 22 Jul 2016 18:21:12 +0000 (15:21 -0300)]
mx7dsabresd_secure_defconfig: Use CONFIG_ARMV7_BOOT_SEC_DEFAULT
There is no need for introducing MX7_SEC, as there is the
CONFIG_ARMV7_BOOT_SEC_DEFAULT option for this purpose.
Switch to CONFIG_ARMV7_BOOT_SEC_DEFAULT and get rid of
MX7_SEC.
Tested by booting a 4.1.15 NXP kernel with mx7dsabresd_secure_defconfig
target.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Stefano Babic [Wed, 20 Jul 2016 15:54:07 +0000 (17:54 +0200)]
pico-imx6ul: drop warning due to redefined
USB gadget configuration is set in defconfig and
must be removed from pico-imx6ul.h.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Stefano Babic [Wed, 20 Jul 2016 15:53:56 +0000 (17:53 +0200)]
mx6: wandboard: fix warning due to missing prototype
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Stefano Babic [Wed, 20 Jul 2016 15:52:53 +0000 (17:52 +0200)]
Fix build for mx7dsabresd (secure config)
After moving CONFIG_USB_EHCI_MX7 to Kconfig,
the flag must be set in defconfig for mx7dsabresd.
It is already for the not secure config, it is
missing in the secure configuration.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Tom Rini [Thu, 28 Jul 2016 02:30:20 +0000 (22:30 -0400)]
Merge git://git.denx.de/u-boot-dm
Xu Ziyuan [Tue, 19 Jul 2016 01:38:22 +0000 (09:38 +0800)]
mmc: dw_mmc: reduce timeout detection cycle
It's no need to speed 10 seconds to wait the mmc device out from busy
status. 500 milliseconds enough.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Stephen Warren [Wed, 13 Jul 2016 19:45:31 +0000 (13:45 -0600)]
Add a power domain framework/uclass
Many SoCs allow power to be applied to or removed from portions of the SoC
(power domains). This may be used to save power. This API provides the
means to control such power management hardware.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:18 +0000 (17:10 -0600)]
dm: spl: mmc: Support raw partitions with CONFIG_BLK
Fix up the call in mmc_load_image_raw_partition() to use the correct
function to obtain the MMC device, so that this code can support driver
model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:17 +0000 (17:10 -0600)]
dm: usb: Use blk_dread/write() instead of direct calls
Update the USB mass storage code to allow it to work with driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:16 +0000 (17:10 -0600)]
dm: socfpga: mmc: Support CONFIG_BLK
Update the driver to support using driver model for block devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:15 +0000 (17:10 -0600)]
dm: mmc: zynq: Convert zynq to use driver model for MMC
Move zynq to the latest driver model support by enabling CONFIG_DM_MMC,
CONFIG_DM_MMC_OPS and CONFIG_BLK.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:14 +0000 (17:10 -0600)]
dm: zynq: usb: Convert to CONFIG_DM_USB
Convert zynq USB to driver model. Note this is tested on zynq-zybo only.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:13 +0000 (17:10 -0600)]
zynq: Increase the early malloc() size
This is needed to support driver-model conversion of USB and block devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:12 +0000 (17:10 -0600)]
net: phy: marvell: Add a missing errno.h header
This corrects a build error on zynqmp.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:11 +0000 (17:10 -0600)]
arm: Show early-malloc() usage in bdinfo
This is useful information to show how close we are to the limit. At present
it is only available by enabling DEBUG in board_r.c.
Make it available with the 'bdinfo' command also.
Note that this affects ARM only. The bdinfo command is different for each
architecture. Rather than duplicating the code it would be better to
refactor it (as was done with global_data).
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:10 +0000 (17:10 -0600)]
dm: Use dm_scan_fdt_dev() directly where possible
Quite a few places have a bind() method which just calls dm_scan_fdt_dev().
We may as well call dm_scan_fdt_dev() directly. Update the code to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:09 +0000 (17:10 -0600)]
dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()
This new function is more convenient for callers, and handles pre-relocation
situations automatically.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:08 +0000 (17:10 -0600)]
dm: core: Add a function to bind child devices
We currently use dm_scan_fdt_node() to bind devices. It is an internal
function and it requires the caller to know whether we are pre- or post-
relocation.
This requirement has become quite common in drivers, so the current function
is not ideal.
Add a new function with fewer arguments, that does not require internal
headers. This can be used directly as a post_bind() method if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Jaehoon Chung [Tue, 28 Jun 2016 06:52:21 +0000 (15:52 +0900)]
dm: mmc: dwmmc: use the callback functions as static
There are no places to call these functions.
It should be used the callback function.
Then it can be used as static functions.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jaehoon Chung [Tue, 28 Jun 2016 06:52:20 +0000 (15:52 +0900)]
dm: mmc: dwmmc: fix the wrong explanation for clock values
This e,g is wrong. Maximum/minimum e.g values are swapped each other.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 27 Jul 2016 19:22:21 +0000 (15:22 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-video
Tom Rini [Tue, 26 Jul 2016 22:33:04 +0000 (18:33 -0400)]
Merge branch 'master' of git.denx.de/u-boot-sunxi
Hans de Goede [Tue, 26 Jul 2016 20:26:39 +0000 (22:26 +0200)]
sunxi: Disable sun8i emac driver
Disable the sun8i emac driver for now, there are 2 issues with it:
1) It is causing issues with network connectivity under the kernel driver,
when booting the kernel with v2 of Corentin's sun8i-h3 emac driver, I get
the connection status bouncing between connected at 100mbps full-duplex
and being down every second.
The second issue is that when trying to use it from u-boot
I get a number of unaligned cache flush errors:
=> dhcp
BOOTP broadcast 1
BOOTP broadcast 2
CACHE: Misaligned operation at range [
7bf594a8,
7bf59628]
BOOTP broadcast 3
CACHE: Misaligned operation at range [
7bf59c90,
7bf59e10]
CACHE: Misaligned operation at range [
7bf5a478,
7bf5a5f8]
DHCP client bound to address 10.42.43.80 (1009 ms)
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Masahiro Yamada [Tue, 26 Jul 2016 18:47:58 +0000 (03:47 +0900)]
ARM: uniphier: move CONFIG_I2C_EEPROM to defconfig
We already have the entry for this option in Kconfig, so let's
migrate to it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tom Rini [Tue, 26 Jul 2016 21:34:51 +0000 (17:34 -0400)]
Merge git://git.denx.de/u-boot-mpc86xx
Tom Rini [Tue, 26 Jul 2016 21:34:28 +0000 (17:34 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq
Chen-Yu Tsai [Fri, 22 Jul 2016 10:16:10 +0000 (18:16 +0800)]
net: sun8i_emac: Drop redundant and incorrect setting of syscon register
In sun8i_emac_board_setup, the driver partially configures the syscon
register for H3 EPHY. However, the settings are incomplete, and
completely unusable. The correct settings are later set in
sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists.
It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not
have a 25 MHz clock the EPHY can use.
This patch removes the setting of the syscon register in board_setup,
and also moves set_syscon above mdio_init. While mdio_init does not
access the PHY, it is better to have the PHY parameters setup before
the MDIO bus is registered.
Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Fri, 22 Jul 2016 10:16:09 +0000 (18:16 +0800)]
net: sun8i_emac: Do not configure AHB2 clock
The sun8i_emac driver erroneously configures the AHB2 clock when it
assumes it is configuring the AXI gates, which is not even documented
or ever appeared in either the WiP kernel driver or Allwinner's original
driver.
As a result, AHB2 clock mux is set to an invalid setting, making the
EPHY unusable.
Fixes: a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Fri, 22 Jul 2016 10:16:08 +0000 (18:16 +0800)]
sunxi: Add EMAC ethernet0 alias for H3 dtsi
The sunxi ethernet address generation code looks for ethernet[0-3]
aliases to find ethernet controllers to generate MAC addresses for.
Without a valid address, the driver fails to register.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Tue, 26 Jul 2016 15:47:16 +0000 (17:47 +0200)]
sunxi: Add defconfig and dts file for the Orange Pi PC Plus SBC
There is a new Orange Pi PC *Plus* version available now,
this is an extended version of the regular Orange Pi PC
with sdio wifi and an eMMC.
The upstream kernel devs have decided that they want a separate
dts for the PC Plus rather then sharing a single dts between the
regular PC and the PC Plus. So add a new orangepi_pc_plus_defconfig
to match.
The added dts file matches the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>