Tien Fong Chee [Sun, 7 Nov 2021 15:08:55 +0000 (23:08 +0800)]
arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBF
This patch triggers warm reset to recover the MPFE NoC from corruption
due to high frequency transient clock output from HPS EMIF IOPLL at
VCO startup after peripheral RBF is programmed.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Tien Fong Chee [Sun, 7 Nov 2021 15:08:54 +0000 (23:08 +0800)]
arm: socfpga: arria10: Setting image magic value to romcode initswstate reg
The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID
value if the current FSBL image is found valid, otherwise BootROM will
look for next subsequent valid FSBL image when warm reset is triggered.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Hari Prasath [Mon, 13 Dec 2021 05:00:03 +0000 (10:30 +0530)]
ARM: mach-at91: Add compile time option to choose proper timer
New SoC's of AT91 family with ARM-9 core includes a regular timer and a 64-bit
timer.This patch adds a compile time option to the Makefile such that the old
timer driver is chosen and compiled as default if none of timer configuration
options are explicitly defined in the board configs.
Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
Tom Rini [Wed, 15 Dec 2021 19:51:44 +0000 (14:51 -0500)]
Merge tag 'clk-2022.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-clk
Clock patches for v2022.01-rc3
This adds better logging support for many CCF drivers, and clarifies some
documentation regarding clk_get_rate.
Patrick Delaunay [Fri, 19 Nov 2021 14:12:07 +0000 (15:12 +0100)]
clk: define LOG_CATEGORY for generic and ccf clocks
Define LOG_CATEGORY to allow filtering with log command
for generic clock and CCF clocks.
This patch also change existing printf, debug and pr_ macro
to log_ or dev_ macro.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Patrick Delaunay [Fri, 19 Nov 2021 14:12:06 +0000 (15:12 +0100)]
clk: cosmetic: reorder include files
Reorder include files in the U-Boot expected order:
the common.h header should always be first,
followed by other headers in order,
then headers with directories,
then local files.
It is a preliminary step for next patch.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Giulio Benetti [Sun, 14 Feb 2021 02:17:18 +0000 (03:17 +0100)]
clk: fix clk_get_rate() documentation
Improve clk_get_rate() @return documentation that otherwise is a bit
ambiguous. At the moment I expect to return 0 as error since the return
type is 'ulong', instead the function really returns negative value in
case the corresponding function pointer is null and returns 0 if the clock
is invalid.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Tom Rini [Wed, 15 Dec 2021 16:49:30 +0000 (11:49 -0500)]
Merge tag 'rpi-next-2022.01' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
- enable RPi Zero 2 W
- fix MMC numbering issue
- Update link to documentation
Tom Rini [Wed, 15 Dec 2021 12:14:20 +0000 (07:14 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Marvell/PCI: Fix size of the configuration cache and disallow ROM BAR
setting in pci_mvebu.c & pci-aardvark.c (Pali & Marek)
Pali Rohár [Thu, 11 Nov 2021 15:35:48 +0000 (16:35 +0100)]
arm: a37xx: pci: Do not allow setting ROM BAR on PCI Bridge
PCI Bridge which represents aardvark PCIe Root Port has Expansion ROM Base
Address register at offset 0x30 but its meaning is different than PCI's
Expansion ROM BAR register. Only address format of register is same.
In reality, this device does not have any configurable PCI BARs. So ensure
that write operation into BARs (including Expansion ROM BAR) is noop and
registers always contain zero address which indicates that bars are
unsupported.
Fixes:
cb056005dc67 ("arm: a37xx: pci: Add support for accessing PCI Bridge on root bus")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Thu, 11 Nov 2021 15:35:45 +0000 (16:35 +0100)]
pci: pci_mvebu: Do not allow setting ROM BAR on PCI Bridge
The PCI Bridge which represents mvebu PCIe Root Port has Expansion ROM
Base Address register at offset 0x30 but its meaning is different that
of PCI's Expansion ROM BAR register, although the address format of
the register is the same.
In reality, this device does not have any configurable PCI BARs. So
ensure that write operation into BARs (including Expansion ROM BAR) is a
noop and registers always contain zero address which indicates that BARs
are unsupported.
Fixes:
a7b61ab58d5d ("pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port)")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Marek Behún [Thu, 11 Nov 2021 15:35:44 +0000 (16:35 +0100)]
pci: pci_mvebu, pci_aardvark: Fix size of configuration cache
Since u32 takes up 4 bytes, we need to divide the number of u32s by 4
for cfgcache.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Tom Rini [Mon, 13 Dec 2021 15:20:25 +0000 (10:20 -0500)]
Merge tag 'u-boot-stm32-
20211213' of https://source.denx.de/u-boot/custodians/u-boot-stm
- enable KSZ90x1 PHY driver on DHCOR
- DHSOM boards:
- increase USB power-good delay
- add update_sf script to install U-Boot into SF
- increase PHY auto-negotiation timeout to 20 seconds
- fix SoM and board coding strap GPIO handling
# gpg verification failed.
Marek Vasut [Sat, 13 Nov 2021 02:28:03 +0000 (03:28 +0100)]
ARM: stm32: Enable KSZ90x1 PHY driver on DHCOR
Enable KSZ9x01 PHY driver in DHCOR common configuration, since the
AV96 board has this PHY populated on the PCB.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Marek Vasut [Sat, 13 Nov 2021 02:27:37 +0000 (03:27 +0100)]
ARM: dts: stm32: Add custom PHY reset bindings on AV96
The ethernet PHY must be reset on AV96, however DWMAC currently does
not support the MDIO-bus PHY GPIO reset bindings and the ethernet MAC
PHY reset property is going away on next DT sync. Add PHY specific
reset bindings to trigger the PHY reset and fix sporadic ethernet
malfunctions, until the next DT sync.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Marek Vasut [Sat, 13 Nov 2021 02:26:39 +0000 (03:26 +0100)]
ARM: stm32: Fix SoM and board coding strap GPIO handling on DHSOM
The variables retaining the strap values have to be initialized, always,
make it so. Moreover, free the requested GPIO list at the end to avoid
wasting memory.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Marek Vasut [Sat, 13 Nov 2021 02:26:05 +0000 (03:26 +0100)]
ARM: stm32: Increase PHY auto-negotiation timeout to 20s on DHSOM
The Micrel PHYs on known DHSOM based boards take a while to come out
of reset, increase the auto-negotiation timeout to prevent it from
timing out in case the ethernet is used right after the board was
reset.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Marek Vasut [Sat, 13 Nov 2021 02:25:13 +0000 (03:25 +0100)]
ARM: stm32: Add update_sf script to install U-Boot into SF on DHSOM
Add script to read U-Boot from SD card and write it to matching
locations in the SPI NOR, thus making the SPI NOR bootable. The
script erases the entire SPI NOR, including U-Boot environment,
to make sure the installation is clean. To retain environment
from current running U-Boot, run 'saveenv' after running the
'update_sf' script.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Marek Vasut [Sat, 13 Nov 2021 02:24:44 +0000 (03:24 +0100)]
ARM: stm32: Increase USB power-good delay on DHSOM
The USB hub on STM32MP1 DHCOM boards needs to wait a bit longer until
the USB Vbus is stable. Increase the USB power-good delay to 1 s.
This adds default-undefined STM32MP_BOARD_EXTRA_ENV variable into
stm32mp15_common.h to reduce duplication in board-specific config
files adding custom environment.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tom Rini [Mon, 13 Dec 2021 12:11:09 +0000 (07:11 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-sh
- A few clean ups for the RZG2
Hari Prasath [Wed, 8 Dec 2021 05:14:01 +0000 (10:44 +0530)]
ARM: mach-at91: update alternate function of signal PD20
The alternate function of PD20 is 4 as per the datasheet of
sama7g5 and not 5 as defined earlier.
Fixes:
558378a4cd ("ARM: mach-at91: add support for new SoC sama7g5")
Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
Adam Ford [Mon, 6 Dec 2021 16:29:30 +0000 (10:29 -0600)]
configs: beacon-rzg2m: Config to address new aliases
The resync of the device trees from Linux 5.16-rc3 caused aliases
to appear on the MMC devices which changed the numbering.
This changed the default boot device and caused boot failure.
Update the mmcdev variable to reflect the new aliases.
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Mon, 6 Dec 2021 16:29:29 +0000 (10:29 -0600)]
ARM: rmobile: Fix rzg2_beacon_defconfig to address new aliases
The resync of the device trees from Linux 5.16-rc3 caused aliases
to appear on the MMC devices which changed the numbering.
This broke the reading/writing of the environmental variables,
so update the defconfig accordingly.
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Mon, 6 Dec 2021 16:29:28 +0000 (10:29 -0600)]
arm: dts: Create common rz-g2-beacon-u-boot file
The rzg2_beacon_defconfig creates an image for RZ/G2[MNH] and
as such creates three different device trees and each of them
have a corresponding -u-boot.dtsi file which are basically
copies of each other. Create a common include file to be
referenced by each of the respective board-u-boot.dtsi files
to reduce duplicate code and simplify support going forward.
This also restores some lost functionality from the device
tree re-sync and updates the MAINTAINER file to include all
beacon-renesom device tree files.
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Mon, 6 Dec 2021 16:29:27 +0000 (10:29 -0600)]
arm: dts: beacon-rzg2: Resync device trees with Linux 5.16-rc3
The device trees for the Beacon RZ/G2[MNH] boards have undergone
some changes over time, so resync them now.
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Mon, 6 Dec 2021 16:29:26 +0000 (10:29 -0600)]
net: ravb: Support multiple clocks
The RZ/G2 series uses an external clock as a reference to the AVB.
If this clock is controlled by an external programmable clock,
it must be requested by the consumer or it will not turn on.
In order to do this, update the driver to use bulk enable and
disable functions to enable clocks for boards with multiple clocks.
Signed-off-by: Adam Ford <aford173@gmail.com>
Tom Rini [Fri, 10 Dec 2021 12:58:43 +0000 (07:58 -0500)]
Merge tag 'efi-2022-01-rc4-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2022-01-rc4-2
UEFI:
* correctly handle missing TPM device
* prepare for block devices for U-Boot as EFI app
# gpg: Signature made Fri 10 Dec 2021 04:29:20 AM EST
# gpg: using RSA key
6DC4F9C71F29A6FA06B76D33C481DBBC2C051AC4
# gpg: Good signature from "Heinrich Schuchardt <xypron.glpk@gmx.de>" [unknown]
# gpg: aka "[jpeg image of size 1389]" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6DC4 F9C7 1F29 A6FA 06B7 6D33 C481 DBBC 2C05 1AC4
Simon Glass [Sat, 4 Dec 2021 15:56:32 +0000 (08:56 -0700)]
efi: Add a media/block driver for EFI block devices
Add a block driver which handles read/write for EFI block devices. This
driver actually already exists ('efi_block') but is not really suitable
for use as a real U-Boot driver:
- The operations do not provide a udevice
- The code is designed for running as part of EFI loader, so uses
EFI_PRINT() and EFI_CALL().
- The bind method probes the device, which is not permitted
- It uses 'EFI' as its parent device
The new driver is more 'normal', just requiring its platform data be set
up in advance.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Simon Glass [Sat, 4 Dec 2021 15:56:31 +0000 (08:56 -0700)]
efi: Add uclass for devices provided by UEFI firmware
UCLASS_EFI_LOADER is used for devices created by applications and
drivers loaded by U-Boots UEFI implementation.
This patch provides a new uclass (UCLASS_EFI_MEDIA) to be used for devices
that provided by a UEFI firmware calling U-Boot as an EFI application.
If the two uclasses can be unified, is left to future redesign.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Simon Glass [Sat, 4 Dec 2021 15:56:30 +0000 (08:56 -0700)]
efi: Rename UCLASS_EFI and IF_TYPE_EFI
These names are better used for access to devices provided by an EFI
layer. Use EFI_LOADER instead here, since these are only available in
U-Boot's EFI_LOADER layer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Masahisa Kojima [Tue, 7 Dec 2021 05:15:33 +0000 (14:15 +0900)]
efi_loader: correctly handle no tpm device error
When the TCG2 protocol is installed in efi_tcg2_register(),
TPM2 device must be present.
tcg2_measure_pe_image() expects that TCP2 protocol is installed
and TPM device is available. If TCG2 Protocol is installed but
TPM device is not found, tcg2_measure_pe_image() returns
EFI_SECURITY_VIOLATION and efi_load_image() ends with failure.
The same error handling is applied to
efi_tcg2_measure_efi_app_invocation().
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Masahisa Kojima [Tue, 7 Dec 2021 05:15:32 +0000 (14:15 +0900)]
efi_loader: check tcg2 protocol installation outside the TCG protocol
There are functions that calls tcg2_agile_log_append() outside
of the TCG protocol invocation (e.g tcg2_measure_pe_image).
These functions must to check that TCG2 protocol is installed.
If not, measurement shall be skipped.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Masahisa Kojima [Tue, 7 Dec 2021 05:15:31 +0000 (14:15 +0900)]
efi_loader: efi_tcg2_register returns appropriate error
This commit modify efi_tcg2_register() to return the
appropriate error.
With this fix, sandbox will not boot because efi_tcg2_register()
fails due to some missing feature in GetCapabilities.
So disable sandbox if EFI_TCG2_PROTOCOL is enabled.
UEFI secure boot variable measurement is not directly related
to TCG2 protocol installation, tcg2_measure_secure_boot_variable()
is moved to the separate function.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Alexander Dahl [Fri, 3 Dec 2021 14:46:57 +0000 (15:46 +0100)]
doc: usage: Fix command in fdt overlay apply sequence
Literally adhering to the docs gave this wrong output:
U-Boot> setenv fdtaddr 0x87f00000
U-Boot> fdtaddr $fdtaddr
Unknown command 'fdtaddr' - try 'help'
Fixes:
d80162cfc559 ("doc: Document how to apply fdt overlays")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Thu, 9 Dec 2021 13:43:30 +0000 (08:43 -0500)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
This fixes two regressions: eMMC operation on boards with WiFi (so using
three MMC devices), and a repeated wrong error message in USB gadget
mode (fastboot, ums).
Andre Przywara [Tue, 2 Nov 2021 19:45:47 +0000 (19:45 +0000)]
sunxi: Remove misleading USB-OTG charger message
The sunxi MUSB glue driver has some code to check for external VBUS
presence when it's going to use the MUSB host mode, and it warns if
there is VBUS provided through the cable (in sunxi_musb_enable()).
This code was apparently copied to the USB gadget detection code
(g_dnl_board_usb_cable_connected()), but here we actually *expect*
external VBUS power, so a warning is wrong and confusing.
So far this message rarely triggered, but a recent patch (
6fa41cdd19b9)
changed this:
===========================
=> ums 0 mmc 2
UMS: LUN 0, dev mmc 2, hwpart 0, sector 0x0, count 0xe90000
A charger is plugged into the OTG
/A charger is plugged into the OTG
\A charger is plugged into the OTG
|A charger is plugged into the OTG
-A charger is plugged into the OTG
....
===========================
Remove the message for the gadget cable detection call, and just return
the status of the VBUS detection, as this is what the callers are after.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Andre Przywara [Tue, 30 Nov 2021 23:18:54 +0000 (23:18 +0000)]
sunxi: dts: Fix typoed eMMC check
Commit
03510bf62149 ("sunxi: only include alias for eMMC when mmc2
used") protected the eMMC alias in U-Boot's DT stub the with the
associated Kconfig symbol, but was actually using the wrong name.
Fix the name of the symbol to match what's defined in Kconfig and what
the defconfig files actually use.
Fixes:
03510bf62149 ("sunxi: only include alias for eMMC when mmc2 used")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: 5kft@5kft.org
Reviewed-by: Icenowy Zheng <icenowy@aosc.io>
Tudor Ambarus [Wed, 3 Nov 2021 17:07:41 +0000 (19:07 +0200)]
ARM: dts: at91: sama7g5ek: Add QSPI0 node
QSPI0 has a MX66LM1G45G SPI NOR flash connected.
Enable the controller and describe the flash.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tudor Ambarus [Wed, 3 Nov 2021 17:07:40 +0000 (19:07 +0200)]
ARM: dts: at91: sama7g5: Add QSPI0 and OSPI1 nodes
sama7g5 embedds an OSPI and a QSPI controller:
1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash
and OctaFlash Protocols Supported.
2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tudor Ambarus [Wed, 3 Nov 2021 16:47:10 +0000 (18:47 +0200)]
spi: atmel-quadspi: Add support for SAMA7G5 QSPI
sama7g5 QSPI has:
1/ One Octal Serial Peripheral Interfaces (QSPI0) Supporting Up to
200 MHz DDR. Octal, TwinQuad, Hyperflash and OctaFlash Protocols Supported
2/ One Quad Serial Peripheral Interfaces (QSPI1) Supporting Up to
90 MHz DDR/133 MHz SDR
The QSPI controller of SAMA7G5 uses different clock domains, hence extra
synchronization operations must be performed before accessing some
registers. Differentiate between the versions of the IP using has_gclk.
Differentiate between QSPI0 and QSPI1 with has_octal.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tom Rini [Mon, 6 Dec 2021 03:42:07 +0000 (22:42 -0500)]
Merge tag 'dm-pull-5dec21a' of https://source.denx.de/u-boot/custodians/u-boot-dm into next
binman refactoring to improve section handling
bloblist - allow it to be allocated
sandbox config-header cleanup
# gpg: Signature made Sun 05 Dec 2021 10:14:24 PM EST
# gpg: using RSA key
B25C0022AF86A7CC1655B6277F173A3E9008ADE6
# gpg: issuer "sjg@chromium.org"
# gpg: Good signature from "Simon Glass <sjg@chromium.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B25C 0022 AF86 A7CC 1655 B627 7F17 3A3E 9008 ADE6
Simon Glass [Wed, 24 Nov 2021 16:26:48 +0000 (09:26 -0700)]
ide: Drop ATA_PORT_ADDR
This is not needed anymore. Drop it to simplify the code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Wed, 24 Nov 2021 16:26:47 +0000 (09:26 -0700)]
ide: Drop unused CONFIG options
CONFIG_SYS_ATA_PORT_ADDR is not used in the code anymore. Drop it and use
ATA_PORT_ADDR() locally instead.
Drop CONFIG_IDE_RESET_ROUTINE and CONFIG_IDE_SWAP_IO which are also
unused.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 24 Nov 2021 16:26:46 +0000 (09:26 -0700)]
sandbox: Drop CONFIG_SYS_TIMER_RATE
This is not used by sandbox since it uses driver model for the timer.
Drop it.
Also update the tools_only build to avoid build errors, since it does
actually build U-Boot too. Enable DM so we can use CONFIG_TIMER,
disable EFI_LOADER to avoid an error about board_quiesce_devices() and
disable NET to avoid having to define CONFIG_AVB_BUF_ADDR
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 24 Nov 2021 16:26:45 +0000 (09:26 -0700)]
keyboard: Add a migration message
A few boards still use the old keyboard mechanism. Set a deadline for them
to update to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 24 Nov 2021 16:26:44 +0000 (09:26 -0700)]
Convert CONFIG_KEYBOARD to Kconfig
This converts the following to Kconfig:
CONFIG_KEYBOARD
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 24 Nov 2021 16:26:41 +0000 (09:26 -0700)]
Convert CONFIG_SYS_FDT_LOAD_ADDR to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_FDT_LOAD_ADDR
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 24 Nov 2021 16:26:40 +0000 (09:26 -0700)]
sandbox: Drop CONFIG_HOST_MAX_DEVICES
This can go in the related header file. Drop the CONFIG option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Wed, 24 Nov 2021 16:26:39 +0000 (09:26 -0700)]
trace: sandbox: Use only the Kconfig options
At present there are Kconfig options for tracing, but sandbox uses
plain #defines to set them. Correct this and make the tracing command
default to enabled so that this is not needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 24 Nov 2021 04:09:53 +0000 (21:09 -0700)]
binman: Rename _ReadSubnodes() to ReadEntries()
This method name is more commonly used for this function. Use it
consistently.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 24 Nov 2021 04:09:52 +0000 (21:09 -0700)]
binman: Support lists of external blobs
Sometimes it is useful to have a list of related external blobs in a
single entry. An example is the DDR binaries used by meson. There are
9 files in total. Add support for this, so we don't have to have a
separate entry for each.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 24 Nov 2021 04:09:51 +0000 (21:09 -0700)]
dtoc: Add support for reading string-list properties
Add a function to read a list of strings from the devicetree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 24 Nov 2021 04:09:50 +0000 (21:09 -0700)]
binman: Allow extracting a file in an alternative format
In some cases entries encapsulate other data and it is useful to access
the data within. An example is the fdtmap which consists of a 16-byte
header, followed by a devicetree.
Provide an option to specify an alternative format when extracting files.
In the case of fdtmap, this is 'fdt', which produces an FDT file which can
be viewed with fdtdump.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 24 Nov 2021 04:09:49 +0000 (21:09 -0700)]
binman: Allow listing an image created by a newer version
If an older version of binman is used to list images created by a newer
one, it is possible that it will contain entry types that are not
supported. At present this produces an error.
Adjust binman to use a plain 'blob' entry type to cope with this, so the
image can at least be listed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 24 Nov 2021 04:09:48 +0000 (21:09 -0700)]
binman: Allow providing tools and blob directories
At present it is necessary to symlink files containing external blobs into
the U-Boot tree in order for binman to find them. This is not very
convenient.
Add two new environment/Makefile variables to help with this. Add
documentation as well, fixing a related nit.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 4 Nov 2021 03:09:20 +0000 (21:09 -0600)]
bloblist: Support allocating the bloblist
Typically the bloblist is positioned at a fixed address in memory until
relocation. This is convenient when it is set up in SPL or before
relocation.
But for EFI we want to set it up only when U-Boot proper is running. Add
a way to allocate it using malloc() and update the documentation to cover
this aspect of bloblist.
Note there are no tests of this feature at present, nor any direct testing
of bloblist_init().
This can be added, e.g. by making this option controllable at runtime.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 3 Dec 2021 14:02:49 +0000 (09:02 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
Simon Glass [Tue, 23 Nov 2021 18:03:54 +0000 (11:03 -0700)]
binman: Rename testCbfsNoCOntents()
Use a lower-case O as was intended.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:53 +0000 (11:03 -0700)]
binman: cfbs: Refactor ObtainContents() for consistency
Update this to use the same arguments as entry_Section uses.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:52 +0000 (11:03 -0700)]
binman: cbfs: Refactor the init process
Update the constructor to work in the recommended way, where the node
properties are read in a separate function. This makes it more similar to
entry_Section.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:51 +0000 (11:03 -0700)]
binman: Use normal entries in cbfs
This currently uses _cbfs_entries[] to store entries. Since the entries
are in fact valid etypes, we may as well use the same name as
entry_Section uses, which is _entries. This allows reusing more of the
code there (in a future patch).
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:50 +0000 (11:03 -0700)]
binman: Move cbfs.ObtainContents() down a bit
It is easier to understand this file if reading the entries comes before
obtaining the contents, since that is the order in which Binman proceeds.
Move the function down a bit.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:49 +0000 (11:03 -0700)]
binman: Update the section documentation
Expand this to explain subclassing better and also to tidy up formatting
for rST.
Fix a few pylint warnings to avoid dropping the score.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:48 +0000 (11:03 -0700)]
binman: Allow control of which entries to read
The ObtainContents() and GetEntryContents() methods in this file read
every single entry in the section. This is the common case.
However when one of the entries has had its data updated (e.g. with
'binman replace') we don't want to read it again from the file. Allow
the entry to be skipped, for this purpose. This is currently done in the
CBFS implementation, so adding it here will allow that to use more of
the entry_Section code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:47 +0000 (11:03 -0700)]
binman: Allow overriding BuildSectionData()
This method is currently marked private. However it is useful to be able
to subclass it, since much of the entry_Section code can be reused. Rename
it.
Also document one confusing part of this code, so people can understand
how to add a test for this case.
Fix up a few pylint warnings to avoid regressing the score.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:46 +0000 (11:03 -0700)]
binman: Drop the filename property in entry_Section
This is not used and does nothing. Drop it.
Add a tweak to avoid reducing the pylint score.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:45 +0000 (11:03 -0700)]
binman: Drop the underscore in _ReadEntries()
This function can be overridden so should not have an underscore. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:44 +0000 (11:03 -0700)]
binman: Correct comments for ReadChildData()
The comment here is incomplete. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:43 +0000 (11:03 -0700)]
binman: Correct init of entry in Entry class
This should not have an underscore. Drop it so that derived classes can
rely on it being set correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:42 +0000 (11:03 -0700)]
binman: Add a way to obtain the version
Add a -V option which shows the version number of binman. For now this
just uses a local 'version' file. Once the tool is packaged in some way
we can figure out an approach that suits.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:41 +0000 (11:03 -0700)]
binman: Tidy up style in cmdline
Update this file to improve the pylint score a little. The remaining item
is:
Function name "ParseArgs" doesn't conform to snake_case naming style
which needs some binman-wide renaming.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:40 +0000 (11:03 -0700)]
dtoc: Add support for reading fixed-length bytes properties
Add functions to read a sequence of bytes from the devicetree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:39 +0000 (11:03 -0700)]
dtoc: Add support for reading 64-bit ints
Add functions to read a 64-bit integer property from the devicetree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 23 Nov 2021 18:03:38 +0000 (11:03 -0700)]
dtoc: Bring in the libfdt module automatically
Use the same technique as with binman to load this module from the U-Boot
tree if available. This allows running tests without having to specify
the PYTHONPATH variable.
Signed-off-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Sat, 20 Nov 2021 12:28:33 +0000 (13:28 +0100)]
sandbox: replace putchar(ch) by fputc(ch, stdout)
When compiled with -Og for better debugability u-boot ends up in a stack
overflow using
gcc (Ubuntu 11.2.0-7ubuntu2) 11.2.0
GNU Binutils for Ubuntu 2.37
putchar(ch) is defined as a macro which ends up calling U-Boot's putc()
implementation instead of the glibc one, which calls os_putc() ...
Let's use fputc(ch, stdout) instead as fputc() does not exist in U-Boot.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Alexander Preißner [Sat, 6 Nov 2021 01:08:59 +0000 (02:08 +0100)]
drivers: core: lists: fix for loop index type
* fixes the bug in function bind_drivers_pass that for
CONFIG_CC_OPTIMIZE_FOR_SIZE=n and no entries in the driver_info list,
i.e. n_ents == 0, the processor steps into the first loop iteration
despite the loop condition being false.
* the Xilinx Zynq-7000 device would eventually hang due to an attempted
access to an invalid memory address
* the bug is fixed by changing the type of idx from uint to int
Board: zynq-zybo
Target: ARM
Compiler: arm-none-eabi-gcc 9.2.1
Signed-off-by: Alexander Preissner <fpga-garage@preissner-muc.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 2 Dec 2021 14:58:20 +0000 (09:58 -0500)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-net
- Two fixes from Marek for designware and mdio.
Tom Rini [Thu, 2 Dec 2021 12:16:04 +0000 (07:16 -0500)]
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-net into next
- New Broadcom NetXtreme driver
- Support for socat for netconsole
- Felix switch soft reset fix
Tom Rini [Thu, 2 Dec 2021 12:12:28 +0000 (07:12 -0500)]
Merge branch '2021-12-01-assorted-updates' into next
- Have SPL skip length 0 images, some clean-ups related to CONFIG
symbols and the known list of unmigrated symbols and pinctrl updates.
Thomas Skibo [Wed, 24 Nov 2021 22:32:10 +0000 (14:32 -0800)]
riscv: Enable SPI flash env for SiFive Unmatched.
Enable saving environment to SPI flash memory on SiFive
Unmatched.
Signed-off-by: Thomas Skibo <thomas-git@skibo.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Thomas Skibo [Wed, 24 Nov 2021 22:32:09 +0000 (14:32 -0800)]
riscv: Support booting SiFive Unmatched from SPI.
Configure SPI flash devices into SPL. Add SPI boot option to spl.c.
Document how to format flash for booting.
Signed-off-by: Thomas Skibo <thomas-git@skibo.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Padmarao Begari [Wed, 17 Nov 2021 12:51:19 +0000 (18:21 +0530)]
doc: board: Update Microchip MPFS Icicle Kit doc
UART1 use for U-Boot and Linux console instead of UART0 and
UART0 is reserved for Hart Software Services(HSS).
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Padmarao Begari [Wed, 17 Nov 2021 12:51:18 +0000 (18:21 +0530)]
riscv: Update Microchip MPFS Icicle Kit support
This patch updates Microchip MPFS Icicle Kit support. For now,
add Microchip I2C driver, set environment variables for
mac addresses and default build for SBI_V02.
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Padmarao Begari [Wed, 17 Nov 2021 12:51:17 +0000 (18:21 +0530)]
riscv: dts: Split Microchip device tree
The device tree split into .dtsi and .dts files, common
device node for eMMC/SD, enable I2C1, UART1 for console
instead of UART0, enable the DDR 2GB memory and in
that 288MB memory is reserved for fabric buffer.
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Padmarao Begari [Wed, 17 Nov 2021 12:51:16 +0000 (18:21 +0530)]
i2c: Add Microchip PolarFire SoC I2C driver
Add I2C driver code for the Microchip PolarFire SoC.
This driver supports I2C data transfer and probe for I2C
slave addresses.
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Padmarao Begari [Wed, 17 Nov 2021 12:51:15 +0000 (18:21 +0530)]
net: macb: Remove Microchip compatible string
Remove the microchip compatible string and default compatible "cdns,macb"
support both 32-bit and 64-bit DMA access.
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Leo Yu-Chi Liang [Thu, 4 Nov 2021 01:53:26 +0000 (09:53 +0800)]
board: ae350: Support autoboot from RAM
Add boot command "bootcmd_ram" to support autoboot from RAM.
This feature could be useful at the very initial state of chip design
when there is only a minimal set of peripheral. (e.g. without mmc and mac ..etc)
The kernel image is default to be loaded at 0x2000000 via debug port,
and the following script serves as an example:
spl()
{
cmd="riscv64-linux-gdb -q \
-ex \"target remote $host:$port\" \
-ex \"load\" \
-ex \"thread apply all set \\\$pc=&_start\" \
-ex \"thread apply all set \\\$a0=\\\$mhartid\" \
-ex \"thread apply all set \\\$a1=<dtb address>\" \
-ex \"restore u-boot.itb binary 0x200000\" \
-ex \"restore Image binary 0x2000000\" \
-ex \"c\" \
spl/u-boot-spl
"
echo $cmd
eval $cmd
}
The address where the kernel is loaded can be altered by
changing the value of KERNEL_IMAGE_ADDR.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Marek Vasut [Sat, 13 Nov 2021 02:23:52 +0000 (03:23 +0100)]
net: dwc_eth_qos: Enable clock in probe
Enable DWC IP clock in driver probe, so the MII access is possible even
outside of active network transfers. This is particularly useful when
using 'mii' or 'mdio' commands to explore PHY state, neither of which
works with DWMAC currently due to the disabled clock.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Marek Vasut [Sat, 13 Nov 2021 02:23:11 +0000 (03:23 +0100)]
net: eth-phy: Handle gpio_request_by_name() return value
The gpio_request_by_name() returns zero in case of success, however the
conditional return value check in gpio_request_by_name() checks only for
(ret != -ENOENT) and if the condition is true, returns ret outright.
This leads to a situation where successful gpio_request_by_name() return
leads to immediate successful eth_phy_of_to_plat() return as well, and
to skipped parsing of "reset-assert-us" and "reset-deassert-us", so the
PHY driver operates with valid reset GPIO, but with assert/deassert times
set to default, which is 0, instead of the values from DT. This breaks
PHY reset.
Fix this by checking if return value is non-zero and then for this one
single allowed non-zero return value, -ENOENT.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Bharat Gooty [Mon, 8 Nov 2021 22:46:11 +0000 (14:46 -0800)]
board: brcm-ns3: Load netXtreme firmware
Load NetXtreme firmware in board_init when BNXT_ETH is selected.
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Roman Bacik <roman.bacik@broadcom.com>
Bharat Gooty [Mon, 8 Nov 2021 22:46:10 +0000 (14:46 -0800)]
net: brcm: netXtreme driver
Broadcom bnxt L2 driver support. Used by the Broadcom
iproc platforms.
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Roman Bacik <roman.bacik@broadcom.com>
Ramon Fried [Thu, 2 Dec 2021 06:15:27 +0000 (08:15 +0200)]
driver: net: Makefile: order file alphabetically
Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
Radu Bulie [Sat, 27 Nov 2021 12:52:35 +0000 (14:52 +0200)]
drivers: net: Soft reset felix switch core
It turns out that in custom designs if the system is reset
multiple times in conjunction with a slight increase in external
temperature, the felix switch starts to behave in a strange way:
packets are no longer received on the ENECT interface connected
to the L2switch internal port (the TX side of internal port stops working
or the packets do not reach there. It is not very clear where
the packets remain blocked. None of the counters points to a disruption
in the L2switch)
The issue is not reproducible on NXP reference designs.
It was observed that by adding the switch core reset, the problem
goes aways, even if intensive testing in temperature chambers
is applied.
The current patch performs soft reset on the switch core to ensure proper
operation of the L2switch.
Signed-off-by: Radu Bulie <radu-andrei.bulie@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Andy Shevchenko [Wed, 17 Nov 2021 17:15:06 +0000 (20:15 +0300)]
tools/netconsole: Add support for socat
socat is a very powerful tool to work with socets (and not only)
in UNIX systems. Let's add support for it in netconsole.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Ferry Toth <fntoth@gmail.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Nishanth Menon [Tue, 19 Oct 2021 17:32:29 +0000 (12:32 -0500)]
spl: fit: Skip attempting to load 0 length image
When, for various reasons, a bad FIT image is used where a loadable
image is marked as 0 length, attempt is made for a 0 length allocation and
read of 0 byte read operation.
Instead provide warning in log and skip attempting to do such a load.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Patrick Delaunay [Fri, 19 Nov 2021 09:02:27 +0000 (10:02 +0100)]
dm: add debug message when failed to select the default pinctrl
Add a message on probe in driver model core when the default
pinctrl selection failed.
This message is displayed only when the pinctrl API is
implemented, i.e. when result is not ENOSYS.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrick Delaunay [Fri, 19 Nov 2021 09:02:26 +0000 (10:02 +0100)]
pinctrl: change result for unsupported API
Use the return value ENOSYS for unsupported API
- pinctrl_generic_set_state
- pinctrl_select_state
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Patrick Delaunay [Mon, 8 Nov 2021 09:21:22 +0000 (10:21 +0100)]
scripts: remove CONFIG_IS_ENABLED and CONFIG_VAL in config_whitelist.txt
The helper macro CONFIG_IS_ENABLED and CONFIG_VAL are not real
configurations and they are no more present in u-boot.cfg so they can
be removed in config_whitelist.txt.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Simon Glass <sjg@chromium.org>
Patrick Delaunay [Mon, 8 Nov 2021 09:21:21 +0000 (10:21 +0100)]
scripts: remove CONFIG_IS_ENABLED and CONFIG_VAL in generated u_boot.cfg
The two helpers macros CONFIG_IS_ENABLED and CONFIG_VAL are defined in
include/linux/kconfig.h but they are not real configurations; they can
be safely removed in the generated configuration file "u-boot.cfg".
This patch simplifies the comparison of this U-Boot configuration file.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 1 Dec 2021 18:30:59 +0000 (13:30 -0500)]
Merge branch '2021-12-01-Kconfig-migrations' into next
- Finish converting CONFIG_USE_BOOTCOMMAND, CONFIG_BOOTCOMMAND,
CONFIG_RAMBOOTCOMMAND, CONFIG_NFSBOOTCOMMAND, all of
CONFIG_SYS_[BO]R[0-7]_PRELIM, CONFIG_FSL_DDR_BIST and
CONFIG_FSL_DDR_INTERACTIVE.