Srinivas Kandagatla [Fri, 2 Dec 2022 15:20:52 +0000 (16:20 +0100)]
arm64: dts: qcom: sm8450: add GPR node
Add Generic Packet Router (GPR) device node with ADSP services.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221202152054.357316-2-krzysztof.kozlowski@linaro.org
Brian Masney [Fri, 2 Dec 2022 12:09:18 +0000 (07:09 -0500)]
arm64: dts: qcom: sa8540p-ride: enable PCIe support
Add the vreg_l11a, pcie3a, pcie3a_phy, and tlmm nodes that are necessary
in order to get PCIe working on the QDrive3.
This patch also increases the width of the ranges property for the PCIe
switch that's found on this platform. Note that this change requires
the latest trustzone (TZ) firmware that's available from Qualcomm as
of November 2022. If this is used against a board with the older
firmware, then the board will go into ramdump mode when PCIe is probed
on startup.
The ranges property is overridden in this sa8540p-ride.dts file since
this is what's used to describe the QDrive3 variant with dual SoCs.
There's another variant of this board that only has a single SoC where
this change is not applicable, and hence why this specific change was
not done in sa8540p.dtsi.
These changes were derived from various patches that Qualcomm
delivered to Red Hat in a downstream kernel.
Signed-off-by: Brian Masney <bmasney@redhat.com>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221202120918.2252647-1-bmasney@redhat.com
Adam Skladowski [Wed, 30 Nov 2022 20:09:50 +0000 (21:09 +0100)]
arm64: dts: qcom: sm6115: Add smmu fallback to qcom generic compatible
Add fallback to generic qcom mmu-500 implementation.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221130200950.144618-13-a39.skl@gmail.com
Adam Skladowski [Wed, 30 Nov 2022 20:09:49 +0000 (21:09 +0100)]
arm64: dts: qcom: sm6115: Add WCN node
Add WCN node to allow using wifi module.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221130200950.144618-12-a39.skl@gmail.com
Adam Skladowski [Wed, 30 Nov 2022 20:09:48 +0000 (21:09 +0100)]
arm64: dts: qcom: sm6115: Add i2c/spi nodes
Add I2C/SPI nodes for SM6115.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221130200950.144618-11-a39.skl@gmail.com
Adam Skladowski [Wed, 30 Nov 2022 20:09:47 +0000 (21:09 +0100)]
arm64: dts: qcom: sm6115: Add GPI DMA
Add GPI DMA node which will be wired to i2c/spi/uart.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221130200950.144618-10-a39.skl@gmail.com
Adam Skladowski [Wed, 30 Nov 2022 20:09:46 +0000 (21:09 +0100)]
arm64: dts: qcom: sm6115: Add mdss/dpu node
Add mdss and dpu node to enable display support on SM6115.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221130200950.144618-9-a39.skl@gmail.com
Adam Skladowski [Wed, 30 Nov 2022 20:09:45 +0000 (21:09 +0100)]
arm64: dts: qcom: sm6115: Add dispcc node
Add display clock controller to allow controlling display related clocks.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Pushed dsi_phy reference into next patch]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221130200950.144618-8-a39.skl@gmail.com
Adam Skladowski [Wed, 30 Nov 2022 20:09:44 +0000 (21:09 +0100)]
arm64: dts: qcom: sm6115: Add rpm-stats node
Add rpm stats node.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221130200950.144618-7-a39.skl@gmail.com
Adam Skladowski [Wed, 30 Nov 2022 20:09:43 +0000 (21:09 +0100)]
arm64: dts: qcom: sm6115: Add PRNG node
Add a node for the PRNG to enable hw-accelerated pseudo-random number
generation.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221130200950.144618-6-a39.skl@gmail.com
Adam Skladowski [Wed, 30 Nov 2022 20:09:42 +0000 (21:09 +0100)]
arm64: dts: qcom: sm6115: Add TSENS node
Add nodes required for TSENS block using the common qcom,tsens-v2 binding.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221130200950.144618-5-a39.skl@gmail.com
Adam Skladowski [Wed, 30 Nov 2022 20:09:41 +0000 (21:09 +0100)]
arm64: dts: qcom: sm6115: Add cpufreq-hw support
Add cpufreq-hw node and assign qcom,freq-domain properties
to CPUs to enable CPU clock scaling.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221130200950.144618-4-a39.skl@gmail.com
Lin, Meng-Bo [Mon, 28 Nov 2022 05:16:32 +0000 (05:16 +0000)]
arm64: dts: qcom: msm8916-wingtech-wt88047: Add flash LED
WT88047 uses OCP 8110 Flash LED driver. Add it to the device tree.
Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221128051512.125148-1-linmengbo0689@protonmail.com
Krzysztof Kozlowski [Fri, 25 Nov 2022 14:42:08 +0000 (15:42 +0100)]
arm64: dts: qcom: align LED node names with dtschema
The node names should be generic and DT schema expects certain pattern:
qcom/msm8998-oneplus-cheeseburger.dtb: leds: 'button-backlight' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
qcom/sc7180-trogdor-coachz-r1.dtb: pwmleds: 'keyboard-backlight' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221125144209.477328-1-krzysztof.kozlowski@linaro.org
Parikshit Pareek [Fri, 18 Nov 2022 02:51:58 +0000 (08:21 +0530)]
arm64: dts: qcom: add SA8540P ride(Qdrive-3)
Introduce the Qualcomm SA8540P ride automotive platform, also known as
Qdrive-3 development board.
This initial contribution supports SMP, CPUFreq, cluster idle, UFS, RPMh
regulators, debug UART, PMICs, remoteprocs and USB.
The SA8540P ride contains four PM8450 PMICs. A separate DTSI file has
been created for PMIC, so that it can be used for future SA8540P based
boards.
Signed-off-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Tested-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Tested-by: Eric Chanudet <echanude@redhat.com>
Reviewed-by: Eric Chanudet <echanude@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221118025158.16902-3-quic_ppareek@quicinc.com
Konrad Dybcio [Thu, 17 Nov 2022 14:16:13 +0000 (15:16 +0100)]
arm64: dts: qcom: sm8450-nagara: Add gpio line names for TLMM
Sony ever so graciously provides GPIO line names in their downstream
kernel (though sometimes they are not 100% accurate and you can judge
that by simply looking at them and with what drivers they are used).
Add these to the PDX223&224 DTSIs to better document the hardware.
Diff between 223 and 224:
< gpio-line-names = "NC", /* GPIO_0 */
< "NC",
< "NC",
< "NC",
> gpio-line-names = "TELE_SPI_MISO", /* GPIO_0 */
> "TELE_SPI_MOSI",
> "TELE_SPI_CLK",
> "TELE_SPI_CS_N",
< "PM8010_2_RESET_N",
> "NC",
< "NC",
> "UWIDEC_PWR_EN",
< "TOF_RST_N",
> "NC"
< "QLINK1_REQ",
< "QLINK1_EN", /* GPIO_160 */
< "QLINK1_WMSS_RESET_N",
> "NC",
> "NC", /* GPIO_160 */
> "NC",
The tele lens setup is different on 1 IV and 5 IV and power wiring
is different for some lenses, so it makes sense. As for QLINK, no
idea.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117141613.19942-1-konrad.dybcio@linaro.org
Konrad Dybcio [Thu, 17 Nov 2022 10:58:44 +0000 (11:58 +0100)]
arm64: dts: qcom: msm8994: Drop spi-max-frequency from SPI host
This is a device property, not a bus host one.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117105845.13644-1-konrad.dybcio@linaro.org
Manivannan Sadhasivam [Thu, 17 Nov 2022 05:31:43 +0000 (11:01 +0530)]
arm64: dts: qcom: sm8450: Supply clock from cpufreq node to CPUs
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.
So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117053145.10409-3-manivannan.sadhasivam@linaro.org
Bryan O'Donoghue [Thu, 17 Nov 2022 00:32:32 +0000 (00:32 +0000)]
arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Add vision mezzanine
The Vision Mezzanine for the RB5 ships with an imx577 and ov9282 populated.
Other sensors and components may be added or stacked with additional
mezzanines.
Enable the IMX577 on the vision mezzanine.
An example media-ctl pipeline for the imx577 is:
media-ctl --reset
media-ctl -v -d /dev/media0 -V '"imx577 '22-001a'":0[fmt:SRGGB10/4056x3040 field:none]'
media-ctl -V '"msm_csiphy2":0[fmt:SRGGB10/4056x3040]'
media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]'
media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]'
media-ctl -l '"msm_csiphy2":1->"msm_csid0":0[1]'
media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-8-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Thu, 17 Nov 2022 00:32:31 +0000 (00:32 +0000)]
arm64: dts: qcom: sm8250: camss: Define ports and ports address/size cells
Define the set of possible ports, one for each CSI PHY along with the port
address and size cells @ the SoC dtsi level.
Suggested-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-7-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Thu, 17 Nov 2022 00:32:30 +0000 (00:32 +0000)]
arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Add navigation mezzanine dts
Move the dts data for the rb3 navigation mezzanine into its own dts file.
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-6-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Thu, 17 Nov 2022 00:32:29 +0000 (00:32 +0000)]
arm64: dts: qcom: sdm845-db845c: Use okay not ok, disabled not disable for status
Use preferred "ok" not "okay".
Use preferred status "disabled" instead of "disable".
There's no functional change here so no Fixes has been applied.
Reported-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-5-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Thu, 17 Nov 2022 00:32:28 +0000 (00:32 +0000)]
arm64: dts: qcom: sdm845-db845c: Drop redundant reg = in port
The reg for the port is specified in the dtsi. Remove from the db845c dts.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-4-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Thu, 17 Nov 2022 00:32:27 +0000 (00:32 +0000)]
arm64: dts: qcom: sdm845-db845c: Drop redundant address-cells, size-cells declaration
sdm845.dtsi camss already defines the address-cells and size-cells for
camss, no need to replicate in sdm845-db845c.dts.
Reported-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-3-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Thu, 17 Nov 2022 00:32:26 +0000 (00:32 +0000)]
arm64: dts: qcom: sdm845: Define the number of available ports
The number of available ports is SoC specific so we should define it in the
SoC dtsi. For the case of the sdm845 that is 4 CSI PHYs => four ports.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221117003232.589734-2-bryan.odonoghue@linaro.org
Konrad Dybcio [Wed, 16 Nov 2022 12:36:12 +0000 (13:36 +0100)]
arm64: dts: qcom: sm8350-sagami: Wire up SDHCI2
Adjust regulators, add required pin setup and finally enable SDHCI2
to get the SD Card slot going on Sagami Xperias.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116123612.34302-4-konrad.dybcio@linaro.org
Konrad Dybcio [Wed, 16 Nov 2022 12:36:11 +0000 (13:36 +0100)]
arm64: dts: qcom: sm8350-sagami: Add GPIO line names for TLMM
Sony ever so graciously provides GPIO line names in their downstream
kernel (though sometimes they are not 100% accurate and you can judge
that by simply looking at them and with what drivers they are used).
Add these to the Sagami-common / PDX215 DTSIs to better document the
hardware.
Diff between 215 and common:
< "NC",
< "NC",
> "WLC_I2C_SDA",
> "WLC_I2C_SCL",
< "NC",
> "WLC_INT_N",
> "CAM_MCLK4",
< "NC",
< "NC",
> "TOF_RST_N",
< "NC",
< "NC",
< "NC",
> "QLINK1_REQ",
> "QLINK1_EN",
> "QLINK1_WMSS_RESET_N",
It's pretty logical as 1 III has WLC (WireLess Charging), and an
additional 3D iToF sensor. As for QLINK, no idea.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116123612.34302-3-konrad.dybcio@linaro.org
Konrad Dybcio [Wed, 16 Nov 2022 12:36:10 +0000 (13:36 +0100)]
arm64: dts: qcom: sm8350: Add SDHCI2
Add and configure the SDHCI host responsible for (mostly) SD Card and
its corresponding pins' sleep states.
The setup is *literally* 1:1 with 8450 (bar SDR50/104 may not be
broken).
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116123612.34302-2-konrad.dybcio@linaro.org
Johan Hovold [Wed, 16 Nov 2022 10:20:54 +0000 (11:20 +0100)]
arm64: dts: qcom: clean up 'regulator-allowed-modes' indentation
When recently adding the missing 'regulator-allowed-modes' properties it
appears that the binding example with its four-spaces indentation
(corresponding to a single tab, which is still to little) was copied
verbatim.
Drop the unnecessary first line break after 'regulator-allowed-modes'
properties and indent the single remaining continuation line properly.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116102054.4673-3-johan+linaro@kernel.org
Srinivasa Rao Mandadapu [Wed, 16 Nov 2022 09:33:04 +0000 (15:03 +0530)]
arm64: dts: qcom: sc7280: Remove unused sleep pin control nodes
Remove unused and redundant sleep pin control entries as they are
not referenced anywhere in sc7280 based platform's device tree variants.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Reported-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1668591184-21099-1-git-send-email-quic_srivasam@quicinc.com
Konrad Dybcio [Tue, 15 Nov 2022 13:26:26 +0000 (14:26 +0100)]
arm64: dts: qcom: pmk8350: Specify PBS register for PON
PMK8350 is the first PMIC to require both HLOS and PBS registers for
PON to function properly (at least in theory, sm8350 sees no change).
The support for it on the driver side has been added long ago,
but it has never been wired up. Do so.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115132626.7465-1-konrad.dybcio@linaro.org
Konrad Dybcio [Tue, 15 Nov 2022 13:09:36 +0000 (14:09 +0100)]
arm64: dts: qcom: sm8150: Use defines for power domain indices
Use the defines from qcom-rpmpd.h instead of bare numbers for
readability.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115130936.6830-2-konrad.dybcio@linaro.org
Konrad Dybcio [Tue, 15 Nov 2022 13:09:35 +0000 (14:09 +0100)]
arm64: dts: qcom: sm8450: Use defines for power domain indices
Use the defines from qcom-rpmpd.h instead of bare numbers for
readability.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115130936.6830-1-konrad.dybcio@linaro.org
Konrad Dybcio [Mon, 14 Nov 2022 10:59:13 +0000 (11:59 +0100)]
arm64: dts: qcom: sm6375-pdx225: Enable ADSP & CDSP
Enable the newly added remote processors and assign them a firmware
path.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114105913.37044-4-konrad.dybcio@linaro.org
Konrad Dybcio [Mon, 14 Nov 2022 10:59:12 +0000 (11:59 +0100)]
arm64: dts: qcom: sm6375: Add ADSP&CDSP
Add ADSP & CDSP remote processors.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114105913.37044-3-konrad.dybcio@linaro.org
Konrad Dybcio [Mon, 14 Nov 2022 10:59:11 +0000 (11:59 +0100)]
arm64: dts: qcom: sm6375: Add SMP2P for ADSP&CDSP
Add nodes for ADSP&CDSP SMP2P.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114105913.37044-2-konrad.dybcio@linaro.org
Konrad Dybcio [Mon, 14 Nov 2022 10:50:43 +0000 (11:50 +0100)]
arm64: dts: qcom: sm6375-pdx225: Enable SD card slot
Set SDHCI VMMC/VQMMC to <=2v96 and allow load setting by the SDHCI
driver, as required by this use case.
Configure the SD Card Detect pin, enable the SDHCI2 controller and
assign it the aforementioned regulators.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114105043.36698-4-konrad.dybcio@linaro.org
Konrad Dybcio [Tue, 15 Nov 2022 15:27:27 +0000 (16:27 +0100)]
arm64: dts: qcom: sm6375-pdx225: Configure Samsung touchscreen
Add a pretty bog-standard-for-Xperias-for-the-past-3-years
touchscreen setup.
The OEM that built the Xperia 10 IV for SONY decided to use some
kind of a GPIO regulator that needs to be enabled at all times
for both the touch panel and the display panel to function.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-10-konrad.dybcio@linaro.org
Konrad Dybcio [Tue, 15 Nov 2022 15:27:26 +0000 (16:27 +0100)]
arm64: dts: qcom: sm6375-pdx225: Configure SMD RPM regulators
Configure regulators present on the Xperia 10 IV that are reachable
via SMD RPM.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-9-konrad.dybcio@linaro.org
Konrad Dybcio [Tue, 15 Nov 2022 15:27:25 +0000 (16:27 +0100)]
arm64: dts: qcom: sm6375-pdx225: Add PMIC peripherals
Add and enable PMIC peripherals for PM6125, PMR735a and PMK8350 on
the Xperia 10 IV.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-8-konrad.dybcio@linaro.org
Konrad Dybcio [Tue, 15 Nov 2022 15:27:24 +0000 (16:27 +0100)]
arm64: dts: qcom: sm6375-pdx225: Enable QUPs & GPI DMA
Enable QUPs & GPI DMA on the Xperia 10 IV.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-7-konrad.dybcio@linaro.org
Konrad Dybcio [Mon, 14 Nov 2022 10:50:42 +0000 (11:50 +0100)]
arm64: dts: qcom: sm6375: Add SDHCI2
Configure the second SDHCI bus controller, which usually the
interface used for SD cards.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114105043.36698-3-konrad.dybcio@linaro.org
Konrad Dybcio [Tue, 15 Nov 2022 15:27:23 +0000 (16:27 +0100)]
arm64: dts: qcom: sm6375: Add QUPs and corresponding SPI/I2C hosts
Add necessary nodes to support various QUP configurations. Note that:
- QUP3/4/5 and 11 are straight up missing
- There may be more QUPs physically on the SoC that work perfectly
fine, but Qualcomm decided not to expose them on the downstream kernel
- Many are missing pinctrls, as there are both missing pin funcs in
the TLMM driver and missing configuration settings (though they are
possible to guesstimate quite easily)
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-6-konrad.dybcio@linaro.org
Konrad Dybcio [Tue, 15 Nov 2022 15:27:22 +0000 (16:27 +0100)]
arm64: dts: qcom: sm6375: Add pin configs for some QUP configurations
Add the pin setup for SPI/I2C configurations that are supported
downstream. I can guesstimate the correct settings for other buses,
but:
- I have no hardware to test it on
- Some QUPs are straight up missing pin funcs in TLMM
- Vendors probably didn't really care and used whatever was there in
the reference design and BSP - should any other be used, they can be
configured at a later time
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-5-konrad.dybcio@linaro.org
Konrad Dybcio [Tue, 15 Nov 2022 15:27:21 +0000 (16:27 +0100)]
arm64: dts: qcom: sm6375: Add GPI DMA nodes
Add nodes for GPI DMA hosts on SM6375.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-4-konrad.dybcio@linaro.org
Konrad Dybcio [Tue, 15 Nov 2022 15:27:20 +0000 (16:27 +0100)]
arm64: dts: qcom: pmk8350: Allow specifying arbitrary SID
PMK8350 is shipped on SID6 with some SoCs, for example with SM6375.
Add some preprocessor logic to allow changing the SID in cases like
this.
While I am not in favour of adding #if's into the device tree, this
is the least messy way to handle this. If one isn't specified, it
will default to 0 (as it has been previously).
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-3-konrad.dybcio@linaro.org
Konrad Dybcio [Mon, 14 Nov 2022 09:56:54 +0000 (10:56 +0100)]
arm64: dts: qcom: sm8450-nagara: Add Samsung touchscreen
Add device node and required pinctrl settings (as well as a fixup for
an existing one, whoops!) to support the Samsung Electronics
touchscreen on Nagara devices.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114095654.34561-4-konrad.dybcio@linaro.org
Konrad Dybcio [Mon, 14 Nov 2022 09:56:53 +0000 (10:56 +0100)]
arm64: dts: qcom: sm8450: Add Xperia 5 IV support
Add a device tree for the Xperia 5 IV (pdx224). It's literally the 1 IV
with a smaller body, different panel, one camera lens (not sensor afaict)
swapped out and no 3D iToF sensor, hence the device-specific DT is tiny.
Be sure to follow the vbmeta disablement steps (detailed in pdx223
introduction commit message), otherwise your phone will not boot and
will reject anything and everything with just a non-descriptive
"Your device is corrupted" followed by a sad reboot. This should not
be the case, as vbmeta should be plainly ignored in unlocked state,
but what can we do..
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114095654.34561-3-konrad.dybcio@linaro.org
Konrad Dybcio [Mon, 14 Nov 2022 09:56:52 +0000 (10:56 +0100)]
arm64: dts: qcom: sm8450-nagara: Separate out Nagara platform dtsi
Turns out 1 IV is not the only Nagara device, reflect that in the DTS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114095654.34561-2-konrad.dybcio@linaro.org
Mao Jinlong [Mon, 14 Nov 2022 09:12:51 +0000 (17:12 +0800)]
arm64: dts: qcom: sm8250: Add coresight components
Add coresight components for sm8250. STM/ETM are added.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114091251.13939-1-quic_jinlmao@quicinc.com
Dzmitry Sankouski [Sat, 12 Nov 2022 20:33:00 +0000 (23:33 +0300)]
arm64: dts: qcom: sagit: add initial device tree for sagit
New device support - Xiaomi Mi6 phone
What works:
- storage
- usb
- power regulators
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Konrad Dybcio <konra.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221112203300.536010-3-dsankouski@gmail.com
AngeloGioacchino Del Regno [Fri, 11 Nov 2022 12:01:56 +0000 (13:01 +0100)]
arm64: dts: qcom: Add support for SONY Xperia X/X Compact
This adds support for the Sony Xperia Loire/SmartLoire platform
with a base configuration that is common across all of the
devices that are based on this project.
Also adds a base DT configuration for the Xperia X and Xperia
X Compact (respectively, Suzu and Kugo) which is valid for both
their RoW (single-sim), DSDS (dual-sim) and other regional
variants of these two smartphones, that makes us able to boot
to a UART console.
Please note that, currently, the APC0/1 (cluster 0/1) vregs
are set to a safe voltage in order to ensure boot stability
until a proper solution for CPU DVFS scaling lands.
Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111120156.48040-12-angelogioacchino.delregno@collabora.com
AngeloGioacchino Del Regno [Fri, 11 Nov 2022 12:01:55 +0000 (13:01 +0100)]
arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs
This commit adds device trees for MSM8956 and MSM8976 SoCs.
They are *almost* identical, with minor differences, such as
MSM8956 having two A72 cores less.
However, there is a bug in Sony Loire bootloader that requires presence
of all 8 cores in the cpu{} node, so these will not be deleted.
Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111120156.48040-11-angelogioacchino.delregno@collabora.com
AngeloGioacchino Del Regno [Tue, 1 Nov 2022 16:18:00 +0000 (17:18 +0100)]
arm64: dts: qcom: Add configuration for PMI8950 peripheral
The PMI8950 features integrated peripherals like ADC, GPIO controller,
MPPs and others.
[luca@z3ntu.xyz: remove pm8950, style changes for 2022 standards, add wled]
Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221101161801.1058969-2-luca@z3ntu.xyz
AngeloGioacchino Del Regno [Fri, 11 Nov 2022 12:01:54 +0000 (13:01 +0100)]
arm64: dts: qcom: Add configuration for PM8950 peripheral
The PM8950 features integrated peripherals like ADC, GPIO controller,
MPPs, PON keys and others.
Add them to DT files that will be imported on boards having this PMIC
combo (or one of them, anyways).
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111120156.48040-10-angelogioacchino.delregno@collabora.com
Johan Hovold [Fri, 11 Nov 2022 09:47:29 +0000 (10:47 +0100)]
arm64: dts: qcom: sm8250: fix USB-DP PHY registers
When adding support for the DisplayPort part of the QMP PHY the binding
(and devicetree parser) for the (USB) child node was simply reused and
this has lead to some confusion.
The third DP register region is really the DP_PHY region, not "PCS" as
the binding claims, and lie at offset 0x2a00 (not 0x2c00).
Similarly, there likely are no "RX", "RX2" or "PCS_MISC" regions as
there are for the USB part of the PHY (and in any case the Linux driver
does not use them).
Note that the sixth "PCS_MISC" region is not even in the binding.
Fixes:
5aa0d1becd5b ("arm64: dts: qcom: sm8250: switch usb1 qmp phy to USB3+DP mode")
Cc: stable@vger.kernel.org # 5.13
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111094729.11842-3-johan+linaro@kernel.org
Johan Hovold [Fri, 11 Nov 2022 09:47:28 +0000 (10:47 +0100)]
arm64: dts: qcom: sm6350: fix USB-DP PHY registers
When adding support for the DisplayPort part of the QMP PHY the binding
(and devicetree parser) for the (USB) child node was simply reused and
this has lead to some confusion.
The third DP register region is really the DP_PHY region, not "PCS" as
the binding claims, and lie at offset 0x2a00 (not 0x2c00).
Similarly, there likely are no "RX", "RX2" or "PCS_MISC" regions as
there are for the USB part of the PHY (and in any case the Linux driver
does not use them).
Note that the sixth "PCS_MISC" region is not even in the binding.
Fixes:
23737b9557fe ("arm64: dts: qcom: sm6350: Add USB1 nodes")
Cc: stable@vger.kernel.org # 5.16
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111094729.11842-2-johan+linaro@kernel.org
Johan Hovold [Fri, 11 Nov 2022 09:38:57 +0000 (10:38 +0100)]
arm64: dts: qcom: sc8280xp: drop reference-clock source
The source clock for the reference clock should not be described by the
devicetree binding and instead this relationship should be modelled in
the clock driver.
Update the USB PHY nodes to match the fixed binding.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111093857.11360-4-johan+linaro@kernel.org
Bjorn Andersson [Fri, 11 Nov 2022 03:25:15 +0000 (19:25 -0800)]
arm64: dts: qcom: sc8280xp: Add bwmon instances
Add the two bwmon instances and define votes for CPU -> LLCC and LLCC ->
DDR, with bandwidth values based on the downstream DeviceTree.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111032515.3460-11-quic_bjorande@quicinc.com
Bjorn Andersson [Fri, 11 Nov 2022 03:25:13 +0000 (19:25 -0800)]
arm64: dts: qcom: sc8280xp: Set up L3 scaling
Add the L3 interconnect path to all CPUs and define the bandwidth
requirements for all opp entries across sc8280xp and sa8540p.
The values are based on the tables reported by the hardware, distributed
such that each value is the largest value, lower than the cluster
frequency.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111032515.3460-9-quic_bjorande@quicinc.com
Bjorn Andersson [Fri, 11 Nov 2022 03:25:12 +0000 (19:25 -0800)]
arm64: dts: qcom: sc8280xp: Add epss_l3 node
Add a device node for the EPSS L3 frequency domain.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111032515.3460-8-quic_bjorande@quicinc.com
Bjorn Andersson [Fri, 11 Nov 2022 03:25:11 +0000 (19:25 -0800)]
arm64: dts: qcom: Align with generic osm-l3/epss-l3
Update all references to OSM or EPSS L3 compatibles, to include the
generic compatible, as defined by the updated binding.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111032515.3460-7-quic_bjorande@quicinc.com
Johan Hovold [Fri, 4 Nov 2022 09:20:45 +0000 (10:20 +0100)]
arm64: dts: qcom: sc8280xp: update UFS PHY nodes
Update the UFS PHY nodes to match the new binding.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221104092045.17410-3-johan+linaro@kernel.org
Christian Marangi [Thu, 3 Nov 2022 21:21:25 +0000 (22:21 +0100)]
arm64: dts: qcom: ipq6018: improve pcie phy pcs reg table
This is not a fix on its own but more a cleanup. Phy qmp pcie driver
currently have a workaround to handle pcs_misc not declared and add
0x400 offset to the pcs reg if pcs_misc is not declared.
Correctly declare pcs_misc reg and reduce PCS size to the common value
of 0x1f0 as done for every other qmp based pcie phy device.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221103212125.17156-2-ansuelsmth@gmail.com
NÃcolas F. R. A. Prado [Wed, 2 Nov 2022 18:20:02 +0000 (14:20 -0400)]
arm64: dts: qcom: sc7180-trogdor: Remove VBAT supply from rt5682s
These devicetrees override a rt5682 node to use the rt5682s compatible,
however, unlike rt5682, rt5682s doesn't have a VBAT supply. Remove the
inexistent supply in the rt5682s nodes.
Signed-off-by: NÃcolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102182002.255282-9-nfraprado@collabora.com
NÃcolas F. R. A. Prado [Wed, 2 Nov 2022 18:20:01 +0000 (14:20 -0400)]
arm64: dts: qcom: sc7180-trogdor: Add missing supplies for rt5682
The DBVDD and LDO1-IN supplies for rt5682 are required but are missing.
They are supplied by the same power rail as AVDD. Add them.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: NÃcolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102182002.255282-8-nfraprado@collabora.com
Bjorn Andersson [Mon, 5 Dec 2022 17:43:09 +0000 (09:43 -0800)]
arm64: dts: qcom: sa8295p-adp: Add RTC node
The first PM8540 PMIC has an available RTC block, describe this in the
SA8295P ADP. Mark it as wakeup-source to allow waking the system from
sleep.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221205174309.16733-1-quic_bjorande@quicinc.com
Johan Hovold [Fri, 4 Nov 2022 09:20:44 +0000 (10:20 +0100)]
arm64: dts: qcom: sc8280xp: fix UFS reference clocks
There are three UFS reference clocks on SC8280XP which are used as
follows:
- The GCC_UFS_REF_CLKREF_CLK clock is fed to any UFS device connected
to either controller.
- The GCC_UFS_1_CARD_CLKREF_CLK and GCC_UFS_CARD_CLKREF_CLK clocks
provide reference clocks to the two PHYs.
Note that this depends on first updating the clock driver to reflect
that all three clocks are sourced from CXO. Specifically, the UFS
controller driver expects the device reference clock to have a valid
frequency:
ufshcd-qcom 1d84000.ufs: invalid ref_clk setting = 0
Fixes:
152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Fixes:
8d6b458ce6e9 ("arm64: dts: qcom: sc8280xp: fix ufs_card_phy ref clock")
Fixes:
f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref clock for ufs_mem_phy")
Link: https://lore.kernel.org/lkml/Y2OEjNAPXg5BfOxH@hovoldconsulting.com/
Cc: stable@vger.kernel.org # 5.20
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221104092045.17410-2-johan+linaro@kernel.org
Johan Hovold [Thu, 24 Nov 2022 14:25:01 +0000 (15:25 +0100)]
arm64: dts: qcom: sc8280xp: fix PCIe DMA coherency
The devices on the SC8280XP PCIe buses are cache coherent and must be
marked as such to avoid data corruption.
A coherent device can, for example, end up snooping stale data from the
caches instead of using data written by the CPU through the
non-cacheable mapping which is used for consistent DMA buffers for
non-coherent devices.
Note that this is much more likely to happen since commit
c44094eee32f
("arm64: dma: Drop cache invalidation from arch_dma_prep_coherent()")
that was added in 6.1 and which removed the cache invalidation when
setting up the non-cacheable mapping.
Marking the PCIe devices as coherent specifically fixes the intermittent
NVMe probe failures observed on the Thinkpad X13s, which was due to
corruption of the submission and completion queues. This was typically
observed as corruption of the admin submission queue (with well-formed
completion):
could not locate request for tag 0x0
nvme nvme0: invalid id 0 completed on queue 0
or corruption of the admin or I/O completion queues (malformed
completion):
could not locate request for tag 0x45f
nvme nvme0: invalid id 25695 completed on queue 25965
presumably as these queues are small enough to not be allocated using
CMA which in turn make them more likely to be cached (e.g. due to
accesses to nearby pages through the cacheable linear map). Increasing
the buffer sizes to two pages to force CMA allocation also appears to
make the problem go away.
Fixes:
813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221124142501.29314-1-johan+linaro@kernel.org
Bjorn Andersson [Fri, 2 Dec 2022 17:09:58 +0000 (11:09 -0600)]
Merge branch 'arm64-fixes-for-6.1' into HEAD
Mergeback arm64-fixes-for-6.1 to avoid merge conflicts.
Konrad Dybcio [Mon, 14 Nov 2022 14:00:11 +0000 (15:00 +0100)]
arm64: dts: qcom: sdm845-polaris: Don't duplicate DMA assignment
The DMA properties in this DT are identical to the ones already
defined in sdm845.dtsi. Remove them.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114140011.43442-1-konrad.dybcio@linaro.org
Konrad Dybcio [Mon, 14 Nov 2022 14:36:42 +0000 (15:36 +0100)]
arm64: dts: qcom: sm8350-sagami: Wire up USB regulators and fix USB3
Wire up necessary supplies to USB PHYs to enable USB3 on Sagami and
remove all the limit-to-USB2 properties.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114143642.44839-2-konrad.dybcio@linaro.org
Konrad Dybcio [Mon, 14 Nov 2022 14:36:41 +0000 (15:36 +0100)]
arm64: dts: qcom: sm8350-sagami: Add most RPMh regulators
Configure most RPMh-controlled regulators on SoMC Sagami. The missing
ones (on pm8350b and pm8008[ij]) will be configured when driver support
is added. Thankfully, it looks like PDX215 and PDX214 don't have any
differences when it comes to PM8350/PM8350C/PMR735a.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114143642.44839-1-konrad.dybcio@linaro.org
Douglas Anderson [Tue, 15 Nov 2022 00:28:28 +0000 (16:28 -0800)]
arm64: dts: qcom: sc7280: Make herobrine-audio-rt5682 mic dtsi's match more
The 1-mic and 3-mic dtsi still had two minor cosmetic differences
after commit '
3d11e7e120ee ("arm64: dts: qcom: sc7280: sort out the
"Status" to last property with
sc7280-herobrine-audio-rt5682.dtsi")'. Let's fix them so the two files
diff better. This is expected to have no effect though it will
slightly change the generated dtb by removing an unnecessary 'status =
"okay"' from the sound node.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221114162807.1.I0900b97128f9bb03e5f96fcb3068c227a33f143a@changeid
Krzysztof Kozlowski [Tue, 15 Nov 2022 10:50:46 +0000 (11:50 +0100)]
arm64: dts: qcom: trim addresses to 8 digits
Hex numbers in addresses and sizes should be rather eight digits, not
nine. Drop leading zeros. No functional change (same DTB).
Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115105046.95254-1-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Tue, 15 Nov 2022 12:53:10 +0000 (13:53 +0100)]
arm64: dts: msm8998: unify PCIe clock order withMSM8996
PCIe on MSM8996 and MSM8998 use the same clocks, so use one order to
make the binding simpler.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115125310.184012-4-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Tue, 15 Nov 2022 12:53:09 +0000 (13:53 +0100)]
arm64: dts: msm8998: add MSM8998 specific compatible
Add new compatible for MSM8998 (compatible with MSM8996) to allow
further customizing if needed and to accurately describe the hardware.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115125310.184012-3-krzysztof.kozlowski@linaro.org
Johan Hovold [Thu, 10 Nov 2022 10:35:58 +0000 (11:35 +0100)]
arm64: dts: qcom: sc8280xp-x13s: enable WiFi controller
Enable the Qualcomm QCNFA765 Wireless Network Adapter connected to
PCIe4.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110103558.12690-10-johan+linaro@kernel.org
Johan Hovold [Thu, 10 Nov 2022 10:35:57 +0000 (11:35 +0100)]
arm64: dts: qcom: sc8280xp-x13s: enable modem
Enable the modem connected to the PCIe3a M.2 connector.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110103558.12690-9-johan+linaro@kernel.org
Johan Hovold [Thu, 10 Nov 2022 10:35:56 +0000 (11:35 +0100)]
arm64: dts: qcom: sc8280xp-x13s: enable NVMe SSD
Enable the NVMe SSD connected to PCIe2.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110103558.12690-8-johan+linaro@kernel.org
Johan Hovold [Thu, 10 Nov 2022 10:35:55 +0000 (11:35 +0100)]
arm64: dts: qcom: sc8280xp-crd: enable WiFi controller
Enable the Qualcomm QCNFA765 Wireless Network Adapter connected to
PCIe4.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110103558.12690-7-johan+linaro@kernel.org
Johan Hovold [Thu, 10 Nov 2022 10:35:54 +0000 (11:35 +0100)]
arm64: dts: qcom: sc8280xp-crd: enable SDX55 modem
Enable the SDX55 modem connected to PCIe3.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110103558.12690-6-johan+linaro@kernel.org
Johan Hovold [Thu, 10 Nov 2022 10:35:53 +0000 (11:35 +0100)]
arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD
Enable the NVMe SSD connected to PCIe2.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110103558.12690-5-johan+linaro@kernel.org
Johan Hovold [Thu, 10 Nov 2022 10:35:52 +0000 (11:35 +0100)]
arm64: dts: qcom: sc8280xp-crd: rename backlight and misc regulators
Rename the backlight and misc regulators according to the net names.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110103558.12690-4-johan+linaro@kernel.org
Johan Hovold [Thu, 10 Nov 2022 10:35:51 +0000 (11:35 +0100)]
arm64: dts: qcom: sa8295p-adp: enable PCIe
The SA8295P-ADP has up to four PCIe interfaces implemented by three or
four controllers: PCIe2A, PCIe3A/PCIe3B and PCIe4.
PCIe2 is used in x4 mode, while PCIe3 can be used in either x2 or x4
mode. Enable both PCIe3A and PCI3B in x2 mode for now.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110103558.12690-3-johan+linaro@kernel.org
Johan Hovold [Thu, 10 Nov 2022 10:35:50 +0000 (11:35 +0100)]
arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes
The SC8280XP platform has seven PCIe controllers:
PCIe0 USB4
PCIe1 USB4
PCIe2A 4-lane
PCIe2B 2-lane
PCIe3A 4-lane
PCIe3B 2-lane
PCIe4 1-lane
while SA8540P only has five (PCIe2-4).
Add devicetree nodes for the PCIe2-4 controllers and their PHYs.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110103558.12690-2-johan+linaro@kernel.org
Richard Acayan [Fri, 11 Nov 2022 00:18:19 +0000 (19:18 -0500)]
arm64: dts: qcom: add sdm670 and pixel 3a device trees
The Qualcomm Snapdragon 670 has been out for a while. Add a device tree
for it and the Google Pixel 3a as the first device.
The Pixel 3a has the same bootloader issue as the Pixel 3 and will not work
on Android 10 bootloaders or later until it gets fixed for the Pixel 3.
SoC Initial Features:
- power management
- clocks
- pinctrl
- eMMC
- USB 2.0
- GENI I2C
- IOMMU
- RPMh
- interrupts
Device-Specific Initial Features:
- side buttons (keys)
- regulators
- touchscreen
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111001818.124901-5-mailingradian@gmail.com
Sibi Sankar [Thu, 10 Nov 2022 07:08:13 +0000 (12:38 +0530)]
arm64: dts: qcom: sc7280: Add Google Herobrine WIFI SKU dts fragment
The Google Herobrine WIFI SKU can save 256M by not having modem/mba/rmtfs
memory regions defined. Add the dts fragment and mark all the board files
appropriately.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110070813.1777-2-quic_sibis@quicinc.com
Sibi Sankar [Thu, 10 Nov 2022 07:08:12 +0000 (12:38 +0530)]
arm64: dts: qcom: sc7280: Mark all Qualcomm reference boards as LTE
When the modem node was re-located to a separate LTE source file
"sc7280-herobrine-lte-sku.dtsi", some of the previous LTE users
weren't marked appropriately. Fix this by marking all Qualcomm
reference devices as LTE.
Suggested-by: Douglas Anderson <dianders@chromium.org>
Fixes:
d42fae738f3a ("arm64: dts: qcom: Add LTE SKUs for sc7280-villager family")
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110070813.1777-1-quic_sibis@quicinc.com
Luca Weiss [Thu, 10 Nov 2022 15:15:06 +0000 (16:15 +0100)]
arm64: dts: qcom: sm7225-fairphone-fp4: Enable SD card
Fairphone 4 uses sdhc_2 for the SD card, configure the pins for it and
enable it.
The regulators which are exclusively used for SDHCI have their maximum
voltage decreased to what downstream sets on the consumer side, like on
many other platforms and allowed to set the load.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110151507.53650-1-luca.weiss@fairphone.com
Krzysztof Kozlowski [Thu, 10 Nov 2022 15:27:41 +0000 (16:27 +0100)]
arm64: dts: qcom: sm8450: drop incorrect spi-max-frequency
spi-max-frequency is a property of SPI device, not the controller:
qcom/sm8450-hdk.dtb: geniqup@8c0000: spi@880000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221110152741.542024-1-krzysztof.kozlowski@linaro.org
Bjorn Andersson [Sat, 30 Jul 2022 19:36:17 +0000 (12:36 -0700)]
arm64: dts: qcom: sc8280xp-x13s: Add LID switch
Add gpio-keys for exposing the LID switch state.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220730193617.1688563-1-bjorn.andersson@linaro.org
Krzysztof Kozlowski [Tue, 8 Nov 2022 14:23:57 +0000 (15:23 +0100)]
arm64: dts: qcom: ipq8074: align TLMM pin configuration with DT schema
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
Srinivasa Rao Mandadapu [Tue, 8 Nov 2022 14:46:02 +0000 (20:16 +0530)]
arm64: dts: qcom: sc7280: Remove redundant soundwire property
Remove redundant and undocumented property qcom,port-offset in
soundwire controller nodes.
This patch is required to avoid dtbs_check errors with
qcom,soundwire.yaml
Fixes:
12ef689f09ab ("arm64: dts: qcom: sc7280: Add nodes for soundwire and va tx rx digital macro codecs")
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Ratna Deepthi Kudaravalli <quic_rkudarav@quicinc.com>
Signed-off-by: Ratna Deepthi Kudaravalli <quic_rkudarav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1667918763-32445-4-git-send-email-quic_srivasam@quicinc.com
Srinivasa Rao Mandadapu [Tue, 8 Nov 2022 14:46:01 +0000 (20:16 +0530)]
arm64: dts: qcom: sm8250: Remove redundant soundwire property
Remove redundant and undocumented property qcom,port-offset in
soundwire controller nodes.
This patch is required to avoid dtbs_check errors with
qcom,soundwire.yaml
Fixes:
24f52ef0c4bf ("arm64: dts: qcom: sm8250: Add nodes for tx and rx macros with soundwire masters")
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Ratna Deepthi Kudaravalli <quic_rkudarav@quicinc.com>
Signed-off-by: Ratna Deepthi Kudaravalli <quic_rkudarav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1667918763-32445-3-git-send-email-quic_srivasam@quicinc.com
Srinivasa Rao Mandadapu [Tue, 8 Nov 2022 14:46:00 +0000 (20:16 +0530)]
arm64: dts: qcom: Update soundwire secondary node names
Update soundwire secondary nodes of WSA speaker to match with
dt-bindings pattern properties regular expression.
This modification is required to avoid dtbs-check errors
occurred with qcom,soundwire.yaml.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Ratna Deepthi Kudaravalli <quic_rkudarav@quicinc.com>
Signed-off-by: Ratna Deepthi Kudaravalli <quic_rkudarav@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1667918763-32445-2-git-send-email-quic_srivasam@quicinc.com
Alex Elder [Tue, 8 Nov 2022 20:16:25 +0000 (14:16 -0600)]
arm64: dts: qcom: sc7280-idp: don't modify &ipa twice
In "sc7280-idp.dts", the IPA node is modified after being defined.
However that file includes "sc7280-idp.dtsi", which also modifies
the IPA node (in the same way). This only needs to be done in
"sc7280-idp.dtsi".
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221108201625.1220919-1-elder@linaro.org
Maulik Shah [Tue, 18 Oct 2022 15:28:34 +0000 (17:28 +0200)]
arm64: dts: qcom: Add power-domains property for apps_rsc
Add power-domains property which allows apps_rsc device to attach
to cluster power domain on sm8150, sm8250, sm8350 and sm8450.
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221018152837.619426-4-ulf.hansson@linaro.org
Dmitry Baryshkov [Wed, 2 Nov 2022 18:44:10 +0000 (21:44 +0300)]
arm64: dts: qcom: msm8996: change order of SMMU clocks on this platform
Change order of SMMU clocks to match the schema.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102184420.534094-2-dmitry.baryshkov@linaro.org
Job Noorman [Mon, 7 Nov 2022 10:56:04 +0000 (11:56 +0100)]
arm64: dts: qcom: sdm632: fairphone-fp3: add touchscreen
Add Himax hx83112b touchscreen to the FP3 DT.
Signed-off-by: Job Noorman <job@noorman.info>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107105604.26541-4-job@noorman.info
projects / platform / kernel / linux-starfive.git / log