Tatsuyuki Ishi [Wed, 6 Sep 2023 12:51:44 +0000 (21:51 +0900)]
radv: Fix dumping vertex descriptors with RADV_DEBUG=hang.
Adding 3 words should be done before the uint32_t ** cast. This is in
line with other places which uses pointer arithmetic on trace_id_ptr.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25081>
Vlad Schiller [Mon, 7 Aug 2023 14:06:15 +0000 (15:06 +0100)]
pvr: Add VK_KHR_driver_properties
This commit will implement the VK_KHR_driver_properties extension.
At the moment, the extension is disabled, because the current conformance
test version does not include the Imagination driver ID. The extension
can be enabled after conformance test version 1.3.6.0.
Co-Authored-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24927>
Lionel Landwerlin [Thu, 31 Aug 2023 06:23:38 +0000 (09:23 +0300)]
pps-producer: add ability to select device with DRI_PRIME
When running with multiple Intel cards in a system, having the ability
to select the device recording performance data is useful.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25051>
Tatsuyuki Ishi [Tue, 5 Sep 2023 14:55:48 +0000 (23:55 +0900)]
radv: Fix IB size for RADV_DEBUG=hang.
cs->base.cdw here is the size of the last CS in the chain, but we are
passing in the first CS in the chain to begin decoding. Hence,
cs->ib_buffers[0].cdw is the correct size here.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25061>
Tapani Pälli [Sun, 3 Sep 2023 17:09:31 +0000 (20:09 +0300)]
mesa: disable snorm readpix clamping with EXT_render_snorm
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25054>
Samuel Pitoiset [Tue, 5 Sep 2023 08:03:13 +0000 (10:03 +0200)]
radv: fix interactions with primitives generated queries and pipeline stats
SAMPLE_STREAMOUTSTATS requires PIPELINESTAT_START to be enabled,
otherwise the hw doesn't count anything.
This fixes
dEQP-VK.transform_feedback.primitives_generated_query.concurrent.pipeline_statistics_2.*
on GFX8. GFX6-9 are probably also affected by this bug, but with NGG
these queries are slightly different and don't use legacy streamout.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25049>
Lionel Landwerlin [Mon, 22 May 2023 06:11:13 +0000 (23:11 -0700)]
anv: Copy/Clear MSAA images over companion RCS while we are on compute
When we have MSAA copy/clear operation on the compute queue, use the
companion RCS command buffer to carry out copy/clear operations.
v2: (Sagar)
- Flush cache according to command buffer
- Invalidate AUX when we create new companion RCS command buffer if
platform support AUX TT.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Sagar Ghuge [Thu, 18 May 2023 01:19:25 +0000 (18:19 -0700)]
anv: Extract batch print code to anv_print_batch helper
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Sagar Ghuge [Thu, 8 Jun 2023 04:38:47 +0000 (21:38 -0700)]
anv: Skip layout transition on the compute queue
v2: (Nanley)
- Make sure we skip layout transition during queue ownership transfer
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Sagar Ghuge [Thu, 18 May 2023 22:04:07 +0000 (15:04 -0700)]
anv: Add secondary companion RCS cmd buffer to primary
Add secondary buffer's companion RCS command buffer to primary buffer's
companion RCS command buffer for execution if secondary RCS is valid.
v2: (Lionel)
- Fix the primary companion RCS check
- Set batch error
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Sagar Ghuge [Mon, 5 Jun 2023 16:59:54 +0000 (09:59 -0700)]
anv: Execute an empty batch to sync main and companion RCS batch
We need to synchronize main (CCS/BCS) and companion rcs batch, so let's
create an empty batch and make both the batches (CCS/BCS) and companion
RCS batch wait on empty sync batch and signal the fence.
Reason to execute the empty batch is we need to make sure the companion
RCS batch finish as soon as the CCS/BCS batch finish. Preemption could
prevent the companion RCS batch execution and we might end up destroying
the CCS/BCS batch before companion RCS finishes.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Sagar Ghuge [Tue, 16 May 2023 05:45:53 +0000 (22:45 -0700)]
anv: Setup companion RCS command buffer submission
Add all the wait fences from the main (CCS/BCS) command buffer to the
companion RCS command buffer so that the companion RCS batch starts at
the same time as the main (CCS/BCS) batch.
v2:
- Drop unncessary flush (Jose)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Sagar Ghuge [Fri, 23 Jun 2023 23:44:02 +0000 (16:44 -0700)]
anv: Execute RCS init batch on companion RCS context/engine
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Sagar Ghuge [Fri, 28 Jul 2023 16:44:38 +0000 (09:44 -0700)]
anv: Move compute specfic bits under compute queue init
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Sagar Ghuge [Sun, 11 Jun 2023 05:13:08 +0000 (22:13 -0700)]
anv: Create companion RCS engine
We need to create companion RCS engine when there is CCS/BCS engine
creation requested.
v2:
- Factor out anv_xe_create_engine code in create_engine (Jose)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Lionel Landwerlin [Fri, 9 Jun 2023 21:22:58 +0000 (14:22 -0700)]
anv: create individual logical engines on i915 when possible
This enables us to create more logical engines than HW engines are
available. This also brings the uAPI usage closer to what is happening
on Xe.
Rework: (Sagar)
- Correct exec_flag at the time of submission
- Handle device status check
- Set queue parameters
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Sagar Ghuge [Thu, 25 May 2023 18:35:39 +0000 (11:35 -0700)]
intel: Pass virtual memory address space ID while creating context
In future patches, we will be creating a separate companion RCS engine
and each engine is created with it's own address space, and we really
don't want. CCS and RCS engine writes should be visible to each other in
order to get the wait/signal mechanism working.
v2:
- Move drm_i915_gem_context_create_ext_setparam out of if block (Lionel)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Sagar Ghuge [Tue, 23 May 2023 20:50:46 +0000 (13:50 -0700)]
intel: Add helper to create/destroy i915 VM
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Sagar Ghuge [Fri, 14 Jul 2023 19:10:40 +0000 (12:10 -0700)]
anv: Handle companion RCS in end/destory/reset code path
If we have valid companion RCS command buffer, we should
end/destroy/reset in the same fashion as of main command buffer.
v2:
- Add lock around anv_cmd_buffer_destroy (Sagar)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Sagar Ghuge [Fri, 19 May 2023 06:15:38 +0000 (23:15 -0700)]
anv: Split out End/Destroy/Reset cmd buffer code into helper
Since we are going to have companion RCS command buffer, we need to
end/destroy/reset companion RCS command buffer similar to main (CCS/BCS)
command buffer.
It's better to split out common code into helper function so that we can
use it later in this series.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Sagar Ghuge [Thu, 11 May 2023 18:41:39 +0000 (11:41 -0700)]
anv: Add helper to create companion RCS command buffer
This helper takes the main command buffer as input and then create a
companion RCS command buffer.
v2:
- Rename anv_get_render_queue_index helper to
anv_get_first_render_queue_index (Jose)
- Rename RCS command buffer to companion RCS command buffer (Lionel)
- Add early return in anv_get_first_render_queue_index (Lionel)
- Add lock around the function (Jose)
- Move companion rcs command pool creation in device create (Sagar)
- Reset companion RCS cmd buffer (Sagar)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23661>
Iago Toral Quiroga [Tue, 5 Sep 2023 10:41:21 +0000 (12:41 +0200)]
v3dv: handle pPlaneLayouts in VkImageDrmFormatModifierExplicitCreateInfoEXT
We have been ignoring these completely until now. V3D isn't very flexible
regarding image layouts anyway, so for the most part we require that
whatever the user puts here matches exactly what the driver would compute
while setting up the slices. The only exceptions are plane offsets which
and array strides.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9742
Tested-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25074>
Iago Toral Quiroga [Tue, 5 Sep 2023 10:39:42 +0000 (12:39 +0200)]
v3dv: be more precise in vkGetImageSubresourceLayout
Only return non-zero values for arrayPitch and depthPitch if
they make sense for the image type.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25074>
Piotr Kocia [Mon, 28 Aug 2023 20:39:59 +0000 (22:39 +0200)]
glsl: ir_function_param_visitor::visit_enter always true condition
The condition
!param->type->is_vector() || !param->type->is_scalar()
alawys evaluates to true:
* type is not scalar or vector -> true
* type is vector, i.e. num_components > 1 -> num_components == 1 is
false and !is_scalar() == true
* type is scalar, i.e. num_components == 1 -> num_components > 1 is
false and !is_vector() == true
There is no comment explaining why such code has been written, therefore
this seems to be a mistake.
To maintain consistency with the surrounding code,
glsl_type_is_scalar_or_vector has been used instead of
replacing || with &&.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24914>
Timothy Arceri [Tue, 5 Sep 2023 01:13:35 +0000 (11:13 +1000)]
glsl_to_nir: add more unhandled function types
These are unhandled but were working ok because a mistake fixed
in the following patch caused all functions to be skipped.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24914>
Timothy Arceri [Fri, 1 Sep 2023 00:45:50 +0000 (10:45 +1000)]
glsl: fix out params in glsl to nir
We must use a temp var for out params and later copy the out values
to the correct parameter otherwise we can end up overwriting
global variables prematurely.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24914>
Mike Blumenkrantz [Wed, 23 Aug 2023 15:05:42 +0000 (11:05 -0400)]
aux/tc: handle stride mismatch during rp-optimized subdata
to avoid splitting renderpasses, this subdata optimization handles the usual
driver dance of staging buffer -> gpu copy
if the pbo stride doesn't match the image format's stride, however, then
a direct copy will yield broken pixels and the image will misrender. to avoid this,
detect stride mismatch and translate the single subdata call into a sequence
of non-overlapping subdata calls that the driver can magically figure out
while continuing to not split renderpasses
fixes #9589
cc: mesa-stable
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24849>
Eric Engestrom [Wed, 6 Sep 2023 21:40:45 +0000 (22:40 +0100)]
docs: add one more 23.1.x release
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25090>
Eric Engestrom [Wed, 6 Sep 2023 21:40:13 +0000 (22:40 +0100)]
docs: update calendar for 23.1.7
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25090>
Eric Engestrom [Wed, 6 Sep 2023 21:40:01 +0000 (22:40 +0100)]
docs: add sha256sum for 23.1.7
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25090>
Eric Engestrom [Wed, 6 Sep 2023 21:28:26 +0000 (22:28 +0100)]
docs: add release notes for 23.1.7
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25090>
Dave Airlie [Wed, 6 Sep 2023 05:49:08 +0000 (15:49 +1000)]
rusticl: don't store ptrs to nir_variables across opt passes.
If we use NIR_DEBUG=serialize all these ptrs will be left hanging,
just store the var locations and look them up after opt passes.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25072>
Sil Vilerino [Tue, 29 Aug 2023 01:01:21 +0000 (21:01 -0400)]
d3d12: Extend video screen AV1 encode tile support checking
Add fallback case to take into account driver reported tile restrictions if
default hardcoded tile configurations are not supported by driver
Reviewed-by: Tanner Van De Walle <tvandewalle@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25070>
Sil Vilerino [Tue, 5 Sep 2023 19:05:27 +0000 (15:05 -0400)]
util/vl_vlc: Use UINT64_MAX instead of ~0UL with MSVC compiler
vl_vlc_removebits fails on MSVC where ~0UL is taken as 32 bits.
Use the UINT64_MAX constant instead in that case.
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25059>
Lionel Landwerlin [Mon, 14 Aug 2023 10:51:00 +0000 (13:51 +0300)]
docs: update Anv documentation about dynamic state emission
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Fri, 11 Aug 2023 10:38:24 +0000 (13:38 +0300)]
anv: split BLEND_STATE packing from BLEND_STATE_POINTERS emit
This way when blorp changes the 3DSTATE_BLEND_STATE_POINTERS, we can
just reemit the prior Vulkan state without repacking any of the values
in the BLEND_STATE structure.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Wed, 2 Aug 2023 08:44:52 +0000 (11:44 +0300)]
anv: remove unused state emission
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Wed, 2 Aug 2023 08:36:39 +0000 (11:36 +0300)]
anv: add new low level emission & dirty state tracking
A single Vulkan state can map to multiple fields in different GPU
instructions. This change introduces the bottom half of a simplified
emission mechanism where we do the following :
Vulkan runtime state
|
V
Intermediate driver state
|
V
Instruction programming
This way we can detect that the intermediate state didn't change and
avoid HW instruction emission.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Thu, 3 Aug 2023 13:10:35 +0000 (16:10 +0300)]
vulkan/runtime: add helper to name dirty states
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Tue, 1 Aug 2023 09:20:19 +0000 (12:20 +0300)]
anv: split pipeline programming into instructions
The goal of this change it to move away from a single batch buffer
containing all kind of pipeline instructions to a list of instructions
we can emit separately.
We will later implement pipeline diffing and finer state tracking that
will allow fewer instructions to be emitted.
This changes the following things :
* instead of having a batch & partially packed instructions, move
everything into the batch
* add a set of pointer in the batch that allows us to point to each
instruction (almost... we group some like URB instructions,
etc...).
At pipeline emission time, we just go through all of those pointers
and emit the instruction into the batch. No additional packing is
involved.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Fri, 4 Aug 2023 10:15:35 +0000 (13:15 +0300)]
anv: add a flag tracking occlusion query count change
We'll use this later to know when to reemit
3DSTATE_STREAMOUT::ForceRendering
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Mon, 31 Jul 2023 15:56:26 +0000 (18:56 +0300)]
anv: split 3DSTATE_VFG emission
Leave the static part in genX_pipeline.c and only repack the dynamic
part in genX_gfx_state.c
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Mon, 31 Jul 2023 12:23:27 +0000 (15:23 +0300)]
anv: split 3DSTATE_TE packing between static & dynamic parts
We can reduce the amount of packing we do by only packing the dynamic
part.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Mon, 31 Jul 2023 12:12:32 +0000 (15:12 +0300)]
anv: categorize partial/final pipeline instruction
The old gfx8 field doesn't apply anymore.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Sun, 30 Jul 2023 07:46:50 +0000 (10:46 +0300)]
anv: rename files to represent their usage
gfx8_cmd_buffer.c does not apply to gfx8 anymore for instance, it can
also be included in all builds.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Sun, 30 Jul 2023 07:34:43 +0000 (10:34 +0300)]
anv: move all dynamic state emission to cmd_buffer_flush_dynamic_state
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Fri, 4 Aug 2023 08:16:14 +0000 (11:16 +0300)]
intel/decoder: implement accumulated prints
Useful when you want to compare 2 batches with different ordering in
instruction emission. Also when the driver tries to avoid re-emitting
state.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Tue, 6 Jun 2023 21:37:03 +0000 (00:37 +0300)]
intel/anv: batch stats util
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Wed, 6 Sep 2023 07:45:26 +0000 (10:45 +0300)]
anv: change anv_batch_emit_merge to also do packing
Instead of having that function do only merging of 2 sets of dwords,
it can also do the packing of the new dynamic values. This saves us a
bunch of local structures to declare and calling the packing functions
ourselves.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Mon, 14 Aug 2023 10:39:35 +0000 (13:39 +0300)]
anv: remove ReorderMode from pipeline 3DSTATE_GS emission
This bit is set in the dynamic state emission. This is currently not
breaking anything because LEADING=0.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
71ebd9b9d7 ("anv,hasvk: respect provoking vertex setting on geometry shaders")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>
Lionel Landwerlin [Wed, 16 Aug 2023 14:57:33 +0000 (17:57 +0300)]
blorp: remove unused variable
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24719>
Lionel Landwerlin [Wed, 16 Aug 2023 08:53:24 +0000 (11:53 +0300)]
hasvk: add state cache invalidation back before fast clears
Prior to
87149cc545, blorp added a state cache invalidation prior to
fast clears. This got dropped on Hasvk.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
87149cc545 ("blorp: update and move fast clear PIPE_CONTROLs to drivers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24719>
Faith Ekstrand [Wed, 6 Sep 2023 15:43:35 +0000 (10:43 -0500)]
nouveau/mme: SPDX everything
For all the Fermi stuff, I've credited Mary because she wrote it before
joining Collabora. For everything else, credit Collabora.
Acked-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25085>
Faith Ekstrand [Wed, 6 Sep 2023 15:38:28 +0000 (10:38 -0500)]
nouveau/nil: SPDX everything
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25085>
Faith Ekstrand [Wed, 6 Sep 2023 15:35:28 +0000 (10:35 -0500)]
nvk: SPDX everything
I chose to use "Collabora Ldt. and Red Hat Inc." as the author line. I
could have gone through and manually checked every single file but I
think it's better to spread the blame around. No one should actually
trust those lines anyway. That's what git blame is for.
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25085>
Faith Ekstrand [Wed, 6 Sep 2023 15:35:02 +0000 (10:35 -0500)]
nvk: Add include guards to nvk_bo_sync.h
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25085>
Faith Ekstrand [Wed, 6 Sep 2023 14:44:46 +0000 (09:44 -0500)]
nvk: Clean up includes
Drop a bunch of totally unnecessary stuff from xf86drm.h from
nvk_private.h and limit it to vk_util and vk_log. In particular, we
drop nvk_entrypoints.h which is auto-generated, allowing NVK headers to
be included in other parts of the tree.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25085>
Gert Wollny [Mon, 14 Aug 2023 15:47:24 +0000 (17:47 +0200)]
r600/sfn: Simplify dependency chain for index loads on EG
Address loads that just load the index register don't need to chain
up like loads if the address register that are used for indirect
register loads. With the latter it is important that the load and the
address register use are in the same clause. For index register loads
this is scheduled accordingly.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24638>
Gert Wollny [Thu, 10 Aug 2023 14:02:48 +0000 (16:02 +0200)]
r600/sfn: factor out resource as extra class
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24638>
Gert Wollny [Thu, 10 Aug 2023 12:42:10 +0000 (14:42 +0200)]
r600/sfn: drop unused ControlFlowInstr type enum
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24638>
Gert Wollny [Mon, 7 Aug 2023 13:10:26 +0000 (15:10 +0200)]
r600/sfn: Make use of four clause local registers
The hardware is actually configures like this, but for fma64
we have to sacrifice a "normal" register to allocate z and w
channels, even though the result written there is not used.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24638>
Lionel Landwerlin [Tue, 8 Aug 2023 06:13:16 +0000 (09:13 +0300)]
intel/fs: limit register flag interaction of FIND_*LIVE_CHANNEL
Those instructions do not access the flag registers on Gfx8+. Removing
the interaction enables CSE to remove more of those instructions.
Results are a bit mixed (DG2 vulkan fossils):
ACO:
Totals from 127 (5.97% of 2128) affected shaders:
Instrs: 139966 -> 138972 (-0.71%); split: -0.85%, +0.14%
Cycles: 1685747 -> 1667480 (-1.08%); split: -2.35%, +1.26%
Max live registers: 10582 -> 10544 (-0.36%)
Max dispatch width: 1048 -> 1040 (-0.76%)
Cyberpunk 2077:
Totals from 2879 (27.95% of 10301) affected shaders:
Instrs: 4264789 -> 4225666 (-0.92%); split: -1.01%, +0.09%
Cycles:
72380209 ->
71619521 (-1.05%); split: -1.63%, +0.58%
Subgroup size: 30624 -> 30632 (+0.03%)
Spill count: 98 -> 101 (+3.06%)
Fill count: 90 -> 93 (+3.33%)
Scratch Memory Size: 8192 -> 9216 (+12.50%)
Max live registers: 217807 -> 217098 (-0.33%); split: -0.59%, +0.26%
Max dispatch width: 23792 -> 24112 (+1.34%)
Gaining 40 SIMD16 shaders
Rise Of The Tomb Raider:
Totals from 622 (5.06% of 12289) affected shaders:
Instrs: 437380 -> 434760 (-0.60%); split: -0.72%, +0.12%
Cycles:
261843085 ->
261580703 (-0.10%); split: -0.73%, +0.63%
Max live registers: 27731 -> 27766 (+0.13%); split: -1.01%, +1.14%
Max dispatch width: 5832 -> 5432 (-6.86%); split: +0.27%, -7.13%
Loosing 26 SIMD32 shaders
Strange Brigade:
Totals from 1298 (31.48% of 4123) affected shaders:
Instrs: 1504408 -> 1487968 (-1.09%); split: -1.17%, +0.08%
Cycles:
20735976 ->
20443216 (-1.41%); split: -1.60%, +0.19%
Max live registers: 89911 -> 89957 (+0.05%)
DG2 shader-db run:
total instructions in shared programs:
23130895 ->
23130036 (<.01%)
instructions in affected programs: 260956 -> 260097 (-0.33%)
helped: 234
HURT: 101
helped stats (abs) min: 1 max: 54 x̄: 6.36 x̃: 4
helped stats (rel) min: 0.05% max: 8.16% x̄: 2.01% x̃: 1.90%
HURT stats (abs) min: 1 max: 37 x̄: 6.23 x̃: 3
HURT stats (rel) min: 0.02% max: 5.67% x̄: 0.89% x̃: 0.55%
95% mean confidence interval for instructions value: -3.62 -1.51
95% mean confidence interval for instructions %-change: -1.33% -0.94%
Instructions are helped.
total loops in shared programs: 6071 -> 6071 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total cycles in shared programs:
898610645 ->
898557166 (<.01%)
cycles in affected programs:
18308201 ->
18254722 (-0.29%)
helped: 315
HURT: 48
helped stats (abs) min: 1 max: 19312 x̄: 404.23 x̃: 128
helped stats (rel) min: 0.02% max: 28.98% x̄: 3.92% x̃: 2.65%
HURT stats (abs) min: 2 max: 14478 x̄: 1538.60 x̃: 409
HURT stats (rel) min: <.01% max: 23.24% x̄: 3.34% x̃: 0.41%
95% mean confidence interval for cycles value: -333.68 39.03
95% mean confidence interval for cycles %-change: -3.51% -2.41%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 5964 -> 5964 (0.00%)
spills in affected programs: 0 -> 0
helped: 0
HURT: 0
total fills in shared programs: 6909 -> 6909 (0.00%)
fills in affected programs: 0 -> 0
helped: 0
HURT: 0
total sends in shared programs: 1040266 -> 1040266 (0.00%)
sends in affected programs: 0 -> 0
helped: 0
HURT: 0
LOST: 3
GAINED: 1
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24553>
Matt Coster [Mon, 4 Sep 2023 12:55:08 +0000 (13:55 +0100)]
pvr: Cleanup comments in pvr_physical_device_get_supported_*()
pvr_physical_device_get_supported_extensions() contained unneeded
/* clang-format off */ guards.
The section comments in pvr_physical_device_get_supported_features()
also now match the pattern in pvr_physical_device_get_properties().
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25033>
Vignesh Raman [Fri, 28 Jul 2023 09:22:19 +0000 (14:52 +0530)]
ci: enforce -Wimplicit-const-int-float-conversion for clang
All -Wimplicit-const-int-float-conversion warnings are fixed and ci
can drop -Wno-error=implicit-const-int-float-conversion.
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Acked-by: Helen Koike <helen.koike@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24362>
Vignesh Raman [Mon, 4 Sep 2023 03:24:04 +0000 (08:54 +0530)]
Do explicit cast to suppress clang warnings
Do explicit cast to suppress the below clang warnings,
../src/mesa/main/get.c:86:31: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
return ( ((F) * 65536.0f > INT_MAX) ? INT_MAX :
../src/mesa/main/texparam.c:967:27: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
((param > INT_MAX) ? INT_MAX : (GLint) (param + 0.5)) :
../src/mesa/main/texparam.c:2609:65: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
*params = LCLAMPF(obj->Sampler.Attrib.MinLod, INT_MIN, INT_MAX);
../src/mesa/main/texparam.c:2624:65: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
*params = LCLAMPF(obj->Sampler.Attrib.MaxLod, INT_MIN, INT_MAX);
../src/mesa/main/texparam.c:2648:72: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
*params = LCLAMPF(obj->Sampler.Attrib.MaxAnisotropy, INT_MIN, INT_MAX);
../src/mesa/main/texparam.c:2693:66: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
*params = LCLAMPF(obj->Sampler.Attrib.LodBias, INT_MIN, INT_MAX);
../src/gallium/drivers/freedreno/a3xx/fd3_emit.c:731:43: error: implicit conversion from 'unsigned int' to 'float' changes value from
4294967295 to
4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));
../src/gallium/drivers/freedreno/a3xx/fd3_emit.c:732:43: error: implicit conversion from 'unsigned int' to 'float' changes value from
4294967295 to
4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));
../src/nouveau/codegen/nv50_ir_peephole.cpp:1647:30: error: implicit conversion from 'unsigned int' to 'float' changes value from
4294967295 to
4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
CASE(TYPE_U32, u32, 0, UINT32_MAX, 0, INT32_MAX, 0, UINT32_MAX);
../src/nouveau/codegen/nv50_ir_peephole.cpp:1648:38: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
CASE(TYPE_S32, s32, INT32_MIN, INT32_MAX, INT32_MIN, INT32_MAX, 0, INT32_MAX);
../src/gallium/drivers/radeonsi/si_nir_lower_vs_inputs.c:400:51: error: implicit conversion from 'unsigned long long' to 'double' changes value from
18446744073709551615 to
18446744073709551616 [-Werror,-Wimplicit-const-int-float-conversion]
loads[chan] = nir_fmul_imm(b, tmp, 1.0 / BITFIELD64_MASK(bits));
../src/gallium/drivers/radeonsi/si_nir_lower_vs_inputs.c:408:43: error: implicit conversion from 'unsigned long long' to 'double' changes value from
18446744073709551615 to
18446744073709551616 [-Werror,-Wimplicit-const-int-float-conversion]
tmp = nir_fmul_imm(b, tmp, 1.0 / BITFIELD64_MASK(bits - 1));
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Acked-by: Helen Koike <helen.koike@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24362>
Vlad Schiller [Thu, 10 Aug 2023 12:14:38 +0000 (13:14 +0100)]
pvr: Remove PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC flag
There has been a recent change to the new powervr KMD to always zero buffer
objects at allocation time to avoid information leaks. This change was made to
address upstream feedback [1]. The result is that the
PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC no longer makes a difference when using this
KMD.
As the powervr KMD is the one we actually care about, it makes sense to mirror
this change when using the downstream pvrsrvkm KMD in order to avoid differences
in behaviour between the two KMDs. As this makes the
PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC flag entirely redundant, remove it.
[1] https://lists.freedesktop.org/archives/dri-devel/2023-August/418042.html
Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24930>
Rohan Garg [Wed, 6 Sep 2023 11:14:42 +0000 (13:14 +0200)]
iris: migrate preemption streamwout wa to WA infra
Fixes: db6c374 ('iris: disable preemption for 3DPRIMITIVE during streamout')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25080>
Samuel Pitoiset [Wed, 6 Sep 2023 06:40:53 +0000 (08:40 +0200)]
zink/ci: merge piglit testing with deqp-runner for RADV
This avoids using an extra script to run GLCTS+piglit.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25062>
Samuel Pitoiset [Tue, 5 Sep 2023 15:54:30 +0000 (17:54 +0200)]
zink/ci: merge GLCTS testing with GLESx for RADV
Both testsuites used to be executed separately because of spurious
failures/hangs but they seem fixed now.
GLCTS+GLES might be faster to run now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25062>
David Heidelberg [Wed, 30 Aug 2023 20:06:35 +0000 (22:06 +0200)]
ci/farms: no need to check RUNNER_TAG for Collabora farm
Since Google Freedreno and Collabora farm definition split,
we don't need to check for runner tag.
Reported-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24961>
Samuel Pitoiset [Wed, 6 Sep 2023 06:26:12 +0000 (08:26 +0200)]
radv: add support for DGC with SQTT
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25035>
Samuel Pitoiset [Tue, 5 Sep 2023 06:39:21 +0000 (08:39 +0200)]
radv: avoid emitting SQTT markers for DGC calls
This confuses RGP.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25035>
Jordan Justen [Tue, 15 Aug 2023 10:07:30 +0000 (03:07 -0700)]
intel/genxml: Fix comparing xml when node counts differ
This fix is more relevant to MR !20593. Normally when sorting the
number of nodes will be equivalent today, so this bug will not be
encountered. But in !20593, we can shrink (--import) or grow the
number of elements (--flatten) when the genxml_import.py tool is used.
Fixes:
e60a0b16163 ("intel/genxml: Move sorting & writing into GenXml class")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24902>
Jordan Justen [Tue, 15 Aug 2023 22:26:34 +0000 (15:26 -0700)]
intel/genxml: Ignore tail leading/trailing whitespace in node_validator()
When importing or flattening genxml with the genxml_import.py script
in MR !20593, it can lead to the tail portion of xml items differing
in whitespace.
If we strip the trailing and leading whitespace from the tail string,
and the strings are equivalent, then we can consider the xml items to
be equivalent.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24903>
Jordan Justen [Wed, 19 Jul 2023 00:01:28 +0000 (17:01 -0700)]
intel/dev/xe: Move placeholder subslice info into XEHP_FEATURES
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24418>
Chris Spencer [Sat, 12 Aug 2023 13:00:26 +0000 (14:00 +0100)]
radv/video: use correct enum value for max level IDC
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24649>
Chris Spencer [Sat, 12 Aug 2023 13:00:14 +0000 (14:00 +0100)]
anv/video: use correct enum value for max level IDC
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24649>
Marek Olšák [Sun, 9 Jul 2023 02:25:19 +0000 (22:25 -0400)]
ac/llvm: don't convert undef to 0 because nir_opt_undef does it now
TOTALS FROM AFFECTED SHADERS (29663/58918)
Code Size:
39163724 ->
37842360 (-3.37 %) bytes
Max Waves: 394813 -> 396334 (0.39 %)
Outputs: 84616 -> 84616 (0.00 %)
Patch Outputs: 0 -> 0 (0.00 %)
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24059>
Marek Olšák [Sat, 8 Jul 2023 23:33:31 +0000 (19:33 -0400)]
nir: remove nir_op_unpack_64 handling from nir_opt_undef
It's no longer needed because undef is replaced with 0 in this case.
It also has a bug that it doesn't freeze the undef value if undef has
multiple uses.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24059>
Marek Olšák [Thu, 6 Jul 2023 08:52:16 +0000 (04:52 -0400)]
nir: replace undef only used by ALU opcodes with 0 or NaN
If undef is consumed by an FP opcode, replace it with NaN to eliminate
that opcode, else replace it with 0, but there are exceptions, such as
when undef is used by stores or phis, it's not touched.
This also contains workarounds for viewperf shaders.
radeonsi:
TOTALS FROM AFFECTED SHADERS (1987/58918)
Code Size: 5158692 -> 5143796 (-0.29 %) bytes
Max Waves: 22456 -> 22513 (0.25 %)
Outputs: 3726 -> 3726 (0.00 %)
Patch Outputs: 0 -> 0 (0.00 %)
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24059>
Jordan Justen [Thu, 30 Mar 2023 07:50:10 +0000 (00:50 -0700)]
intel/clflush: Add support for clflushopt instruction
Rework:
* Split clflushopt into a separate file as recommended by Ken.
If we enable -mclflush on all driver source compilation, then
gcc may insert uses of it on processors that don't support it.
* Add uintptr_t casting to cpu_caps->cacheline usage
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Thu, 30 Mar 2023 06:30:44 +0000 (23:30 -0700)]
meson: Check for the __builtin_ia32_clflushopt function
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Thu, 30 Mar 2023 07:44:52 +0000 (00:44 -0700)]
util/u_cpu_detect: Detect clflushopt support
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Sun, 9 Apr 2023 19:25:14 +0000 (12:25 -0700)]
util/u_cpu_detect: Drop unused has_tsc
This will allow us to add has_clflushopt without spilling into an new
unsigned.
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Fri, 4 Aug 2023 19:55:15 +0000 (12:55 -0700)]
anvil,hasvk: Use intel_flush_range_no_fence to flush command buffers
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Fri, 4 Aug 2023 18:30:17 +0000 (11:30 -0700)]
intel/common: Add intel_flush_range_no_fence
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Fri, 4 Aug 2023 18:37:21 +0000 (11:37 -0700)]
anvil,hasvk: Replace intel_clflush_range with intel_flush_range
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Mon, 10 Apr 2023 06:37:50 +0000 (23:37 -0700)]
intel/common: Move intel_clflush.h to intel_mem.h/intel_mem.c
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Fri, 4 Aug 2023 18:22:05 +0000 (11:22 -0700)]
anvil,hasvk: Rename need_clflush to need_flush
$ git grep -l need_clflush | xargs sed -i 's/need_clflush/need_flush/g'
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Karol Herbst [Tue, 5 Sep 2023 15:58:19 +0000 (17:58 +0200)]
rusticl/mesa: create contexts with PIPE_CONTEXT_NO_LOD_BIAS
It's not a thing in OpenCL
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25067>
Sil Vilerino [Mon, 3 Jul 2023 12:54:18 +0000 (08:54 -0400)]
d3d12: Video Decode - Remove unnecessary copy for texture array case
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25069>
antonino [Mon, 21 Aug 2023 21:34:12 +0000 (23:34 +0200)]
drirc: enable `vk_wsi_force_swapchain_to_current_extent` for "Serious Sam Fusion"
This game handles swapchain size incorrecly and can crash because of
it.
Enable this driconf as a workaround.
Fixes:
6139493ae38 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
antonino [Mon, 21 Aug 2023 20:52:50 +0000 (22:52 +0200)]
drirc: enable `vk_wsi_force_swapchain_to_current_extent` for "The Talos Principle"
This game handles swapchain size incorrecly and can crash because of
it.
Enable this driconf as a workaround.
Fixes:
6139493ae38 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
antonino [Mon, 21 Aug 2023 20:50:34 +0000 (22:50 +0200)]
vulkan/wsi: add `vk_wsi_force_swapchain_to_current_extent` driconf
Add a driconf to force the swapchain size to match
`VkSurfaceCapabilities2KHR::currentExtent` as a workaround for
misbehaved games
Fixes:
6139493ae38 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
Dave Airlie [Fri, 1 Sep 2023 05:11:12 +0000 (15:11 +1000)]
llvmpipe: move to nir lowering for fquantize2f16
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24988>
Tapani Pälli [Mon, 4 Sep 2023 10:30:07 +0000 (13:30 +0300)]
driconf: use lower_depth_range_rate for The Spirit and The Mouse
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9738
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25029>
David Heidelberg [Tue, 5 Sep 2023 14:31:11 +0000 (20:01 +0530)]
Revert "ci: disable Google Freedreno farm, currently timeouting on all jobs"
This reverts commit
fc46062ee52e8c09f10bb8cc80e00b73b592e6f4.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25058>
David Rosca [Mon, 21 Aug 2023 09:01:39 +0000 (11:01 +0200)]
frontends/va: Support chroma sample location in postproc
Rename vlVaSetCscMatrix to vlVaSetProcParameters because it now does
more than just setting csc matrix.
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>
David Rosca [Mon, 21 Aug 2023 08:31:40 +0000 (10:31 +0200)]
gallium/auxiliary/vl: Support chroma sample location in compute shaders
Used only in YUV to RGB video_buffer shader for now.
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>
David Rosca [Mon, 21 Aug 2023 08:00:59 +0000 (10:00 +0200)]
gallium/auxiliary/vl: Clamp coordinates in compute shaders
Video textures include padding, so this is needed to avoid sampling
outside of src rect due to scaling or additional offset.
Fixes wrong colors on right/bottom edge.
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>