Po Liu [Tue, 26 Nov 2013 06:34:07 +0000 (14:34 +0800)]
powerpc/c29xpcie: Getting DDR SPD image from 16-bit sub-address EEPROM
Currently, there is only one EEPROM on c29xpcie board which is AT24C1024.
We program the SPD data at beginning of the AT24C1024.But the AT24C1024
has a 16-bit sub-address mode. This patch is tomake it work when getting
SPD in a 16-bit sub-address EEPROM.
Signed-off-by: Po Liu <Po.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Zhao Qiang [Tue, 26 Nov 2013 05:59:15 +0000 (13:59 +0800)]
powerpc/p1010rdb:modify the mtest start_address
In new board P1010RDB-PB, the interrupt vector table is at
the start of memory. So if the start_address needs to be set
a proper value.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Dave Liu [Thu, 28 Nov 2013 06:58:08 +0000 (14:58 +0800)]
powerpc/corenet: CPC1 speculation disable
In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Tom Rini [Mon, 2 Dec 2013 13:48:02 +0000 (08:48 -0500)]
Merge branch 'serial' of git://git.denx.de/u-boot-microblaze
Tom Rini [Mon, 2 Dec 2013 13:44:28 +0000 (08:44 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mips
Masahiro Yamada [Thu, 21 Nov 2013 07:10:20 +0000 (16:10 +0900)]
Blackfin: remove executable permission of AWK script
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tom Rini [Mon, 2 Dec 2013 13:38:28 +0000 (08:38 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Soren Brinkmann [Tue, 29 Oct 2013 20:11:54 +0000 (13:11 -0700)]
serial: zynq: Remove unused #defines
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: trini, uboot
Paul Burton [Tue, 26 Nov 2013 17:45:28 +0000 (17:45 +0000)]
malta: set CONFIG_SYS_BOOTM_LEN to 64MB
Allow a larger kernel binary to be decompressed - the default 8MB can
become limiting on a Malta.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Tue, 26 Nov 2013 17:45:27 +0000 (17:45 +0000)]
malta: enable PIIX4 SERIRQ
Whilst U-boot does not require this itself, Linux currently relies upon
it having been muxed and enabled by the bootloader. Thus in order to
preserve compatibility with current kernels before a fix is merged in
Linux we will enable the SERIRQ interrupt and mux it to its pin.
Without doing this current kernels will never receive serial port
interrupts and the end result is typically that userland appears to
hang.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Tue, 26 Nov 2013 17:45:26 +0000 (17:45 +0000)]
malta: correct UART baudrate
CONFIG_SYS_NS16550_CLK specifies the rate of the clock 16x the baud
rate. The SMSC FDC37M81x datasheet states that a divider of 1 results in
a UART at 115200 baud, thus the x16 clock rate is 115200 * 16.
Previously the divider was left at 0 which led to a rate of 38400 baud
regardless of CONFIG_BAUDRATE or the baudrate environment variable.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Tue, 26 Nov 2013 17:45:25 +0000 (17:45 +0000)]
mips: don't hardcode Malta env baudrate
The baudrate passed to Linux in the environment was hardcoded at 38400.
Instead pass the correct baudrate from global data, allowing Linux to
correctly inherit the baudrate used by U-boot when console setup is not
explicitly specified.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Tom Rini [Mon, 25 Nov 2013 21:49:32 +0000 (16:49 -0500)]
Prepare v2014.01-rc1
Signed-off-by: Tom Rini <trini@ti.com>
Shengzhou Liu [Fri, 22 Nov 2013 09:39:12 +0000 (17:39 +0800)]
t2080qds/ramboot: enable PBL tool for t2080qds
Add the default RCW(SerDes 0x66_0x16) and PBI configure file for
T2080QDS board, so we can use PBL tool to generate the ramboot
image to support boot from NAND/SPI/SD.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Shengzhou Liu [Fri, 22 Nov 2013 09:39:11 +0000 (17:39 +0800)]
powerpc/t2080qds: add support for t2080qds board
The T2080QDS is a high-performance computing evaluation, development and
test platform supporting the T2080 QorIQ Power Architecture processor.
T2080QDS feature overview
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LV devices
- Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- Four 10Gbps XFI on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
SATA:
- Two SATA 2.0 ports on-board
SRIO:
- Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
- Supports SD/SDHC/SDXC/eMMC Card
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
System Logic:
- QIXIS-II FPGA system controll
Debug Features:
- Support Legacy, COP/JTAG, Aurora, Event and EVT
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: removed Makefile blank line at EOF,
fix conflicts with moving DDR driver]
Acked-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Fri, 22 Nov 2013 09:39:10 +0000 (17:39 +0800)]
powerpc/mpc85xx: Add T2080/T2081 SoC support
Add support for Freescale T2080/T2081 SoC.
T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 16 8
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Fri, 22 Nov 2013 09:39:09 +0000 (17:39 +0800)]
net/fman: Add support for 10GEC3 and 10GEC4
There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080).
This patch adds support for 10GEC3 and 10GEC4.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
York Sun [Tue, 22 Oct 2013 19:39:02 +0000 (12:39 -0700)]
Driver/IFC: Move Freescale IFC driver to a common driver
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Mon, 28 Oct 2013 23:36:02 +0000 (16:36 -0700)]
Driver/DDR: Update DDR driver to allow non-zero base address
The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Mon, 3 Jun 2013 19:39:06 +0000 (12:39 -0700)]
powerpc/mpc8xxx: Extend DDR registers' fields
Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.
TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit
c360ceac.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Mon, 30 Sep 2013 21:20:51 +0000 (14:20 -0700)]
Driver/DDR: Add Freescale DDR driver for ARM
Make PowerPC specific code conditional so ARM SoCs can reuse
this driver. Add DDR3 driver for ARM.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Mon, 18 Nov 2013 18:29:32 +0000 (10:29 -0800)]
Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Mon, 30 Sep 2013 16:22:09 +0000 (09:22 -0700)]
Driver/DDR: Moving Freescale DDR driver to a common driver
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.
Signed-off-by: York Sun <yorksun@freescale.com>
Zhao Qiang [Thu, 26 Sep 2013 01:10:32 +0000 (09:10 +0800)]
p1010rdb: enable mtdparts for NAND
The default partition table matches the .dts files for these boards in
Linux. This allows these partitions to be used by name with U-Boot's
"nand" command.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Tang Yuantian [Thu, 17 Oct 2013 02:47:33 +0000 (10:47 +0800)]
mpc85xx: Fix the offset of register address error
The offset of register address within GPIO module is just
CONFIG_SYS_MPC85xx_GPIO_ADDR. So, fix it. The following platforms
are confirmed: MPC8572, P1023, P1020, P1022, P2020, P4080,
P5020, P5040, T4240, B4860.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Priyanka Jain [Fri, 25 Oct 2013 09:56:27 +0000 (15:26 +0530)]
powerpc/t1040qds: Correct Maintainer name in boards.cfg
Update T1040QDS naem to Poonam Aggrwal.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Tom Rini [Mon, 25 Nov 2013 15:42:53 +0000 (10:42 -0500)]
Merge branch 'sandbox1' of git.denx.de/u-boot-x86
Tom Rini [Mon, 25 Nov 2013 15:42:19 +0000 (10:42 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-net
Tom Rini [Mon, 25 Nov 2013 15:42:13 +0000 (10:42 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
Tom Rini [Mon, 25 Nov 2013 15:42:05 +0000 (10:42 -0500)]
Merge branch 'buildpatman' of git.denx.de/u-boot-x86
Tom Rini [Mon, 18 Nov 2013 13:31:56 +0000 (08:31 -0500)]
sparc: Correct arch/sparc/cpu/leon3/start.S from SPDX conversion
The SPDX tag conversion ate part of this file, put things back to the
way they should be.
Signed-off-by: Tom Rini <trini@ti.com>
Wolfgang Denk [Tue, 19 Nov 2013 07:01:44 +0000 (08:01 +0100)]
blackfin: don't use 'bool' when it causes problems
The use of 'bool' data types in globally used header files cases build
errors like this:
In file included from arch/blackfin/include/asm/blackfin.h:13:0,
from include/common.h:92,
from cmd_test.c:17:
arch/blackfin/include/asm/blackfin_local.h:54:1: error: unknown type name 'bool'
Use plain 'int' instead to avoid such kind of trouble.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Masahiro Yamada [Thu, 21 Nov 2013 10:06:58 +0000 (19:06 +0900)]
MAKEALL: add -b (--board) option
Some board have multiple configurations.
For example, the board "m54455evb" has many configurations:
M54455EVB, M54455EVB_a66, M54455EVB_i66, M54455EVB_intel, ...
When we modify board-related files, we need to test
all configurations based on such a board.
In such a case, the new option -b is useful.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Wed, 20 Nov 2013 09:14:23 +0000 (18:14 +0900)]
bios_emulator: delete an unnecessary include path
-I$(TOPDIR)/include is defined in the top config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Wed, 20 Nov 2013 09:11:57 +0000 (18:11 +0900)]
nand_spl: trivial refactoring of makefiles
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Wed, 20 Nov 2013 03:45:56 +0000 (12:45 +0900)]
Makefile: descend into subdirectories only when CONFIG_API is defined
All objects under api/ and examples/api/ directories are selected
by CONFIG_API.
So we can move CONFIG_API switch to the top Makefile.
In order to use CONFIG_API, the definition of SUBDIR_EXAMPLES-y
must be moved after "sinlude $(obj)include/autoconf.mk".
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 07:24:58 +0000 (16:24 +0900)]
common: Delete unnecessary rules.
The directory tools/ is always built before common/.
So when envcrc tool is necessary in common/Makefile,
it already exists.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 02:18:57 +0000 (11:18 +0900)]
drivers: delete unnecessary HOSTCFLAGS
HOSTCFLAGS is meaningless because no host programs
are compiled there.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 02:17:30 +0000 (11:17 +0900)]
Makefile: move some libraries to lib/Makefile
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 02:08:35 +0000 (11:08 +0900)]
Makefile: descend into subdirectories only when CONFIG_API is defined
All objects under api/ and examples/api/ directories are selected
by CONFIG_API.
So we can move CONFIG_API switch to the top Makefile.
In order to use CONFIG_API, the definition of SUBDIR_EXAMPLES-y
must be moved after "sinlude $(obj)include/autoconf.mk".
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 02:06:00 +0000 (11:06 +0900)]
examples: delete unnecessary CPPFLAGS
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 01:39:39 +0000 (10:39 +0900)]
board: tqm5200: delete its own object make rule
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 01:34:36 +0000 (10:34 +0900)]
spieval: Remove remainders of dead board
Commit
69434e4c deleted spieval board support
but it missed to clean up include/configs/spieval.h file.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 01:25:41 +0000 (10:25 +0900)]
post: remove unnecessary include path settings
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Mon, 18 Nov 2013 00:44:54 +0000 (09:44 +0900)]
board: h2200: Delete an unnecessary make rule
We have a generic rule to generate .o file from *.S
in $(TOPDIR)/config.mk.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Thu, 14 Nov 2013 02:00:30 +0000 (11:00 +0900)]
tools: updater: Remove remainders of dead board
tools/updater needs board/MAI/AmigaOneG3SE board
for compiling.
But AmigaOneG3SE board was already deleted
by Commit 953b7e6.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Thu, 14 Nov 2013 01:58:56 +0000 (10:58 +0900)]
tools: imls: Remove a broken and unused tool.
It looks like tools/imls/Makefile is invoked from nowhere.
And also it is broken.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Igor Grinberg [Thu, 7 Nov 2013 23:03:52 +0000 (01:03 +0200)]
gpio_led: add support for inverted polarity
Some GPIO connected LEDs have inverted polarity.
Introduce new config option: CONFIG_GPIO_LED_INVERTED_TABLE for the
specifying the inverted GPIO LEDs list and add support for this in the
gpio_led driver.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Ilya Ledvich <ilya@compulab.co.il>
Igor Grinberg [Thu, 7 Nov 2013 23:03:51 +0000 (01:03 +0200)]
gpio_led: check gpio_request() return value
Add a check for the gpio_request() function return value and do not try
to configure the GPIO if the gpio_request() call fails.
Also, print an error message indicating the gpio_request() has failed.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Ilya Ledvich <ilya@compulab.co.il>
Igor Grinberg [Thu, 7 Nov 2013 23:03:50 +0000 (01:03 +0200)]
README: document the CONFIG_GPIO_LED symbol
The CONFIG_GPIO_LED symbol does not have any documentation in the README
file. Document the CONFIG_GPIO_LED symbol.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tom Rini [Thu, 7 Nov 2013 12:39:48 +0000 (07:39 -0500)]
hash.c: Correct non-hash subcommand crc32 addr-save support
In the case of not having CONFIG_CMD_HASH but having CONFIG_CMD_CRC32
enabled (and not CONFIG_CRC32_VERIFY), we end up in this part of the
code path on hash_command(). However, we will only have exactly 3 args
here, and 3 > 3 is false, and we will not try and store the hash at the
address given as arg #3. The next problem however is that we've been
moving argv around so the third value is now in argv[0] not argv[3].
Confirmed on AM335x Beaglebone White.
Signed-off-by: Tom Rini <trini@ti.com>
Thierry Reding [Fri, 20 Sep 2013 14:03:43 +0000 (16:03 +0200)]
net: rtl8169: Add support for RTL8168d/8111d
This chip is compatible with the existing driver, except that it uses
BAR2 instead of BAR1 for the I/O memory region. Using this patch I can
use the PCIe ethernet interface on the CompuLab Trimslice to boot from
the network.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Patch: 276477
Thierry Reding [Fri, 20 Sep 2013 14:03:42 +0000 (16:03 +0200)]
net: rtl8169: Improve cache maintenance
Instead of directly calling the low-level invalidate_dcache_range() and
flush_cache() functions, provide thin wrappers that take into account
alignment requirements.
While at it, fix a case where the cache was flushed but should have been
invalidated, two cases where the buffer data was flushed instead of the
descriptor and a missing cache invalidation before reading the packet
data that the NIC just wrote to memory.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Patch: 276474
Srikanth Thokala [Fri, 8 Nov 2013 17:25:48 +0000 (22:55 +0530)]
net: zynq_gem: Add d-cache support
Added d-cache support for zynq_gem.c,
Observed a difference of +0.8 MiB/s when downloading
a file of size of 3007944Bytes.
With d-cache OFF:
----------------
Filename 'uImage'.
Load address: 0x800
Loading: #################################################################
#################################################################
#################################################################
##########
1.3 MiB/s
done
Bytes transferred = 3007944 (2de5c8 hex)
With d-cache ON:
---------------
Filename 'uImage'.
Load address: 0x800
Loading: #################################################################
#################################################################
#################################################################
##########
2.1 MiB/s
done
Bytes transferred = 3007944 (2de5c8 hex)
Changes on zynq_gem for d-cache support:
- Tx and Rx buffers are cache-aligned
- Updated logic for invalidating Rx buffers and flushing Tx buffers.
- Tx and Rx BD's are allocated from non-cacheable region.
(When BDs are cached, we don't see a consistent link)
- Use TX BD status intead of txsr status checks.
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
David Dueck [Tue, 5 Nov 2013 16:23:03 +0000 (17:23 +0100)]
phy: Use general phy code for smsc lan8720a
Signed-off-by: David Dueck <davidcdueck@googlemail.com>
David Dueck [Tue, 5 Nov 2013 16:23:02 +0000 (17:23 +0100)]
phy: Use supported field during autonegotiation
The current code incorrectly detects gigabit capabilities for some
100Mbit/s phys. (lan8720a)
Signed-off-by: David Dueck <davidcdueck@googlemail.com>
Andrew Ruder [Wed, 23 Oct 2013 00:09:02 +0000 (19:09 -0500)]
net: dm9000: random mac address support
When an unprogrammed EEPROM is attached to a dm9000, the dm9000 will
come up with a invalid MAC address of ff:ff:ff:ff:ff:ff. Add code that
gets enabled if CONFIG_RANDOM_MACADDR is enabled that generates a random
(and valid) locally administered MAC address that allows the system to
network boot until a real MAC address can be configured.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Rojhalat Ibrahim [Mon, 7 Oct 2013 16:30:39 +0000 (18:30 +0200)]
drivers/net/e1000: Introduce CONFIG_E1000_NO_NVM
The e1000 driver expects to always have some kind of non-volatile memory
attached directly to the ethernet controller chip. This means that I would
have to add an additional separate flash chip to my custom board just to
store essentially the MAC address. Since I don't want to do that, this patch
introduces a new config option CONFIG_E1000_NO_NVM. If defined it disables
all accesses to the NVM. I have tested the patch with a 82574 controller.
Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
Andrew Ruder [Wed, 23 Oct 2013 00:10:28 +0000 (19:10 -0500)]
net: tftpsrv: Get correct client MAC address
NetServerEther was not being cleared in the tftp server code, so the
destination MAC address would be whatever the last destination MAC
address was.
Scenario:
U-Boot:
dhcp
tftpsrv
Host:
Send device WRQ
Device:
Responds with ACK to dhcp server mac address with
host ip address
By clearing NetServerEther, we force a lookup of the host MAC address
to go with the associated host IP.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Fabio Estevam [Sat, 2 Nov 2013 18:40:42 +0000 (16:40 -0200)]
net: phy: atheros: Fix masks for AR8035 and AR8021
The masks were ignoring the last 4 bits which didn't allow detection differences
between the ar8031 and ar8035.
Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Patch: 288018
Chunhe Lan [Fri, 1 Nov 2013 09:17:44 +0000 (17:17 +0800)]
net/phy: Fix the phy id mask of AR8031
The both AR8031 and AR8035 belong to Atheros 803x serial PHY.
So the phy id mask of AR8031 is the same to the phy id mask
of AR8035. The right mask value is 0x4fffff.
This patch has been tested on the P1010 and P1023.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Patch: 287748
Claudiu Manoil [Mon, 30 Sep 2013 09:44:47 +0000 (12:44 +0300)]
net: tsec: Fix mac addr setup portability, cleanup
Fix the 32-bit memory access that is not "endianess safe",
i.e. not giving the desired byte layout for LE cpus:
tempval = *((uint *) (tmpbuf + 4)), where 'char tmpbuf[]'.
Free the stack from rendundant local vars:
tmpbuf[] and i.
Use a portable type (u32) for the 32bit tsec register value
holder: tempval.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Claudiu Manoil [Mon, 30 Sep 2013 09:44:46 +0000 (12:44 +0300)]
net: tsec: Use portable regs type (uint->u32)
Use cross arch portable u32 instead of uint for the
tsec registers. Remove the typedefs for the register
struct definitions in the process. Fix long lines.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Claudiu Manoil [Fri, 4 Oct 2013 16:13:53 +0000 (19:13 +0300)]
net: tsec: Use portable types and accessors for BDs
Currently, the buffer descriptor (BD) fields cannot be
correctly accessed by a little endian processor. This
patch fixes the issue by making the access of BDs to be
portable among different cpu architectures.
Use portable data types for the Rx/Tx buffer descriptor
fields. Use portable I/O accessors to insure that the
big endian BDs are correctly accessed by little endian
cpus too, and to insure proper sync with the H/W.
Removed the redundant RTXBD "volatile" type, as proper
synchronization around BD data accesses is provided by
the I/O accessors now.
The "sparse" tool was also used to verify the correctness
of these changes.
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Claudiu Manoil [Mon, 30 Sep 2013 09:44:44 +0000 (12:44 +0300)]
net: tsec: Fix CamelCase issues around BD code
Fix bufPtr and the rxIdx/ txIdx occurrences to
solve the related checkpatch warnings for the
coming patches.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Claudiu Manoil [Mon, 30 Sep 2013 09:44:43 +0000 (12:44 +0300)]
net: fsl_mdio: Fix warnings for __iomem pointers
Add the __iomem address space marker for the tsec pointers
to struct tsec_mii_mng memory mapped register regions.
This solves the sparse warnings for mixig normal pointers with
__iomem pointers for tsec. E.g.:
fsl_mdio.c:34:19: warning: incorrect type in argument 1 (different
address spaces)
fsl_mdio.c:34:19: expected unsigned int volatile [noderef]
<asn:2>*addr
fsl_mdio.c:34:19: got unsigned int *<noident>
[...]
tsec.c:91:35: warning: incorrect type in argument 1 (different address
spaces)
tsec.c:91:35: expected struct tsec_mii_mng *phyregs
tsec.c:91:35: got struct tsec_mii_mng [noderef] <asn:2>*phyregs_sgmii
[...]
tsec.c:680:19: warning: incorrect type in assignment (different address
spaces)
tsec.c:680:19: expected struct tsec_mii_mng *regs
tsec.c:680:19: got struct tsec_mii_mng [noderef] <asn:2>*<noident>
[...]
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Claudiu Manoil [Mon, 30 Sep 2013 09:44:42 +0000 (12:44 +0300)]
net: tsec: Cleanup tsec regs init and fix __iomem warns
Remove tsec_t typedef. Define macros as getters of
tsec and mdio register memory regions, for consistent
initialization of various 'regs' fields and also to
manage overly long initialization lines.
Use the __iomem address space marker to address sparse
warnings in tsec.c where IO accessors are used, like:
tsec.c:394:19: warning: incorrect type in argument 1 (different
address spaces)
tsec.c:394:19: expected unsigned int volatile [noderef]
<asn:2>*addr
tsec.c:394:19: got unsigned int *<noident>
[...]
Add the __iomem address space marker for the tsec pointers
to struct tsec_mii_mng memory mapped register regions.
This solves the sparse warnings for mixig normal pointers
with __iomem pointers for tsec.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Claudiu Manoil [Mon, 30 Sep 2013 09:44:41 +0000 (12:44 +0300)]
net: tsec: Fix priv pointer in tsec_mcast_addr()
Access to privlist[1] (hardcoded referece to the 2nd tsec's
priv area) is neither correct nor does it make sense in the
current context. Each tsec dev has access to its own priv
instance only, and hence to its own set of group address
registers (GADDR) to filter multicast addresses.
This fix leads to removal of the unused (faulty) privlist[]
and related global static vars. Note that mcast() can be
called only after eth_device allocation and init, and hence
after priv area allocation, so dev->priv is correctly
initialized upon mcast() call.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Patch: 278990
Claudiu Manoil [Mon, 30 Sep 2013 09:44:40 +0000 (12:44 +0300)]
net: tsec: Fix and cleanup tsec_mcast_addr()
There are several implementation issues for tsec_mcast_addr()
addressed by this patch:
* unmanaged, not portable r/w access to registers; fixed with
setbits_be32()/ clrbits_be32()
* use of volatile pointers
* unnecessary forced cast to u8 for the ether_crc() result
* removed redundant parens
* corrected some comment slips
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Patch: 279000
Claudiu Manoil [Mon, 30 Sep 2013 09:44:39 +0000 (12:44 +0300)]
net: Fix mcast function pointer prototype
This fixes the following compiler warnings when activating
CONFIG_MCAST_TFTP:
tsec.c: In function 'tsec_mcast_addr':
tsec.c:130:2: warning: passing argument 2 of 'ether_crc' makes pointer
from integer without a cast [enabled by default]
In file included from /work/u-boot-net/include/common.h:874:0,
from tsec.c:15:
/work/u-boot-net/include/net.h:189:5: note: expected 'const unsigned
char *' but argument is of type 'u8'
tsec.c: In function 'tsec_initialize':
tsec.c:646:13: warning: assignment from incompatible pointer type
[enabled by default]
eth.c: In function 'eth_mcast_join':
eth.c:358:2: warning: passing argument 2 of 'eth_current->mcast' makes
integer from pointer without a cast [enabled by default]
eth.c:358:2: note: expected 'u32' but argument is of type 'u8 *'
In the eth_mcast_join() implementation, eth_current->mcast()
takes a u8 pointer to the multicast mac address and not a ip
address value as implied by its prototype.
Fix parameter type mismatch for tsec_macst_addr() (tsec.c):
ether_crc() takes a u8 pointer not a u8 value.
mcast() is given a u8 pointer to the multicats mac address.
Update parameter type for the rest of mcast() instances.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Patch: 278989
Alexey Brodkin [Wed, 25 Sep 2013 15:27:48 +0000 (19:27 +0400)]
net: designware: Fix alignment of buffer descriptors
It's important that buffer descriptors are aligned in accordance to GMAC
data bus width (32/64/128-bit). It's safe to align to 128-bit (16-bytes)
for every bus width type.
If buffer descriptor is improperly aligned GMAC discards lower bits of
provided address and as a result reads from improper location that
doesn't match expected fields.
Commit
ef76025a99247cdb8f927a2c9f15400678dfb599 "net: Multiple
updates/enhancements to designware.c" introduced another structure
member "link_printed" right before buffer descriptors while "padding"
member was left untouched. This together with alignment of structure
itself to 16-byte boundary forces buffer descriptoprs always to be
4-byte aligned that causes driver complete disfunction if GMAC bus width
is 64 or 128-bit.
Proposed change makes sure all buffer descriptors are 16-byte (128-bit)
aligned.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Patch: 277902
Alexey Brodkin [Wed, 25 Sep 2013 13:33:10 +0000 (17:33 +0400)]
net: designware: Respect "bus mode" register contents on SW reset
"bus mode" register contains lots of fields and some of them don't
expect to be written with 0 (zero). So since we're only interested in
resetting MAC (which is done with setting the least significant bit of
this register with "0") I believe it's better to modify only 1 bit of
the register.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Vipin Kumar <vipin.kumar@st.com>
Patch: 277864
Nobuhiro Iwamatsu [Tue, 24 Sep 2013 06:38:33 +0000 (15:38 +0900)]
net: sh-eth: Add support R8A7791
R8A7791 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7791.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Joe Hershberger <joe.hershberger@gmail.com>
Heiko Schocher [Sun, 22 Sep 2013 07:55:49 +0000 (09:55 +0200)]
net, phy: fix AR8031 phy_mask
AR8035 driver will be never applied because of wrong mask for
AR8031 driver. Fix this.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Patch: 276944
Thierry Reding [Fri, 20 Sep 2013 14:03:44 +0000 (16:03 +0200)]
net: rtl8169: Add support for RTL8168evl/8111evl
This chip is compatible with other RTL8168 chips and can be found on the
NVIDIA Cardhu and Beaver boards.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Patch: 276475
Thierry Reding [Fri, 20 Sep 2013 14:03:41 +0000 (16:03 +0200)]
net: rtl8169: Fix format string
currticks() is defined as get_timer(0), which returns an unsigned long,
so use %lu instead of %d to print the result.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Patch: 276473
Stefano Babic [Mon, 2 Sep 2013 13:42:32 +0000 (15:42 +0200)]
net: add support for extended registers to mdio command
Some phys (Micrel) have additional registers that can
be accessed using a special sequence. This patch allows
to use standard "mdio" command to accesss these registers.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Stefano Babic [Mon, 2 Sep 2013 13:42:31 +0000 (15:42 +0200)]
net: add function to read/write extended registers in Micrel Phy
Signed-off-by: Stefano Babic <sbabic@denx.de>
Stefano Babic [Mon, 2 Sep 2013 13:42:30 +0000 (15:42 +0200)]
net: add extended function to phy API
Some phys (Micrel) has extended registers that must be
accessed in a special way. Add pointers to the phy driver
structure to allow to use these functions with mdio command.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Stefano Babic [Mon, 2 Sep 2013 13:42:29 +0000 (15:42 +0200)]
net: fix mask for phy Micrel KSZ9031
Signed-off-by: Stefano Babic <sbabic@denx.de>
Stefano Babic [Mon, 2 Sep 2013 13:42:28 +0000 (15:42 +0200)]
phy: add missing constants for Micrel KSZ9031
Signed-off-by: Stefano Babic <sbabic@denx.de>
Bhupesh Sharma [Sat, 31 Aug 2013 23:10:52 +0000 (04:40 +0530)]
net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected
The 'get_phy_driver' code in 'drivers/net/phy/phy.c' uses the following
method to determine which driver is to be loaded for a particular PHY
module:
list_for_each(entry, &phy_drivers) {
drv = list_entry(entry, struct phy_driver, list);
if ((drv->uid & drv->mask) == (phy_id & drv->mask))
return drv;
}
This means that a drv->mask of 0xfffff0 will return incorrect phy driver
for the logic above, even if the drv->uid is anything other than
something ending with a 0x0.
For e.g. if the RTL8211E drv->uid is 0x1cc915 and drv->mask is 0xffffff
and the RTL8211B drv->uid is 0x1cc910 and drv->mask is 0xffffff0, then
the phy driver selected will always be RTL8211B even though the
underlying phy connected on the board is a 8211E module.
This patch fixes this issue.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Arpit Goel [Fri, 23 Aug 2013 14:48:05 +0000 (20:18 +0530)]
net: phy/vitesse: Add support for VSC8514 phy module
This patch adds support for VSC8514 PHY module which can be
found on Freescale's T1040RDB boards.
Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Nobuhiro Iwamatsu [Thu, 22 Aug 2013 04:22:04 +0000 (13:22 +0900)]
net: sh-eth: Add support R8A7790
R8A7790 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7790.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Nobuhiro Iwamatsu [Thu, 22 Aug 2013 04:22:03 +0000 (13:22 +0900)]
net: sh-eth: Add invalidate cache control for rmobile (ARM SoC)
The sh-eth of rmobile needs to use invalidate_cache* function.
This patch adds invalidate_cache* function.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Patch: 268948
Nobuhiro Iwamatsu [Thu, 22 Aug 2013 04:22:02 +0000 (13:22 +0900)]
net: sh-eth: Add control for padding size of packet descriptor
sh-eth can change the alignment size of a packet descriptor according to BUS
size. This patch adds this function.
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Nobuhiro Iwamatsu [Thu, 22 Aug 2013 04:22:01 +0000 (13:22 +0900)]
net: sh-eth: Change cache API of SH
The cache API of SH was changed from dcache_wback_range to flush_dcache_range.
sh-eth uses dcache_wback_range. This patch changes to flush_dcache_range.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Sascha Silbe [Sun, 11 Aug 2013 15:08:23 +0000 (17:08 +0200)]
NET: mvgbe: avoid unused variable warning when used without phylib support
Avoid a recently introduced unused variable warning for boards that
use mvgbe but not phylib.
Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
Patch: 266334
Stephan Bauroth [Thu, 8 Aug 2013 11:44:41 +0000 (13:44 +0200)]
net: trivial: Fix typos in mii field descriptions
Signed-off-by: Stephan Bauroth <stephan.bauroth@iav.de>
Patch: 265707
Shaohui Xie [Thu, 14 Nov 2013 11:00:31 +0000 (19:00 +0800)]
phy: introduce structure fixed-link
fixed-link is used in kernel for PHY-less MAC, so introduce this
structure that U-boot can use it to fixup dtb dynamically.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Shaohui Xie [Fri, 8 Nov 2013 02:46:44 +0000 (10:46 +0800)]
powerpc/p4080: enable support for PCIe SATA
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Thu, 8 Aug 2013 08:33:35 +0000 (16:33 +0800)]
phylib: update atheros ar803x phy
As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the
common driver. Currently AR8031_driver didn't work for AR8033,
hence updated it to have it work on AR8031/AR8033.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
rockly [Sat, 3 Aug 2013 10:09:05 +0000 (18:09 +0800)]
net: tftp: Make sure timeout will not effect wrap offset
When the block 0 store to the memory of client and timeout at this
moment. Because of no ACK packet, the server will send block 0 again,
if this client reconnect to the server at this time,
TftpBlockWrapOffset will become larger than it should be.
Signed-off-by: Rockly <rocklygnome@gmail.com>
Patch: 264417
Simon Glass [Thu, 7 Nov 2013 16:31:58 +0000 (09:31 -0700)]
sandbox: Make map_to_sysmem() use a constant pointer
Very often a constant pointer is passed to this function, so we should
declare this, since map_to_sysmem() does not change the pointer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 10 Nov 2013 17:26:54 +0000 (10:26 -0700)]
sandbox: Correct data sizes and printf() strings in fdtdec.c
There are a few wwrnings in this file when building for sandbox. Addresses
coming from the device tree need to be treated as ulong as elsewhere in
U-Boot and we must use map_sysmem() to convert to a pointer when needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
Simon Glass [Sun, 10 Nov 2013 17:26:53 +0000 (10:26 -0700)]
sandbox: config: Don't use 64-bit physical memory
Sandbox uses an emulated memory map which is quite small. We don't need the
CONFIG_PHYS_64BIT option since we can address memory with a 32-bit offset
into our ram_buf.
Adjust the phys_addr_t and phys_size_t types accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
Simon Glass [Sun, 10 Nov 2013 17:26:48 +0000 (10:26 -0700)]
sandbox: Use system headers first for sandbox's os.c
This file must be compiled with system headers, even if U-Boot has headers
of the same name. The existing solution for this is good enough for libfdt,
but fails when we have headers like stdint.h in U-Boot.
Use -idirafter instead of -I, and remove the -nostdinc and other things
that we don't want for this file. The best way to do this is to keep a
copy of the original flags, rather than trying to filter them later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 19 May 2013 23:45:35 +0000 (16:45 -0700)]
sandbox: Use uint64_t instead of u64 for time
The uint64_t type is defined in linux/types.h, so is safer than u64, which
is not actually a Linux type.
Change-Id: Ifc9a369e6543250c49117b8d3cb3a676eee43e04
Signed-off-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Thu, 10 Oct 2013 16:00:20 +0000 (10:00 -0600)]
buildman: make board selector argument a regex
A common use-case is to build all boards for a particular SoC. This can
be achieved by:
./tools/buildman/buildman -b mainline_dev tegra20
However, when the SoC is a member of a family of SoCs, and each SoC has
a different name, it would be even more useful to build all boards for
every SoC in that family. This currently isn't possible since buildman's
board selection command-line arguments are compared to board definitions
using pure string equality.
To enable this, compare using a regex match instead. This matches
MAKEALL's handling of command-line arguments. This enables:
(all Tegra)
./tools/buildman/buildman -b mainline_dev tegra
(all Tegra)
./tools/buildman/buildman -b mainline_dev '^tegra.*$'
(all Tegra20, Tegra30 boards, but not Tegra114)
./tools/buildman/buildman -b mainline_dev 'tegra[23]'
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Andreas Bießmann [Tue, 5 Nov 2013 09:37:09 +0000 (10:37 +0100)]
buildman: fix README
This is a trivial fix for c'n'p error.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Simon Glass <sjg@chromium.org>