Alyssa Rosenzweig [Mon, 13 Dec 2021 17:15:55 +0000 (12:15 -0500)]
pan/indirect_draw: Split out update_dcd
This is common between vertex/tiler jobs and needs to be duplicated for
IDVS jobs.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Mon, 13 Dec 2021 20:18:56 +0000 (15:18 -0500)]
pan/indirect_draw: Don't upload garbage UBO
There should never be a CPU pointer in GPU memory, let's say that...
Fixes:
2e6d94c198e ("panfrost: Add helpers to support indirect draws")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Rafael Antognolli [Tue, 9 Oct 2018 21:14:15 +0000 (14:14 -0700)]
intel: Emit 3DSTATE_BINDING_TABLE_POOL_ALLOC for XeHP
On XeHP+, Binding Table Pointers are an offset relative to the Surface
State Base Address anymore. Instead, they are relative to the State
Binding Table Pool Address, which is set by the command above.
We emit that command (pointing to the same address as the Surface
State Base Addresss), and everything should stay working as before.
Reworks:
* Jordan: Add iris
* Jordan: Drop i965
* Ken: Set MOCS to avoid a major perf impact. (Found by Felix DeGrood.)
* Jordan: Shrink size from 2MiB to actual iris, anv usage
* Lionel: Add BINDING_TABLE_POOL_BLOCK_SIZE
Ref: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4995
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
[jordan.l.justen@intel.com: Add Iris, adjust sizes]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13992>
Jordan Justen [Mon, 20 Dec 2021 06:22:26 +0000 (22:22 -0800)]
anv: Add BINDING_TABLE_POOL_BLOCK_SIZE
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13992>
Jordan Justen [Mon, 20 Dec 2021 05:31:08 +0000 (21:31 -0800)]
intel/genxml/12.5: Remove bt-pool enable from 3DSTATE_BINDING_TABLE_POOL_ALLOC
This was dropped in gfx12.5.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13992>
Alyssa Rosenzweig [Tue, 14 Dec 2021 19:27:47 +0000 (14:27 -0500)]
docs/macos: Update for recent Mesa changes
- Default c_std is now c11, no need to workaround
89b4f337d50 ("c_std=c11 in meson default_options")
- gallium-xlib has been renamed to xlib:
76791db0882 ("mesa/x11: Remove the swrast-classic-based fake libGL")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14216>
Jason Ekstrand [Fri, 10 Dec 2021 16:34:20 +0000 (10:34 -0600)]
vulkan/runtime: Validate instance version on 1.0 implementations
This isn't something that ANV or RADV have cared about in a long time
but, as people bring up new Vulkan drivers, shipping Vulkan 1.0 is still
a thing that happens in Mesa. The common code should also implement the
1.0 rules.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14150>
Jesse Natalie [Sat, 11 Dec 2021 18:49:21 +0000 (10:49 -0800)]
microsoft/compiler: Load synthesized sysvals via lowered io
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14175>
Jesse Natalie [Sat, 11 Dec 2021 17:57:36 +0000 (09:57 -0800)]
microsoft/compiler: Delete non-sysval deref load/store code
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14175>
Jesse Natalie [Sat, 11 Dec 2021 18:16:21 +0000 (10:16 -0800)]
microsoft/compiler: Lower io
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14175>
Jesse Natalie [Sat, 11 Dec 2021 17:42:03 +0000 (09:42 -0800)]
microsoft/compiler: Support lowered io (nir_intrinsic_load_input/store_output)
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14175>
Simon Ser [Tue, 17 Aug 2021 16:43:45 +0000 (18:43 +0200)]
renderonly: write down usage rules
The renderonly helpers are extremely easy to mis-use. Write down
the expectations.
I've seen *many* mistakes in the past, including:
- Forgetting to create the scanout resource on import [1] [2], causing
bugs such as [3].
- Assuming the scanout resource always exists [4].
- Returning a GEM handle valid for the driver's internal DRM FD, but
invalid for the caller's DRM FD [5].
- Not implementing resource_get_param, breaking stride/offset/modifier
queries when no scanout resource is available [6] [7].
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
[1]: https://gitlab.freedesktop.org/mesa/mesa/-/commit/
4aac98f8a68b4c6407a5f41a91bfd7763f0607d7
[2]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12018
[3]: https://github.com/swaywm/wlroots/issues/2795
[4]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12081
[5]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12074
[6]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12362
[7]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12370
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12418>
Dave Airlie [Fri, 10 Dec 2021 01:06:29 +0000 (11:06 +1000)]
mesa/st: move st strings handling into mesa
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14257>
Dave Airlie [Thu, 9 Dec 2021 19:03:04 +0000 (05:03 +1000)]
mesa/st: migrate barrier code into mesa
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14257>
Dave Airlie [Thu, 9 Dec 2021 06:55:18 +0000 (16:55 +1000)]
mesa/st: move msaa functionality into multisample.c
This moves some state track code into main
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14257>
Dave Airlie [Thu, 9 Dec 2021 06:52:46 +0000 (16:52 +1000)]
mesa/st: move get sample position code to static in mesa
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14257>
Dave Airlie [Wed, 15 Dec 2021 01:46:36 +0000 (11:46 +1000)]
mesa/compute: refactor compute launch to look more like draw
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14256>
Dave Airlie [Wed, 15 Dec 2021 00:51:31 +0000 (10:51 +1000)]
mesa/st: migrate compute dispatch to mesa
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14256>
Dave Airlie [Thu, 9 Dec 2021 00:56:49 +0000 (10:56 +1000)]
mesa/st: refactor compute dispatch to fill grid info earlier.
This fills the grid info earlier and uses info in validation
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14256>
Kostiantyn Lazukin [Thu, 16 Dec 2021 11:23:49 +0000 (13:23 +0200)]
util/ra: Fix numeric overflow during bitset allocation
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Kostiantyn Lazukin <kostiantyn.lazukin@globallogic.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5752
Fixes:
d4a4cd20d52 ("util/ra: use adjacency matrix for undirected graph")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14224>
Thomas H.P. Andersen [Thu, 16 Dec 2021 22:09:55 +0000 (23:09 +0100)]
meson: drop a temp formatting variable
This was only needed in meson < 0.50
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14240>
Thomas H.P. Andersen [Thu, 16 Dec 2021 22:06:37 +0000 (23:06 +0100)]
docs: update the required meson version
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14240>
Thomas H.P. Andersen [Thu, 16 Dec 2021 21:58:58 +0000 (22:58 +0100)]
meson: drop a comment relating to old meson version
This comment was related to an if/else on meson version that has
already been removed in
c1a290bdd57536d6afcff6a02f1512fba7328729
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14240>
Thomas H.P. Andersen [Thu, 16 Dec 2021 21:28:42 +0000 (22:28 +0100)]
meson: drop compatability with < 0.48
Before meson 0.48 the cpu_family() would return 'ppc64le' on little
endian power8. In newer versions it returns 'ppc64' and endianness
should be checked with endian()
We now require meson >= 0.53 so we can drop the compatability with
older versions.
The old behavior was added in
e430a034b9d2be626557931cd29808a3161889f1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14240>
Jason Ekstrand [Wed, 10 Nov 2021 04:55:49 +0000 (22:55 -0600)]
intel/fs: Add a NONE scheduling mode
While our LIFO scheduling mode attempts to optimize for register
pressure, it's often hard for a scheduling algorithm to do better than
the instruction order provided by the shader author. Shader authors
often do perfectly reasonable things like using texture results
immediately after fetching them or constructing texture coordinates
immediately before the texture op. When we throw all the instruction
ordering information away, we loose any help the author may have given
us. By attempting NONE before we fall back to the worst case LIFO mode.
And, yes, I tried this with NONE both before and after LIFO and doing
NONE before LIFO is substantially better, according to shader-db.
total instructions in shared programs:
19673152 ->
19665202 (-0.04%)
instructions in affected programs: 33669 -> 25719 (-23.61%)
helped: 20
HURT: 0
helped stats (abs) min: 15 max: 4609 x̄: 397.50 x̃: 107
helped stats (rel) min: 2.33% max: 67.50% x̄: 14.60% x̃: 9.12%
95% mean confidence interval for instructions value: -867.61 72.61
95% mean confidence interval for instructions %-change: -21.74% -7.46%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs:
935562500 ->
935020920 (-0.06%)
cycles in affected programs:
18620349 ->
18078769 (-2.91%)
helped: 104
HURT: 48
helped stats (abs) min: 88 max: 60986 x̄: 8031.48 x̃: 3680
helped stats (rel) min: 0.61% max: 51.44% x̄: 14.95% x̃: 8.87%
HURT stats (abs) min: 10 max: 54724 x̄: 6118.62 x̃: 1530
HURT stats (rel) min: 0.13% max: 46.45% x̄: 10.28% x̃: 6.46%
95% mean confidence interval for cycles value: -5724.34 -1401.71
95% mean confidence interval for cycles %-change: -9.86% -4.10%
Cycles are helped.
total spills in shared programs: 12158 -> 10327 (-15.06%)
spills in affected programs: 1831 -> 0
helped: 20
HURT: 0
total fills in shared programs: 14749 -> 12635 (-14.33%)
fills in affected programs: 2114 -> 0
helped: 20
HURT: 0
LOST: 8
GAINED: 649
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13734>
Jason Ekstrand [Wed, 10 Nov 2021 01:03:19 +0000 (19:03 -0600)]
intel/fs: Reset instruction order before re-scheduling
The way the current scheduler loop is implemented, each scheduling pass
starts with what the previous pass had. This means that, if PRE screwed
everything up majorly, PRE_NON_LIFO would have to try to fix it. It
also meant that tiny changes to one pass would affect every later pass.
Instead, reset the order of the instructions before each scheduling
pass. This makes the passes entirely independent of each other.
Shader-db results on Ice Lake:
total instructions in shared programs:
19670486 ->
19670648 (<.01%)
instructions in affected programs: 25317 -> 25479 (0.64%)
helped: 2
HURT: 7
helped stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4
helped stats (rel) min: 0.07% max: 0.07% x̄: 0.07% x̃: 0.07%
HURT stats (abs) min: 8 max: 70 x̄: 24.29 x̃: 12
HURT stats (rel) min: 0.41% max: 4.95% x̄: 1.47% x̃: 0.87%
95% mean confidence interval for instructions value: -1.28 37.28
95% mean confidence interval for instructions %-change: -0.04% 2.30%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs:
935535948 ->
935490243 (<.01%)
cycles in affected programs:
421994824 ->
421949119 (-0.01%)
helped: 1269
HURT: 879
helped stats (abs) min: 1 max: 12008 x̄: 259.38 x̃: 52
helped stats (rel) min: <.01% max: 28.02% x̄: 1.12% x̃: 0.14%
HURT stats (abs) min: 1 max: 29931 x̄: 322.46 x̃: 20
HURT stats (rel) min: <.01% max: 32.17% x̄: 1.74% x̃: 0.22%
95% mean confidence interval for cycles value: -71.37 28.81
95% mean confidence interval for cycles %-change: -0.11% 0.21%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 12403 -> 12430 (0.22%)
spills in affected programs: 1355 -> 1382 (1.99%)
helped: 2
HURT: 7
total fills in shared programs: 15128 -> 15182 (0.36%)
fills in affected programs: 3294 -> 3348 (1.64%)
helped: 2
HURT: 7
LOST: 21
GAINED: 28
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13734>
Jason Ekstrand [Wed, 10 Nov 2021 02:17:42 +0000 (20:17 -0600)]
Revert "intel/fs: Do cmod prop again after scheduling"
This reverts commit
ba2fa1ceaf4ccb905e1d841b45f88505449db44e. Doing
optimizations after scheduling but before RA means doing them in the
middle of the scheduling loop which introduces additional dependencies
between one scheduling iteration and the next. That won't work if we
want to make the scheduling modes independent, at least not unless we
have some way of fully cloning the IR.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13734>
Jason Ekstrand [Tue, 9 Nov 2021 22:09:23 +0000 (16:09 -0600)]
intel/eu: Don't double-loop as often in brw_set_uip_jip
brw_find_next_block_end() scans through the instructions to find the end
of the block. We were calling it for every instruction in the program
which is, if you have a single basic block, makes the whole mess a nice
clean O(n^2) when it really doesn't need to be. Instead, only call
brw_find_next_block_end() as-needed. This brings it back to O(n) like
it should have been.
This cuts the runtime of the following Vulkan CTS on my SKL box by 5%
from 1:51 to 1:45: dEQP-VK.ssbo.phys.layout.random.16bit.scalar.13
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13734>
Jason Ekstrand [Tue, 9 Nov 2021 20:38:48 +0000 (14:38 -0600)]
intel/fs: Use OPT() for split_virtual_grfs
Now that we're being conservative in the pass, it's easy to tell when it
makes progress and we can put it in the OPT() macro. This way, we get
nice INTEL_DEBUG=optimizer dumps for it. While we're here, fix the
header comment which is massively out-of-date.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13734>
Jason Ekstrand [Tue, 9 Nov 2021 20:37:57 +0000 (14:37 -0600)]
intel/fs: Be more conservative in split_virtual_grfs
Instead of modifying every single instruction, keep track of which VGRFs
are actually split in a bit-set, and only modify the instructions that
actually touch split regs.
This cuts the runtime of the following Vulkan CTS on my SKL box by 45%
from 3:21 to 1:51: dEQP-VK.ssbo.phys.layout.random.16bit.scalar.13
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13734>
Caio Oliveira [Wed, 15 Sep 2021 20:20:53 +0000 (13:20 -0700)]
spirv: Use the incorporated names
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14209>
Caio Oliveira [Mon, 20 Sep 2021 18:10:10 +0000 (11:10 -0700)]
spirv: Identify non-temporal image operand added in SPIR-V 1.6
Map it to the existing ACCESS_STREAM_CACHE_POLICY access mode.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14209>
Caio Oliveira [Wed, 15 Sep 2021 22:38:23 +0000 (15:38 -0700)]
nir: Handle volatile semantics for loading HelperInvocation builtin
SPV_EXT_demote_to_helper_invocation added OpDemoteToHelperInvocation
operation to turn an invocation into a helper invocation, but the
value of HelperInvocation (a builtin from Input storage class)
couldn't be modified dynamically without breaking compatibility.
For the extension the operation OpIsHelperInvocation was added to get
the dynamic value.
For SPIR-V 1.6, the demote operation was promoted, but now to get the
dynamic value the shader must issue a load to HelperInvocation with
Volatile memory access semantics.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14209>
Caio Oliveira [Wed, 25 Aug 2021 19:25:58 +0000 (12:25 -0700)]
spirv: Update headers and metadata to SPIR-V 1.6, revision 1
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14209>
Eric Engestrom [Fri, 17 Dec 2021 22:32:41 +0000 (22:32 +0000)]
docs: update calendar and link releases notes for 21.3.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14250>
Eric Engestrom [Fri, 17 Dec 2021 22:31:13 +0000 (22:31 +0000)]
docs: add release notes for 21.3.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14250>
Caio Oliveira [Fri, 17 Dec 2021 19:20:10 +0000 (11:20 -0800)]
ci/windows: Remove line numbers of SPIR-V errors in spirv2dxil tests
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14245>
Rhys Perry [Tue, 14 Dec 2021 19:51:50 +0000 (19:51 +0000)]
aco: remove SMEM constant/addition combining out of the loop
There's no reason for this optimization to be in this loop.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13755>
Rhys Perry [Thu, 11 Nov 2021 10:54:56 +0000 (10:54 +0000)]
aco: skip &-4 before SMEM
The hardware ignores the low 2 bits. I'm not sure if they are ignored
before or after the address is calculated, but this optimization should be
cautious enough.
fossil-db (Sienna Cichlid):
Totals from 259 (0.19% of 134572) affected shaders:
SpillSGPRs: 1381 -> 1382 (+0.07%)
SpillVGPRs: 1783 -> 1782 (-0.06%); split: -0.67%, +0.62%
CodeSize: 1598612 -> 1596084 (-0.16%); split: -0.30%, +0.14%
Scratch: 180224 -> 179200 (-0.57%); split: -1.14%, +0.57%
Instrs: 284885 -> 284268 (-0.22%); split: -0.34%, +0.12%
Latency: 6585634 -> 6603388 (+0.27%); split: -0.48%, +0.75%
InvThroughput: 2638983 -> 2648474 (+0.36%); split: -0.58%, +0.94%
VClause: 6797 -> 6820 (+0.34%); split: -0.15%, +0.49%
SClause: 6569 -> 6574 (+0.08%); split: -1.11%, +1.19%
Copies: 50561 -> 50586 (+0.05%); split: -0.61%, +0.66%
Branches: 10058 -> 10062 (+0.04%); split: -0.01%, +0.05%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13755>
Rhys Perry [Tue, 30 Nov 2021 15:45:12 +0000 (15:45 +0000)]
aco: disallow SMEM offsets that are not multiples of 4
These can't be encoded on GFX6/7, and combining these additions causes
CTS failures on GFX10.3.
I think the low 2 MSBs are ignored before the addition, not after, so
load(a + 3, 0) becomes load(a, 3), which is the same as load(a, 0).
No fossil-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13755>
Bas Nieuwenhuizen [Tue, 9 Nov 2021 23:53:14 +0000 (00:53 +0100)]
radv: Add safety check for RGP traces on VanGogh.
To avoid accidental hangs.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5260
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13730>
Emma Anholt [Thu, 16 Dec 2021 20:26:53 +0000 (12:26 -0800)]
crocus: Clamp VS point sizes to the HW limits as required.
Fixes piglit vs-point-size-zero.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14238>
Emma Anholt [Tue, 23 Nov 2021 19:25:41 +0000 (11:25 -0800)]
ci/crocus: Add support for manual CI runs on my G41.
Uses a shared runner at my house so we have an easy way to minimally test
crocus.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14238>
Rhys Perry [Thu, 2 Dec 2021 10:34:44 +0000 (10:34 +0000)]
nir/opt_access: infer CAN_REORDER for global access
fossil-db (Sienna Cichlid):
Totals from 352 (0.26% of 134621) affected shaders:
VGPRs: 17240 -> 17272 (+0.19%)
CodeSize: 1753640 -> 1755744 (+0.12%); split: -0.04%, +0.16%
Instrs: 323190 -> 323801 (+0.19%); split: -0.03%, +0.22%
Latency: 3241205 -> 3241293 (+0.00%); split: -0.10%, +0.10%
InvThroughput: 568927 -> 568067 (-0.15%); split: -0.16%, +0.00%
SClause: 12109 -> 10444 (-13.75%); split: -13.76%, +0.01%
Copies: 27802 -> 27717 (-0.31%); split: -0.56%, +0.26%
PreSGPRs: 14699 -> 14690 (-0.06%)
PreVGPRs: 15793 -> 15799 (+0.04%)
fossil-db (Polaris10):
Totals from 348 (0.26% of 135668) affected shaders:
SGPRs: 21446 -> 21574 (+0.60%); split: -0.15%, +0.75%
VGPRs: 17004 -> 16996 (-0.05%); split: -0.09%, +0.05%
CodeSize: 1782796 -> 1783060 (+0.01%); split: -0.03%, +0.05%
Instrs: 337828 -> 337921 (+0.03%); split: -0.03%, +0.06%
Latency: 3726328 -> 3726721 (+0.01%); split: -0.09%, +0.10%
InvThroughput: 1307917 -> 1299841 (-0.62%); split: -0.62%, +0.00%
VClause: 4327 -> 4337 (+0.23%); split: -0.09%, +0.32%
SClause: 12178 -> 10529 (-13.54%); split: -13.55%, +0.01%
Copies: 40227 -> 40244 (+0.04%); split: -0.19%, +0.24%
PreSGPRs: 14946 -> 14937 (-0.06%)
PreVGPRs: 15637 -> 15643 (+0.04%)
fossil-db (Pitcairn):
Totals from 351 (0.26% of 135668) affected shaders:
SGPRs: 20382 -> 20619 (+1.16%); split: -0.79%, +1.95%
CodeSize: 1789732 -> 1789836 (+0.01%); split: -0.04%, +0.04%
MaxWaves: 1947 -> 1949 (+0.10%)
Instrs: 352274 -> 352318 (+0.01%); split: -0.04%, +0.06%
Latency: 4057829 -> 4058226 (+0.01%); split: -0.08%, +0.09%
InvThroughput: 1332245 -> 1317578 (-1.10%); split: -1.11%, +0.01%
VClause: 8581 -> 8583 (+0.02%); split: -0.13%, +0.15%
SClause: 12187 -> 10552 (-13.42%); split: -13.43%, +0.02%
Copies: 44906 -> 44915 (+0.02%); split: -0.24%, +0.26%
PreSGPRs: 16571 -> 16562 (-0.05%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14227>
Rhys Perry [Tue, 9 Mar 2021 16:51:25 +0000 (16:51 +0000)]
nir/algebraic: optimize more 64-bit imul with constant source
Two 64-bit shifts and an addition are usually faster than the several
multiplications nir_lower_int64 creates.
No fossil-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14227>
Rhys Perry [Tue, 9 Mar 2021 16:11:12 +0000 (16:11 +0000)]
nir/opt_load_store_vectorize: improve ssbo/global alias analysis
If either the global access or the ssbo access is restrict, they shouldn't
alias.
No fossil-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14227>
Samuel Pitoiset [Mon, 13 Dec 2021 09:21:38 +0000 (10:21 +0100)]
radv: fix dynamic rendering global scissor
Make sure to clamp the global scissor to the render area.
This fixes dEQP-VK.draw.dynamic_rendering.*oversized.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14170>
Jason Ekstrand [Tue, 14 Dec 2021 18:17:53 +0000 (12:17 -0600)]
anv/pipeline: Get rid of sample_shading_enable
Putting it in the pipeline is a bit of a lie. We no longer need it for
nir_lower_wpos_center. The only other user is pipeline_has_coarse_pixel
and that is used to build the shader key which we construct before we've
processed any NIR so we don't have accurate information at that time
anyway. Instead, look at ms_info->sampleShadingEnable directly in
pipeline_has_coarse_pixel and trust the back-end to deal with disabling
coarse when we need per-sample dispatch.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
Jason Ekstrand [Thu, 2 Dec 2021 20:41:41 +0000 (14:41 -0600)]
anv,nir: Use sample_pos_or_center in lower_wpos_center
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
Jason Ekstrand [Thu, 2 Dec 2021 20:16:02 +0000 (14:16 -0600)]
intel/fs: Implement the sample_pos_or_center system value
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
Jason Ekstrand [Thu, 2 Dec 2021 20:25:12 +0000 (14:25 -0600)]
intel/fs: Rework emit_samplepos_setup()
This rolls compute_sample_position into emit_samplepos_setup, its only
caller, by using a loop instead of calling it twice. We also
early-return for the !persample_dispatch case instead of doing it as
part of the sample calculation. This means that we don't call
fetch_payload_reg() to get sample_pos_reg unless we're actually going to
use it so the function is safe to call even if we haven't set up
sample_pos_reg. This will be important for the next commit.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
Jason Ekstrand [Mon, 22 Nov 2021 19:42:59 +0000 (13:42 -0600)]
intel/fs: Return fs_reg directly from builtin setup helpers
There's no good reason why we're allocating them on the heap and
returning a pointer. Return the fs_reg directly.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
Jason Ekstrand [Thu, 2 Dec 2021 20:11:21 +0000 (14:11 -0600)]
nir: Add a new sample_pos_or_center system value
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
Jason Ekstrand [Fri, 17 Dec 2021 05:20:31 +0000 (23:20 -0600)]
radeonsi/nir: Check for VARYING_SLOT_PRIMITIVE_ID not SYSTEM_VALUE
This function is called on load/store_input/output. It makes no sense
for it to get a SYSTEM_VALUE enum. This only doesn't explode because
SYSTEM_VALUE_PRIMITIVE_ID happens to be below VARYING_SLOT_VAR0 so it
doesn't interact with any actual varyings. The next commit is going to
add another system value which will push SYSTEM_VALUE_PRIMITIVE_ID up by
one so it will equal VARYING_SLOT_VAR0 and then the first FS input will
always get smashed to flat which isn't what we want.
Fixes:
b59bb9c07ae4 ("radeonsi: force flat for PrimID early in si_nir_scan_shader")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14198>
Pierre-Eric Pelloux-Prayer [Thu, 16 Dec 2021 11:09:16 +0000 (12:09 +0100)]
glthread: only log glthread destroy reason when it's not NULL
Fixes:
670759a208d ("glthread: inline _mesa_glthread_restore_dispatch and merge disable & destroy")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14226>
Pierre-Eric Pelloux-Prayer [Thu, 16 Dec 2021 11:06:52 +0000 (12:06 +0100)]
radeonsi: don't use perp. end caps when line smoothing is on
The line smoothing algorithm causes the diagonal line to be visible.
See: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13700#note_1187405
Fixes:
45717780082 ("radeonsi: set PERPENDICULAR_ENDCAP_ENA for wide AA lines")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14226>
Rhys Perry [Thu, 16 Dec 2021 15:47:53 +0000 (15:47 +0000)]
aco: fix check_vop3_operands() for f16vec2 ffma fneg combine
For v_pk_fma_f16, we should consider all three operands, not the first
two.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes:
15a375b4c86 ("radv,aco: don't lower some ffma instructions")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14229>
Marcin Ślusarz [Fri, 19 Nov 2021 14:47:56 +0000 (15:47 +0100)]
nir/print: print const value near each use of const ssa variable
Without/with NIR_DEBUG=print,print_const:
-vec4 32 ssa_60 = fadd ssa_59, ssa_58
+vec4 32 ssa_60 = fadd ssa_59 /*(0xbf800000, 0x3e800000, 0x00000000, 0x3f800000) = (-1.000000, 0.250000, 0.000000, 1.000000)*/, ssa_58
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13880>
Marcin Ślusarz [Fri, 19 Nov 2021 14:35:37 +0000 (15:35 +0100)]
nir/print: group hex and float vectors together
Vectors are much easier to follow in this format, because developer cares
either about hex or float values, never both.
Before/after:
-vec4 32 ssa_222 = load_const (0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */, 0x3f800000 /* 1.000000 */, 0x3f800000 /* 1.000000 */)
+vec4 32 ssa_222 = load_const (0x00000000, 0x00000000, 0x3f800000, 0x3f800000) = (0.000000, 0.000000, 1.000000, 1.000000)
-vec1 32 ssa_174 = load_const (0xbf800000 /* -1.000000 */)
+vec1 32 ssa_174 = load_const (0xbf800000 = -1.000000)
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13880>
Marcin Ślusarz [Fri, 19 Nov 2021 14:28:49 +0000 (15:28 +0100)]
nir/print: move print_load_const_instr up
... to avoid forward declarations in future commit
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13880>
Juan A. Suarez Romero [Tue, 30 Nov 2021 09:03:29 +0000 (10:03 +0100)]
broadcom/ci: restructure expected results
Sort/rename the files so expected tests are classified by device.
No need to split the tests by driver (e.g., V3D vs V3DV).
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13983>
Bas Nieuwenhuizen [Thu, 16 Dec 2021 00:01:27 +0000 (01:01 +0100)]
radv/amdgpu: Only wait on queue_syncobj when needed.
If signalled on the same queue it is totally useless, so only wait
if we have a syncobj that is explicitly being waited on, which can
be from potentially another queue/ctx. (Ideally we'd check but there
is no way to do so currently. Might revisit when we integrate the
common sync framework)
Fixes:
7675d066caa ("radv/amdgpu: Add support for submitting 0 commandbuffers.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14214>
Jason Ekstrand [Thu, 16 Dec 2021 20:27:50 +0000 (14:27 -0600)]
anv: Drop anv_sync_create_for_bo
The older helper is unused so we can roll it all into
anv_create_sync_for_memory.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14237>
Lionel Landwerlin [Wed, 15 Dec 2021 09:52:44 +0000 (11:52 +0200)]
anv,wsi: simplify WSI synchronization
Rather than using 2 vfuncs, use one since we've unified the
synchronization framework in the runtime with a single vk_sync object.
v2 (Jason Ekstrand):
- create_sync_for_memory is now in vk_device
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14237>
Jason Ekstrand [Thu, 16 Dec 2021 20:14:19 +0000 (14:14 -0600)]
anv: Implement vk_device::create_sync_for_memory
Fixes:
36ea90a3619f ("anv: Convert to the common sync and submit framework")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14237>
Jason Ekstrand [Thu, 16 Dec 2021 16:29:03 +0000 (10:29 -0600)]
vulkan/queue: Handle WSI memory signal information
We handle it by asking the driver to create a vk_sync that wraps a
VkDeviceMemory object and gets passed as one of the signal ops.
Fixes:
9bffd81f1cb7 ("vulkan: Add common implementations of vkQueueSubmit and vkQueueWaitIdle")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14237>
Lionel Landwerlin [Wed, 15 Dec 2021 09:08:17 +0000 (11:08 +0200)]
vulkan: fix missing handling of WSI memory signal
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
b996fa8efaa4 ("anv: implement VK_KHR_synchronization2")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5744
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14237>
Ian Romanick [Thu, 16 Dec 2021 01:53:04 +0000 (17:53 -0800)]
intel/stub: Implement shell versions of DRM_I915_GEM_GET_TILING and DRM_I915_SEM_GET_TILING
This is necessary to use intel_stub_gpu with Crocus.
v2: Remove unused i915_bo::swizzle_mode. Noticed by Emma.
Fixes:
953a4ca6fec ("intel: Add has_bit6_swizzle to devinfo")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14218>
Ian Romanick [Thu, 9 Dec 2021 20:06:39 +0000 (12:06 -0800)]
intel/stub: Silence "initialized field overwritten" warning
src/intel/tools/intel_noop_drm_shim.c:459:36: warning: initialized field overwritten [-Woverride-init]
459 | [DRM_I915_GEM_EXECBUFFER2_WR] = i915_ioctl_noop,
| ^~~~~~~~~~~~~~~
Fixes:
0f4f1d70bfe ("intel: add stub_gpu tool")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14218>
Emma Anholt [Thu, 16 Dec 2021 22:14:09 +0000 (14:14 -0800)]
ci/freedreno: Add known flakes from the last month.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14239>
Adam Jackson [Wed, 16 Jun 2021 18:01:04 +0000 (14:01 -0400)]
glx: Fix GLX_NV_float_buffer fbconfig handling
Since we didn't record this attribute from the server, we wouldn't
account for it in glXChooseFBConfig, and glXGetFBConfigAttrib wouldn't
know about it.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14221>
Chia-I Wu [Mon, 17 May 2021 17:25:52 +0000 (10:25 -0700)]
venus: add some trace points
Add trace points for
- vn_AcquireNextImage2KHR and vn_QueuePresentKHR
- vn_AcquireImageANDROID and vn_QueueSignalReleaseImageANDROID
- vn_BeginCommandBuffer and vn_EndCommandBuffer
- vn_*Wait*
- vn_Queue*
- vn_instance_wait_roundtrip
- shmem allocations and cache miss/skip
v2: fix cache miss/skip trace points (Ryan)
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org> (v1)
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14215>
Michel Zou [Thu, 25 Nov 2021 20:51:07 +0000 (21:51 +0100)]
meson: correctly detect linker arguments
Fixes:
22673a98 ("meson: Check arguments before adding")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13961>
Emma Anholt [Wed, 8 Dec 2021 20:30:20 +0000 (12:30 -0800)]
r300: Remove unused RC_OPCODE_DPH
Nothing generates it in the backend.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
Emma Anholt [Wed, 8 Dec 2021 20:28:43 +0000 (12:28 -0800)]
r300: Remove unused RC_OPCODE_SFL
Nothing generates it in the backend.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
Emma Anholt [Wed, 8 Dec 2021 20:24:13 +0000 (12:24 -0800)]
r300: Remove unused RC_OPCODE_CLAMP.
Nothing generates it in the backend.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
Emma Anholt [Wed, 8 Dec 2021 20:21:11 +0000 (12:21 -0800)]
r300: Remove unused RC_OPCODE_SWZ.
Nothing generates it in the backend.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
Emma Anholt [Wed, 8 Dec 2021 20:19:56 +0000 (12:19 -0800)]
r300: Remove unused RC_OPCODE_XPD.
Nothing generates it in the backend.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
Emma Anholt [Wed, 8 Dec 2021 20:17:43 +0000 (12:17 -0800)]
r300: Remove unused RC_OPCODE_ABS.
Nothing generates it in the backend.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
Emma Anholt [Wed, 8 Dec 2021 19:51:30 +0000 (11:51 -0800)]
r300: Remove support for SCS.
Nothing generates this meta-op in the backend, so we don't need it.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
Emma Anholt [Wed, 8 Dec 2021 19:45:22 +0000 (11:45 -0800)]
r300: Remove some dead compiler code.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
Marcin Ślusarz [Tue, 19 Oct 2021 09:27:40 +0000 (11:27 +0200)]
nir/print: compact printing of intrinsic indices
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14222>
Marcin Ślusarz [Mon, 18 Oct 2021 13:40:13 +0000 (15:40 +0200)]
nir/print: expand printing of io semantics.gs_streams
gs_streams can be set for at least 2 other intrinsics.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14222>
Marcin Ślusarz [Mon, 18 Oct 2021 13:29:23 +0000 (15:29 +0200)]
nir/print: simplify printing of IO semantics
Some of the tested flags are set for other intrinsics and they are
printed only when set, so there's no point in checking exact intrinsic
name or shader stage.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14222>
Kenneth Graunke [Thu, 4 Jun 2020 01:06:45 +0000 (18:06 -0700)]
intel/compiler: Use uppercase enum values in brw_ir_performance.cpp
This is by far the more common style in Mesa. It also gives a cue that
e.g. num_dependency_ids is a fixed definition rather than some kind of
local variable maintaining a count.
While hre, we also rename the enums to have full prefixes to prepare for
a future where we use them in multiple files for future backend work.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14182>
Kenneth Graunke [Tue, 14 Dec 2021 00:52:57 +0000 (16:52 -0800)]
intel/vec4: Inline emit_texture and move helpers to brw_vec4_nir.cpp
emit_texture() only has one caller, nir_emit_texture(). We may as well
inline that. Move the associated helper functions for emitting sampler
messages there as well, to keep associated code nearby.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5183
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14191>
Kenneth Graunke [Tue, 14 Dec 2021 00:46:23 +0000 (16:46 -0800)]
intel/vec4: Use nir_texop in emit_texture instead of translating
We eliminated the GLSL IR -> vec4 backend ages ago, so the only caller
uses a nir_texop enum. Drop a layer of translating.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14191>
Kenneth Graunke [Tue, 14 Dec 2021 00:35:46 +0000 (16:35 -0800)]
intel/vec4: Use ir_texture_opcode less in emit_texture()
This replaces a bunch of uses of the GLSL IR ir_texture_opcode enum with
the backend opcode, in preparation for removing it altogether.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14191>
Samuel Pitoiset [Mon, 13 Dec 2021 10:13:40 +0000 (11:13 +0100)]
radv,aco: do not disable anisotropy filtering for non-mipmap images
This fixes
dEQP-VK.texture.filtering_anisotropy.single_level.anisotropy_*.mag_linear_min_linear.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14171>
Samuel Pitoiset [Mon, 13 Dec 2021 16:39:01 +0000 (17:39 +0100)]
ac/nir: add an option to disable anisotropic filtering for single level images
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14171>
Pierre-Eric Pelloux-Prayer [Mon, 13 Dec 2021 14:07:13 +0000 (15:07 +0100)]
glx: fix querying GLX_FBCONFIG_ID for Window
This commit fixes apps using the following sequence:
1. XCreateWindow(dpy) -> win
2. glXCreateContextAttribsARB(dpy, ...) -> ctx
3. glXMakeCurrent(dpy, win, ctx)
4. glXQueryDrawable(dpy, win, GLX_FBCONFIG_ID, ...)
glXQueryDrawable returned 0 (while correctly returning a valid
GLXFCONFIG_ID for other types of drawables).
This commit adds the same dance as driInferDrawableConfig to get
the GLX visual from the Window, and then the GLXFBCONFIG_ID of
this visual.
This fixes:
* piglit: glx-query-drawable --attr=GLX_FBCONFIG_ID --type=WINDOW
* Maya which uses the config ID from step 4 as an input to
glXChooseFBConfig.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14174>
Adam Jackson [Thu, 9 Dec 2021 20:53:27 +0000 (15:53 -0500)]
dri: Remove unused driGetRendererString
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14199>
Adam Jackson [Thu, 9 Dec 2021 20:52:07 +0000 (15:52 -0500)]
dri: Remove unused driUpdateFramebufferSize
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14199>
Adam Jackson [Thu, 9 Dec 2021 20:51:30 +0000 (15:51 -0500)]
dri: Remove unused driContextSetFlags
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14199>
Adam Jackson [Thu, 9 Dec 2021 20:20:58 +0000 (15:20 -0500)]
mesa: Remove unused _mesa_initialize_visual
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14199>
Sagar Ghuge [Fri, 10 Sep 2021 22:17:54 +0000 (15:17 -0700)]
anv, iris: Implement Wa_14014890652 for DG2
Workaround is to set:
3DSTATE_VFG::GranularityThresholdDisable = 1
3DSTATE_VFG::DistributionGranularity = BATCH
3DSTATE_VF::GeometryDistributionEnable = 1
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14212>
Anuj Phogat [Wed, 12 May 2021 17:42:41 +0000 (10:42 -0700)]
anv, iris: Add Wa_22011440098 for DG2
Rework:
* Jordan: Set MOCS after
7b78b2fcac6 ("intel/genxml: Assert that all MOCS fields are non-zero on Gfx7+")
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14212>
Anuj Phogat [Tue, 4 May 2021 00:39:28 +0000 (17:39 -0700)]
anv, iris: Add Wa_16011773973 for DG2
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14212>
Caio Oliveira [Wed, 15 Dec 2021 09:31:53 +0000 (01:31 -0800)]
Revert "nir: disable a NIR test due to undebuggable & locally unreproducible CI failures"
This reverts commit
6eb3fe2d4fa2c42d7ee1e20b390b3117a8980eaf. The root cause was
a bug in Meson when using the new gtest protocol and a test failed before producing
the XML file expected by it. This was fixed in later versions of Meson, so
we've bumped the required meson version to use that feature. The failure should
now be properly identified, so re-enabling the NIR test.
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14204>
Caio Oliveira [Wed, 15 Dec 2021 09:30:36 +0000 (01:30 -0800)]
meson: Bump version required for gtest protocol
The feature was added in 0.55 but there was a bug when tests
crashed (and no XML file was generated) that was only fixed in 0.59.2.
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14204>