Uros Bizjak [Sun, 1 Mar 2020 17:27:13 +0000 (18:27 +0100)]
doc: Update features.txt for r600 with misc supported features
Update features.txt with misc supported features for r600,
as reported by glxinfo for Cypress XT [Radeon HD 5870].
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4010>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4010>
Lionel Landwerlin [Fri, 28 Feb 2020 08:46:53 +0000 (10:46 +0200)]
intel/tools/dump_gpu: fix getparam values
Don't return the pci_id for all params
Fixes:
76bf38eaf0b6 ("intel/tools/aub_dump: move aub file initialization to maybe_init()")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3994>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3994>
Vinson Lee [Fri, 28 Feb 2020 05:01:55 +0000 (21:01 -0800)]
meson: Enable -Wno-deprecated only for bison > 2.3.
Older versions of bison do not support the -W option.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2571
Fixes:
11a1cb2fa8da ("meson: Disable bison's -Wdeprecated since we still support old bison.")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3993>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3993>
Ilia Mirkin [Sun, 1 Mar 2020 03:08:14 +0000 (22:08 -0500)]
mesa: fix _mesa_draw_nonzero_divisor_bits to return nonzero divisors
The bitmask is _EffEnabledNonZeroDivisor, so no need to invert it before
returning.
Fixes:
fd6636ebc06d (st/mesa: simplify determination whether a draw needs min/max index)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4009>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4009>
Ilia Mirkin [Sun, 1 Mar 2020 20:29:32 +0000 (15:29 -0500)]
gitlab-ci: disable panfrost runners
They seem to be timing out.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4011>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4011>
Samuel Pitoiset [Fri, 28 Feb 2020 14:37:34 +0000 (15:37 +0100)]
radv: fix size of sqtt_file_chunk_asic_info on 32-bit system
The struct is actually 716 bytes, but on 64-bit systems the compiler
aligns it to 720. Add padding to make sure it's always 720.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2580
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2578
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3996>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3996>
Samuel Pitoiset [Fri, 28 Feb 2020 13:23:16 +0000 (14:23 +0100)]
radv: fix 32-bit build failure in radv_queue_internal_submit()
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2580
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2578
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3996>
Timothy Arceri [Mon, 17 Feb 2020 00:01:50 +0000 (11:01 +1100)]
glsl: add some error checks to the nir uniform linker
These are optional for spirv but it shouldnt hurt to enable them.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
Timothy Arceri [Fri, 28 Feb 2020 01:13:55 +0000 (12:13 +1100)]
glsl: fix sampler index calculation in nir linker
Here we reset the counter to 0 for each shader stage not each program.
We also make add a flag to stop iterating over indices that have
already been processed.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
Timothy Arceri [Sun, 9 Feb 2020 22:19:44 +0000 (09:19 +1100)]
glsl: reset next_image_index count for each shader stage
This fixes the image index calculation in the nir linker. We need
to reset the counter to 0 for each shader stage not each program.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
Timothy Arceri [Thu, 6 Feb 2020 01:49:10 +0000 (12:49 +1100)]
glsl: fix resizing of the uniform remap table
In the NIR linker we were not resizing the remap table correctly
for explicit locations when it was needed.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
Timothy Arceri [Thu, 27 Feb 2020 22:53:51 +0000 (09:53 +1100)]
glsl: set the correct number of images in a shader
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
Timothy Arceri [Thu, 20 Feb 2020 22:34:26 +0000 (09:34 +1100)]
glsl: set the correct number of samplers in a shader
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
Timothy Arceri [Wed, 26 Feb 2020 02:21:20 +0000 (13:21 +1100)]
glsl: fix possible memory leak in nir uniform linker
Use UniformDataSlots for the context of UniformDataDefaults rather
than UniformStorage as in some cause UniformStorage may be NULL.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3992>
Jordan Justen [Thu, 24 Oct 2019 18:55:23 +0000 (11:55 -0700)]
intel/compiler: Restrict cs_threads to 64
Our current GPGPU_WALKER code only supports up to 64 threads.
On HSW we could use up to 70 and TGL up to 112, but only if the walker
is adjusted so the width does not exceed 64. Work to support this is
in progress.
Previous to this change, we might try to downgrade to SIMD8 if the
SIMD16 shader spilled. Since HSW and TGL have the max number of
threads above 64, we would then try to emit an invalid GPGPU walker
command.
Fixes:
932045061b5 ("i965/cs: Emit compute shader code and upload programs")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Thong Thai [Fri, 28 Feb 2020 15:15:17 +0000 (10:15 -0500)]
st/va: remove unneeded code
No need to explicitly set the 10-bit buffer format as the correct
buffer format will be allocated later
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3998>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3998>
Rob Clark [Fri, 28 Feb 2020 00:13:01 +0000 (16:13 -0800)]
freedreno/ir3: add assert
Catch problems earlier when inputs are not setup correctly.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Wed, 26 Feb 2020 16:21:32 +0000 (08:21 -0800)]
freedreno/ir3: fix assert with getinfo
Fixes:
dEQP-VK.glsl.texture_functions.query.texturesamples.sampler2dms_fixed_vertex
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Wed, 26 Feb 2020 01:17:55 +0000 (17:17 -0800)]
freedreno/ir3: don't precolor unassigned inputs
Fixes crash seen in:
dEQP-VK.glsl.conversions.matrix_to_matrix.mat4_to_mat3x4_vertex
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Wed, 26 Feb 2020 00:37:26 +0000 (16:37 -0800)]
freedreno/ir3: fix crash with samgq workaround
Need to list_delinit() before we clone the instruction to split it into
individual samgpN instructions, otherwise we get list corruption.
Tested-by: Eduardo Lima Mitev <elima@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Tue, 25 Feb 2020 18:44:26 +0000 (10:44 -0800)]
freedreno/ir3: update SFU delay
1) emperically, 10 seems like a more accurate # than 4
2) push "soft" delay handling into ir3_delayslots(), as
we should also be using it to calculate the costs
that the schedulers use
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Mon, 24 Feb 2020 22:46:04 +0000 (14:46 -0800)]
freedreno/ir3: track half-precision live values
In schedule live value tracking, differentiate between half vs full
precision. Half-precision live values are less costly than full
precision.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Mon, 24 Feb 2020 22:16:15 +0000 (14:16 -0800)]
freedreno/ir3: don't hide latency when there is none to hide
Current scheduler thresholds try to ensure there are warps available to
switch to when hiding texture fetch latency. But if there is none to
hide, we should allow scheduler to use more registers to reduce nops.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Mon, 24 Feb 2020 19:57:52 +0000 (11:57 -0800)]
freedreno/ir3: rewrite regmask to better support a6xx+
To avoid spurious sync flags, we want to, for a6xx+, operate in terms of
half-regs, with a full precision register testing the corresponding two
half-regs that it conflicts with.
And while we are at it, stop open-coding BITSET
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Mon, 24 Feb 2020 19:55:29 +0000 (11:55 -0800)]
freedreno/ir3: remove regmask_set_if_not()
No longer used.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Fri, 21 Feb 2020 21:10:09 +0000 (13:10 -0800)]
freedreno: honor FD_MESA_DEBUG=nogrow
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Fri, 21 Feb 2020 16:42:12 +0000 (08:42 -0800)]
freedreno/a6xx: enable SKIP_IB2_ENABLE properly
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Fri, 21 Feb 2020 16:30:59 +0000 (08:30 -0800)]
freedreno/a6xx: don't emit YIELD packet
We don't implement the rest of this.. and it would probably cause bad
things when kernel gains support for preemption.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Fri, 21 Feb 2020 16:30:47 +0000 (08:30 -0800)]
freedreno/a6xx: whitespace fix
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Sat, 1 Feb 2020 21:57:12 +0000 (13:57 -0800)]
freedreno/a6xx: emit LRZ clear in sysmem too
Fixes rendering issues in manhattan with FD_MESA_DEBUG=nogmem
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Mon, 24 Feb 2020 16:18:25 +0000 (08:18 -0800)]
freedreno/a6xx: remove unused param
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Rob Clark [Mon, 24 Feb 2020 16:16:34 +0000 (08:16 -0800)]
freedreno/ir3: remove from_tgsi
No longer used, other than in ir3 cmdline compiler, where it can be
replaced with a local variable.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3989>
Jonathan Marek [Thu, 27 Feb 2020 19:30:28 +0000 (14:30 -0500)]
turnip: increase array sizes in tu_descriptor_map
Pending the descriptor rework, this allows running the follow test:
dEQP-VK.renderpass.suballocation.attachment_sparse_filling.input_attachment_127
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
Jonathan Marek [Thu, 27 Feb 2020 19:29:05 +0000 (14:29 -0500)]
turnip: fall back to sysmem when attachments don't fit into gmem
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
Jonathan Marek [Thu, 27 Feb 2020 16:20:59 +0000 (11:20 -0500)]
turnip: remove unnecessary fb size check
Framebuffer with 0 width or height is not valid.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
Jonathan Marek [Thu, 27 Feb 2020 16:18:45 +0000 (11:18 -0500)]
turnip: don't hardcode gmem base for input attachment
Newer a6xx no longer has programmable GMEM base, so we can't rely on the
kernel driver setting it to 0x100000 (GMEM base is 0 on such GPUs).
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
Jonathan Marek [Thu, 27 Feb 2020 15:22:02 +0000 (10:22 -0500)]
turnip: fix srgb MRT
Register packing macros makes this only set the first bit. Set to whole
dword to fix srgb for color attachments >0.
Fixes:
59f29fc8 ("turnip: Convert the rest of tu_cmd_buffer.c over to the new pack macros.")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
Jonathan Marek [Tue, 25 Feb 2020 14:28:34 +0000 (09:28 -0500)]
turnip: fix hw binning + render_area offset interaction
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
Jonathan Marek [Wed, 12 Feb 2020 03:16:22 +0000 (22:16 -0500)]
turnip: minify image_view extent
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
Jonathan Marek [Wed, 12 Feb 2020 02:13:38 +0000 (21:13 -0500)]
turnip: remove unecessary MRT_CONTROL fill
Hardware won't use MRT_CONTROL after mrt_count
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
Jonathan Marek [Wed, 12 Feb 2020 02:12:25 +0000 (21:12 -0500)]
turnip: move some constant state to tu6_init_hw
Also remove duplicates.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
Jonathan Marek [Wed, 12 Feb 2020 02:11:07 +0000 (21:11 -0500)]
turnip: check the right alignment requirement on shader iova
I had some trouble because I assumed this was right, tested that the
alignment requirement is actually 16.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3979>
Jonathan Marek [Thu, 27 Feb 2020 20:35:54 +0000 (15:35 -0500)]
turnip: add r5g5b5a1_unorm/b5g5r5a1_unorm formats
r5g5b5a1/b5g5r5a1 tiled/ubwc is the same as a1r5g5b5 (in memory), but
linear is read as 1_5_5_5 and written with 5_5_5_1 with swap.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806>
Jonathan Marek [Thu, 13 Feb 2020 00:57:49 +0000 (19:57 -0500)]
turnip: rework format table to support r5g5b5a1_unorm/b5g5r5a1_unorm
These formats are an exception that can't be modeled in the current format
table. Switch to a table with only a single a6xx_format per vk format,
and deal with the exceptions separately (currently the only exception is
10_10_10_2_UNORM which has a different color format).
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806>
Jonathan Marek [Wed, 12 Feb 2020 23:45:28 +0000 (18:45 -0500)]
util/format: add missing BC4/BC5 vulkan formats
Enables these formats for turnip.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3806>
Icecream95 [Wed, 26 Feb 2020 09:03:13 +0000 (22:03 +1300)]
panfrost: LogicOp fixes and non 8-bit format support
With the previous LogicOp commit almost half of the blend modes were
broken because the surplus bits were not cleared after an inot.
v2:
- Remove u8 "fast path" as 8-bit is not well optimised yet
- Don't mask for 32-bit formats as that triggers an assert
Fixes:
068806c9f6b ("panfrost: LogicOp support")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3943>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3943>
Icecream95 [Wed, 26 Feb 2020 06:29:03 +0000 (19:29 +1300)]
nir: Allow nir_format conversions to work on 32-bit values
The constant has to changed to unsigned long long, as shifting a
32-bit value by 32 is undefined behaviour.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3943>
Greg V [Wed, 26 Feb 2020 20:12:12 +0000 (23:12 +0300)]
r600: add missing <array> include
Fixes error with clang/libc++:
../src/gallium/drivers/r600/sfn/sfn_emitaluinstruction.h:69:88: error: implicit instantiation of undefined template 'std::__1::array<unsigned char, 3>'
bool emit_alu_op3(const nir_alu_instr& instr, EAluOp opcode, std::array<uint8_t, 3> reorder={0,1,2});
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3967>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3967>
Dave Airlie [Mon, 17 Feb 2020 07:15:38 +0000 (17:15 +1000)]
llvmpipe: add support for tessellation shaders
This adds the hooks between llvmpipe and draw to enable tessellation shaders.
It also updates the CI results and docs.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Dave Airlie [Mon, 17 Feb 2020 07:13:58 +0000 (17:13 +1000)]
gallium/nir/tgsi: only scan fragment shader inputs for usage_mask
The scanner doesn't work with tess shaders, but we don't need it for those,
in fact only frag shaders need it.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Dave Airlie [Mon, 17 Feb 2020 07:13:11 +0000 (17:13 +1000)]
draw: hook up final bits of tessellation
This hooks tessellation into various parts of draw, so the
tessellation shaders are used in the correct places as the
last shader of the pipeline.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Dave Airlie [Mon, 17 Feb 2020 07:09:10 +0000 (17:09 +1000)]
draw: add main tessellation code
This is the bulk of the llvm shader builders and tessellation
execution code.
TCS uses a coroutine launcher like compute shaders to handle
barriers. It executes 4-wide with one input vertex per lane.
Tessellation happens before the TES is run.
TES is just a 4-wide launcher, one per primitive is executed,
with one lane per tessellation coordinate input.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Dave Airlie [Mon, 17 Feb 2020 06:58:18 +0000 (16:58 +1000)]
draw: add JIT context/functions for tess stages.
This adds the initial draw_tess.h with a define needed
for the interfaces. TCS input array doesn't need to handle
patch inputs so can be smaller.
The TCS context has some dummy values to align the textures/images
properly.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Dave Airlie [Mon, 17 Feb 2020 06:49:09 +0000 (16:49 +1000)]
gallivm/nir: add tessellation i/o support.
This add support for the tessellation i/o callbacks.
Tessellation requires another level of indirect indexing,
and allows fetches from shader outputs.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Dave Airlie [Mon, 17 Feb 2020 06:47:51 +0000 (16:47 +1000)]
gallivm/tgsi/swr: add mask vec to the tcs store
For the nir paths we want to access the mask vector to only
store when the mask allows it.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Dave Airlie [Mon, 17 Feb 2020 06:42:25 +0000 (16:42 +1000)]
gallivm/nir: align store_var param order with load_var
This was ugly so align load/store to have mostly the same
parameter ordering
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Dave Airlie [Mon, 17 Feb 2020 06:21:21 +0000 (16:21 +1000)]
gallivm/nir: add support for tess system values
hooks up the tessellation specific system values in the NIR paths
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Dave Airlie [Mon, 17 Feb 2020 06:19:57 +0000 (16:19 +1000)]
gallivm/nir: split out 64-bit splitting code
This just lets it be reused for tess later.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Dave Airlie [Mon, 17 Feb 2020 06:17:21 +0000 (16:17 +1000)]
gallium/auxiliary: add the microsoft tessellator and a pipe wrapper.
This adds the same tessellator code that swr uses, swr should
move to using this copy, unfortunately that wasn't trivial on my first
look.
The p_tessellator wrapper wraps it in a form that is a useful interface
for draw.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3841>
Samuel Pitoiset [Thu, 20 Feb 2020 12:22:31 +0000 (13:22 +0100)]
radv: allow to capture SQTT traces with RADV_THREAD_TRACE=<start_frame>
This is pretty basic (and a bit crappy at the moment). I think we
might want some sort of overlay in the future and also be able to
trigger captures with F12 or whatever.
To record a capture, set RADV_THREAD_TRACE to something greater than
zero (eg. RADV_THREAD_TRACE=100 will capture frame #100). If the
driver didn't crash (or the GPU didn't hang), the capture file
should be stored in /tmp.
To open that capture, use Radeon GPU Profiler and enjoy your
profiling times with RADV! \o/
Note that thread trace support is quite experimental, only GFX9 is
supported at the moment, and a bunch of useful stuff are still missing
(shader ISA, pipelines info, etc). More is comming soon.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
Samuel Pitoiset [Thu, 20 Feb 2020 15:24:14 +0000 (16:24 +0100)]
radv: add initial SQTT files generation support
SQTT is also a file format (.rgp extension) that can be consumed
by Radeon GPU Profiler for profiling purposes.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
Samuel Pitoiset [Tue, 18 Feb 2020 07:30:46 +0000 (08:30 +0100)]
radv: emit thread trace markers after every draw/dispatch call
Thread trace markers (also called events in Radeon GPU Profiler)
should be emitted after every draw/dispatch calls to collect data.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
Samuel Pitoiset [Tue, 18 Feb 2020 07:32:33 +0000 (08:32 +0100)]
radv: add initial SQ Thread Trace support for GFX9
SQTT is a hardware block that collects thread trace data (like
wave occupancy, timings, etc) for every draw/dispatch calls.
It's only supported on GFX9 at the moment but I will add other
generations support soon.
This is the first step towards profiling with RADV!
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
Samuel Pitoiset [Fri, 21 Feb 2020 08:35:46 +0000 (09:35 +0100)]
radv: add a small helper that allows to submit internal CS
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
Samuel Pitoiset [Tue, 18 Feb 2020 07:30:12 +0000 (08:30 +0100)]
ac/registers: add definitions for thread trace
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
Samuel Pitoiset [Thu, 20 Feb 2020 10:35:23 +0000 (11:35 +0100)]
ac: add more fields to ac_gpu_info
For RGP traces.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3900>
Eric Anholt [Tue, 17 Dec 2019 05:23:02 +0000 (21:23 -0800)]
ci: Enable -Werror on meson-vulkan and meson-testing.
I want to make sure that I don't introduce warnings in turnip where we
have active work going on, and I also want to make sure that the drivers
we care about testing are warnings-clean.
As with the previous -Werror change, this is for CI only and doesn't
affect end-user builds.
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3607>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3607>
Eric Anholt [Tue, 4 Feb 2020 23:12:18 +0000 (15:12 -0800)]
aco: Fix signed-vs-unsigned warning.
The previous instance of this comparision was 1u to avoid the warning, fix
this one too.
Fixes:
dba71de5c636 ("aco: only create parallelcopy to restore exec at loop exit if needed")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3607>
Marek Olšák [Thu, 27 Feb 2020 00:16:01 +0000 (19:16 -0500)]
gallium/u_vbuf: silence a warning by using unreachable
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3970>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3970>
Marek Olšák [Wed, 26 Feb 2020 22:21:43 +0000 (17:21 -0500)]
mesa: fix 11 warnings
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3970>
Marek Olšák [Wed, 26 Feb 2020 22:20:51 +0000 (17:20 -0500)]
nir: fix 5 warnings
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3970>
Marek Olšák [Wed, 26 Feb 2020 22:00:19 +0000 (17:00 -0500)]
gallivm: fix 5 warnings
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3970>
Marek Olšák [Wed, 26 Feb 2020 21:57:37 +0000 (16:57 -0500)]
nir: replace GCC unroll with an option that works on GCC < 8.0
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3970>
Marek Olšák [Fri, 14 Feb 2020 03:56:54 +0000 (22:56 -0500)]
mesa: fix incorrect prim.begin/end for glMultiDrawElements
This has no effect on Gallium, but it affects tnl.
Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Marek Olšák [Wed, 12 Feb 2020 22:16:45 +0000 (17:16 -0500)]
mesa: optimize glMultiDrawArrays, call Draw only once (v2)
v2: use the macros
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Marek Olšák [Wed, 12 Feb 2020 22:21:35 +0000 (17:21 -0500)]
mesa: don't unroll glMultiDrawElements if one count is 0
let the driver skip or submit an empty draw call.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Marek Olšák [Wed, 12 Feb 2020 20:30:30 +0000 (15:30 -0500)]
mesa: clean up glMultiDrawElements code, use alloca for small draw count (v2)
v2: use calloc, add reusable macros
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de> (v1)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Marek Olšák [Tue, 11 Feb 2020 02:42:56 +0000 (21:42 -0500)]
mesa: move num_instances and base_instance out of _mesa_prim
They are never used by multi draws and internal draws.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Marek Olšák [Tue, 11 Feb 2020 01:25:52 +0000 (20:25 -0500)]
mesa: remove redundant _mesa_prim::is_indexed
Instead, check (ib != NULL) like all other drivers.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Marek Olšák [Tue, 11 Feb 2020 01:19:37 +0000 (20:19 -0500)]
mesa/i965: remove _mesa_prim::indirect_offset
Only i965 was using it.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Marek Olšák [Wed, 26 Feb 2020 20:10:47 +0000 (15:10 -0500)]
gallium/u_threaded: convert dividing by index_size to a bit shift
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Marek Olšák [Fri, 14 Feb 2020 20:28:28 +0000 (15:28 -0500)]
gallium/u_threaded: fix uploading user indices with start != 0
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Marek Olšák [Tue, 21 Jan 2020 03:59:49 +0000 (22:59 -0500)]
gallium: pass cso_velems_state into cso_context instead of pipe_vertex_element
This removes one memcpy from the CSO hashing code.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Marek Olšák [Tue, 11 Feb 2020 23:15:02 +0000 (18:15 -0500)]
gallium/cso_hash: inline struct cso_hash_data
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Marek Olšák [Wed, 22 Jan 2020 01:17:32 +0000 (20:17 -0500)]
gallium/cso_hash: pack cso_node better
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Marek Olšák [Tue, 11 Feb 2020 01:02:30 +0000 (20:02 -0500)]
mesa: remove unused "indirect" parameter from Driver.Draw
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Marek Olšák [Tue, 11 Feb 2020 00:54:44 +0000 (19:54 -0500)]
i965: stop using "indirect" parameter from Driver.Draw (non-indirect)
The parameter will be removed.
v2: added UNUSED, removed "!!"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3990>
Caio Marcelo de Oliveira Filho [Thu, 27 Feb 2020 19:02:17 +0000 (11:02 -0800)]
anv: Remove unused field `urb.total_size`
This was used before the URB calculation functions were shared by GL
and Vulkan. Also drop the substruct for the remaining, `l3_config` is
a good name on its own.
Also-written-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3981>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3981>
Alyssa Rosenzweig [Thu, 27 Feb 2020 14:41:17 +0000 (09:41 -0500)]
pan/midgard: Use address analysis for globals, etc
..instead of opencoding for constants and doing the rest as ALU.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
Alyssa Rosenzweig [Thu, 27 Feb 2020 14:38:21 +0000 (09:38 -0500)]
pan/midgard: Add address analysis framework
Midgard has the ability to calculate addresses as part of the load/store
pipeline. We'd like to make use of this to avoid doing this work on the
ALU pipes. To do so, when emitting globals/SSBOs/shareds, we walk the
tree looking for address arithmetic to try to parse out something the
hardware can work with, letting the original instructions be DCE'd
ideally. This analysis is done at the NIR level to properly account for
some messy details of vectorization which we'd rather not poke at the
backend level. (Originally I wrote this as a MIR pass but I'm fairly
sure it was wrong.)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
Alyssa Rosenzweig [Thu, 27 Feb 2020 15:07:32 +0000 (10:07 -0500)]
pan/midgard: Force address alignment
I thought we already had this but... maybe not..
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
Alyssa Rosenzweig [Thu, 27 Feb 2020 14:37:28 +0000 (09:37 -0500)]
pan/midgard: Round up bytemasks when promoting uniforms
Fixes crashes with uniform promotion in certain mixed type
circumstances.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
Alyssa Rosenzweig [Thu, 27 Feb 2020 14:36:46 +0000 (09:36 -0500)]
pan/midgard: Fix load/store argument sizing
The swizzles are as-if they were 32-bit regardless of the bitness of the
operation, but the source sizes can and do change depending on the
flags. Account for this in the analysis.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
Alyssa Rosenzweig [Thu, 27 Feb 2020 14:35:50 +0000 (09:35 -0500)]
pan/midgard: Add LDST_ADDRESS property
Many load/store ops (used for globals, SSBOs, shared memory, etc) have
the ability to compute addresses directly. Mark off which ones behave
like this.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
Alyssa Rosenzweig [Thu, 27 Feb 2020 14:35:12 +0000 (09:35 -0500)]
pan/midgard: Extract nir_ssa_index helper
In case we don't have a nir_src.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
Alyssa Rosenzweig [Thu, 27 Feb 2020 14:15:00 +0000 (09:15 -0500)]
pan/midgard: Partially fix 64-bit swizzle alignment
When mixing 32/64-bit, we need to align the 32-bit registers to get the
required alignment. This isn't quite enough yet, though, since user
swizzles could bypass and will need to be lowered to 32-bit moves
(outstanding todo).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
Alyssa Rosenzweig [Wed, 26 Feb 2020 18:51:07 +0000 (13:51 -0500)]
pan/midgard: Allow fusing inverted sources for inverted ops
It doesn't make a difference to the actual algorithm, so let's get rid
of them.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
Alyssa Rosenzweig [Wed, 26 Feb 2020 18:50:46 +0000 (13:50 -0500)]
pan/midgard: Allow inverted inverted ops
We'd like to transform `inand.not` back to `iand` and so forth.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
Alyssa Rosenzweig [Wed, 26 Feb 2020 18:37:10 +0000 (13:37 -0500)]
panfrost: Increase SSBO/image limit from 4->8
Fixes an error compiling some shaders.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3978>
Jonathan Marek [Thu, 20 Feb 2020 02:14:35 +0000 (21:14 -0500)]
etnaviv: disable INT_FILTER for ASTC
Tested on GC3000: INT_FILTER bit is incompatible with ASTC formats.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3927>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3927>
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