Arnd Bergmann [Wed, 23 Nov 2022 11:29:23 +0000 (12:29 +0100)]
Merge tag 'aspeed-6.2-devicetree' of git://git./linux/kernel/git/joel/bmc into soc/dt
ASPEED device tree updates for 6.2
- New machines
* IBM Bonnell AST2600 BMC, for a Power10 server
* Delta AHE-50DC AST1250 BMC, for a 1U Open19 power shelf
- Removed machines
* IBM Mihawk AST2500 BMC, a Power9 server similar to Witherspoon
- Fixes and updates for bletchley, mtjade/mtmitchell, rainier/everest
* tag 'aspeed-6.2-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc:
ARM: dts: aspeed: mtjade: Add SMPro nodes
ARM: dts: aspeed: mtjade,mtmitchell: Add BMC SSIF nodes
ARM: dts: aspeed: Add Delta AHE-50DC BMC
dt-bindings: arm: aspeed: document Delta AHE-50DC BMC
ARM: dts: aspeed: rainier: Fix pca9551 nodes
ARM: dts: aspeed: p10bmc: Add occ-hwmon nodes
ARM: dts: aspeed-g6: Add aliases for mdio nodes
ARM: dts: aspeed: Remove Mihawk
ARM: dts: aspeed: rainier,everest: Move reserved memory regions
ARM: dts: aspeed: Add IBM Bonnell system BMC devicetree
ARM: dts: aspeed: bletchley: Enable emmc and ehci1
ARM: dts: aspeed: bletchley: Update and fix gpio-line-names
ARM: dts: aspeed: bletchley: Update fusb302 nodes
ARM: dts: aspeed: bletchley: Bind presence-sledX pins via gpio-keys
ARM: dts: aspeed: bletchley: Disable GPIOV2 pull-down
ARM: dts: aspeed: bletchley: Change LED sys_log_id to active low
Link: https://lore.kernel.org/r/CACPK8Xfsc8BaL_qAgV+3Rk-AFcQoDVfTpMzHvq_rR-UYqwpNNQ@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:03:55 +0000 (11:03 +0100)]
Merge tag 'tegra-for-6.2-arm-dt' of git://git./linux/kernel/git/tegra/linux into soc/dt
ARM: tegra: Device tree changes for v6.2-rc1
This fixes various minor issues in device trees that are flagged by the
DT validation tools.
* tag 'tegra-for-6.2-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Remove duplicate pin entry in pinmux
ARM: tegra: Remove unused interrupt-parent properties
ARM: tegra: Fix nvidia,io-reset properties
ARM: tegra: Add missing power-supply for panels
ARM: tegra: Fixup pinmux node names
ARM: tegra: Use correct compatible string for ASUS TF101 panel
Link: https://lore.kernel.org/r/20221119012025.3968358-6-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 22 Nov 2022 22:10:15 +0000 (23:10 +0100)]
Merge tag 'v6.1-next-dts64' of https://git./linux/kernel/git/matthias.bgg/linux into soc/dt
Fix check warnings all over the place.
mt7986:
- Add crypto, I2C and SPI nodes
mt6795:
- Add clock nodes
- Add DMA support for UARTs
- Add MMC nodes
- Add basic support for Sonyx Xperia M5
mt8195:
- Add video enconder node
- Add PCIe support
- Fine tune capacity-dmips-mhz
- Add support for internal and external display port
* tag 'v6.1-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (35 commits)
arm64: dts: mt7986: add spi related device nodes
arm64: dts: mt7986: move wed_pcie node
arm64: dts: mediatek: Add support for MT6795 Sony Xperia M5 smartphone
dt-bindings: arm: mediatek: Add compatible for MT6795 Sony Xperia M5
arm64: dts: mediatek: mt6795: Add support for eMMC/SD/SDIO controllers
arm64: dts: mediatek: mt6795: Add support for APDMA and wire up UART DMAs
arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg
arm64: dts: mediatek: mt6795: Add topckgen, infra, peri clocks/resets
arm64: dts: mediatek: cherry: Add edptx and dptx support
arm64: dts: mediatek: cherry: Add dp-intf ports
arm64: dts: mt8195: Add edptx and dptx nodes
arm64: dts: mt8195: Add dp-intf nodes
arm64: dts: mediatek: mt6797: Fix 26M oscillator unit name
arm64: dts: mediatek: pumpkin-common: Fix devicetree warnings
arm64: dts: mt2712-evb: Fix usb vbus regulators unit names
arm64: dts: mt2712-evb: Fix vproc fixed regulators unit names
arm64: dts: mt2712e: Fix unit address for pinctrl node
arm64: dts: mt2712e: Fix unit_address_vs_reg warning for oscillators
arm64: dts: mt6779: Fix devicetree build warnings
arm64: dts: mt7896a: Fix unit_address_vs_reg warning for oscillator
...
Link: https://lore.kernel.org/r/8933d687-71f0-e9ad-a7c6-2e5a8993463d@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 22 Nov 2022 22:02:24 +0000 (23:02 +0100)]
Merge tag 'tegra-for-6.2-arm64-dt-v2' of git://git./linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Device tree changes for v6.2-rc1
This contains many new additions, primarily for Tegra234, as well as a
slew of cleanups for issues flagged by the DT validation tools.
* tag 'tegra-for-6.2-arm64-dt-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits)
arm64: tegra: Remove unneeded clock-names for Tegra132 PWM
arm64: tegra: Fix up compatible string for SDMMC1 on Tegra234
arm64: tegra: Remove unused reset-names for QSPI
arm64: tegra: Fixup pinmux node names
arm64: tegra: Remove reset-names for QSPI
arm64: tegra: Use correct compatible string for Tegra234 HDA
arm64: tegra: Use correct compatible string for Tegra194 HDA
arm64: tegra: Use vbus-gpios property
arm64: tegra: Restructure Tegra210 PMC pinmux nodes
arm64: tegra: Update cache properties
arm64: tegra: Remove 'enable-active-low'
arm64: tegra: Add dma-channel-mask in GPCDMA node
arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller
arm64: tegra: Add missing compatible string to Ethernet USB device
arm64: tegra: Separate AON pinmux from main pinmux on Tegra194
arm64: tegra: Add ECAM aperture info for all the PCIe controllers
arm64: tegra: Remove clock-names from PWM nodes
arm64: tegra: Enable GTE nodes
arm64: tegra: Update console for Jetson Xavier and Orin
arm64: tegra: Enable PWM users on Jetson AGX Orin
...
Link: https://lore.kernel.org/r/20221121171239.2041835-7-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 22 Nov 2022 22:00:52 +0000 (23:00 +0100)]
Merge tag 'tegra-for-6.2-dt-bindings-v2' of git://git./linux/kernel/git/tegra/linux into soc/dt
dt-bindings: Changes for v6.2-rc1
New memory client IDs and IOMMU stream IDs, as well as new compatible
strings are introduced to support more hardware on Tegra234. Some device
tree bindings are converted to json-schema to allow formal validation.
* tag 'tegra-for-6.2-dt-bindings-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: usb: tegra-xusb: Convert to json-schema
dt-bindings: pwm: tegra: Convert to json-schema
dt-bindings: pinctrl: tegra194: Separate instances
dt-bindings: pinctrl: tegra: Convert to json-schema
dt-bindings: PCI: tegra234: Add ECAM support
dt-bindings: pwm: tegra: Document Tegra234 PWM
dt-bindings: Add bindings for Tegra234 NVDEC
dt-bindings: tegra: Update headers for Tegra234
dt-bindings: Add headers for NVDEC on Tegra234
Link: https://lore.kernel.org/r/20221121171239.2041835-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 22 Nov 2022 22:00:03 +0000 (23:00 +0100)]
Merge tag 'socfpga_dts_updates_for_v6.2' of git://git./linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA dts updates for v6.2
- Use the "clk-phase-sd-hs" property for SDMMC
- Remove the "clk-phase" fom the sdmmc_clk that is no longer used
- Clean dtschema for mmc node
- Increase NAND partition for Arria10
* tag 'socfpga_dts_updates_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
arm: dts: socfpga: remove "clk-phase" in sdmmc_clk
arm: dts: socfpga: align mmc node names with dtschema
ARM: dts: socfpga: arria10: Increase NAND boot partition size
Link: https://lore.kernel.org/r/20221121163259.341974-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 22 Nov 2022 21:57:53 +0000 (22:57 +0100)]
Merge tag 'riscv-dt-for-v6.2-mw0' of https://git./linux/kernel/git/conor/linux into soc/dt
RISC-V DeviceTrees for v6.2
dt-bindings:
- new compatibles to support the StarFive VisionFive & thead CPU cores
- a fix for the PolarFire SoC's pwm binding, merged through my tree as
suggested by the PWM maintainers
Microchip:
- Non-urgent fix for the node address not matches the reg in a way that
the checkers don't complain about
- Add GPIO controlled LEDs for Icicle
- Support for the "CCC" clocks in the FPGA fabric. Previously these
used fixed-frequency clocks in the dt, but if which CCC is in use is
known, as in the v2022.09 Icicle Kit Reference Design, the rates can
be read dynamically. It's an "is known" as it *can* be set via
constraints in the FPGA tooling but does not have to be.
- A fix for the Icicle's pwm-cells
- Removal of some unused PCI clocks
StarFive:
- Addition of the VisionFive DT, which has been a long time coming!
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
riscv: dts: microchip: remove unused pcie clocks
riscv: dts: microchip: remove pcie node from the sev kit
riscv: dts: microchip: fix the icicle's #pwm-cells
dt-bindings: pwm: fix microchip corePWM's pwm-cells
riscv: dts: starfive: Add StarFive VisionFive V1 device tree
riscv: dts: starfive: Add common DT for JH7100 based boards
dt-bindings: riscv: starfive: Add StarFive VisionFive V1 board
riscv: dts: microchip: fix memory node unit address for icicle
riscv: dts: microchip: icicle: Add GPIO controlled LEDs
riscv: dts: microchip: add the mpfs' fabric clock control
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Sam Shih [Fri, 18 Nov 2022 19:01:21 +0000 (20:01 +0100)]
arm64: dts: mt7986: add spi related device nodes
This patch adds spi support for MT7986.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Frank Wunderlich [Fri, 18 Nov 2022 19:01:16 +0000 (20:01 +0100)]
arm64: dts: mt7986: move wed_pcie node
Move the wed_pcie node to have node aligned by address.
Fixes:
00b9903996b3 ("arm64: dts: mediatek: mt7986: add support for Wireless Ethernet Dispatch")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221118190126.100895-2-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Arnd Bergmann [Mon, 21 Nov 2022 10:56:08 +0000 (11:56 +0100)]
Merge tag 'renesas-arm-dt-for-v6.2-tag2' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt
Renesas ARM DT updates for v6.2 (take two)
- Timer (TMU and CMT) and quad Cortex-A76 CPU topology support for
the R-Car V4H SoC,
- Watchdog, L2 cache, and system controller support for the RZ/V2M
SoC on the RZ/V2M Evaluation Kit 2.0,
- Ethernet Switch and SERDES supports for the R-Car S4-8 SoC and the
Spider development board,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (21 commits)
arm64: dts: renesas: spider-ethernet: Enable Ethernet Switch and SERDES
arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodes
arm64: dts: renesas: r9a09g011: Add system controller node
arm64: dts: renesas: r8a779g0: Add CA76 operating points
arm64: dts: renesas: r8a779g0: Add CPU core clocks
arm64: dts: renesas: r8a779g0: Add CPUIdle support
arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores
arm64: dts: renesas: r8a779g0: Add L3 cache controller
arm64: dts: renesas: r9a09g011: Add L2 Cache node
arm64: dts: renesas: rzv2mevk2: Enable watchdog
arm64: dts: renesas: r9a09g011: Add watchdog node
arm64: dts: renesas: spider-cpu: Switch from SCIF3 to HSCIF0
arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodes
arm64: dts: renesas: r9a09g011: Fix I2C SoC specific strings
arm64: dts: renesas: rzg2l: Add missing cache-level properties
arm64: dts: renesas: r8a779g0: Add CMT node
arm64: dts: renesas: r9a09g011: Fix unit address format error
arm64: dts: renesas: white-hawk-cpu: Sort RWDT entry correctly
arm64: dts: renesas: r8a779g0: Add TMU nodes
arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clock
...
Link: https://lore.kernel.org/r/cover.1668788921.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:53:45 +0000 (11:53 +0100)]
Merge tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt
Renesas RISC-V DT updates for v6.2
- Add initial support for the Renesas RZ/Five SoC and the Renesas
RZ/Five SMARC EVK development board.
* tag 'renesas-riscv-dt-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU
MAINTAINERS: Add entry for Renesas RISC-V
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
Link: https://lore.kernel.org/r/cover.1668788930.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:53:09 +0000 (11:53 +0100)]
Merge tag 'renesas-dt-bindings-for-v6.2-tag2' of git://git./linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DT binding updates for v6.2 (take two)
- Document support for the Andes Technology AX45MP RISC-V CPU Core, as
used on the Renesas RZ/Five SoC,
- Document support for the Renesas RZ/V2M System Configuration.
* tag 'renesas-dt-bindings-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration
dt-bindings: riscv: Add Andes AX45MP core to the list
dt-bindings: riscv: Sort the CPU core list alphabetically
Link: https://lore.kernel.org/r/cover.1668788927.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:44:13 +0000 (11:44 +0100)]
Merge tag 'stm32-dt-for-v6.2-1' of git://git./linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.2, round 1
Highlights:
----------
- MPU:
- ST boards:
- Add MCP23017 IO expander support on stm32mp135f-dk board.
- Add stm32g0 support for USB typeC on stm32mp135f-dk
- Add USB (EHCI / OTG) on stm32mp135f-dk
- Add ADC support on stm32mp135f-dk
- Add USB2514B onboard hub on stm32mp157c-ev1
- DH:
- Fix severals Yaml DT validation issues
* tag 'stm32-dt-for-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (28 commits)
ARM: dts: stm32: Rename mdio0 to mdio on DHCOR Testbench board
ARM: dts: stm32: add mcp23017 IO expander on I2C1 on stm32mp135f-dk
ARM: dts: stm32: add mcp23017 pinctrl entry for stm32mp13
ARM: dts: stm32: enable USB OTG in dual role mode on stm32mp135f-dk
ARM: dts: stm32: add pins for stm32g0 typec controller on stm32mp13
ARM: dts: stm32: enable USB Host EHCI on stm32mp135f-dk
ARM: dts: stm32: enable USB HS phys on stm32mp135f-dk
ARM: dts: stm32: add fixed regulators to support usb on stm32mp135f-dk
ARM: dts: stm32: add USB OTG HS support on stm32mp131
ARM: dts: stm32: add UBSH EHCI and OHCI support on stm32mp131
ARM: dts: stm32: add USBPHYC and dual USB HS PHY support on stm32mp131
ARM: dts: stm32: add PWR fixed regulators on stm32mp131
ARM: dts: stm32: Fix AV96 WLAN regulator gpio property
ARM: dts: stm32: add adc support on stm32mp135f-dk
ARM: dts: stm32: add dummy vdd_adc regulator on stm32mp135f-dk
ARM: dts: stm32: add adc pins muxing on stm32mp135f-dk
ARM: dts: stm32: add adc support to stm32mp13
ARM: dts: stm32: Drop MMCI interrupt-names
ARM: dts: stm32: update vbus-supply of usbphyc_port0 on stm32mp157c-ev1
ARM: dts: stm32: add support for USB2514B onboard hub on stm32mp157c-ev1
...
Link: https://lore.kernel.org/r/3235e5be-d89f-f76c-5e25-5d1210feb857@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:43:39 +0000 (11:43 +0100)]
Merge tag 'hisi-arm64-dt-for-6.2' of https://github.com/hisilicon/linux-hisi into soc/dt
ARM64: DT: HiSilicon ARM64 DT updates for 6.2
- Add missing cache-level properties
* tag 'hisi-arm64-dt-for-6.2' of https://github.com/hisilicon/linux-hisi:
arm64: dts: Update cache properties for hisilicon
Link: https://lore.kernel.org/r/63744D38.9010700@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:40:29 +0000 (11:40 +0100)]
Merge tag 'imx-dt64-6.2' of git://git./linux/kernel/git/shawnguo/linux into soc/dt
i.MX arm64 device tree update for 6.2:
- New device trees for i.MX8MM based Cloos PHG and WB15 SoM/EVK.
- A set of tqma8mpql/mba8mpxl changes, adding USB Host, PCIe, PWM fan
support.
- Rename DTB overlay source files from .dts to .dtso.
- A series from Frank Li to add USB, ADC, FlexSPI, LPSPI support for
i.MX8DXL.
- A couple of librem5-devkit changes, switching LED to use PWM and using
function and color properties for LED.
- Enable wakeup-source for USB PHY for i.MX8MM/N EVK.
- A set of random changes from Marcel Ziswiler to improve i.MX8M based
Verdin device trees.
- A series from Marek Vasut to update Data Modul i.MX8M Mini eDM SBC and
DH electronics i.MX8M Plus DHCOM, modeling PMIC to SNVS RTC clock
path, dropping QCA clk_out setup, adding bluetooth UART, etc.
- A bunch of changes from Peng Fan to add LPSPI, TPM etc for i.MX93,
update i.MX8MP/N EVK with UART, I2C addition.
- Update cache properties per DeviceTree Specification v0.3.
- Add gpio-ranges property for i.MX8DXL and i.MX8Q LSIO Subsystem.
- Misc small and random changes.
* tag 'imx-dt64-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (60 commits)
arm64: dts: freescale: Rename DTB overlay source files from .dts to .dtso
arm64: dts: imx8mm-evk: add vcc supply for pca6416
arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulator
arm64: dts: imx8mn-evk: enable uart1
arm64: dts: imx8mn-evk: add i2c gpio recovery settings
arm64: dts: imx8mn-evk: set off-on-delay-us in regulator
arm64: dts: imx8mn-evk: update vdd_soc dvs voltage
arm64: dts: imx8mp-evk: enable I2C2 node
arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk
arm64: dts: imx8mp-evk: enable uart1/3 ports
ARM64: dts: imx8mp-evk: add pwm support
arm64: dts: imx8mp: add mlmix power domain
arm64: dts: imx8mq: fix dtschema warning for imx7-csi
arm64: dts: Update cache properties for freescale
arm64: dts: imx8mm-phg: Add initial board support
arm64: dts: imx8qxp-ss-lsio: add gpio-ranges property
arm64: dts: imx8qm-ss-lsio: add gpio-ranges property
arm64: dts: imx8dxl-ss-lsio: add gpio-ranges property
arm64: dts: imx8dxl_evk: add lpspi0 support
arm64: dts: imx8dxl: add lpspi support
...
Link: https://lore.kernel.org/r/20221119125733.32719-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:08:01 +0000 (11:08 +0100)]
Merge tag 'imx-dt-6.2' of git://git./linux/kernel/git/shawnguo/linux into soc/dt
i.MX arm device tree update for 6.2:
- New device tree for Kobo Aura 2 E-Boot reader which is built on i.MX6SL
SoC.
- Enable backlight and boost support for imx6sl-tolino-shine2hd.
- Enable CYTTSP5 touchscreen support for E60K02.
- Enable Silergy SY7636A EPD PMIC on imx7d-remarkable2 epaper tablet.
- Add watchdog property 'fsl,suspend-in-wait' for i.MX6UL Phytec Phycore
SoM to avoid watchdog triggering in 'freeze' low power mode.
- Correct the polarity of AT86RF233 reset line for vf610-zii-dev-rev-c
board.
- A bunch of Colibri device tree updates from Marcel Ziswiler and Philippe
Schenker, correct USBH_PEN property, remove spurious debounce property,
add USB dual-role switching, and some cosmetic change.
- Other small and random changes.
* tag 'imx-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: colibri-imx6ull: Enable dual-role switching
ARM: dts: imx: e60k02: Add touchscreen
ARM: dts: imx6qdl-sabre: Add mmc aliases
ARM: dts: imx6ul/ull: suspend i.MX6UL watchdog in wait mode
ARM: dts: imx7d-remarkable2: Enable silergy,sy7636a
ARM: dts: imx6sl-tolino-shine2hd: Add backlight boost
ARM: dts: imx6sl-tolino-shine2hd: Add backlight
ARM: dts: colibri-imx7: fix confusing naming
ARM: dts: colibri-imx6ull: add -hog to gpio hogs
ARM: dts: colibri-imx6ull: enable default peripherals
ARM: dts: colibri-imx6ull: keep peripherals disabled
ARM: dts: ls1021: correct indentation
ARM: dts: vf610-zii-dev-rev-c: fix polarity of at86rf233 reset line
ARM: dts: imx7-colibri: remove spurious debounce property
ARM: dts: colibri-imx6: specify usbh_pen gpio being active-low
ARM: dts: colibri-imx6: move vbus-supply to module level device tree
ARM: dts: colibri-imx6: usb dual-role switching
ARM: dts: imx: Add devicetree for Kobo Aura 2
Link: https://lore.kernel.org/r/20221119125733.32719-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 10:06:42 +0000 (11:06 +0100)]
Merge tag 'imx-bindings-6.2' of git://git./linux/kernel/git/shawnguo/linux into soc/dt
i.MX dt-bindings update for 6.2:
- New vendor prefix for Cloos and InnoComm.
- New compatible for Cloos PHG board, InnoComm WB15 EVK and Kobo Aura 2.
- Improve snvs-lpgpr bindings schema regarding i.MX8M SNVS LPGRP
compatible strings.
- Improve fsl-imx-cspi bindings schema for i.MX8MP ECSPI.
- Add bindings schema for i.MX8M ANATOP device.
- Update SCU firmware resource ID header by syncing with the latest
available SCFW kit version 1.13.0.
* tag 'imx-bindings-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
dt-bindings: arm: fsl: Add an entry for Cloos PHG board
dt-bindings: vendor-prefixes: Add an entry for Cloos
dt-bindings: nvmem: snvs-lpgpr: Fix i.MX8M compatible strings
dt-bindings: spi: fsl-imx-cspi: update i.MX8MP binding
dt-bindings: arm: fsl: add compatible string for Kobo Aura 2
dt-bindings: clock: add i.MX8M Anatop
dt-bindings: arm: fsl: Add InnoComm WB15 EVK
dt-bindings: vendor-prefixes: Add prefix for InnoComm
dt-bindings: firmware: imx: sync with SCFW kit v1.13.0
Link: https://lore.kernel.org/r/20221119125733.32719-3-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Thierry Reding [Thu, 17 Nov 2022 08:32:41 +0000 (09:32 +0100)]
arm64: tegra: Remove unneeded clock-names for Tegra132 PWM
There's only a single clock for this IP block, so it doesn't need a
clock-names property.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 12:38:34 +0000 (13:38 +0100)]
arm64: tegra: Fix up compatible string for SDMMC1 on Tegra234
The compatible string list for SDHCI on Tegra234 should be
"nvidia,tegra234-sdhci", followed by the "nvidia,tegra186-sdhci"
fallback. Use that consistently for all SDHCI controllers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 12:35:57 +0000 (13:35 +0100)]
arm64: tegra: Remove unused reset-names for QSPI
The Tegra QSPI controller uses a single reset line, so there's no need
for a reset-names property. Remove such properties.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 12:35:08 +0000 (13:35 +0100)]
arm64: tegra: Fixup pinmux node names
Pinmux node names should have a pinmux- prefix and not use underscores.
Fix up some cases that didn't follow those rules.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 5 Sep 2022 16:08:55 +0000 (18:08 +0200)]
arm64: tegra: Remove reset-names for QSPI
The Tegra QSPI controllers use a single reset control, so reset-names is
not necessary and therefore not specified in the DT bindings. Drop the
property from device tree files to avoid validation warnings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 13:14:16 +0000 (14:14 +0100)]
arm64: tegra: Use correct compatible string for Tegra234 HDA
The Tegra234 HDA controller is not backwards-compatible with Tegra30, so
drop the corresponding compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 13:11:04 +0000 (14:11 +0100)]
arm64: tegra: Use correct compatible string for Tegra194 HDA
The Tegra194 HDA controller is not backwards-compatible with Tegra30, so
drop the corresponding compatible string from the list.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 13:10:17 +0000 (14:10 +0100)]
arm64: tegra: Use vbus-gpios property
Instead of using the deprecated vbus-gpio property, switch to using the
more standard vbus-gpios property.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 7 Dec 2021 14:03:41 +0000 (15:03 +0100)]
arm64: tegra: Restructure Tegra210 PMC pinmux nodes
The PMC pinmux configuration nodes need to be part of a top-level pinmux
node. Add that new "pinmux" node and move the configuration nodes into
it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Pierre Gondois [Mon, 7 Nov 2022 15:57:08 +0000 (16:57 +0100)]
arm64: tegra: Update cache properties
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Fabio Estevam [Mon, 19 Sep 2022 10:43:50 +0000 (07:43 -0300)]
arm64: tegra: Remove 'enable-active-low'
The 'enable-active-low' property is not a valid one.
Only 'enable-active-high' is valid, and when this property is absent
the gpio regulator will act as active low by default.
Remove the invalid 'enable-active-low' property.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Akhil R [Thu, 10 Nov 2022 17:17:47 +0000 (22:47 +0530)]
arm64: tegra: Add dma-channel-mask in GPCDMA node
Add dma-channel-mask property in Tegra GPCDMA device tree node.
The property would help to specify the channels to be used in
kernel and reserve few for the firmware. This was previously
achieved by limiting the channel number to 31 in the driver.
This is wrong and does not align with the hardware. Correct this
and update the interrupts property to list all 32 interrupts.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Vidya Sagar [Tue, 25 Oct 2022 18:25:08 +0000 (23:55 +0530)]
arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller
Fix the starting address of the non-prefetchable aperture of PCIe C3
controller.
Fixes:
ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Thu, 3 Nov 2022 11:35:48 +0000 (12:35 +0100)]
arm64: tegra: Add missing compatible string to Ethernet USB device
According to the DT schema in usb-device.yaml, each USB device node
needs a compatible string, so add one for the built-in USB Ethernet
device on Jetson TX1.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 14:23:45 +0000 (15:23 +0100)]
arm64: tegra: Separate AON pinmux from main pinmux on Tegra194
The registers for the AON pinmux reside in a partition different from
the registers for the main pinmux. Instead of treating them as one and
the same device, split them up so that they are each their own devices.
Also add gpio-ranges properties to the corresponding GPIO controllers
such that the pinmux and GPIO controllers can be paired up properly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Vidya Sagar [Mon, 14 Nov 2022 15:53:33 +0000 (15:53 +0000)]
arm64: tegra: Add ECAM aperture info for all the PCIe controllers
Add the ECAM aperture information for all the PCIe controllers of
Tegra234.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 4 Nov 2022 11:43:49 +0000 (12:43 +0100)]
arm64: tegra: Remove clock-names from PWM nodes
The Tegra PWFM controllers use a single clock, so there's no need for a
clock-names property.
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dipen Patel [Thu, 3 Nov 2022 17:45:22 +0000 (10:45 -0700)]
arm64: tegra: Enable GTE nodes
Add and enable AON and LIC GTE nodes by default.
Signed-off-by: Dipen Patel <dipenp@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Fri, 28 Oct 2022 12:35:56 +0000 (13:35 +0100)]
arm64: tegra: Update console for Jetson Xavier and Orin
The Tegra Combined UART (TCU) is the default serial interface for Jetson
Xavier and Orin platforms and so update the bootargs for these platforms
to use the TCU.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Sandipan Patra [Mon, 19 Sep 2022 14:14:55 +0000 (19:44 +0530)]
arm64: tegra: Enable PWM users on Jetson AGX Orin
Enable additional PWM controllers in device tree so that the PWM pins on
the Jetson AGX Orin Developer Kit 40-pin header can be used.
Signed-off-by: Sandipan Patra <spatra@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 24 Oct 2022 14:05:57 +0000 (16:05 +0200)]
arm64: tegra: Add missing whitespace
The unit-address of a node should be separated from the opening brace by
a space.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 24 Oct 2022 14:05:16 +0000 (16:05 +0200)]
arm64: tegra: Sort nodes by unit-address
The P2U nodes that were recently added were not added in the correct
order. Sort them in the right place by unit-address.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Prathamesh Shete [Fri, 7 Oct 2022 16:59:41 +0000 (22:29 +0530)]
arm64: tegra: Add Tegra234 SDMMC1 device tree node
Add device tree node for Tegra234 SDMMC1 instance.
Add and enable SD card instance in device tree.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Wed, 19 Oct 2022 14:47:00 +0000 (15:47 +0100)]
arm64: tegra: Add SBSA UART for Tegra234
Populate the SBSA UART for Tegra234 and enable this UART for Jetson AGX
Orin.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Wed, 19 Oct 2022 13:29:03 +0000 (14:29 +0100)]
arm64: tegra: Add PWM fan for Jetson AGX Orin
Add the PWM fan node for the Tegra234 Jetson AGX Orin platform.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Wed, 19 Oct 2022 13:29:02 +0000 (14:29 +0100)]
arm64: tegra: Populate Tegra234 PWMs
Populate all the PWM devices for Tegra234. Finally, update the
compatible string for the existing 'pwm1' node to just be 'tegra194-pwm'
and remove the fallback to 'tegra186-pwm', which aligns with the
binding documentation.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Wed, 19 Oct 2022 13:16:13 +0000 (14:16 +0100)]
arm64: tegra: Remove unused property for I2C
Commit
156af9de0932 ("arm64: tegra: Add Tegra234 I2C devicetree nodes")
populated the I2C device nodes for Tegra234. One of these nodes
contains the property 'nvidia,hw-instance-id' which is neither
documented or used. Remove this unused property.
Fixes:
156af9de0932 ("arm64: tegra: Add Tegra234 I2C devicetree nodes")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Vidya Sagar [Wed, 28 Sep 2022 06:27:31 +0000 (11:57 +0530)]
arm64: tegra: Fix Prefetchable aperture ranges of Tegra234 PCIe controllers
commit
edf408b946d3 ("PCI: dwc: Validate iATU outbound mappings against
hardware constraints") exposes an issue with the existing partitioning of
the aperture space where the Prefetchable apertures of controllers
C5, C7 and C9 in Tegra234 cross the 32GB boundary hardware constraint.
This patch makes sure that the Prefetchable region doesn't spill over
the 32GB boundary.
Fixes:
ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Tue, 20 Sep 2022 08:11:59 +0000 (11:11 +0300)]
arm64: tegra: Add NVDEC on Tegra234
Add a device tree node for NVDEC on Tegra234.
Booting the firmware requires some information regarding offsets
within the firmware binary. These are passed through the device
tree, but since the values vary depending on the firmware version,
and the firmware itself is not available to the OS, the flasher is
expected to provide a device tree overlay with values corresponding
to the firmware it is flashing. The overlay then replaces the
placeholder values here.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Tue, 6 Sep 2022 11:01:34 +0000 (14:01 +0300)]
arm64: tegra: Fix ranges for host1x nodes
The currently specified 'ranges' properties don't actually include
all devices under the host1x bus on Tegra194 and Tegra234. Expand
them appropriately.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 21 Nov 2022 12:29:45 +0000 (13:29 +0100)]
Merge branch for-6.2/dt-bindings into for-6.2/arm64/dt
Thierry Reding [Mon, 22 Nov 2021 16:23:26 +0000 (17:23 +0100)]
dt-bindings: usb: tegra-xusb: Convert to json-schema
Convert the Tegra XUSB controller bindings from the free-form text
format to json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Thu, 17 Nov 2022 21:42:48 +0000 (22:42 +0100)]
dt-bindings: pwm: tegra: Convert to json-schema
Convert the Tegra PWFM bindings from the free-form text format to
json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 1 Jul 2022 14:52:24 +0000 (16:52 +0200)]
dt-bindings: pinctrl: tegra194: Separate instances
Tegra194 has two separate instances of the pin controller, one called
AON (in the always-on domain) and another called "main". Instead of
treating them as a single pin controller, split them up into two
separate controllers. Doing so allows the mapping between the pinmux and
GPIO controllers to be trivial identity mappings and more cleanly
separates the AON from the main IP blocks.
Note that while this changes the DT node in an incompatible way, this
doesn't have any practical implications for backwards-compatibility. The
reason for this is that device trees have only reconfigured a very
narrow subset of pins of the main controller, so the new driver will
remain backwards-compatible with old device trees.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Mon, 22 Nov 2021 12:28:40 +0000 (13:28 +0100)]
dt-bindings: pinctrl: tegra: Convert to json-schema
Convert the NVIDIA Tegra pinmux controller bindings from the free-form
text format to json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Vidya Sagar [Mon, 14 Nov 2022 15:53:32 +0000 (15:53 +0000)]
dt-bindings: PCI: tegra234: Add ECAM support
Add support for ECAM aperture that is only supported for Tegra234
devices.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Co-developed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Sandipan Patra [Mon, 19 Sep 2022 14:14:53 +0000 (19:44 +0530)]
dt-bindings: pwm: tegra: Document Tegra234 PWM
Add compatible for nvidia,tegra234-pwm with nvidia,tegra194-pwm as a
fallback. The PWM controller blocks are identical to the ones found on
the Tegra194 SoC. No driver changes are required and compatible string
"nvidia,tegra194-pwm" will be used as a fallback.
Signed-off-by: Sandipan Patra <spatra@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Tue, 20 Sep 2022 08:11:58 +0000 (11:11 +0300)]
dt-bindings: Add bindings for Tegra234 NVDEC
Update NVDEC bindings for Tegra234. This new engine version only has
two memory clients, but now requires three clocks, and as a bigger
change the engine loads firmware from a secure carveout configured by
the bootloader.
For the latter, we need to add a phandle to the memory controller
to query the location of this carveout, and several other properties
containing offsets into the firmware inside the carveout. This
carveout is not accessible by the CPU, but is needed by NVDEC,
so we need this information to be relayed from the bootloader.
As the binding was getting large with many conditional properties,
also split the Tegra234 version out into a separate file.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Mon, 3 Oct 2022 12:51:41 +0000 (13:51 +0100)]
dt-bindings: tegra: Update headers for Tegra234
Update the device-tree clock, memory, power and reset headers for
Tegra234 by adding the definitions for all the various devices.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
AngeloGioacchino Del Regno [Thu, 27 Oct 2022 09:55:04 +0000 (11:55 +0200)]
arm64: dts: mediatek: Add support for MT6795 Sony Xperia M5 smartphone
Add a basic support for the Sony Xperia M5 (codename "Holly")
smartphone, powered by a MediaTek Helio X10 SoC.
This achieves a console boot.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221027095504.37432-7-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Thu, 27 Oct 2022 09:55:03 +0000 (11:55 +0200)]
dt-bindings: arm: mediatek: Add compatible for MT6795 Sony Xperia M5
Add a compatible for the Sony Xperia M5 smartphone.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221027095504.37432-6-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Thu, 27 Oct 2022 09:55:02 +0000 (11:55 +0200)]
arm64: dts: mediatek: mt6795: Add support for eMMC/SD/SDIO controllers
Add the mmc nodes to support all of the four controllers, used for
eMMC, SD/MicroSD and SDIO storage.
All of these controller nodes are left disabled by default, as
usage is board dependent.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221027095504.37432-5-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Thu, 27 Oct 2022 09:55:01 +0000 (11:55 +0200)]
arm64: dts: mediatek: mt6795: Add support for APDMA and wire up UART DMAs
This SoC has a DMA controller with tx/rx channels for all of the
UART controller IPs: add the apdma node and wire up the DMAs on
all controllers.
When one of the UART controllers is used as a serial console,
the DMA will be automatically ignored.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221027095504.37432-4-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Thu, 27 Oct 2022 09:55:00 +0000 (11:55 +0200)]
arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg
The UART nodes had a dummy clock for early bringup, as it is
expected that these are left on by the bootloader: now that
the pericfg clock controller is supported, we can replace
them with the real clocks.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221027095504.37432-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Thu, 27 Oct 2022 09:54:59 +0000 (11:54 +0200)]
arm64: dts: mediatek: mt6795: Add topckgen, infra, peri clocks/resets
Add nodes for topckgen, infracfg and pericfg, providing various
clocks and resets and needed to support basic IPs of this SoC.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221027095504.37432-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Bo-Chen Chen [Thu, 10 Nov 2022 06:37:16 +0000 (14:37 +0800)]
arm64: dts: mediatek: cherry: Add edptx and dptx support
In cherry projects, we use edptx as the internal display interface
and use dptx as the external display interface. To support this, we
need to add more properties.
- Add pinctrls for edptx and dptx.
- Add ports for edptx and dptx.
The port connections for the internal and external display:
dp-intf0 -> edptx -> panel
dp-intf1 -> dptx
The edptx endpoint is kept empty for now, as the panel addition will
come in a later commit.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221110063716.25677-5-rex-bc.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Bo-Chen Chen [Thu, 10 Nov 2022 06:37:15 +0000 (14:37 +0800)]
arm64: dts: mediatek: cherry: Add dp-intf ports
Dp-intfs provide the pixel data to edptx and dptx. To support edptx
and dptx, we need to add dp-intf0 and dp-intf1 ports.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221110063716.25677-4-rex-bc.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Bo-Chen Chen [Thu, 10 Nov 2022 06:37:14 +0000 (14:37 +0800)]
arm64: dts: mt8195: Add edptx and dptx nodes
In MT8195, we use edptx as the internal display interface and use
dptx as the external display interface. Therefore, we need to add
these nodes to support the internal display and the external display.
- Add dp calibration data in the efuse node.
- Add edptx and dptx nodes for MT8195.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221110063716.25677-3-rex-bc.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Bo-Chen Chen [Thu, 10 Nov 2022 06:37:13 +0000 (14:37 +0800)]
arm64: dts: mt8195: Add dp-intf nodes
Dp-intfs provide the pixel data to edptx and dptx. To support edptx
and dptx, we need to add dp-intf0 and dp-intf1 nodes.
Dp-intf0 is for edptx and dp-intf1 is for dptx.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221110063716.25677-2-rex-bc.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Thu, 13 Oct 2022 15:22:12 +0000 (17:22 +0200)]
arm64: dts: mediatek: mt6797: Fix 26M oscillator unit name
Update its unit name to oscillator-26m and remove the unneeded unit
address to fix a unit_address_vs_reg warning.
Fixes:
464c510f60c6 ("arm64: dts: mediatek: add mt6797 support")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221013152212.416661-9-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Thu, 13 Oct 2022 15:22:11 +0000 (17:22 +0200)]
arm64: dts: mediatek: pumpkin-common: Fix devicetree warnings
Fix the pinctrl submodes and optee node to remove unneeded unit address,
fixing all unit_address_vs_reg warnings.
Fixes:
9983822c8cf9 ("arm64: dts: mediatek: add pumpkin board dts")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221013152212.416661-8-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Thu, 13 Oct 2022 15:22:10 +0000 (17:22 +0200)]
arm64: dts: mt2712-evb: Fix usb vbus regulators unit names
Update the names to regulator-usb-p{0-3}-vbus to fix unit_address_vs_reg
warnings for those.
Fixes:
1724f4cc5133 ("arm64: dts: Add USB3 related nodes for MT2712")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221013152212.416661-7-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Thu, 13 Oct 2022 15:22:09 +0000 (17:22 +0200)]
arm64: dts: mt2712-evb: Fix vproc fixed regulators unit names
Update the names to regulator-vproc-buck{0,1} to fix unit_addres_vs_reg
warnings for those.
Fixes:
f75dd8bdd344 ("arm64: dts: mediatek: add mt2712 cpufreq related device nodes")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221013152212.416661-6-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Thu, 13 Oct 2022 15:22:08 +0000 (17:22 +0200)]
arm64: dts: mt2712e: Fix unit address for pinctrl node
The unit address for the pinctrl node is (0x)
1000b000 and not
(0x)
10005000, which is the syscfg_pctl_a address instead.
This fixes the following warning:
arch/arm64/boot/dts/mediatek/mt2712e.dtsi:264.40-267.4: Warning
(unique_unit_address): /syscfg_pctl_a@
10005000: duplicate
unit-address (also used in node /pinctrl@
10005000)
Fixes:
f0c64340b748 ("arm64: dts: mt2712: add pintcrl device node.")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221013152212.416661-5-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Thu, 13 Oct 2022 15:22:07 +0000 (17:22 +0200)]
arm64: dts: mt2712e: Fix unit_address_vs_reg warning for oscillators
Rename the fixed-clock oscillators to remove the unit address.
This solves unit_address_vs_reg warnings.
Fixes:
5d4839709c8e ("arm64: dts: mt2712: Add clock controller device nodes")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221013152212.416661-4-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Thu, 13 Oct 2022 15:22:06 +0000 (17:22 +0200)]
arm64: dts: mt6779: Fix devicetree build warnings
Rename fixed-clock oscillators to oscillator-26m and oscillator-32k
and remove the unit address to fix the unit_address_vs_reg warning;
fix the unit address for interrupt and intpol controllers by
removing a leading zero in their unit address.
This commit fixes the following warnings:
(unit_address_vs_reg): /oscillator@0: node has a unit name, but
no reg or ranges property
(unit_address_vs_reg): /oscillator@1: node has a unit name, but
no reg or ranges property
(simple_bus_reg): /soc/interrupt-controller@
0c000000: simple-bus
unit address format error, expected "c000000"
(simple_bus_reg): /soc/intpol-controller@
0c53a650: simple-bus
unit address format error, expected "c53a650"
Fixes:
4c7a6260775d ("arm64: dts: add dts nodes for MT6779")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221013152212.416661-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Thu, 13 Oct 2022 15:22:05 +0000 (17:22 +0200)]
arm64: dts: mt7896a: Fix unit_address_vs_reg warning for oscillator
Rename the oscillator fixed-clock to oscillator-40m and remove
the unit address to fix warnings.
arch/arm64/boot/dts/mediatek/mt7986a.dtsi:17.23-22.4: Warning
(unit_address_vs_reg): /oscillator@0: node has a unit name,
but no reg or ranges property
Fixes:
1f9986b258c2 ("arm64: dts: mediatek: add clock support for mt7986a")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221013152212.416661-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
AngeloGioacchino Del Regno [Wed, 5 Oct 2022 09:34:03 +0000 (11:34 +0200)]
arm64: dts: mediatek: mt8195: Fix CPUs capacity-dmips-mhz
The capacity-dmips-mhz parameter was miscalculated: this SoC runs
the first (Cortex-A55) cluster at a maximum of 2000MHz and the
second (Cortex-A78) cluster at a maximum of 3000MHz.
In order to calculate the right capacity-dmips-mhz, the following
test was performed:
1. CPUFREQ governor was set to 'performance' on both clusters
2. Ran dhrystone with
500000000 iterations for 10 times on each cluster
3. Calculate the mean result for each cluster
4. Calculate DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz
5. Scale results to 1024:
result_c0 = (dmips_mhz_c0 - min_dmips_mhz(c0, c1)) /
(max_dmips_mhz(c0, c1) - min_dmips_mhz(c0, c1)) * 1024
The mean results for this SoC are:
Cluster 0 (LITTLE):
11990400 Dhry/s
Cluster 1 (BIG):
59809036 Dhry/s
The calculated scaled results are:
Cluster 0: 307,
934312801831 (rounded to 308)
Cluster 1: 1024
Fixes:
37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221005093404.33102-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Arnd Bergmann [Mon, 21 Nov 2022 10:01:48 +0000 (11:01 +0100)]
Merge branch 'dt/dtbo-rename' of git://git./linux/kernel/git/robh/linux into soc/dt
* 'dt/dtbo-rename' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
kbuild: Cleanup DT Overlay intermediate files as appropriate
staging: pi433: overlay: Rename overlay source file from .dts to .dtso
of: overlay: rename overlay source files from .dts to .dtso
kbuild: Allow DTB overlays to built into .dtbo.S files
kbuild: Allow DTB overlays to built from .dtso named source files
Link: https://lore.kernel.org/r/20221118211103.GA1334449-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 09:57:29 +0000 (10:57 +0100)]
Merge tag 'sunxi-dt-for-6.2-1' of https://git./linux/kernel/git/sunxi/linux into soc/dt
- Added H616 USB node
- Enabled bluetooth on Pinebook A64
- Added f1c100s PWM, I2C, CIR and LRADC nodes
- Added USB HCI0 PHYs property to H3/H5
* tag 'sunxi-dt-for-6.2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sunxi: H3/H5: Add phys property to USB HCI0
ARM: dts: suniv: f1c100s: add LRADC node
ARM: dts: suniv: f1c100s: add CIR DT node
dt-bindings: media: IR: Add F1C100s IR compatible string
ARM: dts: suniv: f1c100s: add I2C DT nodes
ARM: dts: suniv: f1c100s: add PWM node
dt-bindings: pwm: allwinner,sun4i-a10: Add F1C100s compatible
arm64: dts: allwinner: a64: enable Bluetooth on Pinebook
arm64: dts: allwinner: h616: X96 Mate: Add USB nodes
arm64: dts: allwinner: h616: OrangePi Zero 2: Add USB nodes
arm64: dts: allwinner: h616: Add USB nodes
dt-bindings: usb: Add H616 compatible string
ARM: dts: axp22x/axp809: Add GPIO controller nodes
ARM: dts: axp803/axp81x: Drop GPIO LDO pinctrl nodes
Link: https://lore.kernel.org/r/Y3fuAosinWbrj+Dy@jernej-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 09:56:43 +0000 (10:56 +0100)]
Merge tag 'at91-dt-6.2-2' of https://git./linux/kernel/git/at91/linux into soc/dt
AT91 DT for 6.2 #2
It contains:
- one typo fix for a SAMA7G5 pin; the pin is not used anywhere in the
device trees.
* tag 'at91-dt-6.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: at91: sama7g5: fix signal name of pin PD8
Link: https://lore.kernel.org/r/20221118131214.301678-1-claudiu.beznea@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Kunihiko Hayashi [Thu, 17 Nov 2022 16:32:19 +0000 (01:32 +0900)]
ARM: dts: uniphier: Add Pro5 board support
Initial version of devicetree sources for Pro5 EPCORE and ProEX boards.
These boards have UART, I2C, USB, eMMC and PCI endpoint in common.
Pro5 EPCORE board is a kind of Pro5 reference board with PCIe endpoint
card edge connector.
ProEX board shares peripherals with Linux and other systems, and some
of these ports are available in Linux.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20221117163219.3673-3-hayashi.kunihiko@socionext.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Kunihiko Hayashi [Thu, 17 Nov 2022 16:32:18 +0000 (01:32 +0900)]
dt-bindings: arm: uniphier: Add Pro5 boards
Add compatible string for Pro5 EP-Core board and ProEX board support.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221117163219.3673-2-hayashi.kunihiko@socionext.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 21 Nov 2022 09:53:52 +0000 (10:53 +0100)]
Merge tag 'samsung-dt64-6.2' of https://git./linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.2
Correct pin drive strength macros (names) and values used on Tesla FSD
SoC.
* tag 'samsung-dt64-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: fsd: fix drive strength values as per FSD HW UM
arm64: dts: fsd: fix drive strength macros as per FSD HW UM
Link: https://lore.kernel.org/r/20221116093010.18515-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Aakarsh Jain [Wed, 16 Nov 2022 09:30:09 +0000 (10:30 +0100)]
ARM: dts: exynos: Add new SoC specific compatible string for Exynos3250 SoC
Exynos3250 and Exynos5420 are using same compatible string for MFC codec
device but they have different clock hierarchy and complexity. Add new
compatible string followed by mfc-v7 fallback for Exynos3250 SoC.
Suggested-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Aakarsh Jain <aakarsh.jain@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Link: https://lore.kernel.org/r/20221114115024.69591-4-aakarsh.jain@samsung.com
Link: https://lore.kernel.org/r/20221116093010.18515-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Conor Dooley [Sun, 20 Nov 2022 11:12:13 +0000 (11:12 +0000)]
Merge branch 'riscv-thead_c9xx' into riscv-dt-for-next
The bouffalolabs stuff is going to need the thead,c906 compatible too,
so there is no point waiting the D1 stuff to land for it.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Samuel Holland [Mon, 15 Aug 2022 05:08:05 +0000 (00:08 -0500)]
dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C906 core is used in the Allwinner D1 SoC.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Quan Nguyen [Fri, 18 Nov 2022 06:51:09 +0000 (13:51 +0700)]
ARM: dts: aspeed: mtjade: Add SMPro nodes
Add SMPro nodes to Mt. Jade BMC.
Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20221118065109.2339066-1-quan@os.amperecomputing.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Quan Nguyen [Mon, 24 Oct 2022 08:11:15 +0000 (15:11 +0700)]
ARM: dts: aspeed: mtjade,mtmitchell: Add BMC SSIF nodes
Add BMC SSIF node to support IPMI in-band communication.
Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
Link: https://lore.kernel.org/r/20221024081115.3320584-1-quan@os.amperecomputing.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Zev Weiss [Tue, 8 Nov 2022 00:15:51 +0000 (16:15 -0800)]
ARM: dts: aspeed: Add Delta AHE-50DC BMC
This is a 1U Open19 power shelf with six PSUs and 50 12VDC outputs via
LM25066 efuses. It's managed by a pair of AST1250 BMCs in a redundant
active/active configuration using a PCA9541 on each I2C bus to
arbitrate access between the two.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20221108001551.18175-3-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
Zev Weiss [Tue, 8 Nov 2022 00:15:50 +0000 (16:15 -0800)]
dt-bindings: arm: aspeed: document Delta AHE-50DC BMC
Document Delta AHE-50DC BMC board compatible.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221108001551.18175-2-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
Santosh Puranik [Wed, 2 Nov 2022 22:35:54 +0000 (09:05 +1030)]
ARM: dts: aspeed: rainier: Fix pca9551 nodes
The pca9551 compatible LED drivers are under the pca9546 mux
on Rainier pass > 1. On pass 1, they are directly connected to
the aspeed i2c.
Signed-off-by: Santosh Puranik <santosh.puranik@in.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20221102223554.1738642-1-joel@jms.id.au
Eddie James [Tue, 1 Nov 2022 21:32:12 +0000 (16:32 -0500)]
ARM: dts: aspeed: p10bmc: Add occ-hwmon nodes
Add the occ-hwmon nodes in order to specify that the occ-hwmon driver
should not poll the OCC during initialization.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Link: https://lore.kernel.org/r/20221101213212.643472-1-eajames@linux.ibm.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Potin Lai [Tue, 25 Oct 2022 05:50:46 +0000 (13:50 +0800)]
ARM: dts: aspeed-g6: Add aliases for mdio nodes
Add aliases for mdio nodes so that we can use name to lookup the
bus address of Aspeed SOC.
For example:
root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio0
/ahb/mdio@
1e650000
root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio1
/ahb/mdio@
1e650008
root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio2
/ahb/mdio@
1e650010
root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio3
/ahb/mdio@
1e650018
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Link: https://lore.kernel.org/r/20221025055046.1704920-1-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Thu, 20 Oct 2022 22:44:20 +0000 (09:14 +1030)]
ARM: dts: aspeed: Remove Mihawk
The platform has been removed from OpenBMC as it is unmaintained.
Link: https://lore.kernel.org/r/20221020224420.635938-1-joel@jms.id.au
Signed-off-by: Joel Stanley <joel@jms.id.au>
Adriana Kobylak [Fri, 16 Sep 2022 19:55:35 +0000 (14:55 -0500)]
ARM: dts: aspeed: rainier,everest: Move reserved memory regions
Move the reserved regions to account for a decrease in DRAM when ECC is
enabled. ECC takes 1/9th of memory.
Running on HW with ECC off, u-boot prints:
DRAM: already initialized, 1008 MiB (capacity:1024 MiB, VGA:16 MiB, ECC:off)
And with ECC on, u-boot prints:
DRAM: already initialized, 896 MiB (capacity:1024 MiB, VGA:16 MiB, ECC:on, ECC size:896 MiB)
This implies that MCR54 is configured for ECC to be bounded at the
bottom of a 16MiB VGA memory region:
1024MiB - 16MiB (VGA) = 1008MiB
1008MiB / 9 (for ECC) = 112MiB
1008MiB - 112MiB = 896MiB (available DRAM)
The flash_memory region currently starts at offset 896MiB:
0xb8000000 (flash_memory offset) - 0x80000000 (base memory address) = 0x38000000 = 896MiB
This is the end of the available DRAM with ECC enabled and therefore it
needs to be moved.
Since the flash_memory is 64MiB in size and needs to be 64MiB aligned,
it can just be moved up by 64MiB and would sit right at the end of the
available DRAM buffer.
The ramoops region currently follows the flash_memory, but it can be
moved to sit above flash_memory which would minimize the address-space
fragmentation.
Signed-off-by: Adriana Kobylak <anoo@us.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20220916195535.1020185-1-anoo@linux.ibm.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Eddie James [Thu, 18 Aug 2022 20:24:22 +0000 (15:24 -0500)]
ARM: dts: aspeed: Add IBM Bonnell system BMC devicetree
Add a devicetree for the new Bonnell system.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Jim Wright <wrightj@linux.ibm.com>
Link: https://lore.kernel.org/r/20220818202422.741275-1-eajames@linux.ibm.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Potin Lai [Thu, 29 Sep 2022 01:31:30 +0000 (09:31 +0800)]
ARM: dts: aspeed: bletchley: Enable emmc and ehci1
Enable both emmc-controller and emmc nodes for storage soultion on
bletchley, and enable ehci1 node as second storage plan.
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220929013130.1916525-3-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Potin Lai [Thu, 29 Sep 2022 01:31:29 +0000 (09:31 +0800)]
ARM: dts: aspeed: bletchley: Update and fix gpio-line-names
Update new GPIOM7 line name, and fixed typo of GPION6 line name
New GPIO:
- GPIOM7: USB_DEBUG_PWR_BTN_N
Fixed GPIO:
- GPION6: LED_POSTCODE_5 --> LED_POSTCODE_6
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220929013130.1916525-2-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Potin Lai [Mon, 13 Jun 2022 09:51:50 +0000 (17:51 +0800)]
ARM: dts: aspeed: bletchley: Update fusb302 nodes
1. Add interrupt pin of fusb302 on each sled.
2. Add vbus-supply property in each fusb302 node.
3. Fix BMC power-role at source and data-role at host.
4. Disable PD to avoid "HARD Reset" due to incompatible PD ver.
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220613095150.21917-5-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Potin Lai [Mon, 13 Jun 2022 09:51:49 +0000 (17:51 +0800)]
ARM: dts: aspeed: bletchley: Bind presence-sledX pins via gpio-keys
Bind presence-sledX pins via gpio-keys driver to monitor and export
GPIO pin values on DBUS using phosphor-gpio-presence service.
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220613095150.21917-4-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Potin Lai [Mon, 13 Jun 2022 09:51:48 +0000 (17:51 +0800)]
ARM: dts: aspeed: bletchley: Disable GPIOV2 pull-down
The external pull-up cannot drive GPIOV2, so disable GPIOV2 internal
pull-down resistor by the request form HW team.
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220613095150.21917-3-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Potin Lai [Mon, 13 Jun 2022 09:51:47 +0000 (17:51 +0800)]
ARM: dts: aspeed: bletchley: Change LED sys_log_id to active low
change LED sys_log_id to active low base on DVT schematic.
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220613095150.21917-2-potin.lai.pt@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>