Stephen Boyd [Thu, 18 Oct 2018 22:41:51 +0000 (15:41 -0700)]
Merge branch 'clk-qcom-sdm660' into clk-next
- Qualcomm SDM660 GCC support
* clk-qcom-sdm660:
clk: qcom: gcc-sdm660: Add MODULE_LICENSE
clk: qcom: Add Global Clock controller (GCC) driver for SDM660
Stephen Boyd [Thu, 18 Oct 2018 22:41:36 +0000 (15:41 -0700)]
Merge branches 'clk-samsung', 'clk-hisi3670' and 'clk-at91-div-0' into clk-next
- Hisilicon 3670 SoC support
* clk-samsung:
dt-bindings: clock: samsung: Add SPDX license identifiers
clk: samsung: Use clk_hw API for calling clk framework from clk notifiers
clk: samsung: exynos5420: Enable PERIS clocks for suspend
clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420
clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend
clk: samsung: Remove obsolete code for Exynos4412 ISP clocks
clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs
clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume
clk: samsung: exynos5420: Use generic helper for handling suspend/resume
clk: samsung: exynos4: Use generic helper for handling suspend/resume
clk: samsung: Add support for setting registers state before suspend
clk: samsung: exynos5250: Use generic helper for handling suspend/resume
clk: samsung: s5pv210: Use generic helper for handling suspend/resume
clk: samsung: s3c64xx: Use generic helper for handling suspend/resume
clk: samsung: s3c2443: Use generic helper for handling suspend/resume
clk: samsung: s3c2412: Use generic helper for handling suspend/resume
clk: samsung: s3c2410: Use generic helper for handling suspend/resume
clk: samsung: Remove excessive include
* clk-hisi3670:
clk: hisilicon: Add clock driver for Hi3670 SoC
dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk
* clk-at91-div-0:
clk: at91: Fix division by zero in PLL recalc_rate()
Stephen Boyd [Thu, 18 Oct 2018 22:41:21 +0000 (15:41 -0700)]
Merge branch 'clk-ti' into clk-next
* clk-ti:
clk: ti: Prepare for remove of OF node name
clk: Clean up suspend/resume coding style
clk: ti: Add functions to save/restore clk context
clk: clk: Add clk_gate_restore_context function
clk: Add functions to save/restore clock context en-masse
clk: ti: dra7: add new clkctrl data
clk: ti: dra7xx: rename existing clkctrl data as compat data
clk: ti: am43xx: add new clkctrl data for am43xx
clk: ti: am43xx: rename existing clkctrl data as compat data
clk: ti: am33xx: add new clkctrl data for am33xx
clk: ti: am33xx: rename existing clkctrl data as compat data
clk: ti: clkctrl: replace dashes from clkdm name with underscore
clk: ti: clkctrl: support multiple clkctrl nodes under a cm node
dt-bindings: clock: dra7xx: add clkctrl indices for new data layout
dt-bindings: clock: am43xx: add clkctrl indices for new data layout
dt-bindings: clock: am33xx: add clkctrl indices for new data layout
Stephen Boyd [Thu, 18 Oct 2018 22:40:10 +0000 (15:40 -0700)]
Merge branch 'clk-k3-tisci' into clk-next
- TI SCI clks on K3 SoCs
* clk-k3-tisci:
clk: keystone: add missing MODULE_LICENSE
clk: keystone: Enable TISCI clocks if K3_ARCH
Stephen Boyd [Thu, 18 Oct 2018 22:39:08 +0000 (15:39 -0700)]
Merge branches 'clk-mvebu-periph-pm', 'clk-meson', 'clk-allwinner', 'clk-mvebu-dup' and 'clk-davinci' into clk-next
- S2RAM support for Marvell mvebu periph clks
* clk-mvebu-periph-pm:
clk: mvebu: armada-37xx-periph: add suspend/resume support
clk: mvebu: armada-37xx-periph: save the IP base address in the driver data
* clk-meson:
clk: meson: meson8b: use the regmap in the internal reset controller
clk: meson: meson8b: register the clock controller early
clk: meson-axg: pcie: drop the mpll3 clock parent
clk: meson: axg: round audio system master clocks down
clk: meson: clk-pll: drop hard-coded rates from pll tables
clk: meson: clk-pll: remove od parameters
clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
clk: meson: clk-pll: add enable bit
* clk-allwinner:
dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro
clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
clk: sunxi-ng: a64: Add minimal rate for video PLLs
clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks
clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs
clk: sunxi-ng: nkmp: Add constraint for maximum rate
clk: sunxi-ng: r40: Add max. rate constraint to video PLLs
clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video
clk: sunxi-ng: Add maximum rate constraint to NM PLLs
clk: sunxi-ng: h6: fix PWM gate/reset offset
clk: sunxi-ng: h6: fix bus clocks' divider position
* clk-mvebu-dup:
clk: mvebu: ap806: Remove superfluous of_clk_add_provider
* clk-davinci:
clk: davinci: kill davinci_clk_reset_assert/deassert()
Stephen Boyd [Thu, 18 Oct 2018 22:39:01 +0000 (15:39 -0700)]
Merge branches 'clk-qcom-sdm845-camcc' and 'clk-mtk-unused' into clk-next
- Qualcomm SDM845 camera clock controller
* clk-qcom-sdm845-camcc:
clk: qcom: Add camera clock controller driver for SDM845
dt-bindings: clock: Introduce QCOM Camera clock bindings
* clk-mtk-unused:
clk: mediatek: remove unused array audio_parents
Stephen Boyd [Thu, 18 Oct 2018 22:38:51 +0000 (15:38 -0700)]
Merge branch 'clk-renesas' into clk-next
* clk-renesas: (36 commits)
clk: renesas: r7s9210: Add SPI clocks
clk: renesas: r7s9210: Move table update to separate function
clk: renesas: r7s9210: Convert some clocks to early
clk: renesas: cpg-mssr: Add early clock support
clk: renesas: r8a77970: Add TPU clock
clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0
clk: renesas: cpg-mssr: Add r8a774c0 support
clk: renesas: Add r8a774c0 CPG Core Clock Definitions
clk: renesas: r8a7743: Add r8a7744 support
clk: renesas: Add r8a7744 CPG Core Clock Definitions
dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding
dt-bindings: clock: renesas: Convert to SPDX identifiers
clk: renesas: cpg-mssr: Add R7S9210 support
clk: renesas: r8a77970: Add TMU clocks
clk: renesas: r8a77970: Add CMT clocks
clk: renesas: r9a06g032: Fix UART34567 clock rate
clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI
clk: renesas: r8a77980: Add CMT clocks
clk: renesas: r8a77990: Add missing I2C7 clock
...
Stephen Boyd [Thu, 18 Oct 2018 22:33:52 +0000 (15:33 -0700)]
Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next
- Use updated printk format for OF node names
- Fix TI code to only search DT subnodes
- Various static analysis finds
* clk-dt-name:
clk: Convert to using %pOFn instead of device_node.name
* clk-ti-of-node:
clk: ti: fix OF child-node lookup
* clk-sa:
clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in probe
reset: hisilicon: fix potential NULL pointer dereference
clk: cdce925: release child device nodes
clk: qcom: clk-branch: Use true and false for boolean values
Stephen Boyd [Thu, 18 Oct 2018 22:33:28 +0000 (15:33 -0700)]
Merge branches 'clk-spdx', 'clk-qcom-dfs', 'clk-smp2s11-include', 'clk-qcom-8996-missing' and 'clk-qcom-qspi' into clk-next
- Tag various drivers with SPDX license tags
- Support dynamic frequency switching (DFS) on qcom SDM845 GCC
- Only use s2mps11 dt-binding defines instead of redefining them in the driver
- Add some more missing clks to qcom MSM8996 GCC
- Quad SPI clks on qcom SDM845
* clk-spdx:
clk: mvebu: use SPDX-License-Identifier
clk: renesas: Convert to SPDX identifiers
clk: renesas: use SPDX identifier for Renesas drivers
clk: s2mps11,s3c64xx: Add SPDX license identifiers
clk: max77686: Add SPDX license identifiers
* clk-qcom-dfs:
clk: qcom: Allocate space for NULL terimation in DFS table
clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845
clk: qcom: Add support for RCG to register for DFS
* clk-smp2s11-include:
clk: s2mps11: Use existing defines from bindings for clock IDs
* clk-qcom-8996-missing:
clk: qcom: Add some missing gcc clks for msm8996
* clk-qcom-qspi:
clk: qcom: Add qspi (Quad SPI) clocks for sdm845
clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header
Stephen Boyd [Thu, 18 Oct 2018 18:20:11 +0000 (11:20 -0700)]
clk: qcom: gcc-sdm660: Add MODULE_LICENSE
Add a module license to match the license at the top of this file and
silence a build warning.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Gregory CLEMENT [Wed, 10 Oct 2018 18:18:38 +0000 (20:18 +0200)]
clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in probe
The parent clock is get only to have its name, and then the clock is no
more used, so we can safely free it using clk_put. Furthermore as between
the successful devm_clk_get() and the devm_clk_put() call we don't exit
the probe function in error so I can use non managed version of clk_get()
and clk_put().
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Taniya Das [Tue, 25 Sep 2018 17:35:58 +0000 (18:35 +0100)]
clk: qcom: Add Global Clock controller (GCC) driver for SDM660
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
[craig: rename parents to fit upstream, and other cleanups]
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Rename gcc_660 to gcc_sdm660 and fix numbering of
defines to avoid duplicates]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Ronald Wahl [Wed, 10 Oct 2018 13:54:54 +0000 (15:54 +0200)]
clk: at91: Fix division by zero in PLL recalc_rate()
Commit
a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached MUL
and DIV values") removed a check that prevents a division by zero. This
now causes a stacktrace when booting the kernel on a at91 platform if
the PLL DIV register contains zero. This commit reintroduces this check.
Fixes:
a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached...")
Cc: <stable@vger.kernel.org>
Signed-off-by: Ronald Wahl <rwahl@gmx.de>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Manivannan Sadhasivam [Fri, 21 Sep 2018 06:01:03 +0000 (23:01 -0700)]
clk: hisilicon: Add clock driver for Hi3670 SoC
Add clock driver for HiSilicon Hi3670 SoC utilizing HiSilicon's
common clk code.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Manivannan Sadhasivam [Fri, 21 Sep 2018 06:01:00 +0000 (23:01 -0700)]
dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk
Add devicetree bindings for HiSilicon Hi3670 clock controller.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Mon, 15 Oct 2018 23:38:33 +0000 (16:38 -0700)]
clk: ti: Prepare for remove of OF node name
Another patch is going to change this code to use %pOFn for DT node
names. Fix up the code to make this easy to pick this side of the merge
instead of fixing it up in a merge commit later.
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Mon, 15 Oct 2018 17:01:41 +0000 (10:01 -0700)]
Merge tag 'clk-v4.20-samsung' of git://git./linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
- consolidation of system suspend related code in Exynos, S5P, S3C SoC clk drivers,
- fixes of system suspend support on Exynos542x (Odroid boards) and Exynos5433 SoC,
- removal of obsoleted Exynos4212 ISP clock definitions,
- correction of Exynos CPU clock implementation,
- addition of SPDX license identifiers.
* tag 'clk-v4.20-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
dt-bindings: clock: samsung: Add SPDX license identifiers
clk: samsung: Use clk_hw API for calling clk framework from clk notifiers
clk: samsung: exynos5420: Enable PERIS clocks for suspend
clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420
clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend
clk: samsung: Remove obsolete code for Exynos4412 ISP clocks
clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs
clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume
clk: samsung: exynos5420: Use generic helper for handling suspend/resume
clk: samsung: exynos4: Use generic helper for handling suspend/resume
clk: samsung: Add support for setting registers state before suspend
clk: samsung: exynos5250: Use generic helper for handling suspend/resume
clk: samsung: s5pv210: Use generic helper for handling suspend/resume
clk: samsung: s3c64xx: Use generic helper for handling suspend/resume
clk: samsung: s3c2443: Use generic helper for handling suspend/resume
clk: samsung: s3c2412: Use generic helper for handling suspend/resume
clk: samsung: s3c2410: Use generic helper for handling suspend/resume
clk: samsung: Remove excessive include
Stephen Boyd [Thu, 11 Oct 2018 16:28:13 +0000 (09:28 -0700)]
clk: Clean up suspend/resume coding style
The normal style is to use 'core' for struct clk_core pointers and to
directly access the core pointer from the clk_hw pointer when we're
within the common clk framework. Update the patches to make it a bit
easier to handle.
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Thu, 11 Oct 2018 07:22:55 +0000 (00:22 -0700)]
Merge tag 'clk-ti-for-4.20' of git://git./linux/kernel/git/kristo/linux into clk-ti
Pull TI clock driver updates from Tero Kristo:
This tag adds changes for the Texas Instruments clock driver. Included
changes are:
- clkctrl driver changes switching the layout from CM based to clockdomain
based. Needed for ongoing hwmod transition towards sysc driver. Changed
SoCs for this include am3,am4,am5,dra7.
- RTC+DDR sleep mode support code for clock save/restore. The deep sleep
states will wipe the clock register space on the SoC, requiring save/
restore support so that the state can be retained over the sleep state.
* tag 'clk-ti-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
clk: ti: Add functions to save/restore clk context
clk: clk: Add clk_gate_restore_context function
clk: Add functions to save/restore clock context en-masse
clk: ti: dra7: add new clkctrl data
clk: ti: dra7xx: rename existing clkctrl data as compat data
clk: ti: am43xx: add new clkctrl data for am43xx
clk: ti: am43xx: rename existing clkctrl data as compat data
clk: ti: am33xx: add new clkctrl data for am33xx
clk: ti: am33xx: rename existing clkctrl data as compat data
clk: ti: clkctrl: replace dashes from clkdm name with underscore
clk: ti: clkctrl: support multiple clkctrl nodes under a cm node
dt-bindings: clock: dra7xx: add clkctrl indices for new data layout
dt-bindings: clock: am43xx: add clkctrl indices for new data layout
dt-bindings: clock: am33xx: add clkctrl indices for new data layout
clk: ti: fix OF child-node lookup
Arnd Bergmann [Fri, 5 Oct 2018 16:11:15 +0000 (18:11 +0200)]
clk: keystone: add missing MODULE_LICENSE
A randconfig build showed that two clk modules have no license tag:
WARNING: modpost: missing MODULE_LICENSE() in drivers/clk/keystone/gate.o
see include/linux/module.h for more information
WARNING: modpost: missing MODULE_LICENSE() in drivers/clk/keystone/pll.o
see include/linux/module.h for more information
Add the appropriate information from the comment at the start of the
two files.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Santosh Shilimkar <ssantosh@krenel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Krzysztof Kozlowski [Thu, 27 Sep 2018 17:03:47 +0000 (19:03 +0200)]
dt-bindings: clock: samsung: Add SPDX license identifiers
Replace GPL license statements with SPDX license identifiers (GPL-2.0).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Tue, 2 Oct 2018 11:52:10 +0000 (13:52 +0200)]
clk: samsung: Use clk_hw API for calling clk framework from clk notifiers
clk_notifier_register() documentation states, that the provided notifier
callbacks associated with the notifier must not re-enter into the clk
framework by calling any top-level clk APIs. Fix this by replacing
clk_get_rate() calls with clk_hw_get_rate(), which is safe in this
context.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Mon, 24 Sep 2018 11:01:20 +0000 (13:01 +0200)]
clk: samsung: exynos5420: Enable PERIS clocks for suspend
Ensure that clocks for core SoC modules (including TZPC0..9 modules)
are enabled for suspend/resume cycle. This fixes suspend/resume
support on Exynos5422-based Odroid XU3/XU4 boards.
Suggested-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Joonyoung Shim [Mon, 24 Sep 2018 11:00:56 +0000 (13:00 +0200)]
clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420
The bit of GATE_BUS_PERIS1 for CLK_SECKEY is just reserved on
exynos5422/5800, not exynos5420. Define gate clk for exynos5420 to
handle the bit only on exynos5420.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
[m.szyprow: rewrote commit subject]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Wed, 12 Sep 2018 13:16:41 +0000 (15:16 +0200)]
clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend
All sclk_uart clocks in TOP CMU have to be kept enabled for suspend/resume
cycle, otherwise TM2(e) boards hangs before entering the suspend mode.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Wed, 11 Oct 2017 09:25:15 +0000 (11:25 +0200)]
clk: samsung: Remove obsolete code for Exynos4412 ISP clocks
Exynos4412 ISP clock are provided by separate Exynos4412 ISP clock
driver, so support for them in Exynos4-clk driver can be removed.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Thu, 6 Sep 2018 16:02:36 +0000 (18:02 +0200)]
clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs
Before entering system suspend, one has to ensure that some clocks from
TOP, CPIF and PERIC CMUs are enabled. This is needed by the firmware
to properly perform system suspend operation. Instead of adding more and
more clocks with CRITICAL flag, simply enable those clocks directly in
respective CMU registers using 'suspend_regs' feature.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Thu, 6 Sep 2018 16:02:35 +0000 (18:02 +0200)]
clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume
SoC clock drivers should suspend after every other drivers in the system,
which are using clocks and resume before them. The last stage for calling
suspend device callbacks is NOIRQ stage and there exists driver, which use
that state (dwmmc-exynos), so Exynos5433 clocks driver should also use it.
During the same stage, clocks driver will be always suspended after its
clients as a direct result of proper device probe order (deferred probe
reorders the suspend call sequence).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Thu, 6 Sep 2018 15:55:32 +0000 (17:55 +0200)]
clk: samsung: exynos5420: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Thu, 6 Sep 2018 15:55:31 +0000 (17:55 +0200)]
clk: samsung: exynos4: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Handling of PLLs is a bit different in generic code, as they are handled
in the same way as other clock registers. Such approach was already used
on later Exynos SoCs and worked fine. Tests have shown that it works also
on Exynos4 SoCs and significantly simplifies the code.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Thu, 6 Sep 2018 15:55:30 +0000 (17:55 +0200)]
clk: samsung: Add support for setting registers state before suspend
Some registers of clock controller have to be set to certain values before
entering system suspend state. Till now drivers did that on their own,
but it will be easier to handle it by generic code and let drivers simply
to provide the list of registers and their state.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Thu, 6 Sep 2018 15:55:29 +0000 (17:55 +0200)]
clk: samsung: exynos5250: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Thu, 6 Sep 2018 15:55:28 +0000 (17:55 +0200)]
clk: samsung: s5pv210: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Thu, 6 Sep 2018 15:55:27 +0000 (17:55 +0200)]
clk: samsung: s3c64xx: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
[snawrocki@kernel.org: Whitespace correction]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Russ Dill [Tue, 4 Sep 2018 06:49:37 +0000 (12:19 +0530)]
clk: ti: Add functions to save/restore clk context
SoCs like AM43XX lose clock registers context during RTC-only
suspend. Hence add functions to save/restore the clock registers
context.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Keerthy [Tue, 4 Sep 2018 06:49:36 +0000 (12:19 +0530)]
clk: clk: Add clk_gate_restore_context function
The clock gate restore context function enables or disables
the gate clocks based on the enable_count. This is done in cases
where the clock context is lost and based on the enable_count
the clock either needs to be enabled/disabled.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Russ Dill [Tue, 4 Sep 2018 06:49:35 +0000 (12:19 +0530)]
clk: Add functions to save/restore clock context en-masse
Deep enough power saving mode can result into losing context of the clock
registers also, and they need to be restored once coming back from the power
saving mode. Hence add functions to save/restore clock context.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tero Kristo [Mon, 13 Aug 2018 11:30:49 +0000 (14:30 +0300)]
clk: ti: dra7: add new clkctrl data
The new clkctrl data layout for dra7xx is split based on clockdomain
boundaries. Previously the split was based on CM boundaries. This patch
adds the new data as separate data entity, retaining the compatibility
data also for now. The compatibility data can be removed once no longer
needed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Mon, 13 Aug 2018 08:11:33 +0000 (11:11 +0300)]
clk: ti: dra7xx: rename existing clkctrl data as compat data
Rename the existing clkctrl data in preparation of upcoming clkdm
based split for it. Once the DT data has transitioned also, the
compat data can be removed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Mon, 13 Aug 2018 07:48:52 +0000 (10:48 +0300)]
clk: ti: am43xx: add new clkctrl data for am43xx
The new clkctrl data layout for am43xx is split based on clockdomain
boundaries. Previously the split was based on CM boundaries. This patch
adds the new data as separate data entity, retaining the compatibility
data also for now. The compatibility data can be removed once no longer
needed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Mon, 13 Aug 2018 07:38:40 +0000 (10:38 +0300)]
clk: ti: am43xx: rename existing clkctrl data as compat data
Rename the existing clkctrl data in preparation of upcoming clkdm
based split for it. Once the DT data has transitioned also, the
compat data can be removed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Fri, 10 Aug 2018 15:35:03 +0000 (18:35 +0300)]
clk: ti: am33xx: add new clkctrl data for am33xx
The new clkctrl data layout for am33xx is split based on clockdomain
boundaries. Previously the split was based on CM boundaries. This patch
adds the new data as separate data entity, retaining the compatibility
data also for now. The compatibility data can be removed once no longer
needed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Fri, 10 Aug 2018 15:22:02 +0000 (18:22 +0300)]
clk: ti: am33xx: rename existing clkctrl data as compat data
Rename the existing clkctrl data in preparation of upcoming clkdm
based split for it. Once the DT data has transitioned also, the
compat data can be removed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Thu, 30 Aug 2018 06:58:31 +0000 (09:58 +0300)]
clk: ti: clkctrl: replace dashes from clkdm name with underscore
The change in the DTS data node naming prevents using underscore
within the node names and force usage of dash instead. On the other
hand, clockdomains use underscore instead of dash, so this must be
replaced within the driver code so that the mapping between the two
can be done properly.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Fri, 10 Aug 2018 08:29:09 +0000 (11:29 +0300)]
clk: ti: clkctrl: support multiple clkctrl nodes under a cm node
Currently, only one clkctrl node can be added under a specific CM node
due to limitation with the implementation. Modify the code to pick-up
clockdomain name from the clkctrl node instead of CM node if provided.
Also, add a new flag to the TI clock driver so that both modes can
be supported simultaneously.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Fri, 31 Aug 2018 14:44:09 +0000 (17:44 +0300)]
dt-bindings: clock: dra7xx: add clkctrl indices for new data layout
The new data layout will be split based on clockdomain boundaries, instead
of CM boundaries. This introduces a few new clkctrl providers, that have
different indices for the clkctrl data.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Fri, 31 Aug 2018 14:42:31 +0000 (17:42 +0300)]
dt-bindings: clock: am43xx: add clkctrl indices for new data layout
The new data layout will be split based on clockdomain boundaries, instead
of CM boundaries. This introduces a few new clkctrl providers, that have
different indices for the clkctrl data.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Tero Kristo [Fri, 31 Aug 2018 14:38:57 +0000 (17:38 +0300)]
dt-bindings: clock: am33xx: add clkctrl indices for new data layout
The new data layout will be split based on clockdomain boundaries, instead
of CM boundaries. This introduces a few new clkctrl providers, that have
different indices for the clkctrl data.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Nishanth Menon [Tue, 28 Aug 2018 00:50:56 +0000 (19:50 -0500)]
clk: keystone: Enable TISCI clocks if K3_ARCH
K3_ARCH uses TISCI for clocks as well. Enable the same
for the driver support.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Bartosz Golaszewski [Thu, 21 Jun 2018 07:37:04 +0000 (09:37 +0200)]
clk: davinci: kill davinci_clk_reset_assert/deassert()
This code is no longer used. Remove it.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Gregory CLEMENT [Wed, 12 Sep 2018 15:35:49 +0000 (17:35 +0200)]
clk: mvebu: ap806: Remove superfluous of_clk_add_provider
While applying the commit
a8309cedcdce ("clk: apn806: Add eMMC clock to
system controller driver"), of_clk_add_provider was added wheres it was
already present in the probe function.
This extraneous call is harmless but not useful so remove it.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Gregory CLEMENT [Wed, 12 Sep 2018 13:40:17 +0000 (15:40 +0200)]
clk: mvebu: use SPDX-License-Identifier
Convert the remaining files to SPDX license description.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Mon, 1 Oct 2018 21:57:43 +0000 (14:57 -0700)]
Merge tag 'sunxi-clk-for-4.20' of https://git./linux/kernel/git/sunxi/linux into clk-allwinner
Pull allwinner clock changes from Maxime Ripard:
Our usual set of changes for the Allwinner SoCs clock support.
The most notable changes are:
- A bunch of changes and fixes to support the A64 display engine
- Some fixes to support the A83t display engine
* tag 'sunxi-clk-for-4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro
clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
clk: sunxi-ng: a64: Add minimal rate for video PLLs
clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks
clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs
clk: sunxi-ng: nkmp: Add constraint for maximum rate
clk: sunxi-ng: r40: Add max. rate constraint to video PLLs
clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video
clk: sunxi-ng: Add maximum rate constraint to NM PLLs
clk: sunxi-ng: h6: fix PWM gate/reset offset
clk: sunxi-ng: h6: fix bus clocks' divider position
Stephen Boyd [Mon, 1 Oct 2018 17:56:17 +0000 (10:56 -0700)]
Merge tag 'clk-renesas-for-v4.20-tag2' of git://git./linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for CMT timer clocks on R-Car V3H
- Add support for SHDI and various timer clocks on R-Car V3M
- Add support for the new RZ/A2 (R7S9210) SoC, including early clock
support for the Renesas CPG/MSSR driver
- Add support for the new RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs
- Convert DT binding includes to SPDX license identifiers
* tag 'clk-renesas-for-v4.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r7s9210: Add SPI clocks
clk: renesas: r7s9210: Move table update to separate function
clk: renesas: r7s9210: Convert some clocks to early
clk: renesas: cpg-mssr: Add early clock support
clk: renesas: r8a77970: Add TPU clock
clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0
clk: renesas: cpg-mssr: Add r8a774c0 support
clk: renesas: Add r8a774c0 CPG Core Clock Definitions
clk: renesas: r8a7743: Add r8a7744 support
clk: renesas: Add r8a7744 CPG Core Clock Definitions
dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding
dt-bindings: clock: renesas: Convert to SPDX identifiers
clk: renesas: cpg-mssr: Add R7S9210 support
clk: renesas: r8a77970: Add TMU clocks
clk: renesas: r8a77970: Add CMT clocks
clk: renesas: r9a06g032: Fix UART34567 clock rate
clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI
clk: renesas: r8a77980: Add CMT clocks
Stephen Boyd [Mon, 1 Oct 2018 17:32:32 +0000 (10:32 -0700)]
Merge tag 'meson-clk-4.20-1' of https://github.com/BayLibre/clk-meson into clk-meson
Pull meson clk driver updates from Jerome Brunet:
- clk-pll driver improvements and updates
- add axg audio controller system clocks
- drop mpll3 from the possible pcie clock parent of the axg
- register meson8b clock controller early
* tag 'meson-clk-4.20-1' of https://github.com/BayLibre/clk-meson:
clk: meson: meson8b: use the regmap in the internal reset controller
clk: meson: meson8b: register the clock controller early
clk: meson-axg: pcie: drop the mpll3 clock parent
clk: meson: axg: round audio system master clocks down
clk: meson: clk-pll: drop hard-coded rates from pll tables
clk: meson: clk-pll: remove od parameters
clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
clk: meson: clk-pll: add enable bit
Kuninori Morimoto [Tue, 25 Sep 2018 07:34:05 +0000 (09:34 +0200)]
clk: renesas: Convert to SPDX identifiers
This patch updates license to use SPDX-License-Identifier
instead of verbose license text.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[rebased against clk-spdx]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chris Brandt [Wed, 26 Sep 2018 13:39:56 +0000 (08:39 -0500)]
clk: renesas: r7s9210: Add SPI clocks
Add RSPI clocks for RZ/A2.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Chris Brandt [Mon, 24 Sep 2018 16:49:37 +0000 (11:49 -0500)]
clk: renesas: r7s9210: Move table update to separate function
Same functionality, just easier to read.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Chris Brandt [Mon, 24 Sep 2018 16:49:36 +0000 (11:49 -0500)]
clk: renesas: r7s9210: Convert some clocks to early
The OSTM timer driver for RZ/A2 uses TIMER_OF_DECLARE which requires the
ostm module clocks to be registers early in boot.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Chris Brandt [Mon, 24 Sep 2018 16:49:35 +0000 (11:49 -0500)]
clk: renesas: cpg-mssr: Add early clock support
Add support for SoCs that need to register core and module clocks early in
order to use OF drivers that exclusively use macros such as
TIMER_OF_DECLARE.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Martin Blumenstingl [Sat, 21 Jul 2018 19:14:00 +0000 (21:14 +0200)]
clk: meson: meson8b: use the regmap in the internal reset controller
For now the reset controller was using raw register access because the
early init did not initialize the regmap. However, now that clocks are
initialized early we can simply use the regmap also for the reset
controller.
No functional changes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Martin Blumenstingl [Sat, 21 Jul 2018 19:13:59 +0000 (21:13 +0200)]
clk: meson: meson8b: register the clock controller early
Until now only the reset controller (part of the clock controller
register space) was registered early in the boot process, while the
clock controller itself was registered later on.
However, some parts of the SoC are initialized early in the boot process,
such as the SRAM and the TWD timer. The bootloader already enables these
clocks so we didn't see any issues so far.
Register the clock controller early so other drivers (such as the SRAM
and TWD timer) can use the clocks early in the boot process.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Yixun Lan [Wed, 1 Aug 2018 12:16:24 +0000 (12:16 +0000)]
clk: meson-axg: pcie: drop the mpll3 clock parent
We found the PCIe driver doesn't really work with
the mpll3 clock which is actually reserved for debug,
So drop it from the mux list.
Fixes:
33b89db68236 ("clk: meson-axg: add clocks required by pcie driver")
Tested-by: Jianxin Qin <jianxin.qin@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Wed, 1 Aug 2018 14:07:32 +0000 (16:07 +0200)]
clk: meson: axg: round audio system master clocks down
Some of the master clocks provided by the axg audio clock controller are
system clock (spdifin and pdm sysclk). They are used to clock an internal
DSP of the related devices. Having them constantly rounded down instead
of closest is preferable.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Wed, 1 Aug 2018 14:00:53 +0000 (16:00 +0200)]
clk: meson: clk-pll: drop hard-coded rates from pll tables
Putting hard-coded rates inside the parameter tables assumes that
the parent is known and will never change. That's a big assumption
we should not make.
We have everything we need to recalculate the output rate using
the parent rate and the rest of the parameters. Let's do so and
drop the rates from the tables.
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Wed, 1 Aug 2018 14:00:52 +0000 (16:00 +0200)]
clk: meson: clk-pll: remove od parameters
Remove od parameters from pll clocks and add post dividers clocks
instead. Some clock, especially the one which feature several ods,
may provide output between those ods. Also, some drivers, such
as the hdmi driver, may require a more detailed control of the
clock dividers, compared to what CCF would perform automatically.
One added benefit of removing ods is that it also greatly reduce the
size of the rate parameter tables.
In the future, we could possibly take the predivider 'n' out of this
driver as well. To do so, we will need to understand the constraints
for the PLL to lock and whether or not it depends on the input clock
rate.
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Wed, 1 Aug 2018 14:00:51 +0000 (16:00 +0200)]
clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
CLK_GET_RATE_NOCACHE should only be necessary when the registers
controlling the rate of clock may change outside of CCF. On Amlogic,
it should only be the case for the hdmi pll which is directly controlled
by the display driver (WIP to fix this).
The other plls should not require this flag.
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Wed, 1 Aug 2018 14:00:50 +0000 (16:00 +0200)]
clk: meson: clk-pll: add enable bit
Add the enable the bit of the pll clocks.
These pll clocks may be disabled but we can't model this as an external
gate since the pll needs to lock when enabled.
Adding this bit allows to drop the poke of the first register of PLL.
This will be useful to model the different components of the pll using
generic clocks elements
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Sergei Shtylyov [Wed, 19 Sep 2018 18:10:40 +0000 (21:10 +0300)]
clk: renesas: r8a77970: Add TPU clock
The TPU0 clock wasn't present in the original R8A77970 patch by Daisuke
Matsushita, it was added in a later BSP version...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Geert Uytterhoeven [Tue, 18 Sep 2018 08:55:29 +0000 (10:55 +0200)]
clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
PLL0 runs at 4.8 GHz, i.e. EXTAL x 100.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Wed, 12 Sep 2018 10:41:54 +0000 (11:41 +0100)]
dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0
This patch documents RZ/G2E (a.k.a. R8A774C0) bindings for the
Clock Pulse Generator driver.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Fabrizio Castro [Wed, 12 Sep 2018 10:41:53 +0000 (11:41 +0100)]
clk: renesas: cpg-mssr: Add r8a774c0 support
Add RZ/G2E (R8A774C0) Clock Pulse Generator / Module Standby and
Software Reset support.
Based on Table 8.2g of "RZ/G Series, 2nd Generation User's Manual:
Hardware (Rev. 0.61, June 12, 2018)".
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Fabrizio Castro [Wed, 12 Sep 2018 10:41:52 +0000 (11:41 +0100)]
clk: renesas: Add r8a774c0 CPG Core Clock Definitions
Add all RZ/G2E (a.k.a. R8A774C0) Clock Pulse Generator Core
Clock Outputs, as listed in Table 8.2g ("List of Clocks
[RZ/G2E]") of the RZ/G2 Hardware User's Manual.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Biju Das [Tue, 11 Sep 2018 10:12:49 +0000 (11:12 +0100)]
clk: renesas: r8a7743: Add r8a7744 support
Add RZ/G1N (R8A7744) Clock Pulse Generator / Module Standby and Software
Reset support.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Biju Das [Tue, 11 Sep 2018 10:12:48 +0000 (11:12 +0100)]
clk: renesas: Add r8a7744 CPG Core Clock Definitions
Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's
Manual.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Biju Das [Tue, 11 Sep 2018 10:12:47 +0000 (11:12 +0100)]
dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding
Add binding documentation for the RZ/G1N (R8A7744) Clock Pulse
Generator driver.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 7 Sep 2018 01:52:28 +0000 (01:52 +0000)]
dt-bindings: clock: renesas: Convert to SPDX identifiers
This patch updates license to use SPDX-License-Identifier
instead of verbose license text on Renesas related headers.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Chris Brandt [Fri, 7 Sep 2018 16:58:49 +0000 (11:58 -0500)]
clk: renesas: cpg-mssr: Add R7S9210 support
Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module
Standby.
The Module Standby HW in the RZ/A series is very close to R-Car HW, except
for how the registers are laid out.
The MSTP registers are only 8-bits wide, there are no status registers
(MSTPSR), and the register offsets are a little different. Since the RZ/A
hardware manuals refer to these registers as the Standby Control Registers,
we'll use that name to distinguish the RZ/A type from the R-Car type.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Rob Herring <robh@kernel.org> # DT bits
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Sergei Shtylyov [Thu, 6 Sep 2018 20:28:12 +0000 (23:28 +0300)]
clk: renesas: r8a77970: Add TMU clocks
The TMU clocks weren't present in the original R8A77970 patch by Daisuke
Matsushita, they were added in a later BSP version...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Sergei Shtylyov [Wed, 5 Sep 2018 16:59:48 +0000 (19:59 +0300)]
clk: renesas: r8a77970: Add CMT clocks
Add the R8A77970 CMT module clocks.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Phil Edworthy [Fri, 31 Aug 2018 11:26:36 +0000 (12:26 +0100)]
clk: renesas: r9a06g032: Fix UART34567 clock rate
The clock for UARTs 0 through 2 is UART012, the clock for UARTs 3 through
7 is UART34567.
For UART012, we stop the clock driver from changing the clock rate. This
is because the Synopsys UART driver simply sets the reference clock to 16x
the baud rate, but doesn't check if the actual rate is within the required
tolerance. The RZ/N1 clock divider can't provide this (we have to rely on
the UART's internal divider to set the correct clock rate), so you end up
with a clock rate that is way off what you wanted.
In addition, since the clock is shared between multiple UARTs, you don't
want the driver trying to change the clock rate as it may affect the other
UARTs (which may not have been configured yet, so you don't know what baud
rate they will use). Normally, the clock rate is set early on before Linux
to some very high rate that supports all of the clock rates you want.
This change stops the UART34567 clock rate from changing for the same
reasons.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Fixes:
4c3d88526eba2143 ("clk: renesas: Renesas R9A06G032 clock driver")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Marek Szyprowski [Thu, 6 Sep 2018 15:55:26 +0000 (17:55 +0200)]
clk: samsung: s3c2443: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Thu, 6 Sep 2018 15:55:25 +0000 (17:55 +0200)]
clk: samsung: s3c2412: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Thu, 6 Sep 2018 15:55:24 +0000 (17:55 +0200)]
clk: samsung: s3c2410: Use generic helper for handling suspend/resume
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Marek Szyprowski [Thu, 6 Sep 2018 15:55:23 +0000 (17:55 +0200)]
clk: samsung: Remove excessive include
Exynos Audio SubSystem and Exynos3250 clock drivers don't use any syscore
function, so don't include linux/syscore_ops.h in their code.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Jagan Teki [Tue, 4 Sep 2018 04:40:49 +0000 (12:40 +0800)]
dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro
Allwinner A64 HDMI PHY clock has PLL_VIDEO0 as a parent.
Include the macro on dt-bindings so-that the same can be used
while defining CCU clock phandles.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Icenowy Zheng [Tue, 4 Sep 2018 04:40:44 +0000 (12:40 +0800)]
clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
Video PLLs on A64 can be set to higher rate that it is actually
supported by HW.
Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
clock driver. Interestengly, user manual specifies maximum frequency to
be 600 MHz. Historically, this data was wrong in some user manuals for
other SoCs, so more faith is put in BSP clock driver.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Jagan Teki [Tue, 4 Sep 2018 04:40:43 +0000 (12:40 +0800)]
clk: sunxi-ng: a64: Add minimal rate for video PLLs
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both A64 video PLLs to 192 MHz.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Icenowy Zheng [Mon, 20 Aug 2018 13:40:13 +0000 (21:40 +0800)]
clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks
On the H6, the MMC module clocks are fixed in the new timing mode,
i.e. they do not have a bit to select the mode. These clocks have
a 2x divider somewhere between the clock and the MMC module.
To be consistent with other SoCs supporting the new timing mode,
we model the 2x divider as a fixed post-divider on the MMC module
clocks.
This patch adds the post-dividers to the MMC clocks, following the
approach on A64.
Fixes:
524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Sergei Shtylyov [Sat, 1 Sep 2018 20:12:28 +0000 (23:12 +0300)]
clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. In fact, the layout is the same as on R-Car gen2
SoCs, so we'll need to copy the divisor tables from the R-Car gen2 driver.
We'll also need to support the SoC specific clock types, thus we're adding
CLK_TYPE_GEN3_SOC_BASE at the end of 'enum rcar_gen3_clk_types', declare
SD0H/SDH clocks in 'enum r8a77970_clk_types', and handle those clocks in
the overridden cpg_clk_register() method; then, finally, add the SD-IF
module clock (derived from the SD0 clock).
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Sergei Shtylyov [Sat, 1 Sep 2018 18:54:27 +0000 (21:54 +0300)]
clk: renesas: r8a77980: Add CMT clocks
Now that RCLK has been added by Geert, we can add the CMT module clocks.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Miquel Raynal [Fri, 13 Jul 2018 13:44:46 +0000 (15:44 +0200)]
clk: mvebu: armada-37xx-periph: add suspend/resume support
Add suspend/resume hooks in Armada 37xx peripheral clocks driver to
handle S2RAM operations.
One can think that these hooks are useless by comparing the register
values before and after a suspend/resume cycle: they will look the same
anyway. This is because of some scripts executed by the Cortex-M3 core
during ATF operations to init both the clocks and the DDR. These values
could be modified by the BL33 stage or by Linux itself and should be
preserved.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Miquel Raynal [Fri, 13 Jul 2018 13:44:45 +0000 (15:44 +0200)]
clk: mvebu: armada-37xx-periph: save the IP base address in the driver data
Prepare the introduction of suspend/resume hooks by having an easy way
to access all the registers in one go just from a device: add the IP
base address in the driver data.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Gustavo A. R. Silva [Thu, 26 Jul 2018 00:47:19 +0000 (19:47 -0500)]
reset: hisilicon: fix potential NULL pointer dereference
There is a potential execution path in which function
platform_get_resource() returns NULL. If this happens,
we will end up having a NULL pointer dereference.
Fix this by replacing devm_ioremap with devm_ioremap_resource,
which has the NULL check and the memory region request.
This code was detected with the help of Coccinelle.
Cc: stable@vger.kernel.org
Fixes:
97b7129cd2af ("reset: hisilicon: change the definition of hisi_reset_init")
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Fri, 31 Aug 2018 17:13:53 +0000 (10:13 -0700)]
Merge tag 'clk-renesas-for-v4.20-tag1' of git://git./linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Improve OSC and RCLK (watchdog) handling on R-Car Gen3 SoCs,
- Add support for SATA and Fine Display Processor (FDP) clocks on
R-Car M3-N,
- Add support for the new RZ/G2M (r8a774a1) SoC,
- Small fixes and clean ups.
* tag 'clk-renesas-for-v4.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r8a77990: Add missing I2C7 clock
clk: renesas: r8a77965: Add FDP clock
clk: renesas: cpg-mssr: Add r8a774a1 support
clk: renesas: Add r8a774a1 CPG Core Clock Definitions
clk: renesas: r8a77965: Add SATA clock
clk: renesas: r8a77980: Add RCLK for watchdog timer
clk: renesas: rcar-gen3: Add support for mode pin clock selection
clk: renesas: r8a77995: Correct RCLK handling
clk: renesas: r8a77990: Correct RCLK handling
clk: renesas: rcar-gen3: Add support for RCKSEL clock selection
clk: renesas: cpg-mssr: Add support for fixed rate clocks
clk: renesas: r8a77980: Add OSC predivider configuration and clock
clk: renesas: r8a77965: Add OSC EXTAL predivider configuration
clk: renesas: r8a7796: Add OSC EXTAL predivider configuration
clk: renesas: r8a7795: Add OSC EXTAL predivider configuration
clk: renesas: rcar-gen3: Add support for OSC EXTAL predivider
clk: renesas: rcar-gen3: Rename rint to .r
Geert Uytterhoeven [Thu, 30 Aug 2018 15:21:26 +0000 (17:21 +0200)]
clk: renesas: r8a77990: Add missing I2C7 clock
When trying to use I2C7 on R-Car E3:
renesas-cpg-mssr
e6150000.clock-controller: Cannot get module clock 1003: -2
i2c-rcar
e6690000.i2c: failed to add to PM domain always-on: -2
i2c-rcar: probe of
e6690000.i2c failed with error -2
Unlike other R-Car Gen3 SoCs, R-Car E3 has more than 7 I2C bus
interfaces. Add the forgotten module clock for the 8th instance to fix
this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Colin Ian King [Mon, 6 Aug 2018 13:44:02 +0000 (14:44 +0100)]
clk: mediatek: remove unused array audio_parents
Array audio_parents is declared but never used, hence it is redundant
and can be removed.
Cleans up clang warning:
warning: 'audio_parents' defined but not used [-Wunused-const-variable=]
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Amit Nischal [Wed, 8 Aug 2018 10:47:19 +0000 (16:17 +0530)]
clk: qcom: Add camera clock controller driver for SDM845
Add support for the camera clock controller found on SDM845
based devices. This would allow camera drivers to probe and
control their clocks.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Amit Nischal [Mon, 23 Jul 2018 11:26:32 +0000 (16:56 +0530)]
dt-bindings: clock: Introduce QCOM Camera clock bindings
Add device tree bindings for camera clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Wolfram Sang [Tue, 21 Aug 2018 22:02:14 +0000 (00:02 +0200)]
clk: renesas: use SPDX identifier for Renesas drivers
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>