Jaehoon Chung [Mon, 10 Apr 2023 02:14:16 +0000 (11:14 +0900)]
RISCV: configs: enable motorcomm phy driver
Enable motrocomm phy driver to use ethernet.
Change-Id: I71e988989fc9332b2d38339858fa49109daf6163
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Dan Carpenter [Wed, 15 Feb 2023 04:21:47 +0000 (07:21 +0300)]
net: phy: motorcomm: uninitialized variables in yt8531_link_change_notify()
These booleans are never set to false, but are just used without being
initialized.
Fixes:
4ac94f728a58 ("net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy")
Signed-off-by: Dan Carpenter <error27@gmail.com>
Reviewed-by: Frank Sae <Frank.Sae@motor-comm.com>
Link: https://lore.kernel.org/r/Y+xd2yJet2ImHLoQ@kili
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: I1b34e53290b0e99aa7d2e5c7269625cdc6a779cb
Frank Sae [Thu, 2 Feb 2023 03:00:37 +0000 (11:00 +0800)]
net: phy: Add driver for Motorcomm yt8531 gigabit ethernet phy
Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have
verified the driver on AM335x platform with yt8531 board. On the
board, yt8531 gigabit ethernet phy works in utp mode, RGMII
interface, supports 1000M/100M/10M speeds, and wol(magic package).
Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: Iaab41bb4da6fc537ec994ec09beaf65a92a4d8f6
Frank Sae [Thu, 2 Feb 2023 03:00:36 +0000 (11:00 +0800)]
net: phy: Add dts support for Motorcomm yt8531s gigabit ethernet phy
Add dts support for Motorcomm yt8531s gigabit ethernet phy.
Change yt8521_probe to support clk config of yt8531s. Becase
yt8521_probe does the things which yt8531s is needed, so
removed yt8531s function.
This patch has been verified on AM335x platform with yt8531s board.
Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: I85e5655baba7120eadad1e25c4da1797c9943154
Frank Sae [Thu, 2 Feb 2023 03:00:35 +0000 (11:00 +0800)]
net: phy: Add dts support for Motorcomm yt8521 gigabit ethernet phy
Add dts support for Motorcomm yt8521 gigabit ethernet phy.
Add ytphy_rgmii_clk_delay_config function to support dst config for
the delay of rgmii clk. This funciont is common for yt8521, yt8531s
and yt8531.
This patch has been verified on AM335x platform.
Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: I96c978c5b0ee9c6d227f771b35001e331882f33a
Frank Sae [Thu, 2 Feb 2023 03:00:34 +0000 (11:00 +0800)]
net: phy: Add BIT macro for Motorcomm yt8521/yt8531 gigabit ethernet phy
Add BIT macro for Motorcomm yt8521/yt8531 gigabit ethernet phy.
This is a preparatory patch. Add BIT macro for 0xA012 reg, and
supplement for 0xA001 and 0xA003 reg. These will be used to support dts.
Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: Ia86f4b51b61329bcc4b585ec4cfa26fe80943d02
Frank Sae [Sat, 28 Jan 2023 06:35:58 +0000 (14:35 +0800)]
net: phy: motorcomm: change the phy id of yt8521 and yt8531s to lowercase
The phy id is usually defined in lower case.
Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20230128063558.5850-2-Frank.Sae@motor-comm.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: If5dba6dda0ac08f235f08bb333298b093d180853
Frank Sae [Sat, 28 Jan 2023 06:35:57 +0000 (14:35 +0800)]
net: phy: fix the spelling problem of Sentinel
CHECK: 'sentinal' may be misspelled - perhaps 'sentinel'?
Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20230128063558.5850-1-Frank.Sae@motor-comm.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: I1b526c10df1df49984224c1a2cd8d690918f0a72
Frank [Tue, 22 Nov 2022 08:42:32 +0000 (16:42 +0800)]
net: phy: add Motorcomm YT8531S phy id.
We added patch for motorcomm.c to support YT8531S. This patch has
been tested on AM335x platform which has one YT8531S interface
card and passed all test cases.
The tested cases indluding: YT8531S UTP function with support of
10M/100M/1000M; YT8531S Fiber function with support of 100M/1000M;
and YT8531S Combo function that supports auto detection of media type.
Since most functions of YT8531S are similar to YT8521 and we reuse some
codes for YT8521 in the patch file.
Signed-off-by: Frank <Frank.Sae@motor-comm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: Ic52d4469045c2bfbf97250e137004729fc6dea46
Frank [Fri, 4 Nov 2022 08:44:41 +0000 (16:44 +0800)]
net: phy: fix yt8521 duplicated argument to & or |
cocci warnings: (new ones prefixed by >>)
>> drivers/net/phy/motorcomm.c:1122:8-35: duplicated argument to & or |
drivers/net/phy/motorcomm.c:1126:8-35: duplicated argument to & or |
drivers/net/phy/motorcomm.c:1130:8-34: duplicated argument to & or |
drivers/net/phy/motorcomm.c:1134:8-34: duplicated argument to & or |
The second YT8521_RC1R_GE_TX_DELAY_xx should be YT8521_RC1R_FE_TX_DELAY_xx.
Fixes:
70479a40954c ("net: phy: Add driver for Motorcomm yt8521 gigabit ethernet phy")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Frank <Frank.Sae@motor-comm.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: I3f15389f5b7c13d23c068b1f5c178dc9462d05d1
Frank [Fri, 28 Oct 2022 09:26:21 +0000 (17:26 +0800)]
net: phy: Add driver for Motorcomm yt8521 gigabit ethernet phy
Add a driver for the motorcomm yt8521 gigabit ethernet phy. We have verified
the driver on StarFive VisionFive development board, which is developed by
Shanghai StarFive Technology Co., Ltd.. On the board, yt8521 gigabit ethernet
phy works in utp mode, RGMII interface, supports 1000M/100M/10M speeds, and
wol(magic package).
Signed-off-by: Frank <Frank.Sae@motor-comm.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Change-Id: I98c7dd937da59afce8a5a79fa78c6cca8dc47096
Jaehoon Chung [Wed, 5 Apr 2023 00:12:46 +0000 (09:12 +0900)]
RISCV: configs: enable FUSE_FS configuration
Enable CONFIG_FUSE_FS configs and other missed configs.
Change-Id: If6c234ad9b945bd0e9b634cd03fafe681a15dfe1
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Jaehoon Chung [Mon, 3 Apr 2023 02:00:43 +0000 (11:00 +0900)]
RISCV: configs: Enanble some configs from module to static
Enable some configs from module to static.
Current module partitions is using to 32MB, so it needs to decrease
module size under 32MB.
Change-Id: I9925f0019540b984e4d400b1fbc054ee8b05e960
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Marek Pikuła [Fri, 31 Mar 2023 14:16:59 +0000 (16:16 +0200)]
config: Enable FTRACE
Required by IoT-headless preset.
Change-Id: I779f566b1e7bd74a7db168c909e1ebdb7287caee
Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>
Marek Pikuła [Fri, 31 Mar 2023 13:14:22 +0000 (15:14 +0200)]
packaging: Add version to modules directory
Prevents conflict with `filesystem` package.
Change-Id: I5281cf8f5349d82bdcaed9b66fdc0cb6896af96b
Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>
Marek Pikuła [Fri, 31 Mar 2023 13:13:17 +0000 (15:13 +0200)]
config: Enable NBD module
Useful for development with networked SD card emulation.
Change-Id: Ie02b2bdd81b44d874978497cb9dded874a9482a3
Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>
Łukasz Stelmach [Wed, 29 Mar 2023 12:28:23 +0000 (14:28 +0200)]
media: starfive: add "WITH Linux-syscall-note" to SPDX tag of uapi headers
UAPI headers licensed under GPL are supposed to have exception
"WITH Linux-syscall-note" so that they can be included into non-GPL
user space application code.
Change-Id: I129c7bf343e3da61f8d49a023b5d16699cb18796
Origin: upstream, https://github.com/starfive-tech/linux/pull/94
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
Jaehoon Chung [Wed, 29 Mar 2023 08:06:58 +0000 (17:06 +0900)]
RISCV: configs: enable USB/ETH configurations
Enable USB/ETH configuration relevant to JH7110.
Change-Id: I14b9e28cb96b38765997373375f87bdb71ca00f7
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Jaehoon Chung [Tue, 28 Mar 2023 08:32:52 +0000 (17:32 +0900)]
build: add the separated device tree file
Add the separated device tree file according to VisionFive2 board
revision.
Change-Id: I35fa7e81199f363e0cda53fd9ecac5943743a3ab
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Jaehoon Chung [Mon, 13 Mar 2023 03:31:05 +0000 (12:31 +0900)]
build: Add local build script for VisionFive2
Add local build script for VisionFive2.
Change-Id: I0ca80fd1e383b9ce62797944fba1755e315fa9c7
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Jaehoon Chung [Fri, 10 Mar 2023 06:31:40 +0000 (15:31 +0900)]
packaging: Add linux-visionfive2 spec file
Add linux-visionfive2 spec vile to build with gbs.
This is for only visionfive2 board.
Change-Id: Icc8feec48b9d77c27b4ce8f2d9468ca882d1fca1
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Marek Szulc [Fri, 19 Aug 2022 10:29:48 +0000 (12:29 +0200)]
riscv: fix riscv64 unrecognized opcode build error
Considering older gcc version, "imafd" has to be changed
to "g", in order for asm to handle "zicsr" and "zifencei"
extensions.
Support for the mentioned extensions has been added
in GCC 11.1, hence this commit may be removed
after GCC update.
The lack of this causes following errors:
Error: unrecognized opcode `csrr a5,0xc01'
Error: unrecognized opcode `csrr a2,0xc01'
Change-Id: I0768a7b1255c828c4fc319f74f2783bc7e1581bf
Signed-off-by: Marek Szulc <m.szulc3@samsung.com>
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
Jaehoon Chung [Fri, 10 Mar 2023 05:32:13 +0000 (14:32 +0900)]
RISCV: configs: Add tizen_vf2_defconfig file
Add tizen_vf2_defconfig file for VisionFive2 boardi.
This defconfig is an initial version to use Tizen on VisionFive2.
Change-Id: Ie675e71129f698d294f637f7545be323466537de
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Sia Jee Heng [Tue, 14 Mar 2023 05:03:16 +0000 (13:03 +0800)]
RISC-V: Add arch functions to support hibernation/suspend-to-disk
Low level Arch functions were created to support hibernation.
swsusp_arch_suspend() relies code from __cpu_suspend_enter() to write
cpu state onto the stack, then calling swsusp_save() to save the memory
image.
Arch specific hibernation header is implemented and is utilized by the
arch_hibernation_header_restore() and arch_hibernation_header_save()
functions. The arch specific hibernation header consists of satp, hartid,
and the cpu_resume address. The kernel built version is also need to be
saved into the hibernation image header to making sure only the same
kernel is restore when resume.
swsusp_arch_resume() creates a temporary page table that covering only
the linear map. It copies the restore code to a 'safe' page, then start
to restore the memory image. Once completed, it restores the original
kernel's page table. It then calls into __hibernate_cpu_resume()
to restore the CPU context. Finally, it follows the normal hibernation
path back to the hibernation core.
To enable hibernation/suspend to disk into RISCV, the below config
need to be enabled:
- CONFIG_ARCH_HIBERNATION_HEADER
- CONFIG_ARCH_HIBERNATION_POSSIBLE
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Sia Jee Heng [Tue, 14 Mar 2023 05:03:14 +0000 (13:03 +0800)]
RISC-V: Factor out common code of __cpu_resume_enter()
The cpu_resume() function is very similar for the suspend to disk and
suspend to ram cases. Factor out the common code into suspend_restore_csrs
macro and suspend_restore_regs macro.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Sia Jee Heng [Tue, 14 Mar 2023 05:03:13 +0000 (13:03 +0800)]
RISC-V: Change suspend_save_csrs and suspend_restore_csrs to public function
Currently suspend_save_csrs() and suspend_restore_csrs() functions are
statically defined in the suspend.c. Change the function's attribute
to public so that the functions can be used by hibernation as well.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Minda Chen [Wed, 15 Mar 2023 10:44:11 +0000 (18:44 +0800)]
dts: usb: add StarFive JH7110 USB dts configuration.
USB Glue layer and Cadence USB subnode configuration,
also includes USB and PCIe phy dts configuration.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Minda Chen [Wed, 15 Mar 2023 10:44:10 +0000 (18:44 +0800)]
usb: cdns3: add StarFive JH7110 USB driver.
There is a Cadence USB3 core for JH7110 SoCs, the cdns
core is the child of this USB wrapper module device.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Minda Chen [Wed, 15 Mar 2023 10:44:09 +0000 (18:44 +0800)]
dt-binding: Add JH7110 USB wrapper layer doc.
The dt-binding doc of Cadence USBSS-DRD controller wrapper
layer.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Peter Chen <peter.chen@kernel.org>
Minda Chen [Wed, 15 Mar 2023 10:44:08 +0000 (18:44 +0800)]
phy: starfive: add JH7110 PCIE 2.0 and USB 2.0 PHY driver.
Add Starfive JH7110 SoC PCIe 2.0 and USB 2.0 PHY driver support.
PCIe 2.0 PHY can used as USB 3.0 PHY
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Minda Chen [Wed, 15 Mar 2023 10:44:07 +0000 (18:44 +0800)]
dt-bindings: phy: Add StarFive JH7110 USB/PCIe document
Add StarFive JH7110 SoC USB 2.0/3.0 and PCIe 2.0 PHY dt-binding.
PCIe 2.0 phy can use as USB 3.0 PHY.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Jack Zhu [Fri, 10 Mar 2023 12:05:53 +0000 (20:05 +0800)]
media: starfive: Add Starfive Camera Subsystem driver
Add the driver for Starfive Camera Subsystem found on
Starfive JH7110 SoC. It is used for handing image sensor
data.
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Jack Zhu [Thu, 9 Mar 2023 10:48:44 +0000 (18:48 +0800)]
MAINTAINERS: Add Starfive Camera Subsystem driver
Add an entry for Starfive Camera Subsystem driver.
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Jack Zhu [Fri, 10 Mar 2023 12:05:51 +0000 (20:05 +0800)]
media: cadence: Add support for external dphy and JH7110 SoC
Add support for external MIPI D-PHY and Starfive JH7110 SoC which
has the cadence csi2 receiver.
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Jack Zhu [Fri, 10 Mar 2023 12:05:50 +0000 (20:05 +0800)]
media: admin-guide: Add starfive_camss.rst for Starfive Camera Subsystem
Add the file 'starfive_camss.rst' that documents the Starfive Camera
Subsystem driver which is used for handing image sensor data.
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Jack Zhu [Fri, 10 Mar 2023 12:05:49 +0000 (20:05 +0800)]
media: dt-bindings: cadence-csi2rx: Convert to DT schema
Convert DT bindings document for Cadence MIPI-CSI2 RX controller
to DT schema format and add new properties.
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Jack Zhu [Fri, 10 Mar 2023 12:05:48 +0000 (20:05 +0800)]
media: dt-bindings: Add bindings for JH7110 Camera Subsystem
Add the bindings documentation for Starfive JH7110 Camera Subsystem
which is used for handing image sensor data.
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Changhuang Liang [Wed, 15 Mar 2023 10:04:21 +0000 (03:04 -0700)]
riscv: dts: starfive: Add dphy rx node
Add dphy rx node for the StarFive JH7110 SoC. It is used to transfer CSI
camera data.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Changhuang Liang [Wed, 15 Mar 2023 10:04:20 +0000 (03:04 -0700)]
phy: starfive: Add mipi dphy rx support
Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to
transfer CSI camera data.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Changhuang Liang [Wed, 15 Mar 2023 10:04:19 +0000 (03:04 -0700)]
dt-bindings: phy: Add starfive,jh7110-dphy-rx
StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on
a M31 IP. Add a binding for it.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Jia Jie Ho [Mon, 13 Mar 2023 13:56:46 +0000 (21:56 +0800)]
crypto: starfive - Add hash and HMAC support
Adding hash/HMAC support for SHA-2 and SM3 to StarFive cryptographic
module.
Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Jia Jie Ho [Tue, 22 Nov 2022 05:56:50 +0000 (13:56 +0800)]
riscv: dts: starfive: Add crypto and DMA node for VisionFive 2
Add StarFive cryptographic module and dedicated DMA controller node to
VisionFive 2 SoCs.
Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Jia Jie Ho [Mon, 13 Mar 2023 13:56:44 +0000 (21:56 +0800)]
crypto: starfive - Add crypto engine support
Adding device probe and DMA init for StarFive cryptographic module.
Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Jia Jie Ho [Mon, 13 Mar 2023 13:56:43 +0000 (21:56 +0800)]
dt-bindings: crypto: Add StarFive crypto module
Add documentation to describe StarFive cryptographic engine.
Co-developed-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Huan Feng <huan.feng@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Jia Jie Ho [Fri, 2 Dec 2022 06:25:38 +0000 (14:25 +0800)]
riscv: dts: starfive: Add TRNG node for VisionFive 2
Adding StarFive TRNG controller node to VisionFive 2 board.
Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Walker Chen [Mon, 27 Feb 2023 12:51:36 +0000 (20:51 +0800)]
riscv: dts: starfive: add dma controller node
Add the dma controller node for the Starfive JH7110 SoC.
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Walker Chen [Tue, 14 Mar 2023 08:35:36 +0000 (16:35 +0800)]
dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMA
Add DMA reset operation in device probe and use different configuration
on CH_CFG registers according to match data. Update all uses of
of_device_is_compatible with of_device_get_match_data.
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Walker Chen [Tue, 14 Mar 2023 08:35:35 +0000 (16:35 +0800)]
dt-bindings: dma: snps,dw-axi-dmac: constrain the items of resets for JH7110 dma
The DMA controller needs two reset items to work properly on JH7110 SoC,
so there is need to constrain the items' value to 2, other platforms
have 1 reset item at most.
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Emil Renner Berthing [Sun, 6 Jun 2021 20:31:18 +0000 (22:31 +0200)]
riscv: dts: starfive: visionfive-2: Add thermal-zones
Add thermal-zones for StarFive VisionFive 2 board.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Emil Renner Berthing [Sun, 6 Jun 2021 20:31:18 +0000 (22:31 +0200)]
riscv: dts: starfive: jh7110: Add temperature sensor node
Add temperature sensor support for StarFive JH7110 SoC.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Emil Renner Berthing [Sun, 6 Jun 2021 20:31:18 +0000 (22:31 +0200)]
hwmon: (sfctemp) Add StarFive JH71x0 temperature sensor
Add driver for the StarFive JH71x0 temperature sensor. You
can enable/disable it and read temperature in milli Celcius
through sysfs.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Samin Guo <samin.guo@starfivetech.com>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Emil Renner Berthing [Sun, 6 Jun 2021 20:15:22 +0000 (22:15 +0200)]
dt-bindings: hwmon: Add starfive,jh71x0-temp
Add bindings for the temperature sensor on the StarFive JH7100 and
JH7110 SoCs.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Samin Guo [Tue, 1 Nov 2022 10:11:02 +0000 (18:11 +0800)]
riscv: dts: starfive: visionfive 2: Add configuration of gmac and phy
v1.3B:
v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and
inverse configurations.
The tx_clk of v1.3B uses an external clock and needs to be
switched to an external clock source.
v1.2A:
v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay
configurations.
v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to
switch rx and rx to external clock sources.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Samin Guo [Fri, 3 Mar 2023 08:49:31 +0000 (16:49 +0800)]
riscv: dts: starfive: jh7110: Add ethernet device nodes
Add JH7110 ethernet device node to support gmac driver for the JH7110
RISC-V SoC.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Samin Guo [Thu, 2 Mar 2023 11:52:37 +0000 (19:52 +0800)]
net: stmmac: starfive_dmac: Add phy interface settings
dwmac supports multiple modess. When working under rmii and rgmii,
you need to set different phy interfaces.
According to the dwmac document, when working in rmii, it needs to be
set to 0x4, and rgmii needs to be set to 0x1.
The phy interface needs to be set in syscon, the format is as follows:
starfive,syscon: <&syscon, offset, shift>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Samin Guo [Fri, 3 Mar 2023 08:50:58 +0000 (16:50 +0800)]
net: stmmac: Add glue layer for StarFive JH7110 SoC
This adds StarFive dwmac driver support on the StarFive JH7110 SoC.
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Yanhong Wang [Mon, 31 Oct 2022 10:08:15 +0000 (18:08 +0800)]
dt-bindings: net: Add support StarFive dwmac
Add documentation to describe StarFive dwmac driver(GMAC).
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Samin Guo [Mon, 27 Feb 2023 10:26:04 +0000 (18:26 +0800)]
dt-bindings: net: snps,dwmac: Add 'ahb' reset/reset-name
According to:
stmmac_platform.c: stmmac_probe_config_dt
stmmac_main.c: stmmac_dvr_probe
dwmac controller may require one (stmmaceth) or two (stmmaceth+ahb)
reset signals, and the maxItems of resets/reset-names is going to be 2.
The gmac of Starfive Jh7110 SOC must have two resets.
it uses snps,dwmac-5.20 IP.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Emil Renner Berthing [Sun, 7 Aug 2022 20:26:00 +0000 (22:26 +0200)]
net: stmmac: platform: Add snps,dwmac-5.20 IP compatible string
Add "snps,dwmac-5.20" compatible string for 5.20 version that can avoid
to define some platform data in the glue layer.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Emil Renner Berthing [Mon, 8 Aug 2022 15:13:34 +0000 (17:13 +0200)]
dt-bindings: net: snps,dwmac: Add dwmac-5.20 version
Add dwmac-5.20 IP version to snps.dwmac.yaml
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
William Qiu [Wed, 1 Mar 2023 08:45:11 +0000 (16:45 +0800)]
riscv: dts: starfive: Add PWM node
Adding StarFive PWM controller node to VisionFive 2 SoC.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
William Qiu [Tue, 21 Mar 2023 05:52:28 +0000 (13:52 +0800)]
pwm: starfive: Add PWM driver support
Add Pulse Width Modulation driver support for StarFive
JH7110 soc.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
William Qiu [Tue, 21 Mar 2023 05:52:27 +0000 (13:52 +0800)]
dt-bindings: PWM: Add StarFive PWM module
Add documentation to describe StarFive Pulse Width Modulation
controller driver.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
William Qiu [Thu, 2 Mar 2023 08:42:57 +0000 (16:42 +0800)]
riscv: dts: starfive: jh7110: Add qspi controller node
Add the quad spi controller node for the Starfive JH7110 SoC.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
William Qiu [Thu, 2 Mar 2023 10:52:21 +0000 (18:52 +0800)]
spi: cadence-quadspi: Add support for StarFive JH7110 QSPI
Add QSPI reset operation in device probe and add RISCV support to
QUAD SPI Kconfig.
Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Link: https://lore.kernel.org/r/20230302105221.197421-3-william.qiu@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
William Qiu [Thu, 2 Mar 2023 10:52:20 +0000 (18:52 +0800)]
dt-bindings: qspi: cdns,qspi-nor: constrain minItems/maxItems of resets
The QSPI controller needs three reset items to work properly on JH7110 SoC,
so there is need to change the maxItems's value to 3 and add minItems
whose value is equal to 2. Other platforms do not have this constraint.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Link: https://lore.kernel.org/r/20230302105221.197421-2-william.qiu@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
William Qiu [Wed, 15 Feb 2023 09:51:55 +0000 (17:51 +0800)]
riscv: dts: starfive: Add mmc node
Adds the mmc node for the StarFive JH7110 SoC.
Set mmco node to emmc and set mmc1 node to sd.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Xingyu Wu [Tue, 1 Nov 2022 13:54:04 +0000 (21:54 +0800)]
riscv: dts: jh7110: starfive: Add timer node
Add the timer node for the Starfive JH7110 SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Tue, 1 Nov 2022 13:45:06 +0000 (21:45 +0800)]
clocksource: Add StarFive timer driver
Add timer driver for the StarFive JH7110 SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Tue, 1 Nov 2022 08:50:47 +0000 (16:50 +0800)]
dt-bindings: timer: Add timer for StarFive JH7110 SoC
Add bindings for the timer on the JH7110 RISC-V SoC
by StarFive Technology Ltd.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Thu, 3 Nov 2022 02:37:08 +0000 (10:37 +0800)]
riscv: dts: starfive: jh7110: Add watchdog node
Add the watchdog node for the Starfive JH7110 SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Mon, 6 Mar 2023 02:42:07 +0000 (10:42 +0800)]
riscv: dts: starfive: jh7100: Add watchdog node
Add watchdog node for the StarFive JH7100 RISC-V SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Xingyu Wu [Thu, 3 Nov 2022 02:29:12 +0000 (10:29 +0800)]
drivers: watchdog: Add StarFive Watchdog driver
Add watchdog driver for the StarFive JH7100 and JH7110 SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Wed, 2 Nov 2022 08:48:26 +0000 (16:48 +0800)]
dt-bindings: watchdog: Add watchdog for StarFive JH7100 and JH7110
Add bindings to describe the watchdog for the StarFive JH7100/JH7110 SoC.
And Use JH7100 as first StarFive SoC with watchdog.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Xingyu Wu [Thu, 16 Mar 2023 03:05:14 +0000 (11:05 +0800)]
riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node
Add the PLL clock node for the Starfive JH7110 SoC and
modify the SYSCRG node to add PLL clocks.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Thu, 16 Mar 2023 03:05:13 +0000 (11:05 +0800)]
clk: starfive: jh7110-sys: Modify PLL clocks source
Modify PLL clocks source to be got from dts instead of
the fixed factor clocks.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Thu, 16 Mar 2023 03:05:12 +0000 (11:05 +0800)]
dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
Add PLL clock inputs from PLL clock generator.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Xingyu Wu [Thu, 16 Mar 2023 03:05:11 +0000 (11:05 +0800)]
dt-bindings: soc: starfive: syscon: Add optional patternProperties
Add optional compatible and patternProperties.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Thu, 16 Mar 2023 03:05:10 +0000 (11:05 +0800)]
clk: starfive: Add StarFive JH7110 PLL clock driver
Add driver for the StarFive JH7110 PLL clock controller.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Thu, 16 Mar 2023 03:05:09 +0000 (11:05 +0800)]
dt-bindings: clock: Add StarFive JH7110 PLL clock generator
Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Xingyu Wu [Tue, 25 Oct 2022 06:48:25 +0000 (14:48 +0800)]
riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes
Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110
System-Top-Group, Image-Signal-Process and Video-Output
clock and reset drivers for the JH7110 RISC-V SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Xingyu Wu [Tue, 14 Mar 2023 12:44:03 +0000 (20:44 +0800)]
riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks
Add DVP and HDMI TX pixel external fixed clocks and the rates are
74.25MHz and 297MHz.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Tue, 14 Mar 2023 12:44:02 +0000 (20:44 +0800)]
clk: starfive: Add StarFive JH7110 Video-Output clock driver
Add driver for the StarFive JH7110 Video-Output clock controller.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Tue, 14 Mar 2023 12:44:01 +0000 (20:44 +0800)]
reset: starfive: jh7110: Add StarFive Video-Output reset support
Add auxiliary_device_id to support StarFive JH7110 Video-Output resets
of which the auxiliary device name is "clk_starfive_jh71x0.reset-vout".
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Tue, 14 Mar 2023 12:44:00 +0000 (20:44 +0800)]
dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
Add bindings for the Video-Output clock and reset generator (VOUTCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Xingyu Wu [Tue, 14 Mar 2023 12:43:59 +0000 (20:43 +0800)]
clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver
Add driver for the StarFive JH7110 Image-Signal-Process clock controller.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Tue, 14 Mar 2023 12:43:58 +0000 (20:43 +0800)]
reset: starfive: jh7110: Add StarFive Image-Signal-Process reset support
Add auxiliary_device_id to support StarFive JH7110 Image-Signal-Process
resets of which the auxiliary device name is
"clk_starfive_jh71x0.reset-isp".
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Tue, 14 Mar 2023 12:43:57 +0000 (20:43 +0800)]
dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Emil Renner Berthing [Tue, 14 Mar 2023 12:43:56 +0000 (20:43 +0800)]
clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
Add driver for the StarFive JH7110 System-Top-Group clock controller.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Tue, 14 Mar 2023 12:43:55 +0000 (20:43 +0800)]
reset: starfive: jh7110: Add StarFive System-Top-Group reset support
Add auxiliary_device_id to support StarFive JH7110 System-Top-Group resets
of which the auxiliary device name is "clk_starfive_jh71x0.reset-stg".
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Tue, 14 Mar 2023 12:43:54 +0000 (20:43 +0800)]
dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
Add bindings for the System-Top-Group clock and reset generator (STGCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
William Qiu [Wed, 15 Mar 2023 05:58:13 +0000 (13:58 +0800)]
riscv: dts: starfive: Add syscon node
Add stg_syscon/sys_syscon/aon_syscon node for JH7110 Soc.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
William Qiu [Wed, 15 Mar 2023 05:58:12 +0000 (13:58 +0800)]
dt-bindings: soc: starfive: Add StarFive syscon doc
Add documentation to describe StarFive System Controller Registers.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Walker Chen [Mon, 16 Jan 2023 07:14:52 +0000 (15:14 +0800)]
riscv: dts: starfive: add pmu controller node
Add the pmu controller node for the Starfive JH7110 SoC. The PMU needs
to be used by other modules such as VPU, ISP, etc.
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Emil Renner Berthing [Sat, 9 Jul 2022 12:37:38 +0000 (14:37 +0200)]
riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
Add a minimal device tree for StarFive JH7110 VisionFive 2 board
which has version A and version B. Support booting and basic
clock/reset/pinctrl/uart drivers.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Jianlong Huang [Fri, 9 Sep 2022 01:41:38 +0000 (09:41 +0800)]
riscv: dts: starfive: Add StarFive JH7110 pin function definitions
Add pin function definitions for StarFive JH7110 SoC.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Emil Renner Berthing [Sat, 9 Jul 2022 12:37:38 +0000 (14:37 +0200)]
riscv: dts: starfive: Add initial StarFive JH7110 device tree
Add initial device tree for the JH7110 RISC-V SoC by StarFive
Technology Ltd.
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Sun, 19 Feb 2023 14:47:33 +0000 (22:47 +0800)]
dt-bindings: riscv: Add SiFive S7 compatible
Add a new compatible string in cpu.yaml for SiFive S7 CPU
core which is used on SiFive U74-MC core complex etc.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Emil Renner Berthing [Sun, 10 Jul 2022 20:12:44 +0000 (22:12 +0200)]
dt-bindings: interrupt-controller: Add StarFive JH7110 plic
Add compatible string for StarFive JH7110 plic.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Emil Renner Berthing [Sun, 10 Jul 2022 20:10:44 +0000 (22:10 +0200)]
dt-bindings: timer: Add StarFive JH7110 clint
Add compatible string for the StarFive JH7110 clint.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
projects / platform / kernel / linux-starfive.git / log