Andre Vieira [Wed, 7 Jul 2021 14:57:15 +0000 (15:57 +0100)]
[LIBC] Add an optimized memcmp implementation for AArch64
Differential Revision: https://reviews.llvm.org/D105441
Daniel McIntosh [Wed, 28 Apr 2021 16:15:42 +0000 (12:15 -0400)]
[SystemZ][z/OS][libcxx] mark aligned allocation tests UNSUPPORTED on z/OS
zOS doesn't support aligned allocation, so these tests are failing.
For more details on aligned allocation in zOS, see
https://reviews.llvm.org/D87611 and https://reviews.llvm.org/D90178
Reviewed By: ldionne, #libc
Differential Revision: https://reviews.llvm.org/D102798
Philip Reames [Wed, 7 Jul 2021 14:40:36 +0000 (07:40 -0700)]
[LV] Unconditionally branch from middle to scalar preheader if the scalar loop must execute (try 4)
Resubmit after the following changes:
* Fix a latent bug related to unrolling with required epilogue (see e49d65f). I believe this is the cause of the prior PPC buildbot failure.
* Disable non-latch exits for epilogue vectorization to be safe (9ffa90d)
* Split out assert movement (600624a) to reduce churn if this gets reverted again.
Previous commit message (try 3)
Resubmit after fixing test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
Previous commit message...
This is a resubmit of 3e5ce4 (which was reverted by 7fe41ac). The original commit caused a PPC build bot failure we never really got to the bottom of. I can't reproduce the issue, and the bot owner was non-responsive. In the meantime, we stumbled across an issue which seems possibly related, and worked around a latent bug in 80e8025. My best guess is that the original patch exposed that latent issue at higher frequency, but it really is just a guess.
Original commit message follows...
If we know that the scalar epilogue is required to run, modify the CFG to end the middle block with an unconditional branch to scalar preheader. This is instead of a conditional branch to either the preheader or the exit block.
The motivation to do this is to support multiple exit blocks. Specifically, the current structure forces us to identify immediate dominators and *which* exit block to branch from in the middle terminator. For the multiple exit case - where we know require scalar will hold - these questions are ill formed.
This is the last change needed to support multiple exit loops, but since the diffs are already large enough, I'm going to land this, and then enable separately. You can think of this as being NFCIish prep work, but the changes are a bit too involved for me to feel comfortable tagging the review that way.
Differential Revision: https://reviews.llvm.org/D94892
Irina Dobrescu [Mon, 5 Jul 2021 14:06:20 +0000 (15:06 +0100)]
[AArch64][GlobalISel] Lower vector types for min/max
Differential Revision: https://reviews.llvm.org/D105433
Dylan Fleming [Wed, 7 Jul 2021 13:28:13 +0000 (14:28 +0100)]
[SVE] Fix ShuffleVector cast<FixedVectorType> in truncateToMinimalBitwidths
Depends on D104239
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D105341
patacca [Wed, 7 Jul 2021 14:26:44 +0000 (16:26 +0200)]
[Polly][Isl] Use isl::union_set::unite() instead of isl::union_set::add_set(). NFC
This is part of an effort to reduce the differences between the custom C++ bindings used right now by polly in `lib/External/isl/include/isl/isl-noxceptions.h` and the official isl C++ interface.
Changes made:
- Use `isl::union_set::unite()` instead of `isl::union_set::add_set()`
- `isl-noexceptions.h` has been generated by this https://github.com/patacca/isl/commit/
390c44982b5cee7eb43f8f7a80e185e6d21466b2
Depends on D104994
Reviewed By: Meinersbur
Differential Revision: https://reviews.llvm.org/D105444
Tom Stellard [Wed, 7 Jul 2021 13:56:15 +0000 (06:56 -0700)]
unittests: Fix library dependency name
Corrects the library name of LLVMAsmParser added in
2e4ec3e5d6a3bf7f61bea6898286cba64be7b764.
Tom Stellard [Wed, 7 Jul 2021 02:46:21 +0000 (19:46 -0700)]
unittests: Fix build with LLVM_LINK_LLVM_DYLIB=ON
The build system was linking the PluginsTests unittest against libLLVM.so
and LLVMAsmParser which was causing the test to fail with this error:
LLVM ERROR: inconsistency in registered CommandLine options
We need to add llvm libraries to LLVM_LINK_COMPONENTS so that
they are dropped from the linker arguments when linking with
LLVM_LINK_LLVM_DYLIB=ON
Reviewed By: aeubanks
Differential Revision: https://reviews.llvm.org/D105523
Louis Dionne [Wed, 7 Jul 2021 13:45:26 +0000 (09:45 -0400)]
[libc++] NFC: Fix incorrect comments in CMake
Sander de Smalen [Wed, 7 Jul 2021 12:19:59 +0000 (13:19 +0100)]
[CostModel] Express cost(urem) as cost(div+mul+sub) when set to Expand.
The Legalizer expands the operations of urem/srem into a div+mul+sub or divrem
when those are legal/custom. This patch changes the cost-model to reflect that
cost.
Since there is no 'divrem' Instruction in LLVM IR, the cost of divrem
is assumed to be the same as div+mul+sub since the three operations will
need to be executed at runtime regardless.
Patch co-authored by David Sherwood (@david-arm)
Reviewed By: RKSimon, paulwalker-arm
Differential Revision: https://reviews.llvm.org/D103799
Alexander Belyaev [Wed, 7 Jul 2021 13:09:59 +0000 (15:09 +0200)]
[mlir] Use indices instead of affine maps when composing 2 reshape ops.
https://llvm.discourse.group/t/rfc-reshape-ops-restructuring/3310
Differential Revision: https://reviews.llvm.org/D105550
Arnold Schwaighofer [Tue, 6 Jul 2021 18:26:17 +0000 (11:26 -0700)]
[coro async] Move code to proper switch
While upstreaming patches this code somehow was applied to the wrong switch statement.
Differential Revision: https://reviews.llvm.org/D105504
Zarko Todorovski [Wed, 7 Jul 2021 12:42:50 +0000 (08:42 -0400)]
[AIX] Use VSSRC/VSFRC Register classes for f32/f64 callee arguments on P8 and above
Adding usage of VSSRC and VSFRC when adding the live in registers on AIX.
This matches the behaviour of the rest of PPC Subtargets.
Reviewed By: nemanjai, #powerpc
Differential Revision: https://reviews.llvm.org/D104396
Simon Pilgrim [Wed, 7 Jul 2021 12:52:39 +0000 (13:52 +0100)]
[IndVarSimplify][X86] Regenerate loop-invariant-conditions.ll test checks
Simon Pilgrim [Wed, 7 Jul 2021 11:55:07 +0000 (12:55 +0100)]
[CostModel][X86] Adjust sext/zext SSE/AVX legalized costs based on llvm-mca reports.
Update costs based on the worst case costs from the script in D103695.
Move to using legalized types wherever possible, which allows us to prune the cost tables.
Alexey Bataev [Fri, 2 Jul 2021 20:45:56 +0000 (13:45 -0700)]
[OPENMP]Remove const firstprivate allocation as a variable in a constant space.
Current implementation is not compatible with asynchronous target
regions, need to remove it.
Differential Revision: https://reviews.llvm.org/D105375
Alexander Belyaev [Wed, 7 Jul 2021 11:45:33 +0000 (13:45 +0200)]
[mlir] Move common reshapeops-related code to ReshapeOpsUtils.h.
This is a first step to move (Tensor)Expand/CollapseShapeOp to tensor/memref
dialects.
Differential Revision: https://reviews.llvm.org/D105547
Nicolas Vasilache [Wed, 7 Jul 2021 08:08:20 +0000 (08:08 +0000)]
[mlir][Linalg] Rewrite PadTensorOp to enable its comprehensive bufferization.
Add the rewrite of PadTensorOp to InitTensor + InsertSlice before the
bufferization analysis starts.
This is exercised via a more advanced integration test.
Since the new behavior triggers folding, 2 tests need to be updated.
One of those seems to exhibit a folding issue with `switch` and is modified.
Differential Revision: https://reviews.llvm.org/D105549
Yi Zhang [Tue, 6 Jul 2021 16:01:11 +0000 (16:01 +0000)]
Refactor GenericPadTensorOpVectorizationPattern
Refactor the original code to rewrite a PadTensorOp into a
sequence of InitTensorOp, FillOp and InsertSliceOp without
vectorization by default. `GenericPadTensorOpVectorizationPattern`
provides a customized OptimizeCopyFn to vectorize the
copying step.
Reviewed By: silvas, nicolasvasilache, springerm
Differential Revision: https://reviews.llvm.org/D105293
Nicolas Vasilache [Wed, 7 Jul 2021 08:02:02 +0000 (08:02 +0000)]
[mlir][Linalg] Proper handling of ForOp and TiledLoopOp
The `bufferizesToMemoryRead` condition was too optimistics in the case
of operands that map to a block argument.
This is the case for ForOp and TiledLoopOp.
For such ops, forward the call to all uses of the matching BBArg.
Differential Revision: https://reviews.llvm.org/D105540
Simon Pilgrim [Tue, 6 Jul 2021 18:49:01 +0000 (19:49 +0100)]
[CostModel][X86] Adjust sitofp/uitofp SSE/AVX legalized costs based on llvm-mca reports.
Update (mainly) vXi8/vXi16 -> vXf32/vXf64 sitofp/uitofp costs based on the worst case costs from the script in D103695.
Move to using legalized types wherever possible, which allows us to prune the cost tables.
LLVM GN Syncbot [Wed, 7 Jul 2021 10:14:59 +0000 (10:14 +0000)]
[gn build] Port
6829db727e9e
Louis Dionne [Thu, 24 Jun 2021 17:29:35 +0000 (13:29 -0400)]
[libc++] Implement copyable-box from Ranges
Differential Revision: https://reviews.llvm.org/D102135
Max Kazantsev [Wed, 7 Jul 2021 10:00:48 +0000 (17:00 +0700)]
[NFC] Remove duplicate function calls
Removed repeated call of L->getHeader(). Now using previously stored return value.
Patch by Dmitry Makogon!
Differential Revision: https://reviews.llvm.org/D105535
Reviewed By: mkazantsev
Dylan Fleming [Wed, 7 Jul 2021 09:21:46 +0000 (10:21 +0100)]
[SVE] Fixed cast<FixedVectorType> on scalable vector in SelectionDAGBuilder::getUniformBase
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D105350
Adrian Kuegel [Wed, 7 Jul 2021 08:32:56 +0000 (10:32 +0200)]
Add Log1pOp to complex dialect.
Also add a lowering pattern from Complex to Standard/Math dialect.
Differential Revision: https://reviews.llvm.org/D105538
Bairen Yi [Wed, 7 Jul 2021 09:26:50 +0000 (11:26 +0200)]
[mlir][CAPI] Export mlirValueEqual in C API
Somehow it is not exported in C API.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D105422
David Green [Wed, 7 Jul 2021 09:21:07 +0000 (10:21 +0100)]
[DAG] Reassociate Add with Or
We already have reassociation code for Adds and Ors separately in DAG
combiner, this adds it for the combination of the two where Ors act like
Adds. It reassociates (add (or (x, c), y) -> (add (add (x, y), c)) where
we know that the Ors operands have no common bits set, and the Or has
one use.
Differential Revision: https://reviews.llvm.org/D104765
Saiyedul Islam [Thu, 1 Jul 2021 14:06:35 +0000 (19:36 +0530)]
[Clang] Add test dependency on llvm-ar
Following clang driver tests invoke llvm-ar, so ensure that
check-clang rebuilds llvm-ar.
* test/Driver/clang-offload-bundler.c
* test/Driver/hip-link-save-temps.hip
* test/Driver/hip-link-static-library.hip
* test/Driver/hip-toolchain-rdc-static-lib.hip
Differential Revision: https://reviews.llvm.org/D105285
Dylan Fleming [Wed, 7 Jul 2021 08:33:52 +0000 (09:33 +0100)]
[SVE] Fix cast<FixedVectorType> in truncateToMinimalBitwidths
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D104239
Alex Zinenko [Wed, 7 Jul 2021 07:46:27 +0000 (09:46 +0200)]
[mlir] factor out common parts of the converstion to the LLVM dialect
"Standard-to-LLVM" conversion is one of the oldest passes in existence. It has
become quite large due to the size of the Standard dialect itself, which is
being split into multiple smaller dialects. Furthermore, several conversion
features are useful for any dialect that is being converted to the LLVM
dialect, which, without this refactoring, creates a dependency from those
conversions to the "standard-to-llvm" one.
Put several of the reusable utilities from this conversion to a separate
library, namely:
- type converter from builtin to LLVM dialect types;
- utility for building and accessing values of LLVM structure type;
- utility for building and accessing values that represent memref in the LLVM
dialect;
- lowering options applicable everywhere.
Additionally, remove the type wrapping/unwrapping notion from the type
converter that is no longer relevant since LLVM types has been reimplemented as
first-class MLIR types.
Reviewed By: pifon2a
Differential Revision: https://reviews.llvm.org/D105534
Nicolas Vasilache [Wed, 7 Jul 2021 06:59:23 +0000 (06:59 +0000)]
[mlir][Linalg] Add an InitTensor -> DimOp canonicalization pattern.
Differential Revision: https://reviews.llvm.org/D105537
Jay Foad [Tue, 6 Jul 2021 16:46:39 +0000 (17:46 +0100)]
[AMDGPU] Simplify tablegen files. NFC.
There is no need to cast records to strings before comparing them.
Jean Perier [Wed, 7 Jul 2021 08:06:43 +0000 (10:06 +0200)]
[flang] Create HostAssocDetails symbols when needed for mis-parsed ArrayRef
Name resolution is always creating symbols with HostAssocDetails
for host variable names inside internal procedures. This helps lowering
identifying and dealing with such variables inside internal procedures.
However, the case where the variable appears in an ArrayRef mis-parsed
as a FunctionRef goes through a different name resolution path that did
not create such HostAssocDetails when needed. Pointer assignment RHS
are also skipping this path.
Add the logic to create HostAssocDetails for host symbols inisde internal
procedures that appear in mis-parsed ArrayRef or in pointer assignment RHS.
Differential Revision: https://reviews.llvm.org/D105464
Srishti Srivastava [Wed, 7 Jul 2021 07:31:38 +0000 (13:01 +0530)]
[MLIR] Simplify affine.if having yield values and trivial conditions
When an affine.if operation is returning/yielding results and has a
trivially true or false condition, then its 'then' or 'else' block,
respectively, is promoted to the affine.if's parent block and then, the
affine.if operation is replaced by the correct results/yield values.
Relevant test cases are also added.
Signed-off-by: Srishti Srivastava <srishti.srivastava@polymagelabs.com>
Differential Revision: https://reviews.llvm.org/D105418
Fangrui Song [Wed, 7 Jul 2021 06:02:33 +0000 (23:02 -0700)]
[llvm-readobj][test] Improve grouped option test
Uday Bondhugula [Wed, 23 Jun 2021 04:47:46 +0000 (10:17 +0530)]
[MLIR] Split out GPU ops library from Transforms
Split out GPU ops library from GPU transforms. This allows libraries to
depend on GPU Ops without needing/building its transforms.
Differential Revision: https://reviews.llvm.org/D105472
Hsiangkai Wang [Tue, 25 May 2021 08:13:34 +0000 (16:13 +0800)]
[Clang][RISCV] Implement vlseg and vlsegff.
Differential Revision: https://reviews.llvm.org/D103527
Stanislav Mekhanoshin [Tue, 6 Jul 2021 22:37:18 +0000 (15:37 -0700)]
[AMDGPU] isPassEnabled() helper to check cl::opt and OptLevel
We have several checks for both cl::opt and OptLevel over our
pass config, although these checks do not properly work if
default value of a cl::opt will be false. Create a helper to
use instead and properly handle it. NFC for now.
Differential Revision: https://reviews.llvm.org/D105517
Johannes Doerfert [Sat, 26 Jun 2021 00:01:31 +0000 (19:01 -0500)]
[Attributor][FIX] Replace uses first, then values
Before we replaced value by registering all their uses. However, as we
replace a value old uses become stale. We now replace values explicitly
and keep track of "new values" when doing so to avoid replacing only
uses in stale/old values but not their replacements.
Johannes Doerfert [Sat, 26 Jun 2021 05:12:41 +0000 (00:12 -0500)]
[Attriibutor][NFC] Precommit heap-2-stack test case
Johannes Doerfert [Sat, 8 May 2021 04:18:24 +0000 (23:18 -0500)]
[Attributor] Introduce a helper function to deal with undef + none
We often need to deal with the value lattice that contains none and
undef as special values. A simple helper makes this much nicer.
Differential Revision: https://reviews.llvm.org/D103857
Johannes Doerfert [Tue, 22 Jun 2021 18:19:39 +0000 (13:19 -0500)]
[Attributor] Simplify operands inside of simplification AAs first
When we do simplification via AAPotentialValues or AAValueConstantRange
we need to simplify the operands of an instruction we deconstruct first.
This does not only improve the result, see for example range.ll, but is
required as we allow outside AAs to provide simplification rules via
callbacks. If we do ignore the simplification rules and base other
simplifications on the IR instead we can create an inconsistent state.
Uday Bondhugula [Tue, 6 Jul 2021 09:54:43 +0000 (15:24 +0530)]
[MLIR][NFC] Move normalizeAffine methods to Affine utils
The normalizeAffineForOp and normalizedAffineParallel methods were
misplaced in the AffineLoopNormalize pass file while their declarations
were in affine utils. Move these to affine Utils.cpp. NFC.
Differential Revision: https://reviews.llvm.org/D105468
Tom Stellard [Wed, 7 Jul 2021 01:46:21 +0000 (18:46 -0700)]
tests/CodeGen: Use %python lit substitution when invoking python
This will use the python that LLVM was configured to use rather than
python from PATH.
Reviewed By: serge-sans-paille
Differential Revision: https://reviews.llvm.org/D105224
Nemanja Ivanovic [Wed, 7 Jul 2021 00:15:45 +0000 (19:15 -0500)]
[PowerPC] Re-enable combine for i64 BSWAP on targets without LDBRX
The combine was disabled in
4e22c7265d86 as it caused failures in
the ppc64be-multistage (bootstrap) bot.
It turns out that the combine did not correctly update the MMO for
the high load which caused aliased stores to be reported as unaliased.
This patch fixes that problem and re-enables the combine.
Matheus Izvekov [Fri, 2 Jul 2021 22:56:16 +0000 (00:56 +0200)]
[clang] fixes named return of variables with dependent alignment
Named return of a variable with aligned attribute would
trip an assert in case alignment was dependent.
Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>
Reviewed By: rsmith
Differential Revision: https://reviews.llvm.org/D105380
Eli Friedman [Wed, 7 Jul 2021 00:01:40 +0000 (17:01 -0700)]
[AArch64] Add more tests related to vselect with constant condition.
Not a complete set of tests, but a starting point if anyone wants to
look at improving this.
Eli Friedman [Wed, 7 Jul 2021 00:00:07 +0000 (17:00 -0700)]
[AArch64] Sync isDef32 to the current x86 version.
We should probably come up with some better way to do this, but let's
make sure to catch known issues for now.
David Blaikie [Tue, 6 Jul 2021 23:25:45 +0000 (16:25 -0700)]
DebugInfo: Mangle K&R declarations for debug info linkage names
This fixes a gap in the `overloadable` attribute support (K&R declared
functions would get mangled symbol names, but that name wouldn't be
represented in the debug info linkage name field for the function) and
in -funique-internal-linkage-names (this came up in review discussion on
D98799) where K&R static declarations would not get the uniqued linkage
names.
Stanislav Mekhanoshin [Tue, 6 Jul 2021 21:34:28 +0000 (14:34 -0700)]
[AMDGPU] Move atomic expand past infer address spaces
There are cases where infer address spaces pass cannot yet
infer an address space in the opt pipeline and then in the
llc pipeline it runs too late for atomic expand pass to
benefit from a specific address space.
Move atomic expand pass past the infer address spaces.
Fixes: SWDEV-293410
Differential Revision: https://reviews.llvm.org/D105511
Stanislav Mekhanoshin [Tue, 6 Jul 2021 22:10:58 +0000 (15:10 -0700)]
[AMDGPU] Do not run IR optimizations at -O0
Differential Revision: https://reviews.llvm.org/D105515
Stanislav Mekhanoshin [Tue, 6 Jul 2021 21:58:42 +0000 (14:58 -0700)]
[AMDGPU] Fix pass name of AMDGPULowerKernelAttributes. NFC.
This was obviously copy-pasted.
Tony Tye [Fri, 2 Jul 2021 22:10:17 +0000 (22:10 +0000)]
[NFC][AMDGPU] Add link to AMD GPU gfx906 instruction set architecture
Reviewed By: kzhuravl
Differential Revision: https://reviews.llvm.org/D105377
Krzysztof Parzyszek [Fri, 25 Jun 2021 14:30:59 +0000 (09:30 -0500)]
[Hexagon] Generate trap/undef if misaligned access is detected
This applies to memory accesses to (compile-time) constant addresses
(such as memory-mapped registers). Currently when a misaligned access
to such an address is detected, a fatal error is reported. This change
will emit a remark, and the compilation will continue with a trap,
and "undef" (for loads) emitted.
This fixes https://llvm.org/PR50838.
Differential Revision: https://reviews.llvm.org/D50524
Nico Weber [Tue, 6 Jul 2021 13:30:20 +0000 (09:30 -0400)]
[lld/mac] Give several LTO tests an "lto-" prefix
Differential Revision: https://reviews.llvm.org/D105476
Eli Friedman [Tue, 6 Jul 2021 18:25:49 +0000 (11:25 -0700)]
Recommit [ScalarEvolution] Make getMinusSCEV() fail for unrelated pointers.
As part of making ScalarEvolution's handling of pointers consistent, we
want to forbid multiplying a pointer by -1 (or any other value). This
means we can't blindly subtract pointers.
There are a few ways we could deal with this:
1. We could completely forbid subtracting pointers in getMinusSCEV()
2. We could forbid subracting pointers with different pointer bases
(this patch).
3. We could try to ptrtoint pointer operands.
The option in this patch is more friendly to non-integral pointers: code
that works with normal pointers will also work with non-integral
pointers. And it seems like there are very few places that actually
benefit from the third option.
As a minimal patch, the ScalarEvolution implementation of getMinusSCEV
still ends up subtracting pointers if they have the same base. This
should eliminate the shared pointer base, but eventually we'll need to
rewrite it to avoid negating the pointer base. I plan to do this as a
separate step to allow measuring the compile-time impact.
This doesn't cause obvious functional changes in most cases; the one
case that is significantly affected is ICmpZero handling in LSR (which
is the source of almost all the test changes). The resulting changes
seem okay to me, but suggestions welcome. As an alternative, I tried
explicitly ptrtoint'ing the operands, but the result doesn't seem
obviously better.
I deleted the test lsr-undef-in-binop.ll becuase I couldn't figure out
how to repair it to test what it was actually trying to test.
Recommitting with fix to MemoryDepChecker::isDependent.
Differential Revision: https://reviews.llvm.org/D104806
Louis Dionne [Tue, 6 Jul 2021 16:33:28 +0000 (12:33 -0400)]
[libc++] Do not set CMAKE_BUILD_WITH_INSTALL_NAME_DIR
I'm not sure what that gains us, and it creates a problem when
trying to run the tests against libc++ with a custom install name
dir (e.g. /usr/lib), since the library that we link against (in
the build tree) will advertise itself as /usr/lib/libc++.dylib,
so we end up linking against the system dylib at runtime.
Differential Revision: https://reviews.llvm.org/D105499
Louis Dionne [Tue, 6 Jul 2021 18:45:41 +0000 (14:45 -0400)]
[libc++] NFC: Sort header lists and remove outdated comments in modulemap
Craig Topper [Tue, 6 Jul 2021 17:25:37 +0000 (10:25 -0700)]
[RISCV] Implement lround*/llround*/lrint*/llrint* with fcvt instruction with -fno-math-errno
These are fp->int conversions using either RMM or dynamic rounding modes.
The lround and lrint opcodes have a return type of either i32 or
i64 depending on sizeof(long) in the frontend which should follow
xlen. llround/llrint should always return i64 so we'll need a libcall
for those on rv32.
The frontend will only emit the intrinsics if -fno-math-errno is in
effect otherwise a libcall will be emitted which will not use
these ISD opcodes.
gcc also does this optimization.
Reviewed By: arcbbb
Differential Revision: https://reviews.llvm.org/D105206
Michał Górny [Tue, 6 Jul 2021 16:10:50 +0000 (18:10 +0200)]
[compiler-rt] [test] Fix asan symbolize tests on py3.10
Update the asan_symbolize_script for changes in argparse output
in Python 3.10. The parser output 'options' instead of 'optional
arguments'.
Differential Revision: https://reviews.llvm.org/D105489
Michał Górny [Tue, 6 Jul 2021 11:58:26 +0000 (13:58 +0200)]
[openmp] [test] Add missing <limits> include to capacity_nthreads
Differential Revision: https://reviews.llvm.org/D105474
David Green [Tue, 6 Jul 2021 18:23:52 +0000 (19:23 +0100)]
[Tests] Update some tests for D104765. NFC
LLVM GN Syncbot [Tue, 6 Jul 2021 18:17:43 +0000 (18:17 +0000)]
[gn build] Port
8517a26d442f
Eli Friedman [Tue, 6 Jul 2021 18:16:01 +0000 (11:16 -0700)]
Revert "[ScalarEvolution] Make getMinusSCEV() fail for unrelated pointers."
This reverts commit
74d6ce5d5f169e9cf3fac0eb1042602e286dd2b9.
Seeing crashes on buildbots in MemoryDepChecker::isDependent.
Jake Egan [Tue, 6 Jul 2021 18:15:10 +0000 (14:15 -0400)]
[AIX] Define __TOS_AIX__ predefined macro
%%%
Transfer the predefined macro, __TOS_AIX__, from the AIX XL C/C++ compilers.
__TOS_AIX__ indicates that the target operating system is AIX.
%%%
Reviewed By: cebowleratibm
Differential Revision: https://reviews.llvm.org/D103587
Louis Dionne [Tue, 6 Jul 2021 14:39:01 +0000 (10:39 -0400)]
[libc++][docs] Overhaul the documentation for building and using libc++
This patch overhauls the documentation around building libc++
for vendors, and using libc++ for end-users. It also:
- Removes mention of the standalone build, which we've been trying to
get rid of for a long time.
- Removes mention of using a local ABI installation, which we don't do
and is documented as "not recommended".
- Removes mention of the separate libc++filesystem.a library, which isn't
relevant anymore since filesystem support is in the main library.
- Adds mention of the GDB pretty printers and how to use them.
Fangrui Song [Tue, 6 Jul 2021 18:08:47 +0000 (11:08 -0700)]
[profile][test] Improve coverage-linkage.cpp with ld.lld --gc-sections
The __llvm_prf_names section uses SHF_GNU_RETAIN. However, GNU ld before 2015-10
(https://sourceware.org/bugzilla/show_bug.cgi?id=19161) neither supports it nor
retains __llvm_prf_names according to __start___llvm_prf_names. So --gc-sections
does not work on such old GNU ld.
This is not a problem for gold and sufficiently new lld.
Sanjay Patel [Tue, 6 Jul 2021 17:23:43 +0000 (13:23 -0400)]
[InstSimplify] fix bug in poison propagation for FP ops
If any operand of a math op is poison, that takes
precedence over general undef/NaN.
This should not be visible with binary ops because
it requires 2 constant operands to trigger (and if
both operands of a binop are constant, that should
get handled first in ConstantFolding).
Sanjay Patel [Tue, 6 Jul 2021 16:28:21 +0000 (12:28 -0400)]
[InstSimplify][test] add tests for poison propagation through FP calls; NFC
Christopher Di Bella [Tue, 29 Jun 2021 02:32:59 +0000 (02:32 +0000)]
[libcxx][modularisation] splices `<iterator>` into individual headers
Differential Revision: https://reviews.llvm.org/D105076
Philip Reames [Tue, 6 Jul 2021 17:49:13 +0000 (10:49 -0700)]
[LV] Disable epilogue vectorization for non-latch exits
When skimming through old review discussion, I noticed a post commit comment on an earlier patch which had gone unaddressed. Better late (4 months), than never right?
I'm not aware of an active problem with the combination of non-latch exits and epilogue vectorization, but the interaction was not considered and I'm not modivated to make epilogue vectorization work with early exits. If there were a bug in the interaction, it would be pretty hard to hit right now (as we canonicalize towards bottom tested loops), but an upcoming change to allow multiple exit loops will greatly increase the chance for error. Thus, let's play it safe for now.
Philip Reames [Tue, 6 Jul 2021 15:11:11 +0000 (08:11 -0700)]
[LoopVersion] Move an assert [nfc-ish]
Eli Friedman [Tue, 6 Jul 2021 17:54:41 +0000 (10:54 -0700)]
[ScalarEvolution] Make getMinusSCEV() fail for unrelated pointers.
As part of making ScalarEvolution's handling of pointers consistent, we
want to forbid multiplying a pointer by -1 (or any other value). This
means we can't blindly subtract pointers.
There are a few ways we could deal with this:
1. We could completely forbid subtracting pointers in getMinusSCEV()
2. We could forbid subracting pointers with different pointer bases
(this patch).
3. We could try to ptrtoint pointer operands.
The option in this patch is more friendly to non-integral pointers: code
that works with normal pointers will also work with non-integral
pointers. And it seems like there are very few places that actually
benefit from the third option.
As a minimal patch, the ScalarEvolution implementation of getMinusSCEV
still ends up subtracting pointers if they have the same base. This
should eliminate the shared pointer base, but eventually we'll need to
rewrite it to avoid negating the pointer base. I plan to do this as a
separate step to allow measuring the compile-time impact.
This doesn't cause obvious functional changes in most cases; the one
case that is significantly affected is ICmpZero handling in LSR (which
is the source of almost all the test changes). The resulting changes
seem okay to me, but suggestions welcome. As an alternative, I tried
explicitly ptrtoint'ing the operands, but the result doesn't seem
obviously better.
I deleted the test lsr-undef-in-binop.ll becuase I couldn't figure out
how to repair it to test what it was actually trying to test.
Differential Revision: https://reviews.llvm.org/D104806
Jonas Paulsson [Tue, 6 Jul 2021 17:14:47 +0000 (19:14 +0200)]
[SystemZ] Support the 'N' code for the odd register in inline-asm.
The odd register of a (128 bit) register pair is accessed with the 'N' code
with an inline assembly operand.
Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D105502
Jeremy Morse [Wed, 2 Jun 2021 14:14:37 +0000 (15:14 +0100)]
[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations
This patch emits DBG_INSTR_REFs for two remaining flavours of variable
locations that weren't supported: copies, and inter-block VRegs. There are
still some locations that must be represented by DBG_VALUE such as
constants, but they're mostly independent of optimisations.
For variable locations that refer to values defined in different blocks,
vregs are allocated before isel begins, but the defining instruction
might not exist until late in isel. To get around this, emit
DBG_INSTR_REFs in a "half done" state, where the first operand refers to a
VReg. Then at the end of isel, patch these back up to refer to
instructions, using the finalizeDebugInstrRefs method.
Copies are something that I complained about the original RFC, and I
really don't want to have to put instruction numbers on copies. They don't
define a value: they move them. To address this isel, salvageCopySSA
interprets:
* COPYs,
* SUBREG_TO_REG,
* Anything that isCopyInstr thinks is a copy.
And follows chains of copies back to the defining instruction that they
read from. This relies on any physical registers that COPYs read being
defined in the same block, or being entry-block arguments. For the former
we can put an instruction number on the defining instruction; for the
latter we can drop a DBG_PHI that reads the incoming value.
Differential Revision: https://reviews.llvm.org/D88896
Craig Topper [Tue, 6 Jul 2021 16:55:57 +0000 (09:55 -0700)]
[RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors.
This adds a DAG combine to detect sext/zext inputs and emit a
new ISD opcode. The extends will either be removed or replaced
with narrower extends.
Isel patterns are used to match add and widening mul to vwmacc
similar to the recently added vmacc patterns.
There's still some work to be to match vmulsu.
We should also rewrite splats that were extended as scalars and
then splatted.
Reviewed By: arcbbb
Differential Revision: https://reviews.llvm.org/D104802
Arnold Schwaighofer [Thu, 1 Apr 2021 22:51:56 +0000 (15:51 -0700)]
Fix coro lowering of single predecessor phis
Code assumes that uses of single predecessor phis are not live accross
suspend points. Cleanup any single predecessor phis preceeding the code
making this assumption.
rdar://
76020301
Differential Revision: https://reviews.llvm.org/D105488
Simon Pilgrim [Tue, 6 Jul 2021 16:27:46 +0000 (17:27 +0100)]
[CostModel][X86] fptosi/fptoui to i8/i16 are truncated from fptosi to i32
Provide a generic fallback that performs the fptosi to i32 types, then truncates to sub-i32 scalars.
These numbers can be tweaked for specific sse levels, but we should get the default handling in place first.
ShihPo Hung [Sat, 3 Jul 2021 18:17:40 +0000 (02:17 +0800)]
[RISCV] Remove Zvamo implication for v1.0-rc change
As v1.0-rc specs say Zvamo is removed from standard extension,
Zvamo has to be specified explicitly.
Reviewed By: evandro
Differential Revision: https://reviews.llvm.org/D105396
Jonas Paulsson [Sat, 5 Jun 2021 00:32:03 +0000 (19:32 -0500)]
[SystemZ] Generate XC loop for memset 0 of variable length.
Benchmarking has shown that it is worthwhile to implement a variable length
memset of 0 with XC (exclusive or) like gcc does, instead of using a libcall.
This requires the use of the EXecute Relative Long (EXRL) instruction which
can now be done in a framework that can also be used with other target
instructions (not just XC).
Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D103865
Jon Chesterfield [Tue, 6 Jul 2021 16:06:36 +0000 (17:06 +0100)]
[libomptarget][nfc] Group environment variables, drop accesses to DeviceInfo global
[libomptarget][nfc] Group environment variables, drop accesses to DeviceInfo global
Folds some duplicates logic into a helper function, passes the new environment
struct into getLaunchVals which no longer reads the DeviceInfo global.
Implemented on top of D105237
Reviewed By: dhruvachak
Differential Revision: https://reviews.llvm.org/D105239
Alexey Bataev [Mon, 28 Jun 2021 14:22:27 +0000 (07:22 -0700)]
[SLP]Fix non-determinism in PHI sorting.
Compare type IDs and DFS numbering for basic block instead of addresses
to fix non-determinism.
Differential Revision: https://reviews.llvm.org/D105031
Arnold Schwaighofer [Tue, 6 Jul 2021 14:55:58 +0000 (07:55 -0700)]
Use swift mangling for resume functions
The resume partial functions generated for swift suspend points will now
use a Swift mangling suffix.
Await resume partial functions will use the suffix 'TQ'[0-9]+'_' (e.g "...TQ0_")
and suspend resume partial functions will use the suffix 'TY'[0-9]+'_'
(e.g "...TY1_").
Reviewed By: nate_chandler
Differential Revision: https://reviews.llvm.org/D104144
Nico Weber [Tue, 6 Jul 2021 04:25:01 +0000 (00:25 -0400)]
[lld/mac] Partially implement -export_dynamic
This implements the part of -export_dynamic that adds external
symbols as dead strip roots even for executables.
It does not yet implement the effect -export_dynamic has for LTO.
I tried just replacing `config->outputType != MH_EXECUTE` with
`(config->outputType != MH_EXECUTE || config->exportDynamic)` in
LTO.cpp, but then local symbols make it into the symbol table too,
which is too much (and also doesn't match ld64). So punt on this
for now until I understand it better.
(D91583 may or may not be related too).
Differential Revision: https://reviews.llvm.org/D105482
Bradley Smith [Thu, 1 Jul 2021 16:48:24 +0000 (16:48 +0000)]
[AArch64][SVE] Fix selection failures for scalable MLOAD nodes with passthru
Differential Revision: https://reviews.llvm.org/D105348
Louis Dionne [Tue, 6 Jul 2021 14:04:54 +0000 (10:04 -0400)]
[libc++] NFC: Remove outdated link to TS status
Louis Dionne [Tue, 6 Jul 2021 13:46:29 +0000 (09:46 -0400)]
[libc++] NFC: Move the status docs to their own subdirectory
This cleans up the libcxx/doc directory quite a bit and will avoid the
proliferation of status files in that directory as new standards are voted.
Florian Hahn [Tue, 6 Jul 2021 12:08:28 +0000 (13:08 +0100)]
Recommit "[VPlan] Add VPReductionPHIRecipe (NFC)." and follow-ups.
This reverts commit
706bbfb35bd31051e46ac77aab3e9b2dbc3abe78.
The committed version moves the definition of VPReductionPHIRecipe out
of an ifdef only intended for ::print helpers. This should resolve the
build failures that caused the revert
Simon Pilgrim [Tue, 6 Jul 2021 12:58:38 +0000 (13:58 +0100)]
[CostModel][X86] i8/i16 sitofp/uitofp are sext/zext to i32 for sitofp
Provide a generic fallback that extends sub-i32 scalars before using the existing sitofp instructions.
These numbers can be tweaked for specific sse levels, but we should get the default handling in place first.
We get the extension for free for non-vector loads.
Nico Weber [Tue, 6 Jul 2021 12:49:43 +0000 (08:49 -0400)]
Revert "[profile][test] Improve coverage-linkage.cpp"
This reverts commit
36ba86fe8a29cdf3251b786db7f342efde666cb2.
Fails on some bots, see comments on
https://reviews.llvm.org/rG36ba86fe8a29cdf3251b786db7f342efde666cb2
Louis Dionne [Mon, 5 Jul 2021 16:27:14 +0000 (12:27 -0400)]
[runtimes] Move enable_32bit to the DSL
This is necessary for from-scratch configurations to support the 32-bit
mode of the test suite.
Differential Revision: https://reviews.llvm.org/D105435
Kerry McLaughlin [Tue, 6 Jul 2021 09:49:43 +0000 (10:49 +0100)]
[LV] Prevent vectorization with unsupported element types.
This patch adds a TTI function, isElementTypeLegalForScalableVector, to query
whether it is possible to vectorize a given element type. This is called by
isLegalToVectorizeInstTypesForScalable to reject scalable vectorization if
any of the instruction types in the loop are unsupported, e.g:
int foo(__int128_t* ptr, int N)
#pragma clang loop vectorize_width(4, scalable)
for (int i=0; i<N; ++i)
ptr[i] = ptr[i] + 42;
This example currently crashes if we attempt to vectorize since i128 is not a
supported type for scalable vectorization.
Reviewed By: sdesmalen, david-arm
Differential Revision: https://reviews.llvm.org/D102253
Peter Waller [Wed, 26 May 2021 14:18:27 +0000 (14:18 +0000)]
[CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory
This avoids the use of the vector unit for copying from scalar to
vector. There is an extra ptrue instruction, but a predicate register
with the ptrue pattern populated is likely to be free in the context of
real code.
Tests were generated from a template to cover the axes mentioned at the
top of the test file.
Co-authored-by: Francesco Petrogalli <francesco.petrogalli@arm.com>
Differential Revision: https://reviews.llvm.org/D103170
Florian Mayer [Wed, 30 Jun 2021 14:47:53 +0000 (15:47 +0100)]
[hwasan] Fix incorrect candidate matching for stack OOB.
We would find an address with matching tag, only to discover in
ShowCandidate that it's very far away from [stack].
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D105197
Florian Hahn [Tue, 6 Jul 2021 11:06:54 +0000 (12:06 +0100)]
Revert "[VPlan] Add VPReductionPHIRecipe (NFC)." and follow-ups
This reverts commit
3fed6d443f802c43aade1b5b1b09f5e2f8b3edb1,
bbcbf21ae60c928e07dde6a1c468763b3209d1e6 and
6c3451cd76cbd0cd973d9c2b08b168dcd0bce3c2.
The changes causing build failures with certain configurations, e.g.
https://lab.llvm.org/buildbot/#/builders/67/builds/3365/steps/6/logs/stdio
lib/libLLVMVectorize.a(LoopVectorize.cpp.o): In function `llvm::VPRecipeBuilder::tryToCreateWidenRecipe(llvm::Instruction*, llvm::ArrayRef<llvm::VPValue*>, llvm::VFRange&, std::unique_ptr<llvm::VPlan, std::default_delete<llvm::VPlan> >&) [clone .localalias.8]':
LoopVectorize.cpp:(.text._ZN4llvm15VPRecipeBuilder22tryToCreateWidenRecipeEPNS_11InstructionENS_8ArrayRefIPNS_7VPValueEEERNS_7VFRangeERSt10unique_ptrINS_5VPlanESt14default_deleteISA_EE+0x63b): undefined reference to `vtable for llvm::VPReductionPHIRecipe'
collect2: error: ld returned 1 exit status
Florian Hahn [Tue, 6 Jul 2021 10:59:33 +0000 (11:59 +0100)]
[VPlan] Mark overriden function in VPWidenPHIRecipe as virtual.
VPReductionRecipe overrides those implementations. Mark them as virtual
in the VPWidenPHIRecipe to unbreak build in certain configurations.
Florian Hahn [Tue, 6 Jul 2021 10:39:44 +0000 (11:39 +0100)]
[VPlan] Add destructor to VPReductionRecipe to unbreak build.
Attempt to unbreak
https://lab.llvm.org/buildbot/#/builders/67/builds/3363/steps/6/logs/stdio
Jay Foad [Tue, 6 Jul 2021 10:24:06 +0000 (11:24 +0100)]
[AMDGPU] Remove outdated comment and tidy up. NFC.
This was left over from D94746.
Florian Hahn [Tue, 6 Jul 2021 06:09:54 +0000 (07:09 +0100)]
[VPlan] Add VPReductionPHIRecipe (NFC).
This patch is a first step towards splitting up VPWidenPHIRecipe into
separate recipes for the 3 distinct cases they model:
1. reduction phis,
2. first-order recurrence phis,
3. pointer induction phis.
This allows untangling the code generation and allows us to reduce the
reliance on LoopVectorizationCostModel during VPlan code generation.
Discussed/suggested in D100102, D100113, D104197.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D104989