review.tizen.org Git - platform/upstream/mesa.git/log

radv/llvm: fix enabled_channels for compressed exports

The old values seemed to work fine, but the ISA docs recommend 0x0,0x3,0xc
and 0xf:

COMPR==1: export half-dword enable. Valid values are: 0x0,3,c,f
[0] enables VSRC0 : R,G from one VGPR (R in low bits, G high)
[2] enables VSRC1 : B,A from one VGPR (B in low bits, A high)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9459>

aco: set compr for fp16 exports

Obviously this didn't affect correctness. Not sure about performance.

It also changes enabled_channels to match radeonsi.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: f29c81f863c ("aco: use VOP2 for v_cvt_pkrtz_f16_f32 if possible")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9459>

meson: detect winflex/bison only on native win32

we want to detect the native bison when cross-compiling

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9375>

radeonsi: update pipe_screen::num_contexts

This allows skipping mutex locking. Don't take the aux context into account.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9356>

gallium: add pipe_screen::num_contexts for skipping mutex locking in util_range

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9356>

gallium/u_threaded: don't sync in create_stream_output_target

Manhattan needs this.

radeonsi can handle it since https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9028/diffs?commit_id=33ac9dec91d07ef353e110ac376842d84ec539b4.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9356>

freedreno: threaded_context async flush support

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

freedreno: threaded_context support

Currently only initialized for a6xx, mostly because that is the easiest
setup for me to test and debug at the moment. But the couple a6xx changes
should not require counterparts in older gens.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

freedreno: Check cb0 in rebind_resource()

Previously we were expecting cb0 to be user_buffer. (We did in some
cases upload it to a gpu buffer, but this was an internally allocated
buffer and not something subject to rebind.) But with TC it becomes
a gpu buffer.

(Technically, with pctx->const_uploader, we shouldn't hit the rebind
path for cb0, but better to not try to be overly clever.. sooner or
later that would bite us.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

freedreno/a6xx: Move UBWC demotion to first sampler view bind

With threaded_context, CSO creation happens in the frontend thread,
which means it is no longer safe to do blits (if needed, for sampler
views with format that cannot be UBWC). So move this to the first
time that the sampler view is bound.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

freedreno: Add transfer_pool_unsync

With threaded_context, in the TC_TRANSFER_MAP_UNSYNC case, we are
getting called from the frontend thread, rather than driver thread.
So we need a different slab_child_pool for that.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

freedreno: Add fd_replace_buffer_storage()

This will be used by threaded_context to avoid stalls in the
DISCARD_WHOLE_RESOURCE case (and DISCARD_RANGE cases that can
be promoted to DISCARD_WHOLE_RESOURCE).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

freedreno: Extract out helper for transfer-map flag munging

Split out the usage simplification from main part of transfer_map and
handle the threaded-context specific TC_TRANSFER_x flags.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

freedreno: Extend threaded_transfer

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

freedreno: Extend threaded_resource

No functional change, just big churny

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

freedreno: Restructure transfer_map()

Separate the parts that, with threaded_context, can be called from
either driver or frontend thread.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

freedreno: Split out batch/resource tracking

For threaded_context, to properly handle replace_buffer_storage, we'll
need to handle multiple "iterations" of a resource using the same
tracking in order to implement transfer_map() correctly.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

freedreno: Factor out common fd_resource init

Before adding new things that would need initialization in both paths,
refactor out a shared helper.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

freedreno: Fix u_blitter constant-buffer leak

We didn't see this before without threaded_context because we (normally)
wouldn't upload cb0 (the slot u_blitter uses). But with cb0 getting
uploaded we could hit a leak due to constant state only being restored
in the fd_blitter_clear() path. Move cb0 save to the one path that uses
it.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

gallium/u_threaded: use mesa_log for debug msgs

On android, this will show up in logcat, rather than being lost into the
ether.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

gallium/u_threaded: Add helper to assert driver thread

Useful for drivers to add some sanity checks to avoid/detect threading
issues caused by things that might be called (indirectly) from frontend
thread.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

util: Extract thread-id helpers from u_current

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9323>

Revert "glsl: default to compat shaders in compat profile"

This reverts commit 6c8cc9be12dc5d6c0d2386d6addb69d8f2fb5399.

A spec bug was resolved confirming the original behaviour. Also it
seems the game Foundation no longer depends on the incorrect
behaviour.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9486>

gallium/indices: Use "__restrict" to help the compiler

In a perf trace translate_quads_uint2uint_last2last_prdisable() was
showing up as a huge hot spot. Digging through the assembly on arm64
found that the compiler wasn't doing any read caching. Specifically,
the generated code looked roughly like this:

  out[j+0] = in[i+0];
  out[j+1] = in[i+1];
  out[j+2] = in[i+3];
  out[j+3] = in[i+1];
  out[j+4] = in[i+2];
  out[j+5] = in[i+3];

...and the compiler was loading "i+1" and "i+3" from memory twice for
no reason (instead of caching it).

If we sprinkle generous amounts of the `__restrict` keyword then the
compiler is able to be much smarter. Not only does it avoid
double-loading but it also generates better instructions. It uses two
LDRD instructions instead of 6 LDR instructions and uses some STRD
too.

In one example test this increased FPS from ~25.7 to ~34.5.

Change-Id: I88bf8bd9ac421fe48a7d6961e224425c3ae7beee
Reported-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9485>

vulkan/alloc: Use char * for pointer arithmetic

MSVC doesn't like arithmetic on void *.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9511>

vulkan/util: Add a type parameter to vk_multialloc_add

We also switch from using __alignof__ to alignof() in util/macros.h
which works on MSVC with the one unfortunate downside of requiring an
actual type and not a value.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9511>

vulkan/alloc: Add VK_MULTIALLOC_DECL macros

These both declare the variable and add it to the allocator in one go.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9511>

vk/alloc: Handle zero sizes better in vk_multialloc_add

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9511>

vulkan: Use ALWAYS_INLINE for multialloc

This way it properly compiles on Visual Studio.

Fixes: 145444d2651b "anv: Move multialloc to common code"
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9506>

intel: Rename "GEN_" prefix used in common code to "INTEL_"

This patch renames all macros with "GEN_" prefix defined in
common code.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9413>

intel: Fix broken alignment due to gen_ prefix renaming

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9413>

intel: Rename "gen_" prefix used in common code to "intel_"

This patch renames functions, structures, enums etc. with "gen_"
prefix defined in common code.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9413>

intel: Rename files with gen_ prefix in common code to intel_

Changes in this patch include:
- Rename all files in src/intel/common path
- Update the filenames used in source and build files

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9413>

intel/fs: Handle payload node interference in destinations

Starting with d0d039a4d3f49, we emit writes to the push constant chunk
of the payload to stomp out-of-bounds data to zero for Vulkan.  Then, in
369eab9420cfc, we started emitting shader preamble code for emulated
push constants on Gen12.5 parts.  In either of these cases, we can run
into issues if we don't have a proper live range for some of the payload
registers where they get used for something and then smashed by our push
handling code.  We've not seen many issues with this yet because it only
happens when you have dead push constants.

Fixes: d0d039a4d3f49 "anv: Emit pushed UBO bounds checking code..."
Fixes: 369eab9420cfc "intel/fs: Emit code for Gen12-HP indirect..."
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9501>

intel/fs: Use INTEL_MASK for pushish constant address masking

It's easier to compare with the HW docs than a pile of hex.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9501>

turnip: fix alpha to coverage in no color and unused attachment cases

In cases where the alpha coverage is enabled but the color attachment is
either unused or absent there should be a dummy mrt to make the draw behave
correctly.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Yannik Marek <yannik@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8952>

zink: Fix a thinko in instance setup

It really does help to size these arrays correctly.

Fixes: 2b4fcf0a063 zink: generate instance creation code with a python script
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9499>

turnip: Remove unused TU_DEBUG_IR3 flag

Replaced by IR3_SHADER_DEBUG=disasm,{vs,...,cs} and unused since the
commit referenced below.

Fixes: 808992fc506 ("tu: Use the ir3 shader API")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8249>

ci/freedreno: Mark another a5xx TF flake.

Showed up with an iommu fault preceding it each time it failed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9488>

radeonsi: enable RGP on gfx10.3

It seems to work on VanGogh.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9492>

radv: Drop CreateRenderPass

We can use the generic fall-back which calls CreateRenderPass2 instead.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8857>

radv/meta: Use CreateRenderPass2

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8857>

anv: Drop CreateRenderPass

Fall back to the common implementation instead.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8857>

vulkan: Preserve preserve attachments in CreateRenderPass

This is trivial so I really don't know why it wasn't handled in the
initial turnip code.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8857>

vulkan: Add some asserts and checks for multiview in CreateRenderPass

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8857>

vulkan: Use correct aspectMask in CreateRenderPass

If a VkRenderPassInputAttachmentAspectCreateInfo is provided, we use the
aspects specified there. Otherwise, we default to every aspect in the
format. For attachments which are not input attachments, aspectMask is
left zero.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8857>

anv: Move vk_format helpers to common code

The Android ones we put in anv_android.c. Maybe one day we'll want a
vk_android.h to put some common Android stuff but, for now, let's keep
it contained to ANV's android code.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8857>

vulkan: Use VK_MULTIALLOC in CreateRenderPass

The variable-length stack allocations are causing issues with ubsan when
the array size is zero. Also, a heap allocation is probably safer.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8857>

anv: Move multialloc to common code

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8857>

turnip: Move the CreateRenderPass wrapper to common code

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8857>

ac: remove switch cases for pc_lines for compute-only chips

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9389>

ac,radeonsi: use correct VGPR granularity on Aldebaran

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9389>

ac: handle bigger instruction prefetch for Aldebaran

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9389>

ac/llvm: unpack thread IDs on Aldebaran

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9389>

ac: set the TCC line size for Aldebaran

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9389>

ac,radeonsi: add sampler changes for Aldebaran

- no 3D and cube textures
- no mipmapping
- no border color
- image_sample is the only supported opcode with a sampler (behaves like _lz)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9389>

amd: add Aldebaran chip enum

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9389>

ir3: use OPC_GETBUF to get size of sampler buffers

The maximum value which OPC_GETSIZE could return for one dimension
is 0x007ff0, however sampler buffer could be much bigger.
Blob uses OPC_GETBUF for them.

Fixes tests:
dEQP-VK.memory.pipeline_barrier.transfer_dst_uniform_texel_buffer.1048576

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9391>

freedreno/a5xx: port handling of PIPE_BUFFER textures from a6xx

Otherwise, we won't be able to use OPC_GETBUF to get their size.

After this change we also could get rid of the hack for OPC_GETSIZE
which scaled the size for texture buffers.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9391>

turnip: fix SP_HS_WAVE_INPUT_SIZE value

It appears that storage for varyings in a wave has an upper
limit of wavesize * max_a831 where max_a831 is 64.
Exceeding the limit seam to force gpu to reduce primitives
processed per wave, at least calculations make sense with
such interpretation.

With blob SP_HS_WAVE_INPUT_SIZE never exceeds 64 and setting
it to 65 in freedreno leads to a hang.

Copied from the commit to freedreno e5499ca2

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8187>

freedreno/computerator: Add branching example

Mainly to be able to test label resolution without having to replace a
shader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9463>

ir3/parser: Add ability to specify branchstack

This lets you test branching with computerator.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9463>

ir3/parser: Support labels

This fixes the assembly for many scenarios where you want to use shader
replacement.

Note: unfortunately this leaks the identifier string created while
lexing, but I couldn't find a way to avoid leaking it except for
bringing in ralloc or something (which would be way more complicated).
The only other place doing something similar in mesa is the glsl parser,
which is using ralloc (actually a linear context).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9463>

freedreno/computerator: Fix example assembly

Use the new bindless cat6 syntax for a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9463>

ir3/parser: Fix parsing of "0.0" in @const line

Trying to specify a floating-point value in a @const line would result
in it getting interpreted as a FLUT value and failing parsing. Fix this
by making the various FLUT tokens include the surrounding parentheses.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9463>

etnaviv: Fix point sprite Z,W coordinate replacement

Mesa fixed pipeline texture loading on programmable pipeline hardware emits
a generic fragment shader program which contains gl_TexCoord.xyzw as a vec4
and then expects to configure the varying assignments to the shader in the
pipeline command stream, to select what is wired to the XYZW fragment shader
inputs.

This gl_TexCoord.xyzw is turned into texture load with projection (TGSI TXP
opcode, similar for NIR). Texture load with projection does not exist in the
Vivante GPU as a dedicated opcode and is emulated. The shader program first
divides texture coordinates XYZ by projector W and then applies regular TEX
opcode to load the texture (i.e. TEX(gl_TexCoord.xyzw/gl_TexCoord.wwww)).

For point sprites, XY are the point coordinates from VS, Z=0 and W=1, always.
The Vivante GPU can only configure varying to be either of -- point coord X,
point coord Y, used, unused -- which covers XYZ, but not W. Z is fine because
unused means 0.

W used to be 0 too before this patch and that led to division by 0 in shader.
The only known way to solve this is to set Z=0, W=1 in the shader program
itself if the point sprites are enabled. This means we have to generate a
special shader variant which does extra SET to set the W=1 in case the point
sprites are enabled.

In case of TGSI, emitting the SET.TRUE opcode permits setting W=1 without
allocating additional constants. With NIR, use nir_lower_texcoord_replace()
to lower TEXn to PNTC, which sets Z=0, W=1, and let NIR optimize the shader.
Note that nir_lower_texcoord_replace() must be called before input linking
is set up, as it might add new FS input.

Also note that it should be possible to simply drop PIPE_CAP_POINT_SPRITE
in the long run, ST would then apply the same optimization pass, but that
option is so far misbehaving. And for etnaviv TGSI this is not applicable
yet.

This fixes neverball point sprites (exit cylinder stars) and eglretrace of
gl4es pointsprite test:
https://github.com/ptitSeb/gl4es/blob/master/traces/pointsprite.tgz

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8618>

v3dv: call util_cpu_detect() when initializing the instance

Fixes this assert in debug builds:

in __GI___assert_fail (assertion=0x7ffff731f66b "util_cpu_caps.nr_cpus >= 1", file=0x7ffff731f650 "../src/util/u_cpu_detect.h", line=116,
function=0x7ffff7323280 <__PRETTY_FUNCTION__.11654> "util_get_cpu_caps") at assert.c:101
in util_get_cpu_caps () at ../src/util/u_cpu_detect.h:116
in _mesa_float_to_float16_rtz (val=0) at ../src/util/half_float.h:93
in util_format_r16g16b16a16_float_pack_rgba_float (dst_row=0x7fffffffbdc0 "", dst_stride=0, src_row=0x7fffffffbf90, src_stride=0, width=1, height=1)
at src/util/format/u_format_table.c:13459
in util_format_pack_rgba (format=PIPE_FORMAT_R16G16B16A16_FLOAT, dst=0x7fffffffbdc0, src=0x7fffffffbf90, w=1) at ../src/util/format/u_format.h:1525
in util_pack_color (rgba=0x7fffffffbf90, format=PIPE_FORMAT_R16G16B16A16_FLOAT, uc=0x7fffffffbdc0) at ../src/gallium/auxiliary/util/u_pack_color.h:432
in v3dv_get_hw_clear_color (color=0x7fffffffbf90, internal_type=6, internal_size=8, hw_color=0x7fffffffbf10) at ../src/broadcom/vulkan/v3dv_cmd_buffer.c:1241

v2: move call from physical device to instance init.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9408>

broadcom/compiler: disallow ldunif during ldvary sequences if possible

This restores many of the hurt shaders from the previous patch at the
expense of re-adding ldvary tracking in the scheduler.

total instructions in shared programs: 13760415 -> 13755738 (-0.03%)
instructions in affected programs: 1207560 -> 1202883 (-0.39%)
helped: 5080
HURT: 1731
Instructions are helped.

total max-temps in shared programs: 2322991 -> 2322828 (<.01%)
max-temps in affected programs: 5063 -> 4900 (-3.22%)
helped: 229
HURT: 108
Max-temps are helped.

total sfu-stalls in shared programs: 31827 -> 31545 (-0.89%)
sfu-stalls in affected programs: 478 -> 196 (-59.00%)
helped: 304
HURT: 21
Sfu-stalls are helped.

total inst-and-stalls in shared programs: 13792242 -> 13787283 (-0.04%)
inst-and-stalls in affected programs: 1220856 -> 1215897 (-0.41%)
helped: 5162
HURT: 1697
Inst-and-stalls are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9471>

broadcom/compiler: simplify ldvary pipelining

We get optimal ldvary pipelining by doing the following:

1) Carefully merge a paired ldvary into the previous instruction when
   possible.
2) When the above succeeds, flag the ldvary as scheduled immediately so
   we can merge one of its children into the current instruction.
3) When scheduling ldvary sequences, only pick up instructions that are
   part of the sequence to avoid picking up something that prevents
   successful pipelining.

This patch skips 3) assuming some hurt shaders in exchange for better
scheduling flexibility during ldvary sequences. Besides eliminating most
of the code dedicated to special handling ldvary sequences, this also
usually allows us to produce better code by merging instructions that are
unrelated to ldvary sequences into the ldvary sequences, which is
particularly effective to fill up the gaps produced when scheduling the
first and last ldvary sequences as well as the gaps produced by flat
and noperspective varyings sequences that don't have both mul and add
instructions.

Notice that there are some hurt shaders, because some times the extra
scheduler flexibility can lead to picking up instructions that will
break a sequence without compensating for that, typically an ldunif
that prevents us from doing the fixup for a follow-up ldvary. We will
try to correct some of these cases with the next patch.

total instructions in shared programs: 13786037 -> 13760415 (-0.19%)
instructions in affected programs: 3201387 -> 3175765 (-0.80%)
helped: 16155
HURT: 4146
Instructions are helped.

total max-temps in shared programs: 2324834 -> 2322991 (-0.08%)
max-temps in affected programs: 22160 -> 20317 (-8.32%)
helped: 1340
HURT: 103
Max-temps are helped.

total sfu-stalls in shared programs: 30685 -> 31827 (3.72%)
sfu-stalls in affected programs: 782 -> 1924 (146.04%)
helped: 253
HURT: 1416
Inconclusive result.

total inst-and-stalls in shared programs: 13816722 -> 13792242 (-0.18%)
inst-and-stalls in affected programs: 3171642 -> 3147162 (-0.77%)
helped: 15331
HURT: 4179
Inst-and-stalls are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9471>

broadcom/compiler: move code block around

These checks depend on prev_inst being set, so move them down below
with all the other checks with the same requirement.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9471>

broadcom/compiler: add an additional sanity check assert to the ldvary fixup

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9471>

radv: check if dynamic line stipple state changed

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9458>

radv: check if dynamic VRS state changed

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9458>

radv: do not declare push constants for DCC decompress on compute

We don't use push constants at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9475>

intel/blorp: Fix condition to figure out aux_address

Fixes: 4dfabac4 ("blorp/gen12: Don't use aux address if implicit CCS")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9491>

Revert "Revert "blorp/gen12: Don't use aux address if implicit CCS""

This reverts commit cbd5d82bae794f323bb3d1508360afda69ca309d.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9491>

Revert "blorp/gen12: Don't use aux address if implicit CCS"

This reverts commit 4dfabac493614e98ca9b388cd4eea844e30b4bd0.

The offending commit broke tens of thousands of tests in Intel's Mesa
CI. Iris asserted in iris_use_pinned_bo at:

assert(bo->kflags & EXEC_OBJECT_PINNED);

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9489>

ci/bare-metal: fix fastboot

Only copy results from NFS if BM_FASTBOOT_NFSROOT is set.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9482>

freedreno/a5xx: Flush depth at the end of sysmem, like a6xx does.

On a6xx, this flush fixed some force-bypass tests. Doesn't affect
anything in our current a5xx test set.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9481>

freedreno/a5xx: Introduce an event write helper like a6xx has.

This should help the next person trying to diff a5xx to a6xx behavior.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9481>

compiler/nir: Increment shader input count and mark as used when adding new gl_PointCoord

In case a new gl_PointCoord shader input is created, increment shader
input count and set valid driver_location to the new input variable,
otherwise the input gets aliased to input 0 and shows up in NIR_PRINT
output as whatever shader input 0 is instead of gl_PointCoord. Also
set the input as used, otherwise it might get removed.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9214>

shader_info: convert textures_used to a bitset.

For now keep it a bitset of 1 32-bit dword.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9456>

util/bitset: add a new last bit api

This is to be used where the bitset is a predefined array size.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9456>

util/panfrost/glsl: rename BITSET_LAST_BIT to BITSET_LAST_BIT_SIZED

The current users all pass in the number of dwords, but I'd like
to provide an interface that doess ARRAY_SIZE implicitly.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9456>

anv/image: Make memory layout more explicit

Future patches for VK_EXT_image_drm_format_modifier will, in some cases,
place the aux surface and fast clear state into a driver-private bo.
This increases the complexity of image memory layout to such a degree
that, to maintain sanity, we must improve how we track the layout.

Define new types:
  - anv_image_memory_range
  - anv_image_memory_binding
  - anv_image_binding

Delete many fields in anv_image (and its children), and replace them
with the new types.

This patch does not change how anv_image tracks (or, rather, does not
track) the memory of gen12 implicit ccs. We should probably do that, but
that's left as a future exercise.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>

blorp/gen12: Don't use aux address if implicit CCS

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>

anv/image: Add anv_image_address()

It calculates the address to a surface or to metadata in the image.

Refactor only. No intended change in behavior.

This patch prepares for, and reduces much noise in, the upcoming patch
that rewrites image memory tracking.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>

anv: Refactor anv_image_get_compression_state_addr

Reduces noise in the path that introduces anv_image_mem_range.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>

anv/image: Clean up anv_GetImageMemoryRequirements2

If the image is disjoint, there is no reason to calculate image-global
memory requirements. Instead, only per-plane memory requirements are
needed.

Also, delete a large duplicate comment.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>

anv: Add anv_surface_is_valid()

Current code checks for surface validity with `surface.isl.size_B > 0`.
Replace the checks with anv_surface_is_valid().

This prepares for adding new members to anv_surface that may
be accidentally used as a validity-indicator.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>

anv/android: Fix size check for imported gralloc bo

1. Don't compare bo->size to image->size. An upcoming patch replaces
anv_image::size with complicated stuff. Instead, properly query the
required size with anv_GetImageMemoryRequirements.

2. Require the bo to fit the *aligned* image size.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>

anv/image: Fix interpretation of 'disjoint'

The calculation of the subsurfaces' memory requirements assumed that the
image was disjoint if the image was created with
VK_IMAGE_CREATE_DISJOINT_BIT. But the Vulkan spec also requires that the
VkFormat be multi-planar.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>

anv/image: Drop duplicate 'format' in anv_image_create()

Reduces the chance of misusing unitialized 'n_planes' and 'format'
during image creation.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>

anv/image: Move vkGetImageMemoryRequirements

Move from anv_device.c to anv_image.c, to live alongside
vkBindImageMemory* and related code.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>

anv/image: Rename anv_image_plane::surface -> primary_surface

This disambiguates code that accesses `image->planes[*].surface`.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>

anv/image: Replace bo_is_owned with from_gralloc (v2)

The name anv_image_plane::bo_is_owned will be made ambiguous by the
implementation of VK_EXT_image_drm_format_modifier, which may bind the
plane to multiple bo's.

Also, bo_is_owned was set if and only if the image was imported from
gralloc, and it was set only on the first plane. Therefore, let's rename
the field to from_gralloc, and move it to the toplevel of anv_image.

v2: Fix build in anv_android.c.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>

zink: fix instance/device versioning (for real this time)

the maximum allowable runtime version of vk can be computed by MIN(instance_version, device_version)

despite this, instances and devices can be created using the maximum version available
for each respective type. the restriction is applied only at the point of
enabling/applying features and extensions, meaning that to correctly handle this,
zink must:

1. create an instance using the maximum allowable version
2. select a physical device using the instance
3. compute MIN(instance_version, device_version)
4. only now begin to enable/use features requiring vk 1.1+

ref #4392

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9479>

freedreno/hw: fix populating branch targets in isa_decode pre-pass

pre-pass ran with branch_labels being false which made it no-op.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9476>

docs: Add some documentation of game GL buffer object mapping behavior.

There are a variety of paths that apps take (this is by no means a
complete enumeration, I tried to keep going until I saw repeats but
eventually ran out of steam), and it should be useful to driver developers
writing their pipe_transfer_map() and invalidate_resource() calls to see a
bunch of the patterns without having to do performance debug on each app.

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9231>