Mike Blumenkrantz [Thu, 4 Aug 2022 18:33:27 +0000 (14:33 -0400)]
zink: move gfx program update/creation into zink_program.c
this doesn't need to be c++
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18135>
Mike Blumenkrantz [Thu, 4 Aug 2022 18:21:37 +0000 (14:21 -0400)]
zink: deduplicate some program destroy code
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18135>
Mike Blumenkrantz [Thu, 4 Aug 2022 18:17:50 +0000 (14:17 -0400)]
zink: deduplicate some program creation code
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18135>
Matt Turner [Mon, 15 Aug 2022 16:36:42 +0000 (16:36 +0000)]
freedreno/ir3: Use nir_opt_idiv_const
Notably reduces the number of instructions in manhattan31/377 by 101:
instructions helped: shaders/closed/android/gfxbench/manhattan31/377.shader_test CL: 1700 -> 1599 (-5.94%)
total instructions in shared programs: 1713536 -> 1713313 (-0.01%)
instructions in affected programs: 7635 -> 7412 (-2.92%)
helped: 12
HURT: 9
total nops in shared programs: 377253 -> 377188 (-0.02%)
nops in affected programs: 3170 -> 3105 (-2.05%)
helped: 13
HURT: 8
total non-nops in shared programs: 1336283 -> 1336125 (-0.01%)
non-nops in affected programs: 3134 -> 2976 (-5.04%)
helped: 12
HURT: 4
total mov in shared programs: 66642 -> 66641 (<.01%)
mov in affected programs: 145 -> 144 (-0.69%)
helped: 1
HURT: 4
total cov in shared programs: 20215 -> 20223 (0.04%)
cov in affected programs: 64 -> 72 (12.50%)
helped: 0
HURT: 8
total dwords in shared programs: 3650282 -> 3649876 (-0.01%)
dwords in affected programs: 11222 -> 10816 (-3.62%)
helped: 12
HURT: 0
total constlen in shared programs: 246636 -> 246656 (<.01%)
constlen in affected programs: 72 -> 92 (27.78%)
helped: 0
HURT: 5
total cat0 in shared programs: 411874 -> 411809 (-0.02%)
cat0 in affected programs: 3414 -> 3349 (-1.90%)
helped: 13
HURT: 8
total cat1 in shared programs: 87109 -> 87116 (<.01%)
cat1 in affected programs: 398 -> 405 (1.76%)
helped: 1
HURT: 12
total cat2 in shared programs: 797105 -> 797030 (<.01%)
cat2 in affected programs: 1619 -> 1544 (-4.63%)
helped: 12
HURT: 0
total cat3 in shared programs: 348412 -> 348322 (-0.03%)
cat3 in affected programs: 404 -> 314 (-22.28%)
helped: 12
HURT: 0
total sstall in shared programs: 133300 -> 133302 (<.01%)
sstall in affected programs: 73 -> 75 (2.74%)
helped: 0
HURT: 1
total (ss) in shared programs: 36137 -> 36139 (<.01%)
(ss) in affected programs: 54 -> 56 (3.70%)
helped: 0
HURT: 2
total systall in shared programs: 323494 -> 323624 (0.04%)
systall in affected programs: 1591 -> 1721 (8.17%)
helped: 4
HURT: 2
total (sy) in shared programs: 14306 -> 14308 (0.01%)
(sy) in affected programs: 46 -> 48 (4.35%)
helped: 0
HURT: 2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18085>
Matt Turner [Mon, 15 Aug 2022 16:25:44 +0000 (16:25 +0000)]
freedreno/ir3: Don't use the broken idiv lowering
This hurts, but we really can't tolerate incorrect results.
Notably hurts manhattan31/377 (but half of the damage is handled by the
next commit).
instructions HURT: shaders/closed/android/gfxbench/manhattan31/377.shader_test CL: 1509 -> 1700 (12.66%)
total instructions in shared programs: 1674990 -> 1713536 (2.30%)
instructions in affected programs: 205016 -> 243562 (18.80%)
helped: 10
HURT: 357
total nops in shared programs: 370499 -> 377253 (1.82%)
nops in affected programs: 54465 -> 61219 (12.40%)
helped: 74
HURT: 289
total non-nops in shared programs: 1304491 -> 1336283 (2.44%)
non-nops in affected programs: 147087 -> 178879 (21.61%)
helped: 5
HURT: 348
total mov in shared programs: 64188 -> 66642 (3.82%)
mov in affected programs: 5667 -> 8121 (43.30%)
helped: 5
HURT: 346
total cov in shared programs: 23603 -> 20215 (-14.35%)
cov in affected programs: 9274 -> 5886 (-36.53%)
helped: 347
HURT: 0
total dwords in shared programs: 3385438 -> 3650282 (7.82%)
dwords in affected programs: 630672 -> 895516 (41.99%)
helped: 0
HURT: 690
total full in shared programs: 93112 -> 93127 (0.02%)
full in affected programs: 390 -> 405 (3.85%)
helped: 10
HURT: 22
total constlen in shared programs: 245400 -> 246636 (0.50%)
constlen in affected programs: 19504 -> 20740 (6.34%)
helped: 0
HURT: 309
total cat0 in shared programs: 405120 -> 411874 (1.67%)
cat0 in affected programs: 57075 -> 63829 (11.83%)
helped: 74
HURT: 289
total cat1 in shared programs: 87987 -> 87109 (-1.00%)
cat1 in affected programs: 13032 -> 12154 (-6.74%)
helped: 282
HURT: 17
total cat2 in shared programs: 775647 -> 797105 (2.77%)
cat2 in affected programs: 106737 -> 128195 (20.10%)
helped: 0
HURT: 347
total cat3 in shared programs: 337200 -> 348412 (3.33%)
cat3 in affected programs: 17551 -> 28763 (63.88%)
helped: 0
HURT: 347
total sstall in shared programs: 133312 -> 133300 (<.01%)
sstall in affected programs: 85 -> 73 (-14.12%)
helped: 1
HURT: 0
total (ss) in shared programs: 36146 -> 36137 (-0.02%)
(ss) in affected programs: 345 -> 336 (-2.61%)
helped: 20
HURT: 11
total systall in shared programs: 323432 -> 323494 (0.02%)
systall in affected programs: 2762 -> 2824 (2.24%)
helped: 11
HURT: 15
total (sy) in shared programs: 14301 -> 14306 (0.03%)
(sy) in affected programs: 54 -> 59 (9.26%)
helped: 0
HURT: 4
Total CPU time (seconds): 0 -> 0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18085>
Alyssa Rosenzweig [Mon, 1 Aug 2022 23:11:09 +0000 (19:11 -0400)]
pan/bi: Use nir_opt_idiv_const
Mitigates some of the hurt from idiv lowering.
total instructions in shared programs: 2734512 -> 2734269 (<.01%)
instructions in affected programs: 10419 -> 10176 (-2.33%)
helped: 11
HURT: 4
helped stats (abs) min: 9.0 max: 49.0 x̄: 22.45 x̃: 19
helped stats (rel) min: 1.84% max: 7.50% x̄: 3.65% x̃: 3.30%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.14% max: 0.14% x̄: 0.14% x̃: 0.14%
95% mean confidence interval for instructions value: -25.34 -7.06
95% mean confidence interval for instructions %-change: -3.91% -1.37%
Instructions are helped.
total cycles in shared programs: 140629.05 -> 140628.61 (<.01%)
cycles in affected programs: 25.12 -> 24.69 (-1.74%)
helped: 3
HURT: 0
helped stats (abs) min: 0.0625 max: 0.3125 x̄: 0.15 x̃: 0
helped stats (rel) min: 0.82% max: 3.17% x̄: 1.60% x̃: 0.82%
total cvt in shared programs: 14826.25 -> 14819.52 (-0.05%)
cvt in affected programs: 189.64 -> 182.91 (-3.55%)
helped: 42
HURT: 0
helped stats (abs) min: 0.046875 max: 1.015625 x̄: 0.16 x̃: 0
helped stats (rel) min: 0.74% max: 11.76% x̄: 3.73% x̃: 2.82%
95% mean confidence interval for cvt value: -0.23 -0.09
95% mean confidence interval for cvt %-change: -4.65% -2.82%
Cvt are helped.
total sfu in shared programs: 8601.81 -> 8613.56 (0.14%)
sfu in affected programs: 85.62 -> 97.38 (13.72%)
helped: 0
HURT: 41
HURT stats (abs) min: 0.0625 max: 1.25 x̄: 0.29 x̃: 0
HURT stats (rel) min: 3.45% max: 33.33% x̄: 15.48% x̃: 16.67%
95% mean confidence interval for sfu value: 0.21 0.36
95% mean confidence interval for sfu %-change: 13.28% 17.69%
Sfu are HURT.
total quadwords in shared programs: 1479736 -> 1479616 (<.01%)
quadwords in affected programs: 3392 -> 3272 (-3.54%)
helped: 8
HURT: 0
helped stats (abs) min: 8.0 max: 24.0 x̄: 15.00 x̃: 16
helped stats (rel) min: 1.54% max: 4.62% x̄: 3.57% x̃: 3.71%
95% mean confidence interval for quadwords value: -20.58 -9.42
95% mean confidence interval for quadwords %-change: -4.39% -2.75%
Quadwords are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17266>
Alyssa Rosenzweig [Fri, 24 Jun 2022 15:04:15 +0000 (11:04 -0400)]
pan/bi: Don't use the broken idiv lowering
Rip off the band-aid. We can't tolerate straight-up wrong results, after all.
Addresses the Bifrost/Valhall portion of #6555.
Fixes test_integer_ops uint_math / subcase.
total instructions in shared programs: 2674840 -> 2734512 (2.23%)
instructions in affected programs: 189964 -> 249636 (31.41%)
helped: 0
HURT: 383
HURT stats (abs) min: 8.0 max: 184.0 x̄: 155.80 x̃: 173
HURT stats (rel) min: 1.85% max: 126.09% x̄: 32.38% x̃: 34.46%
95% mean confidence interval for instructions value: 150.98 160.63
95% mean confidence interval for instructions %-change: 31.27% 33.48%
Instructions are HURT.
total cycles in shared programs: 140627.36 -> 140629.05 (<.01%)
cycles in affected programs: 24.81 -> 26.50 (6.80%)
helped: 0
HURT: 4
HURT stats (abs) min: 0.1875 max: 0.9375 x̄: 0.42 x̃: 0
HURT stats (rel) min: 2.52% max: 37.50% x̄: 13.26% x̃: 6.52%
95% mean confidence interval for cycles value: -0.14 0.99
95% mean confidence interval for cycles %-change: -13.14% 39.67%
Inconclusive result (value mean confidence interval includes 0).
total fma in shared programs: 22578.03 -> 22549.94 (-0.12%)
fma in affected programs: 1056.33 -> 1028.23 (-2.66%)
helped: 383
HURT: 0
helped stats (abs) min: 0.015625 max: 0.375 x̄: 0.07 x̃: 0
helped stats (rel) min: 0.55% max: 50.00% x̄: 3.07% x̃: 2.34%
95% mean confidence interval for fma value: -0.08 -0.07
95% mean confidence interval for fma %-change: -3.39% -2.75%
Fma are helped.
total cvt in shared programs: 14128.91 -> 14826.25 (4.94%)
cvt in affected programs: 1636.23 -> 2333.58 (42.62%)
helped: 0
HURT: 383
HURT stats (abs) min: 0.0625 max: 2.109375 x̄: 1.82 x̃: 2
HURT stats (rel) min: 2.52% max: 162.50% x̄: 43.50% x̃: 46.40%
95% mean confidence interval for cvt value: 1.76 1.88
95% mean confidence interval for cvt %-change: 42.07% 44.93%
Cvt are HURT.
total sfu in shared programs: 7549.31 -> 8601.81 (13.94%)
sfu in affected programs: 758.62 -> 1811.12 (138.74%)
helped: 0
HURT: 383
HURT stats (abs) min: 0.375 max: 5.0 x̄: 2.75 x̃: 3
HURT stats (rel) min: 23.08% max: 266.67% x̄: 136.66% x̃: 150.00%
95% mean confidence interval for sfu value: 2.67 2.83
95% mean confidence interval for sfu %-change: 133.02% 140.29%
Sfu are HURT.
total quadwords in shared programs: 1449928 -> 1479736 (2.06%)
quadwords in affected programs: 96544 -> 126352 (30.88%)
helped: 0
HURT: 382
HURT stats (abs) min: 8.0 max: 96.0 x̄: 78.03 x̃: 88
HURT stats (rel) min: 1.82% max: 100.00% x̄: 31.71% x̃: 34.38%
95% mean confidence interval for quadwords value: 75.63 80.43
95% mean confidence interval for quadwords %-change: 30.67% 32.75%
Quadwords are HURT.
total threads in shared programs: 53556 -> 53479 (-0.14%)
threads in affected programs: 154 -> 77 (-50.00%)
helped: 0
HURT: 77
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -1.00 -1.00
95% mean confidence interval for threads %-change: -50.00% -50.00%
Threads are HURT.
Bifrost is hit harder, unfortunately:
total instructions in shared programs: 2414877 -> 2468058 (2.20%)
instructions in affected programs: 184585 -> 237766 (28.81%)
helped: 0
HURT: 383
HURT stats (abs) min: 12.0 max: 160.0 x̄: 138.85 x̃: 155
HURT stats (rel) min: 1.52% max: 111.94% x̄: 29.43% x̃: 31.44%
95% mean confidence interval for instructions value: 134.47 143.24
95% mean confidence interval for instructions %-change: 28.42% 30.45%
Instructions are HURT.
total tuples in shared programs: 1927478 -> 1964218 (1.91%)
tuples in affected programs: 133176 -> 169916 (27.59%)
helped: 0
HURT: 383
HURT stats (abs) min: 5.0 max: 113.0 x̄: 95.93 x̃: 107
HURT stats (rel) min: 1.02% max: 87.04% x̄: 28.44% x̃: 30.57%
95% mean confidence interval for tuples value: 92.80 99.05
95% mean confidence interval for tuples %-change: 27.47% 29.41%
Tuples are HURT.
total clauses in shared programs: 354853 -> 359513 (1.31%)
clauses in affected programs: 22918 -> 27578 (20.33%)
helped: 0
HURT: 381
HURT stats (abs) min: 1.0 max: 15.0 x̄: 12.23 x̃: 14
HURT stats (rel) min: 1.14% max: 60.00% x̄: 20.81% x̃: 22.58%
95% mean confidence interval for clauses value: 11.84 12.62
95% mean confidence interval for clauses %-change: 20.13% 21.49%
Clauses are HURT.
total cycles in shared programs: 166542.56 -> 167639.31 (0.66%)
cycles in affected programs: 5012.37 -> 6109.13 (21.88%)
helped: 0
HURT: 329
HURT stats (abs) min: 0.
20833199999999863 max: 4.
666665999999999 x̄: 3.33 x̃: 3
HURT stats (rel) min: 1.05% max: 51.06% x̄: 22.28% x̃: 22.78%
95% mean confidence interval for cycles value: 3.22 3.45
95% mean confidence interval for cycles %-change: 21.45% 23.10%
Cycles are HURT.
total arith in shared programs: 73643 -> 75173.17 (2.08%)
arith in affected programs: 5344.04 -> 6874.21 (28.63%)
helped: 0
HURT: 383
HURT stats (abs) min: 0.
20833199999999863 max: 4.666667 x̄: 4.00 x̃: 4
HURT stats (rel) min: 1.05% max: 97.92% x̄: 29.47% x̃: 31.64%
95% mean confidence interval for arith value: 3.87 4.13
95% mean confidence interval for arith %-change: 28.45% 30.49%
Arith are HURT.
total quadwords in shared programs: 1673974 -> 1701720 (1.66%)
quadwords in affected programs: 111686 -> 139432 (24.84%)
helped: 0
HURT: 383
HURT stats (abs) min: 5.0 max: 84.0 x̄: 72.44 x̃: 81
HURT stats (rel) min: 1.11% max: 78.72% x̄: 25.59% x̃: 27.56%
95% mean confidence interval for quadwords value: 70.16 74.73
95% mean confidence interval for quadwords %-change: 24.74% 26.43%
Quadwords are HURT.
total threads in shared programs: 53655 -> 53590 (-0.12%)
threads in affected programs: 130 -> 65 (-50.00%)
helped: 0
HURT: 65
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -1.00 -1.00
95% mean confidence interval for threads %-change: -50.00% -50.00%
Threads are HURT.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17266>
Alyssa Rosenzweig [Tue, 2 Aug 2022 14:16:11 +0000 (10:16 -0400)]
pan/bi: Optimize pattern from nir_lower_idiv
This takes advantage of the .i1 modifier on the comparison to get b2i32 "for
free" in typical circumstances, saving an instruction. Will help with an instr
count regression from lower_idiv.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17266>
Alyssa Rosenzweig [Fri, 19 Aug 2022 19:41:29 +0000 (15:41 -0400)]
pan/bi: Optimize bitwise arithmetic of booleans
This is easier to schedule on Bifrost. In theory it's also better on Valhall,
but in practice the CVT unit is too overloaded on Valhall for this to help
at the moment. We can revisit these rules for Valhall in the future where the
Valhall optimizer is more mature and/or Valhall grows a scheduler to balance the
execution units.
total instructions in shared programs: 2415350 -> 2414877 (-0.02%)
instructions in affected programs: 120948 -> 120475 (-0.39%)
helped: 192
HURT: 49
helped stats (abs) min: 1.0 max: 5.0 x̄: 2.89 x̃: 4
helped stats (rel) min: 0.25% max: 4.35% x̄: 0.66% x̃: 0.52%
HURT stats (abs) min: 1.0 max: 3.0 x̄: 1.67 x̃: 1
HURT stats (rel) min: 0.11% max: 7.14% x̄: 1.73% x̃: 0.77%
95% mean confidence interval for instructions value: -2.24 -1.68
95% mean confidence interval for instructions %-change: -0.37% 0.02%
Inconclusive result (%-change mean confidence interval includes 0).
total tuples in shared programs: 1928474 -> 1927478 (-0.05%)
tuples in affected programs: 146482 -> 145486 (-0.68%)
helped: 514
HURT: 73
helped stats (abs) min: 1.0 max: 8.0 x̄: 2.11 x̃: 1
helped stats (rel) min: 0.18% max: 9.52% x̄: 1.35% x̃: 0.76%
HURT stats (abs) min: 1.0 max: 2.0 x̄: 1.23 x̃: 1
HURT stats (rel) min: 0.15% max: 7.14% x̄: 1.07% x̃: 0.76%
95% mean confidence interval for tuples value: -1.85 -1.55
95% mean confidence interval for tuples %-change: -1.19% -0.91%
Tuples are helped.
total clauses in shared programs: 354985 -> 354853 (-0.04%)
clauses in affected programs: 8562 -> 8430 (-1.54%)
helped: 124
HURT: 22
helped stats (abs) min: 1.0 max: 8.0 x̄: 1.24 x̃: 1
helped stats (rel) min: 0.83% max: 7.14% x̄: 2.47% x̃: 1.72%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 1.25% max: 20.00% x̄: 5.08% x̃: 4.35%
95% mean confidence interval for clauses value: -1.11 -0.70
95% mean confidence interval for clauses %-change: -1.92% -0.75%
Clauses are helped.
total cycles in shared programs: 166575.48 -> 166542.56 (-0.02%)
cycles in affected programs: 4556.58 -> 4523.67 (-0.72%)
helped: 395
HURT: 65
helped stats (abs) min: 0.
041665999999999315 max: 0.
33333199999999863 x̄: 0.09 x̃: 0
helped stats (rel) min: 0.19% max: 11.11% x̄: 1.42% x̃: 0.81%
HURT stats (abs) min: 0.
041665999999999315 max: 0.
08333400000000069 x̄: 0.05 x̃: 0
HURT stats (rel) min: 0.15% max: 8.33% x̄: 1.21% x̃: 0.83%
95% mean confidence interval for cycles value: -0.08 -0.06
95% mean confidence interval for cycles %-change: -1.22% -0.87%
Cycles are helped.
total arith in shared programs: 73687.88 -> 73643 (-0.06%)
arith in affected programs: 6339 -> 6294.13 (-0.71%)
helped: 570
HURT: 72
helped stats (abs) min: 0.
041665999999999315 max: 0.
3333340000000007 x̄: 0.08 x̃: 0
helped stats (rel) min: 0.19% max: 12.50% x̄: 1.41% x̃: 0.77%
HURT stats (abs) min: 0.
041665999999999315 max: 0.
08333400000000069 x̄: 0.05 x̃: 0
HURT stats (rel) min: 0.15% max: 8.33% x̄: 1.13% x̃: 0.75%
95% mean confidence interval for arith value: -0.08 -0.06
95% mean confidence interval for arith %-change: -1.27% -0.98%
Arith are helped.
total quadwords in shared programs: 1674486 -> 1673974 (-0.03%)
quadwords in affected programs: 117696 -> 117184 (-0.44%)
helped: 424
HURT: 127
helped stats (abs) min: 1.0 max: 6.0 x̄: 1.64 x̃: 1
helped stats (rel) min: 0.19% max: 4.88% x̄: 1.00% x̃: 0.82%
HURT stats (abs) min: 1.0 max: 5.0 x̄: 1.46 x̃: 1
HURT stats (rel) min: 0.15% max: 6.25% x̄: 1.31% x̃: 0.88%
95% mean confidence interval for quadwords value: -1.07 -0.79
95% mean confidence interval for quadwords %-change: -0.58% -0.36%
Quadwords are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17266>
Marek Olšák [Tue, 16 Aug 2022 15:47:47 +0000 (11:47 -0400)]
winsys/amdgpu: change num_rejected_cs to a bool flag
and don't increment the total sum after the first rejection
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17968>
Marek Olšák [Tue, 9 Aug 2022 21:27:18 +0000 (17:27 -0400)]
winsys/amdgpu: flatten huge if and reorder code in amdgpu_cs_submit_ib
This correctly tracks when we get a failure and jump to cleanup.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17968>
Marek Olšák [Tue, 9 Aug 2022 21:04:47 +0000 (17:04 -0400)]
winsys/amdgpu: terminate process on CS rejection when unrobust context is lost
We agreed on this with the kernel team as the most graceful way to deal
with this scenario.
Remove the allow_context_lost use because it's always true there
if num_rejected_cs is true.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17968>
Marek Olšák [Tue, 9 Aug 2022 20:55:41 +0000 (16:55 -0400)]
radeonsi: allow lost context with aux_contexts
We'll terminate the process if a context is lost, so we don't have any
other choice.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17968>
Marek Olšák [Tue, 9 Aug 2022 17:06:37 +0000 (13:06 -0400)]
radeonsi: rename stop_exec_on_failure -> allow_context_lost
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17968>
Mike Blumenkrantz [Fri, 19 Aug 2022 17:37:57 +0000 (13:37 -0400)]
Revert "zink: add all format modifiers when adding for dmabuf export"
This reverts commit
247b8f2924b7832d8520e890cff6891217f5a860.
this attempted to work around what is likely a bug in nvidia's modifier
support, namely their refusal to expose LINEAR as a valid modifier for
some bizarre reason
cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18148>
Mike Blumenkrantz [Fri, 19 Aug 2022 17:37:38 +0000 (13:37 -0400)]
Revert "zink: try to reuse swapchain modifier for dmabuf export"
This reverts commit
49efa73ba11c4cacaed0052b984e1fb884cf7600.
this happens to work with mesa (sometimes), but it's going to be
illegal most of the time since swapchain images are treated as though
they are created with OPTIMAL tiling
cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18148>
Sami Kyöstilä [Mon, 15 Aug 2022 10:08:17 +0000 (20:08 +1000)]
intel/ds: Update to Perfetto API v28.0
Perfetto v28.0 changes the naming scheme of generated enum constants.
Update our code to match and roll the version of Perfetto forward
accordingly.
No functional changes.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18056>
Chia-I Wu [Tue, 16 Aug 2022 19:10:34 +0000 (12:10 -0700)]
turnip: lower the queue priority to 1
To match the default priority of the gallium driver.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18093>
Chia-I Wu [Tue, 16 Aug 2022 18:08:11 +0000 (11:08 -0700)]
freedreno/pps: improve interaction with turnip
turnip uses priority 0. pps should too (actually, it makes sense to do
so regardless of what turnip does).
turnip is not expected to starve pps, but it does with drm-next for
5.20.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18093>
Alyssa Rosenzweig [Fri, 19 Aug 2022 15:42:46 +0000 (11:42 -0400)]
pan/bi: Test int8/16 -> float32 opts
These are easy, since round modes don't matter.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17857>
Alyssa Rosenzweig [Fri, 19 Aug 2022 15:51:20 +0000 (11:51 -0400)]
pan/bi: Fuse [US][8|16]_TO_F32 ops
This combines nicely with the previous isel change. Now GLSL like
float(int_x >> 24)
will generate a single machine instruction
S8_TO_F32 int_x.b3
Noticed when debugging
KHR-GLES31.core.shader_bitfield_operation.unpackSnorm4x8.0
...but naturally no real workloads care. Helped shaders are from Android games
that appear to have run through a translator, naturally.
total instructions in shared programs: 2674831 -> 2674783 (<.01%)
instructions in affected programs: 11493 -> 11445 (-0.42%)
helped: 31
HURT: 0
helped stats (abs) min: 1.0 max: 3.0 x̄: 1.55 x̃: 1
helped stats (rel) min: 0.16% max: 2.90% x̄: 0.51% x̃: 0.41%
95% mean confidence interval for instructions value: -1.87 -1.22
95% mean confidence interval for instructions %-change: -0.69% -0.33%
Instructions are helped.
total cvt in shared programs: 14128.84 -> 14128.09 (<.01%)
cvt in affected programs: 78.17 -> 77.42 (-0.96%)
helped: 31
HURT: 0
helped stats (abs) min: 0.015625 max: 0.046875 x̄: 0.02 x̃: 0
helped stats (rel) min: 0.36% max: 4.26% x̄: 1.28% x̃: 1.20%
95% mean confidence interval for cvt value: -0.03 -0.02
95% mean confidence interval for cvt %-change: -1.62% -0.94%
Cvt are helped.
total quadwords in shared programs: 1449920 -> 1449840 (<.01%)
quadwords in affected programs: 2184 -> 2104 (-3.66%)
helped: 10
HURT: 0
helped stats (abs) min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
helped stats (rel) min: 2.44% max: 5.88% x̄: 4.11% x̃: 4.76%
95% mean confidence interval for quadwords value: -8.00 -8.00
95% mean confidence interval for quadwords %-change: -5.11% -3.12%
Quadwords are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17857>
Alyssa Rosenzweig [Tue, 2 Aug 2022 14:37:52 +0000 (10:37 -0400)]
pan/bi: Implement some extracts and inserts
Rather than lowering in NIR. Importantly for Valhall, this allows
nir_opt_algebraic to optimize various bitwise ops into extracts and inserts,
taking pressure off the low-throughout SFU pipe and moving it onto the
high-throughput CVT pipe. This will mitigate a cycle count regression from
switching to the precise idiv lowering.
This also generates more integer widening conversions which we can fold into
32-bit instructions later, to allow optimizing GLSL like "(a & 0xFFFF) + b"
Valhall:
total instructions in shared programs: 2674836 -> 2674840 (<.01%)
instructions in affected programs: 6473 -> 6477 (0.06%)
helped: 14
HURT: 6
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.16% max: 1.37% x̄: 0.41% x̃: 0.49%
HURT stats (abs) min: 3.0 max: 3.0 x̄: 3.00 x̃: 3
HURT stats (rel) min: 1.19% max: 1.62% x̄: 1.35% x̃: 1.24%
95% mean confidence interval for instructions value: -0.68 1.08
95% mean confidence interval for instructions %-change: -0.30% 0.53%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs: 140627.42 -> 140627.36 (<.01%)
cycles in affected programs: 2.31 -> 2.25 (-2.70%)
helped: 1
HURT: 0
total cvt in shared programs: 14127.25 -> 14128.91 (0.01%)
cvt in affected programs: 153.50 -> 155.16 (1.08%)
helped: 0
HURT: 41
HURT stats (abs) min: 0.015625 max: 0.09375 x̄: 0.04 x̃: 0
HURT stats (rel) min: 0.27% max: 4.44% x̄: 1.61% x̃: 1.22%
95% mean confidence interval for cvt value: 0.03 0.05
95% mean confidence interval for cvt %-change: 1.29% 1.93%
Cvt are HURT.
total sfu in shared programs: 7555.69 -> 7549.31 (-0.08%)
sfu in affected programs: 107.31 -> 100.94 (-5.94%)
helped: 48
HURT: 0
helped stats (abs) min: 0.0625 max: 0.375 x̄: 0.13 x̃: 0
helped stats (rel) min: 1.34% max: 50.00% x̄: 13.57% x̃: 7.14%
95% mean confidence interval for sfu value: -0.15 -0.11
95% mean confidence interval for sfu %-change: -17.07% -10.06%
Sfu are helped.
total quadwords in shared programs: 1449912 -> 1449928 (<.01%)
quadwords in affected programs: 256 -> 272 (6.25%)
helped: 0
HURT: 2
Bifrost:
total instructions in shared programs: 2415370 -> 2415380 (<.01%)
instructions in affected programs: 1642 -> 1652 (0.61%)
helped: 2
HURT: 6
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.40% max: 0.40% x̄: 0.40% x̃: 0.40%
HURT stats (abs) min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.95% max: 1.27% x̄: 1.07% x̃: 1.00%
95% mean confidence interval for instructions value: 0.09 2.41
95% mean confidence interval for instructions %-change: 0.13% 1.29%
Instructions are HURT.
total tuples in shared programs: 1928495 -> 1928476 (<.01%)
tuples in affected programs: 3329 -> 3310 (-0.57%)
helped: 9
HURT: 2
helped stats (abs) min: 1.0 max: 6.0 x̄: 2.56 x̃: 2
helped stats (rel) min: 0.25% max: 2.33% x̄: 1.00% x̃: 0.75%
HURT stats (abs) min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.48% max: 0.48% x̄: 0.48% x̃: 0.48%
95% mean confidence interval for tuples value: -3.46 0.00
95% mean confidence interval for tuples %-change: -1.35% -0.10%
Inconclusive result (value mean confidence interval includes 0).
total clauses in shared programs: 354978 -> 354983 (<.01%)
clauses in affected programs: 398 -> 403 (1.26%)
helped: 3
HURT: 8
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 2.33% max: 3.85% x̄: 2.83% x̃: 2.33%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 2.27% max: 3.70% x̄: 2.88% x̃: 2.78%
95% mean confidence interval for clauses value: -0.17 1.08
95% mean confidence interval for clauses %-change: -0.51% 3.16%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs: 166575.69 -> 166575.65 (<.01%)
cycles in affected programs: 6.88 -> 6.83 (-0.61%)
helped: 1
HURT: 0
total arith in shared programs: 73688.79 -> 73688 (<.01%)
arith in affected programs: 127.29 -> 126.50 (-0.62%)
helped: 9
HURT: 2
helped stats (abs) min: 0.
04166700000000034 max: 0.25 x̄: 0.11 x̃: 0
helped stats (rel) min: 0.26% max: 2.45% x̄: 1.07% x̃: 0.80%
HURT stats (abs) min: 0.
08333299999999966 max: 0.
08333299999999966 x̄: 0.08 x̃: 0
HURT stats (rel) min: 0.55% max: 0.55% x̄: 0.55% x̃: 0.55%
95% mean confidence interval for arith value: -0.14 0.00
95% mean confidence interval for arith %-change: -1.44% -0.11%
Inconclusive result (value mean confidence interval includes 0).
total quadwords in shared programs: 1674514 -> 1674480 (<.01%)
quadwords in affected programs: 9086 -> 9052 (-0.37%)
helped: 23
HURT: 2
helped stats (abs) min: 1.0 max: 6.0 x̄: 1.65 x̃: 1
helped stats (rel) min: 0.15% max: 2.79% x̄: 0.63% x̃: 0.33%
HURT stats (abs) min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.53% max: 0.53% x̄: 0.53% x̃: 0.53%
95% mean confidence interval for quadwords value: -2.08 -0.64
95% mean confidence interval for quadwords %-change: -0.86% -0.21%
Quadwords are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17857>
Roland Scheidegger [Thu, 18 Aug 2022 13:56:43 +0000 (15:56 +0200)]
gallivm: always do per-pixel LOD for cube maps
In the past we were doing per-quad lod for cube maps (when no_quad_lod
wasn't set), however commit
d413fd02190d ("gallivm: Always take the
per-pixel LOD path for cubemaps.") unconditionally enabled calculating
per-pixel derivatives.
However, the actual lod calculation was still only done per quad, which
probably doesn't make much sense, so unconditionally enable taking the
per-pixel lod path for cubemaps (for op_is_lodq we always force
no_quad_lod to false in any case so there's no difference there neither).
v2: adjust ci results accordingly
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18126>
Roland Scheidegger [Thu, 14 Jul 2022 19:09:32 +0000 (21:09 +0200)]
lavapipe: initialize index_bias to zero for non-indexed draws
This is mostly just cosmetic, since the index bias will be ignored.
(The multi draw function already initializes this to 0 too.)
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18126>
José Roberto de Souza [Thu, 4 Aug 2022 19:56:17 +0000 (12:56 -0700)]
anv: Do not duplicate intel_device_info memory in each logical device
Each logical device can point to its physical device intel_device_info
saving at least one intel_device_info.
This also allow us to set 'const' to avoid values in intel_device_info
being changed by mistake.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17897>
Mike Blumenkrantz [Thu, 18 Aug 2022 16:18:12 +0000 (12:18 -0400)]
vk/render_pass: don't deref null resolve attachments
Fixes:
d2990b65997 ("vulkan: hook up VK_EXT_multisampled_render_to_single_sampled")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18134>
Alyssa Rosenzweig [Wed, 17 Aug 2022 19:20:28 +0000 (15:20 -0400)]
panfrost: Don't segfault on unknown models
If we don't recognize the model, dev->model will be NULL. In that case, we can't
dereference dev->model to get the tilebuffer size. If we do, we'll segfault,
instead of gracefully refusing to probe and loading the swrast instead.
Fixes:
96d65b47c71 ("panfrost: Use implementation-specific tile size")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18115>
Glenn Kennard [Fri, 30 Jul 2021 16:44:54 +0000 (18:44 +0200)]
nv30: Fix non-scissored clears after a scissor has been set
Additionally add support for PIPE_CAP_CLEAR_SCISSORED since we are already
touching the scissor state.
Fixes various gnome-shell rendering artifacts.
v2: Remove NEW_SCISSOR as clear now updates scissor registers explicitly
v3: Reset scissor_off state since its not off now after clear
Cc: mesa-stable
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18137>
Erik Faye-Lund [Tue, 9 Aug 2022 16:28:55 +0000 (18:28 +0200)]
zink: remove needless check
textureCompressionBC is just a short-hand to know is *all* BPTC formats
are supported. We're already checking per format, so we don't need this
coarser check.
Besides, it's also kinda wrong; textureCompressionBC also requires all
BC formats, not just BPTC. In other words, all DXT formats and RGTC
formats were missing from the check.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17986>
Danylo Piliaiev [Wed, 17 Aug 2022 08:06:55 +0000 (11:06 +0300)]
freedreno: Disable LRZ write when alpha-to-coverage is enabled
Alpha-to-coverage acts like discard and happens after FS ends,
so like with discard LRZ write should be disabled.
With discard we don't know at the moment of binning whether
fragment would be not discarded, so we cannot write its depth to LRZ.
Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18102>
Konstantin Seurer [Tue, 9 Aug 2022 18:10:51 +0000 (20:10 +0200)]
radv: Inline bvh build headers
Thos are only included once, so just move the code into the
corresponding .comp files.
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17963>
SoroushIMG [Mon, 15 Aug 2022 22:17:09 +0000 (23:17 +0100)]
zink: Fix incorrect emission of SPIR-V shift ops
SPIR-V shift ops unlike NIR have undefined behavior if shift count
larger than or equalt to bitwidth.
This means that true translation of NIR ishl/ishr/ushr to SPIR-V requires
masking like that done in gallivm.
This was seen in the case of soft fp64 in cts case
KHR-GL46.gpu_shader_fp64.builtin.ceil_double.
Cc: mesa-stable
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18074>
Gert Wollny [Tue, 16 Aug 2022 08:39:02 +0000 (10:39 +0200)]
r600: Fix SCRATCH OP de-assembly
1d871aa6268159cdc63ef846599456d9ba567206
r600g: Implement spilling of temp arrays (v2)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
Gert Wollny [Tue, 16 Aug 2022 08:33:36 +0000 (10:33 +0200)]
r600: Don't use SB with R600 style scratch reads
SB fails when handling indirect READ_SCRATCH commands.
Fixes:
1d871aa6268159cdc63ef846599456d9ba567206
r600g: Implement spilling of temp arrays (v2)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
Gert Wollny [Tue, 16 Aug 2022 07:59:02 +0000 (09:59 +0200)]
r600/sfn: Handle R600 scratch read
Fixes:
33765aa92aa5c150873fc210e9d6c1fe22cf8646
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
Gert Wollny [Mon, 15 Aug 2022 16:52:09 +0000 (18:52 +0200)]
r600: Force NOPs when loading AR on R600 class hardware
Loading indirectly from a register that was just written to
doesn't work on R600 class hardware, so add a NOP group with
the address register load being emitted in the t-slot. to make
sure that the register write was finished.
Fixes:
33765aa92aa5c150873fc210e9d6c1fe22cf8646
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
Gert Wollny [Mon, 15 Aug 2022 15:15:43 +0000 (17:15 +0200)]
r600/sfn: Initialize out buffer when printing op
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Closes: #7021
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
Gert Wollny [Sun, 14 Aug 2022 16:17:08 +0000 (18:17 +0200)]
r600/sfn: Fix color outputs when color0 writes all
Fixes:
33765aa92aa5c150873fc210e9d6c1fe22cf8646
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
Gert Wollny [Sun, 14 Aug 2022 12:44:29 +0000 (14:44 +0200)]
r600/sfn: Sort FS inputs to make interpolated values come first
On R600 and R700 class hardware the input declaration order maps
directly to the register the hardware writes the inputs to, so
make all interpolated inputs come first, and only then emit the
system values like POS or FACE.
Related: #7035
Fixes:
33765aa92aa5c150873fc210e9d6c1fe22cf8646
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
Gert Wollny [Fri, 5 Aug 2022 17:55:41 +0000 (19:55 +0200)]
r600/sfn: Add GS thread fix just like the TGSI code path
The old code does the same for R600.
Fixes:
33765aa92aa5c150873fc210e9d6c1fe22cf8646
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
Gert Wollny [Thu, 4 Aug 2022 08:20:33 +0000 (10:20 +0200)]
r600/sfn: Schedule shift instruction on R600 in t-slot
Fixes:
33765aa92aa5c150873fc210e9d6c1fe22cf8646
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18130>
Dave Airlie [Thu, 30 Dec 2021 21:07:48 +0000 (07:07 +1000)]
crocus: sync performance monitor code with iris.
This provides the same info as iris does now, and exposes
INTEL_performance_query
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18099>
Timothy Arceri [Wed, 17 Aug 2022 05:32:03 +0000 (15:32 +1000)]
glsl: dont lower precision for textureGatherOffsets
textureGatherOffsets always takes a highp array of constants. As
per the discussion in [1] trying to lower the precision results in segfault
later on in the compiler as textureGatherOffsets will end up being passed
a temp when its expecting a constant as required by the spec.
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16547#note_1393704
Fixes:
b83f4b9fa23d ("glsl: Add an IR lowering pass to convert mediump operations to 16-bit")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18101>
Roman Stratiienko [Thu, 4 Aug 2022 09:59:01 +0000 (12:59 +0300)]
v3dv: Avoid swapchain_info handling on Android
Allows following tests to pass.
dEQP-VK.wsi.android.swapchain.create#image_swapchain_create_info
dEQP-VK.wsi.android.swapchain.simulate_oom#image_swapchain_create_info
Venus code was used as example.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18047>
Roman Stratiienko [Fri, 5 Aug 2022 13:23:10 +0000 (16:23 +0300)]
v3dv: Limit API version to v1.0 for Android
Android CDD has additional requirements that must be met in order to
enable 1.1+:
- samplerYcbcrConversion
- VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
- VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
- VK_ANDROID_external_memory_android_hardware_buffer >= v2
Requirements are checked by:
android.graphics.cts.VulkanFeaturesTest#testVulkan1_1Requirements CTS
Fixes:
2686c5419d67 ("v3dv: add Android support")
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18047>
Roman Stratiienko [Tue, 9 Aug 2022 10:27:10 +0000 (13:27 +0300)]
v3dv: Enable sync_fd importing/exporting on Android
vk_common_AcquireImageANDROID and vk_common_QueueSignalReleaseImageANDROID
expect sync_fd import/export to be enabled, otherwise they crashes
while trying to ImportSemaphoreFdKHR() / GetSemaphoreFdKHR().
Features was disabled on Linux to skip sync_fd CTS tests, which is using
late vkEvent signalling which causes deadlock / dEQP timeout on v3dv.
One of the options was implementing blocking v3dv-specific
AcquireImageANDROID / QueueSignalReleaseImageANDROID to avoid importing
/ exporting sync_fd, but since these features are also required by CDD
for Vulkan 1.1 and above, it was decided to enable the extensions for
Android in exchange of a few failed dEQP tests (which should not cause
any issues in non-dEQP scenarious).
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6977
Fixes:
316728a55bc8 ("v3dv: Switch to the common submit framework")
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18047>
Karol Herbst [Wed, 17 Aug 2022 13:02:37 +0000 (15:02 +0200)]
ci: bumping all tags to make sure we don't have hidden fails
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18108>
Karol Herbst [Wed, 17 Aug 2022 16:47:43 +0000 (18:47 +0200)]
ci: update fails list
one might want to investigate this, but for now let's move on and unblock
MRs.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18108>
Mike Blumenkrantz [Thu, 11 Aug 2022 12:54:52 +0000 (08:54 -0400)]
ci: remove broken device-select-layer from build
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18108>
Marcin Ślusarz [Fri, 12 Aug 2022 15:16:17 +0000 (17:16 +0200)]
intel/compiler: fix mesh urb write regression
Right now even the simplest mesh test (func.mesh.basic.mesh from crucible) fails like this:
ASSERT: Scalar MESH validation failed!
load_payload(16) vgrf11+0.0:F, vgrf8:D
../../src/intel/compiler/brw_fs_validate.cpp:61: inst->dst.offset / REG_SIZE + regs_written(inst) <= alloc.sizes[inst->dst.nr]
Because we try to load 8 regs with LOAD_PAYLOAD in SIMD16 mode.
Fixes:
349a040f684 ("intel/fs: Make logical URB write instructions more like other logical instructions")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18075>
Ikshwaku Chauhan [Wed, 3 Aug 2022 05:12:09 +0000 (10:42 +0530)]
Revert "radeon: add EFC support to only VCN2.0 devices"
This reverts commit
23e5b910c57158030ba246530c57ab13a51245f3.
Reason for revert:
It's causing the regression for H264 transcoding. We will Enable EFC
once we verify all corner cases and as of now disabling
Signed-off-by: Ikshwaku Chauhan <ikshwaku.chauhan@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17869>
Kenneth Graunke [Wed, 17 Aug 2022 23:24:24 +0000 (16:24 -0700)]
iris: Fix PIPE_CAP_UMA
If we have VRAM we're not exactly a unified memory architecture, are we?
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18123>
Kenneth Graunke [Mon, 15 Aug 2022 07:18:59 +0000 (00:18 -0700)]
intel/compiler: Drop variable group size lowering
This backend lowering code has been dead since the removal of i965 -
nothing in the current source tree ever sets the flag.
This is handled by iris_setup_uniforms() and crocus_setup_uniforms().
Variable group size does not appear to be a feature in anv.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18055>
Dmitry Osipenko [Wed, 10 Aug 2022 22:04:31 +0000 (01:04 +0300)]
llvmpipe: Align persistent mappings to page size
KVM requires memory mapping to be aligned to page size, otherwise it
refuses to do the mapping. In particular this causes KVM mapping errors
when llvmpipe is used by virtio-gpu on host and guest tries to map buffer
that has a persistent mapping, i.e. it tries to map the llvmpipe's host
blob/buffer. Mesa virgl driver uses host blobs only for the buffers with
persistent mapping, hence let's align buffer allocations to the page size
when the persistence flag is set to fix the KVM fault.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Acked-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18053>
Mike Blumenkrantz [Tue, 16 Aug 2022 16:37:47 +0000 (12:37 -0400)]
zink: try to reuse swapchain modifier for dmabuf export
the non-negotiated path assumes that drivers know what implicit modifiers they're
using, but zink doesn't know what it's doing, so instead try to copy the
swapchain's modifier and reuse that since in theory it should work
Fixes:
247b8f2924b ("zink: add all format modifiers when adding for dmabuf export")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18095>
Mike Blumenkrantz [Tue, 16 Aug 2022 14:37:49 +0000 (10:37 -0400)]
zink: iterate over all modifiers and nuke the ones that aren't supported
the spec mandates that all modifiers passed to the driver be valid, so
iterate through all of them and delete the invalid ones
Fixes:
247b8f2924b ("zink: add all format modifiers when adding for dmabuf export")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18095>
Mike Blumenkrantz [Fri, 5 Aug 2022 16:32:17 +0000 (12:32 -0400)]
zink: bail out of dmabuf resource creation when srgb explosion is expected
if srgb-ness isn't supported by the driver for dmabuf, bail out early with an
error message with the assumption that this would later (maybe) explode when
trying to create a view for srgb framebuffer
ref !17900
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18095>
Jesse Natalie [Thu, 11 Aug 2022 22:55:19 +0000 (15:55 -0700)]
microsoft/compiler: Fix PSV struct when numthreads is 0
Fixes:
d9e575d4 ("microsoft/compiler: DXIL validator 1.6 uses a new PSV struct version")
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18023>
Jesse Natalie [Fri, 12 Aug 2022 01:47:33 +0000 (18:47 -0700)]
dxil_nir_lower_int_cubemaps: When not lowering samplers, don't touch sampler types
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18025>
Jesse Natalie [Fri, 12 Aug 2022 15:52:45 +0000 (08:52 -0700)]
microsoft/compiler: Discard shouldn't be marked readnone
Cc: mesa-stable
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18034>
Georg Lehmann [Thu, 11 Aug 2022 12:43:23 +0000 (14:43 +0200)]
aco: Force tex operand to have the correct sub dword size before packing.
get_ssa_temp's and NIR's bit size can differ for scalar sources.
This causes broken packing of the MIMG operands with A16/G16.
Fixes:
f5f73db846e ("aco: Support 16bit sources for texture ops.")
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18008>
Victor Hermann Chiletto [Sat, 14 May 2022 20:00:21 +0000 (17:00 -0300)]
radv: refactor descriptor set layout tracking
Separately track descriptor set layouts for pools with
FREE_DESCRIPTOR_SET disabled, instead of reusing
`radv_descriptor_pool::entries`. This saves 8 bytes for each entry and
also avoids some indirection.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16541>
Yonggang Luo [Sat, 13 Aug 2022 04:29:29 +0000 (12:29 +0800)]
c11: #include <threads.h> when the os/platform provide it
Closes #6964
CC: mesa-stable
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18043>
Rob Clark [Wed, 17 Aug 2022 21:19:36 +0000 (14:19 -0700)]
llvmpipe: Add some missing locking
The lp_rasterizer is shared across contexts, and lp_rast_fence called
without holding rast_mutex could race with rast_mutex being replaced and
unref'd on a different thread.
Fixes:
a680fd078c0 ("llvmpipe: make last_fence a screen/rast object not a context one.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18116>
Mike Blumenkrantz [Tue, 16 Aug 2022 17:07:14 +0000 (13:07 -0400)]
nir: add uses_bindless flag for shader_info
this is cumbersome to detect, so detect it here
the flag denotes the use of either bindless texture operations
or shader variables such that drivers can infer the use of bindless
descriptor management functionality
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18088>
Rob Clark [Sat, 13 Aug 2022 17:38:30 +0000 (10:38 -0700)]
egl/dri2: Error path cleanups
Simplify things for the next patch.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
Rob Clark [Sat, 13 Aug 2022 17:42:18 +0000 (10:42 -0700)]
egl/dri2: Indenting fix
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
Rob Clark [Thu, 11 Aug 2022 17:01:01 +0000 (10:01 -0700)]
egl: Add some locking asserts
Make it obvious if we screw up while reworking locking.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
Rob Clark [Thu, 11 Aug 2022 16:56:37 +0000 (09:56 -0700)]
egl: Convert to simple_mtx_t
Mostly because simple_mtx_assert_locked() will come in handy during
locking re-work.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
Rob Clark [Thu, 11 Aug 2022 17:44:56 +0000 (10:44 -0700)]
egl: Remove redundant fxn param
*Technically* we should be unlocking with the 'disp' and not the 'dpy'
(even though they are the same thing).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
Rob Clark [Thu, 11 Aug 2022 16:20:53 +0000 (09:20 -0700)]
egl: Drop unused _EGL_FUNC_START() arg
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
Rob Clark [Thu, 11 Aug 2022 16:07:18 +0000 (09:07 -0700)]
egl: Drop _eglSetFuncName() return
It always returned EGL_TRUE
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
Rob Clark [Sat, 13 Aug 2022 16:47:52 +0000 (09:47 -0700)]
util: Fix vs2019 build error
Needed for dependency on MAX_INT.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
Rob Clark [Tue, 9 Aug 2022 20:30:45 +0000 (13:30 -0700)]
freedreno/drm/virtio: Add some atrace
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
Rob Clark [Tue, 9 Aug 2022 16:28:57 +0000 (09:28 -0700)]
egl: atrace support
Perfetto is showing mutex contention on disp->Mutex when multiple
threads are making egl calls on their own current context. This
makes it easier to see what is contending with what.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
Rob Clark [Mon, 8 Aug 2022 21:52:07 +0000 (14:52 -0700)]
freedreno/drm: Avoid lock in fd_pipe_del()
If we aren't dropping the last refcnt we don't need the lock. This
avoids contention between retire-queue against others.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18111>
Samuel Pitoiset [Wed, 17 Aug 2022 13:21:09 +0000 (15:21 +0200)]
radv: do not compress DCC in presence of render loops on GFX10+
DCC shouldn't be compressed for Vulkan feedback loops (ie. render pass
with input attachments). It looks like it has always been broken...
Note that GFX9 and earlier chips aren't affected because they don't
compress DCC on GENERAL.
This fixes
dEQP-VK.rasterization.rasterization_order_attachment_access.format*.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18104>
Charmaine Lee [Tue, 16 Aug 2022 01:55:45 +0000 (18:55 -0700)]
svga: support TGSI_SEMANTIC_TEXCOORD in swtnl draw context
Since PIPE_CAP_TGSI_TEXCOORD is now enabled, texcoord is now declared
as TGSI_SEMANTIC_TEXCOORD instead of TGSI_SEMANTIC_GENERIC.
Fixes assert running REDTurbineDEMO with MTL Renderer when the guest needs to
fallback to swtnl for line stipple.
Fixes:
e73443b7a50 ("svga: enable PIPE_CAP_TGSI_TEXCOORD for vgpu10 and up")
Reviewed-by: Martin Krastev <krastevm@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18113>
Alyssa Rosenzweig [Mon, 15 Aug 2022 21:21:13 +0000 (21:21 +0000)]
pan/mdg: Remove disassembler stats
They're now unused and they were never especially useful.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>
Alyssa Rosenzweig [Mon, 15 Aug 2022 23:58:43 +0000 (23:58 +0000)]
pan/decode: Clean up _bifrost_ decode routines
It's noisy since Bifrost was introduced, unnecessary since we converted to
per-arch GenXML, and wrong since Valhall was added.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>
Alyssa Rosenzweig [Mon, 15 Aug 2022 23:52:52 +0000 (23:52 +0000)]
pan/decode: Centrally declare pandecode entrypoints
Deduplicate in preparation for CSF.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>
Alyssa Rosenzweig [Mon, 15 Aug 2022 21:18:22 +0000 (21:18 +0000)]
pan/decode: Defeature disassembler stats
Architecturally, these only work for Midgard, and even on Midgard didn't turn
out to be too useful. While we're removing pandecode cruft, let's remove the
stats that just add noise to Bifrost and Valhall (and largely just noise to
Midgard too).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>
Alyssa Rosenzweig [Mon, 15 Aug 2022 19:10:04 +0000 (19:10 +0000)]
pan/decode: Unify SFBD/MFBD decoding
It's the same core logic. Unify and let GenXML do its thing.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>
Alyssa Rosenzweig [Mon, 15 Aug 2022 18:55:17 +0000 (18:55 +0000)]
pan/decode: Reorder MFBD decoding
Eliminate some #ifdef by grouping v5 and v6 state separately.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>
Alyssa Rosenzweig [Mon, 15 Aug 2022 18:54:20 +0000 (18:54 +0000)]
pan/decode: Simplify pandecode_fbd
Remove unsued width/height properties, and use cleaner C syntax to build the
return value.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>
Alyssa Rosenzweig [Mon, 15 Aug 2022 18:49:04 +0000 (18:49 +0000)]
pan/decode: Stop passing suffixes around
Unused.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>
Alyssa Rosenzweig [Mon, 15 Aug 2022 18:45:28 +0000 (18:45 +0000)]
pan/decode: Stop passing job index around
There are a lot of problems with passing job_index around:
* Almost entirely unused
* Not particularly helpful even when used
* Mostly ignored for Valhall already
* Doesn't extend to CSF
It only really exists due to the early days of pandecode generating valid C code
as the trace format. With GenXML instead, that's not applicable.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>
Alyssa Rosenzweig [Mon, 15 Aug 2022 18:38:56 +0000 (18:38 +0000)]
pan/decode: Remove pandecode_msg
It hasn't had a consistent semantic meaning since we've switched decoding over
to GenXML.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>
Alyssa Rosenzweig [Mon, 15 Aug 2022 18:35:45 +0000 (18:35 +0000)]
pan/decode: Don't pass around memory handles
The hardware doesn't care what BO a given buffer resides in, only what GPU
address it's at. It's simpler to fetch from a GPU address, rather than the pair
of a GPU address and a backing allocation. This cleans up a lot of cruft in
pandecode.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18094>
Mark Collins [Wed, 17 Aug 2022 07:32:38 +0000 (13:02 +0530)]
tu: Implement VK_EXT_non_seamless_cube_map
Passes CTS tests: dEQP-VK.texture.*non_seamless_*
Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18079>
Friedrich Vock [Wed, 10 Aug 2022 19:22:43 +0000 (21:22 +0200)]
radv/winsys: Return VK_ERROR_INVALID_EXTERNAL_HANDLE if buffer imports fail
Section 11.2.6 of the Vulkan spec states:
"Importing memory from a particular host pointer may not be possible due to
additional platform-specific restrictions beyond the scope of this
specification in which case the implementation must fail the memory
import operation with the error code VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17995>
Pierre-Eric Pelloux-Prayer [Wed, 10 Aug 2022 10:31:35 +0000 (12:31 +0200)]
radeonsi: prevent u_blitter recursion in si_update_ps_colorbuf0_slot
When u_blitter calls util_blitter_restore_fragment_states we may
end up in si_update_ps_colorbuf0_slot.
This commit makes sure we don't call u_blitter from there.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6921
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17981>
Samuel Pitoiset [Tue, 29 Mar 2022 12:30:59 +0000 (14:30 +0200)]
radv: add a very initial implementation of VK_EXT_graphics_pipeline_library
This experimental and very suboptimal implementation of graphics
pipeline library shouldn't be used by anyone, except for development
purposes. It's still under active development from my side. This
extension is only exposed via RADV_PERFTEST=gpl anyways.
It's very suboptimal because RADV doesn't yet support PS epilogs and
VS prologs need to be improved/reworked because GPL changed the logic
(eg. can't know the next stage when compiling a prolog). So, currently
the driver ALWAYS retains NIR shaders during libs creation and it links
and compiles in the final pipeline.
I have WIP branches for approximately everything but it looks simpler
to start merging an initial implementation in order to improve steps
by steps from main. This commit might look simple and short but I
already merged TON of preliminary work. RADV was definitely not ready
for GPL and it's still not completely fine. Expect refactoring again.
This implementation currently pass
dEQP-VK.pipeline.pipeline_library.* on NAVI21, except few feedback
creation tests due to CTS bugs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17542>
Samuel Pitoiset [Fri, 12 Aug 2022 11:48:06 +0000 (13:48 +0200)]
radv: prevent accessing rasterization state when it's NULL
It might be NULL for gfx pipeline libs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17542>
Samuel Pitoiset [Tue, 16 Aug 2022 08:53:06 +0000 (10:53 +0200)]
radv: store vk_graphics_pipeline_state to radv_graphics_pipeline
For gfx pipeline libraries we would have to keep track of the gfx
state, so change how it's allocated.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17542>
Samuel Pitoiset [Wed, 1 Jun 2022 07:59:14 +0000 (09:59 +0200)]
radv: introduce a new pipeline type for graphics libs
It currently inherits from radv_graphics_pipeline because it's simpler
but I think it could be improved because most of fields won't be useful
for libs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17542>
Samuel Pitoiset [Wed, 1 Jun 2022 08:05:06 +0000 (10:05 +0200)]
radv: add radv_graphics_pipeline_import_info() helper
It also initializes dynamic states and active stages. It will also be
used when creating a graphics pipeline library.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17542>
Samuel Pitoiset [Thu, 14 Jul 2022 12:26:53 +0000 (14:26 +0200)]
radv: remove unused pCreateInfo from radv_pipeline_init_blend_state()
I missed this one last time.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17542>
Danylo Piliaiev [Tue, 16 Aug 2022 13:45:39 +0000 (16:45 +0300)]
tu: Disable LRZ write when alpha-to-coverage is enabled
Alpha-to-coverage acts like discard and happens after FS ends,
so like with discard LRZ write should be disabled.
With discard we don't know at the moment of binning whether
fragment would be not discarded, so we cannot write its depth to LRZ.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6876
Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18083>
Matt Turner [Tue, 16 Aug 2022 15:20:21 +0000 (11:20 -0400)]
intel/tools: Also look for 'batch' tag
This changed in the kernel at some point, but I'm not sure when.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18087>
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