Philip Reames [Thu, 8 Apr 2021 21:02:39 +0000 (14:02 -0700)]
[funcattrs] Infer nosync from instruction walk
Pretty straightforward use of existing infrastructure and port of the attributor inference rules for nosync.
A couple points of interest:
* I deliberately switched from "monotonic or better" to "unordered or better". This is simply me being conservative and is better in line with the rest of the optimizer. We treat monotonic conservatively pretty much everywhere.
* The operand bundle test change is suspicious. It looks like we might have missed something here, but if so, it's an issue with the existing nofree inference as well. I'm going to take a closer look at that separately.
* I needed to keep the previous inference from readnone. This surprised me, but made sense once I realized readonly inference goes to lengths to reason about local vs non-local memory and that writes to local memory are okay. This is fine for the purpose of nosync, but would e.g. prevent us from inferring nofree from readnone - which is slightly surprising.
Differential Revision: https://reviews.llvm.org/D99769
Arthur Eubanks [Thu, 8 Apr 2021 18:44:23 +0000 (11:44 -0700)]
[GVN] Properly invalidate ICF cache when we simplify a value
This fixes a "Cached first special instruction is wrong!" assert.
The assert fires because replacing a value with another can cause an
instruction to no longer be "special" to ICF. In this case,
devirtualization happened, turning an indirect call to a
call to a willreturn function which is no longer special.
Reviewed By: nikic, rnk
Differential Revision: https://reviews.llvm.org/D99977
Dan Liew [Thu, 8 Apr 2021 04:33:24 +0000 (21:33 -0700)]
Include `count` in AppleClang toolchains.
The motivation here is so we can run the compiler-rt tests
from a standalone build against AppleClang.
In particular the `Posix/halt_on_error-torture.cpp` and
`Posix/halt_on_error_suppress_equal_pcs.cpp` ASan test cases currently
require this binary for the tests to pass.
rdar://
76366784
Differential Revision: https://reviews.llvm.org/D100087
Thomas Preud'homme [Wed, 10 Mar 2021 13:53:40 +0000 (13:53 +0000)]
[FileCheck, test] Rename checkWildcardRegexCharMatchFailure
Proposed edit https://reviews.llvm.org/D97845#inline-922769 in D97845
suggests the checkWildcardRegexCharMatchFailure function name is
misleading because it is not clear it checks for a match failure on each
character in the string parameter. This commit renames it to an
hopefully clearer name.
Reviewed By: jdenny
Differential Revision: https://reviews.llvm.org/D98343
Konstantin Zhuravlyov [Thu, 8 Apr 2021 20:42:05 +0000 (16:42 -0400)]
AMDGPU: Add gfx90c support to code object v2 for backwards compatibility
Differential Revision: https://reviews.llvm.org/D100126
Stanislav Mekhanoshin [Thu, 8 Apr 2021 20:24:46 +0000 (13:24 -0700)]
[AMDGPU] Check for all meta instrs in GCNRegBankReassign
It used to work correctly even with a KILL, but there is
no reason to consider meta instructions since they do not
create real HW uses.
Differential Revision: https://reviews.llvm.org/D100135
Jason Molenda [Thu, 8 Apr 2021 20:28:59 +0000 (13:28 -0700)]
Add setting to disable LanguageRuntime UnwindPlans
When debugging LanguageRuntime unwindplans, it can be
helpful to disable their use and see the normal
stack walk. Add a setting for this.
Differential Revision: https://reviews.llvm.org/D99828
Nikita Popov [Sat, 3 Apr 2021 13:57:58 +0000 (15:57 +0200)]
[LoopRotate] Don't split loop pass manager
After D99249 we use three different loop pass managers for LICM,
LoopRotate and LICM+LoopUnswitch. This happens because LazyBFI
and LazyBPI are not preserved by LoopRotate (note that D74640
is no longer needed). Avoid this by marking them as preserved.
My understanding of D86156 is that it is okay to simply preserve
them (which LoopUnswitch already does for the same reason) and
rely on callbacks to deal with deleted blocks.
Differential Revision: https://reviews.llvm.org/D99843
Stanislav Mekhanoshin [Wed, 7 Apr 2021 22:22:48 +0000 (15:22 -0700)]
[AMDGPU] Allow -amdgpu-unsafe-fp-atomics to ignore denorm mode
Fixes: SWDEV-274276
Differential Revision: https://reviews.llvm.org/D100072
Xiangling Liao [Thu, 8 Apr 2021 17:40:27 +0000 (13:40 -0400)]
[AIX] Support init priority attribute
Differential Revision: https://reviews.llvm.org/D99291
Arnamoy Bhattacharyya [Thu, 8 Apr 2021 18:33:04 +0000 (14:33 -0400)]
[flang][OpenMP] Add functionality to check "close nesting" of regions, which can be used for Semantic checks. Also adding more test cases.
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D99970
Hanhan Wang [Thu, 8 Apr 2021 19:15:15 +0000 (12:15 -0700)]
[mlir][StandardToSPIRV] Handle i1 case for lowering memref.load/store op
This patch unconditionally converts i1 types to i8 types on memrefs. If the
extensions or capabilities are not met, they will be converted to i32. Hence the
logic in IntLoadPattern and IntStorePattern are also updated.
Also added the implementation of SPIRVTypeConverter::getOptions().
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D99724
Wouter van Oortmerssen [Thu, 25 Mar 2021 23:04:10 +0000 (16:04 -0700)]
[WebAssembly] Fix for PIC external symbol ISEL
wasm64 was missing DAG ISEL patterns for external symbol based global.get, but simply adding these analogous to the existing 32-bit versions doesn't work.
This is because we are conflating the 32-bit global index with the pointer represented by the external symbol, which for wasm32 happened to work.
The simplest fix is to pretend we have a 64-bit global index. This sounds incorrect, but is immaterial since once this index is stored as a MachineOperand it becomes 64-bit anyway (and has been all along). As such, the EmitInstrWithCustomInserter based implementation I experimented with become a no-op and no further changes in the C++ code are required.
Differential Revision: https://reviews.llvm.org/D99904
Congzhe Cao [Thu, 8 Apr 2021 18:53:09 +0000 (14:53 -0400)]
[LoopInterchange] Fix transformation bugs in loop interchange
After loop interchange, the (old) outer loop header should not jump to
the `LoopExit`. Note that the old outer loop becomes the new inner loop
after interchange. If we branched to `LoopExit` then after interchange
we would jump directly from the (new) inner loop header to `LoopExit`
without executing the rest of outer loop.
This patch modifies adjustLoopBranches() such that the old outer
loop header (which becomes the new inner loop header) jumps to the
old inner loop latch which becomes the new outer loop latch after
interchange.
Reviewed By: bmahjour
Differential Revision: https://reviews.llvm.org/D98475
Levy Hsu [Thu, 8 Apr 2021 18:40:49 +0000 (11:40 -0700)]
[RISCV] Add InstAlias for Zbb Zbp and Zbs extension
Add InstAlias that allows the last operand to be an imm for following instructions:
1. Zbb or Zbp:
- ror
- rorw (RV64 Only)
2. Zbs
- best
- bclr
- binv
- bext
Reviewed By: craig.topper, jrtc27
Differential Revision: https://reviews.llvm.org/D100083
Sanjay Patel [Thu, 8 Apr 2021 18:29:33 +0000 (14:29 -0400)]
[InstCombine] fold min/max intrinsic with negated operand to abs
The smax case shows up in https://llvm.org/PR49885 .
The others seem unlikely, but we might as well try
for uniformity (although that could mean an extra
instruction to create "nabs").
smax -- https://alive2.llvm.org/ce/z/8yYaGy
smin -- https://alive2.llvm.org/ce/z/0_7zc_
umax -- https://alive2.llvm.org/ce/z/EcsZWs
umin -- https://alive2.llvm.org/ce/z/Xw6WvB
Sanjay Patel [Thu, 8 Apr 2021 17:47:48 +0000 (13:47 -0400)]
[InstCombine] add tests for min/max with negated operand; NFC
Craig Topper [Thu, 8 Apr 2021 16:12:57 +0000 (09:12 -0700)]
[RISCV] Prevent __builtin_riscv_orc_b_64 from being compiled RV32 target.
The backend can't handle this and will throw a fatal error from
type legalization. It's easy enough to fix that for this intrinsic
by just splitting the IR intrinsic since it works on individual bytes.
There will be other intrinsics in the future that would be harder
to support through splitting, for example grev, gorc, and shfl. Those
would require a compare and a select be inserted to check the MSB of
their control input.
This patch adds support for preventing this in the frontend with
a nice diagnostic.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D99984
Stanislav Mekhanoshin [Mon, 5 Apr 2021 20:01:44 +0000 (13:01 -0700)]
Set IgnoreLLVMUsed to false in CallGraph::addToCallGraph()
clang++ uses llvm.compiler.used in certain cases to preserve
symbol which is fully inlined. D96087 has resulted in undefined
symbols in such cases. Set it to false by default to preserve
old behavior but keep the option for specific uses where we
want to ignore these (e.g. to detect a potential indirect call
to a function).
Differential Revision: https://reviews.llvm.org/D99897
Jez Ng [Thu, 8 Apr 2021 18:11:45 +0000 (14:11 -0400)]
[lld-macho][nfc] Use varargs form of hasArg()
Jez Ng [Thu, 8 Apr 2021 18:12:20 +0000 (14:12 -0400)]
[lld-macho] Support -add_ast_path
Swift builds seem to use it. All it requires is emitting the
corresponding paths as STABS.
Fixes llvm.org/PR49385.
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D100076
Michał Górny [Thu, 8 Apr 2021 18:03:21 +0000 (20:03 +0200)]
[lldb] [test] Skip clone() tests on Linux/aarch64
Paul C. Anagnostopoulos [Thu, 8 Apr 2021 17:55:16 +0000 (13:55 -0400)]
Revert "[TableGen] Add support for the 'assert' statement in multiclasses"
This reverts commit
3b9a15d910a8c748b1444333a4a3905a996528bc.
Sushma Unnibhavi [Thu, 8 Apr 2021 17:55:55 +0000 (10:55 -0700)]
[lldb] Improve the documentation (#42017)
Added punctuation and changed "So for instance" to "For instance".
Fixes https://llvm.org/PR42017
Differential revision: https://reviews.llvm.org/D100053
Lei Zhang [Thu, 8 Apr 2021 17:40:35 +0000 (13:40 -0400)]
[mlir][linalg] Fix loop upper bounds in conv fusion test
Reviewed By: mravishankar
Differential Revision: https://reviews.llvm.org/D100112
Valeriy Savchenko [Wed, 24 Mar 2021 13:15:04 +0000 (16:15 +0300)]
[analyzer] Fix false positives in inner pointer checker (PR49628)
This patch supports std::data and std::addressof functions.
rdar://
73463300
Differential Revision: https://reviews.llvm.org/D99260
Valeriy Savchenko [Tue, 23 Mar 2021 12:38:55 +0000 (15:38 +0300)]
[analyzer] Fix crash on spaceship operator (PR47511)
rdar://
68954187
Differential Revision: https://reviews.llvm.org/D99181
Stephen Tozer [Thu, 8 Apr 2021 16:54:45 +0000 (17:54 +0100)]
Revert "[DebugInfo] Correctly track SDNode dependencies for list debug values"
Reverted due to failure on the sanitizer-x86_64-linux-fast bot.
This reverts commit
e10493eb5012a2c313471489646bde9595ea06c0.
Michał Górny [Fri, 12 Mar 2021 08:02:36 +0000 (09:02 +0100)]
[lldb] [Process] Watch for fork/vfork notifications
Watch for fork(2)/vfork(2) (also fork/vfork-style clone(2) on Linux)
notifications and explicitly detach the forked child process, and add
initial tests for these cases. The code covers FreeBSD, Linux
and NetBSD process plugins. There is no new user-visible functionality
provided -- this change lays foundations over subsequent work on fork
support.
Differential Revision: https://reviews.llvm.org/D98822
Yuanfang Chen [Thu, 8 Apr 2021 16:43:08 +0000 (09:43 -0700)]
abtest.py: support bisection based on a response file
Also makes LINK_TEST customizable from commandline with `--test` option.
Andrew Savonichev [Fri, 15 Jan 2021 13:08:58 +0000 (16:08 +0300)]
[MCA] Add tests for IPC on Cortex-A55
The tests compare IPC statistics that MCA provides with IPC values
measured on Cortex-A55 hardware. For hardware tests, each snippet is
run in a loop unrolled by 1000, and IPC is measured by linux-perf.
Several tests do not match the hardware: the skewed ALU is not
supported, LDR seem to be missing a forwarding path.
Differential Revision: https://reviews.llvm.org/D98174
Jez Ng [Thu, 8 Apr 2021 16:14:48 +0000 (12:14 -0400)]
[lld-macho][nfc] Extend abs-symbol.s to test for local absolute symbols
Addresses an old TODO.
Reviewed By: #lld-macho, oontvoo
Differential Revision: https://reviews.llvm.org/D100082
Jez Ng [Thu, 8 Apr 2021 16:14:47 +0000 (12:14 -0400)]
[lld-macho] Support --thinlto-jobs
The test is loosely based off LLD-ELF's `thinlto.ll`. However, I
found that test questionable because the the -save_temps behavior it
checks for is identical regardless of whether we are running in single-
or multi-threaded mode. I tried writing a test based on `--time-trace`
but couldn't get it to run deterministically... so I've opted to just
skip checking that behavior for now.
Reviewed By: #lld-macho, gkm
Differential Revision: https://reviews.llvm.org/D99356
Arjun P [Thu, 8 Apr 2021 15:29:58 +0000 (20:59 +0530)]
[MLIR] Support symbols in emptiness checks for FlatAffineConstraints
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D100114
Stephen Tozer [Fri, 26 Mar 2021 14:52:56 +0000 (14:52 +0000)]
[DebugInfo] Correctly track SDNode dependencies for list debug values
During SelectionDAG, we must track the SDNodes that each SDDbgValue depends on
to compute its value. These are ultimately derived from the location operands to
the SDDbgValue, but were stored in a separate vector prior to this patch. This
resulted in cases where one of the lists was updated incorrectly, resulting in
crashes during compilation. This patch fixes the issue by directly recomputing
the dependency list from the SDDbgOperands in getDependencies().
Differential Revision: https://reviews.llvm.org/D99423
Jay Foad [Thu, 8 Apr 2021 15:24:19 +0000 (16:24 +0100)]
[AMDGPU] Add some implicit uses to tests. NFC.
This is just to stop a future patch from optimizing away the things that
we actually want to check for.
Jay Foad [Thu, 8 Apr 2021 15:32:25 +0000 (16:32 +0100)]
[AMDGPU] SIFoldOperands: remove an unneeded isReg check. NFC.
Dávid Bolvanský [Thu, 8 Apr 2021 15:28:57 +0000 (17:28 +0200)]
Revert "Reduce the number of attributes attached to each function"
This reverts commit
053dc95839b3b8a36db46f8c419e36e632e989cd. It causes perf regressions - see discussion in D97116.
David Spickett [Thu, 8 Apr 2021 14:52:15 +0000 (15:52 +0100)]
[lsan] Mark 2 new lsan tests unsupported on arm-linux
These tests were added in:
1daa48f005bd477ba8711ecdf91a1f1515f01383
59e422c90bf4796fc73237e838d8954b4e2099b1
malloc_zero.c and realloc_too_big.c fail when only
leak sanitizer is enabled.
http://lab.llvm.org:8011/#/builders/59/builds/1635
(also in an armv8 32 bit build)
(I would XFAIL them but the same test is run with
address and leak sanitizer enabled and that one does
pass)
Pavel Labath [Sat, 27 Mar 2021 20:21:14 +0000 (21:21 +0100)]
[lldb/DWARF] Fix a crash parsing invalid dwarf (pr49678)
If the debug info is missing the terminating null die, we would crash
when trying to access the nonexisting children/siblings. This was
discovered because the test case for D98619 accidentaly produced such
input.
Pavel Labath [Thu, 8 Apr 2021 14:31:18 +0000 (16:31 +0200)]
[lldb] Re-skip TestVSCode_launch
The test is flaky (sleeps didn't help).
serge-sans-paille [Thu, 8 Apr 2021 14:09:40 +0000 (16:09 +0200)]
Jay Foad [Thu, 8 Apr 2021 13:33:51 +0000 (14:33 +0100)]
[AMDGPU] SIFoldOperands: make use of emplace_back. NFC.
Jay Foad [Thu, 8 Apr 2021 13:32:36 +0000 (14:32 +0100)]
[AMDGPU] SIFoldOperands: remove an unneeded make_early_inc_range. NFC.
Jay Foad [Thu, 8 Apr 2021 13:09:31 +0000 (14:09 +0100)]
[AMDGPU] SIFoldOperands: try harder to fold cndmask instructions
Look through copies to find more cases where the two values being
selected are identical. The motivation for this is just to be able to
remove the weird special case where tryFoldCndMask was called from
foldInstOperand, part way through folding a move-immediate into its
users, without regressing any lit tests.
Florian Hahn [Thu, 8 Apr 2021 13:15:39 +0000 (14:15 +0100)]
[LV] Pass VPWidenPHIRecipe to widenPHIInstruction (NFC).
Instead of passing the start value and the defined value to
widenPHIInstruction, pass the VPWidenPHIRecipe directly, which can be
used to get both (and more in future patches).
Valeriy Savchenko [Wed, 24 Mar 2021 13:50:19 +0000 (16:50 +0300)]
[analyzer] Fix dead store checker false positive
It is common to zero-initialize not only scalar variables,
but also structs. This is also defensive programming and
we shouldn't complain about that.
rdar://
34122265
Differential Revision: https://reviews.llvm.org/D99262
Joseph Tremoulet [Thu, 8 Apr 2021 13:06:52 +0000 (09:06 -0400)]
Support: mapped_file_region: Pass MAP_NORESERVE to mmap
This allows mapping larger files, delaying OOM failures until too many
pages of them are accessed. This is makes the behavior of the
mapped_file_region in this regard consistent between its "Unix" and
"Windows" implementations.
Guard the code witih #if defined(MAP_NORESERVE), consistent with other
uses of MAP_NORESERVE in llvm-project, because some FreeBSD versions do
not provide this flag.
Reviewed By: clayborg
Differential Revision: https://reviews.llvm.org/D96626
Jay Foad [Thu, 8 Apr 2021 13:04:49 +0000 (14:04 +0100)]
[AMDGPU] SIFoldOperands: make tryFoldCndMask a member function. NFC.
Sebastian Neubauer [Thu, 8 Apr 2021 12:00:33 +0000 (14:00 +0200)]
[AMDGPU] Fix computing live registers in prolog
ScratchExecCopy needs to be marked as live, we cannot use that register
while EXEC is stored in there.
Marking SGPRForFPSaveRestoreCopy and SGPRForBPSaveRestoreCopy as
available is unnecessary, they should not be live at that point anway.
Differential Revision: https://reviews.llvm.org/D100098
Sanjay Patel [Thu, 8 Apr 2021 12:28:59 +0000 (08:28 -0400)]
[InstCombine] add icmp with no-wrap add tests; NFC
Goes with D100095
Paul C. Anagnostopoulos [Mon, 5 Apr 2021 13:13:25 +0000 (09:13 -0400)]
[TableGen] Make behavior of list slice suffix consistent across all values
Differential Revision: https://reviews.llvm.org/D99883
Paul C. Anagnostopoulos [Thu, 1 Apr 2021 17:01:43 +0000 (13:01 -0400)]
[TableGen] Add support for the 'assert' statement in multiclasses
David Sherwood [Wed, 7 Apr 2021 08:13:00 +0000 (09:13 +0100)]
[CodeGen][AArch64] Fix isel crash for truncating FP stores
When attempting to truncate a FP vector and store the result out
to memory we crashed because we had no pattern for truncating FP
stores. In fact, we don't support these types of stores and the
correct fix is to stop marking these truncating stores as legal.
Tests have been added here:
CodeGen/AArch64/sve-fptrunc-store.ll
Differential Revision: https://reviews.llvm.org/D100025
Lei Zhang [Wed, 7 Apr 2021 18:52:16 +0000 (14:52 -0400)]
[mlir][spirv] Add control for non-32-bit scalar type emulation
Non-32-bit scalar types require special hardware support that may not
exist on all GPUs. This is reflected in SPIR-V as that non-32-bit scalar
types require special capabilities or extensions.
Previously when there is a non-32-bit type and no native support, we
unconditionally emulate it with 32-bit ones. This isn't good given that
it can have implications over ABI and data layout consistency.
This commit introduces an option to control whether to use 32-bit
types to emulate.
Differential Revision: https://reviews.llvm.org/D100059
Lei Zhang [Wed, 7 Apr 2021 18:52:07 +0000 (14:52 -0400)]
[mlir][spirv] Timely fail type conversion
Per the TypeConverter API contract, returning `llvm:None` means
other conversion rules should be tried. But we only have one
rule per input type. So there is no need to try others and we can
just directly fail, which should return `nullptr`. This avoids
unnecessary checks.
Differential Revision: https://reviews.llvm.org/D100058
Jay Foad [Thu, 8 Apr 2021 12:03:20 +0000 (13:03 +0100)]
[AMDGPU] SIFoldOperands: refactor tryFoldCndMask with early-outs. NFC.
Stephen Tozer [Fri, 26 Mar 2021 14:52:43 +0000 (14:52 +0000)]
[DebugInfo] Prevent invalid debug info being produced during LoopStrengthReduce
During LoopStrengthReduce, some of the SSA values that are used by debug values
may be lost and/or salvaged. After LSR we attempt to recover any undef debug
values, including any that were salvaged but then lost their values afterwards,
by replacing the lost values with any live equal values (plus a possible
constant offset) that have been gathered prior to running LSR. When we do this
we restore the debug value's original DIExpression, to undo any salvaging (as we
have gone back to using the original debug value).
This process can currently produce invalid debug info if the number of operands
has changed by salvaging during LSR. Replacing old values during the
applyEqualValues step does not change the number of location operands, which
means that when we restore the old DIExpression we may have a mismatch between
the number of operands used by the debug value and the number of operands
referenced by the DIExpression. This patch fixes this by restoring the full
original location metadata at the start of the applyEqualValues step, so that
there is no mismatch in operand count between the debug value and its
DIExpression.
Differential Revision: https://reviews.llvm.org/D98644
Roman Lebedev [Thu, 8 Apr 2021 11:56:05 +0000 (14:56 +0300)]
[NFC][X86][CostModel] Add some load/store tests w/ non-power-of-two elt cnt vectors
For example the cost to load <48 x i16> should likely be 3,
because that's just 3x load i256.
Michał Górny [Fri, 12 Mar 2021 08:02:36 +0000 (09:02 +0100)]
[lldb] [client] Support for multiprocess extension
Add a minimal support for the multiprocess extension in gdb-remote
client. It accepts PIDs as part of thread-ids, and rejects PIDs that
do not match the current inferior.
Differential Revision: https://reviews.llvm.org/D99603
Mikael Holmen [Thu, 8 Apr 2021 11:21:07 +0000 (13:21 +0200)]
[NVPTX] Fix compiler warning in NDEBUG build [NFC]
Without the fix we get
../lib/Target/NVPTX/NVPTXLowerArgs.cpp:236:24: error: lambda capture 'Arg' is not used [-Werror,-Wunused-lambda-capture]
auto IsALoadChain = [Arg](Value *Start) {
^~~
1 error generated.
Andrzej Warzynski [Thu, 8 Apr 2021 10:01:35 +0000 (10:01 +0000)]
[flang][nfc] Rename some test files
Update test names as per Flang's coding style guide [1]:
```
File names should use dashes, not underscores.
```
[1] https://github.com/llvm/llvm-project/blob/main/flang/docs/C%2B%2Bstyle.md#files
Anastasia Stulova [Thu, 8 Apr 2021 09:59:44 +0000 (10:59 +0100)]
[OpenCL][Docs] Fix typo in section label
Serguei Katkov [Thu, 8 Apr 2021 07:55:07 +0000 (14:55 +0700)]
[GreedyRA ORE] Add function level spill/reloads stats
Reviewers: reames, MatzeB, anemet, thegameg
Reviewed By: reames, thegameg
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D100014
Andrzej Warzynski [Tue, 30 Mar 2021 10:35:42 +0000 (10:35 +0000)]
[flang][driver] Add debug options not requiring semantic checks
This patch adds two debugging options in the new Flang driver
(flang-new):
*fdebug-unparse-no-sema
*fdebug-dump-parse-tree-no-sema
Each of these options combines two options from the "throwaway" driver
(left: f18, right: flang-new):
* `-fdebug-uparse -fdebug-no-semantics` --> `-fdebug-unparse-no-sema`
* `-fdebug-dump-parse-tree -fdebug-no-semantics` -->
`-fdebug-dump-parse-tree-no-sema`
There are no plans to implement `-fdebug-no-semantics` in the new
driver. Such option would be too powerful. Also, it would only make
sense when combined with specific frontend actions (`-fdebug-unparse`
and `-fdebug-dump-parse-tree`). Instead, this patch adds 2 specialised
options listed above. Each of these is implemented through a dedicated
FrontendAction (also added).
The new frontend actions are implemented in terms of a new abstract base
action: `PrescanAndSemaAction`. This new base class was required so that
we can have finer control over what steps within the frontend are
executed:
* `PrescanAction`: run the _prescanner_
* `PrescanAndSemaAction`: run the _prescanner_ and the _parser_ (new
in this patch)
* `PrescanAndSemaAction`: run the _prescanner_, _parser_ and run the
_semantic checks_
This patch introduces `PrescanAndParseAction::BeginSourceFileAction`.
Apart from the semantic checks removed at the end, it is similar to
`PrescanAndSemaAction::BeginSourceFileAction`.
Differential Revision: https://reviews.llvm.org/D99645
David Green [Thu, 8 Apr 2021 09:39:47 +0000 (10:39 +0100)]
[LV] Logical and/or select costs
D99674 stopped the folding of certain select operations into and/or, due
to incorrect folding in the presence of poison. D97360 added some costs
to attempt to account for the change, but only worked at the getUserCost
level, not the getCmpSelInstrCost that the vectorizer will use directly.
This adds similar logic into the vectorizer to handle these logical
and/or selects, treating them like and/or directly.
This fixes 60% performance regressions from code like the attached test
case.
Differential Revision: https://reviews.llvm.org/D99884
David Green [Thu, 8 Apr 2021 09:27:06 +0000 (10:27 +0100)]
[LV] Add a logical and/or select cost test. NFC
Fraser Cormack [Wed, 7 Apr 2021 09:03:22 +0000 (10:03 +0100)]
[RISCV] Support OR/XOR/AND reductions on vector masks
This patch adds RVV codegen support for OR/XOR/AND reductions for both
scalable- and fixed-length vector types. There are a few possible
codegen strategies for each -- vmfirst.m, vmsbf.m, and vmsif.m could be
used to some extent -- but the vpopc.m instruction was chosen since it
produces the scalar result in one instruction, after which scalar
instructions can finish off the computation.
The reductions are lowered identically for both scalable- and
fixed-length vectors, although some alternate strategies may be more
optimal on fixed-length vectors since it's cheaper to get the length of
those types.
Other reduction types were not deemed to be relevant for mask vectors.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D100030
Sven van Haastregt [Thu, 8 Apr 2021 08:51:44 +0000 (09:51 +0100)]
[OpenCL] Fix mipmap read_image return types
The return type did not match the function name.
Jason Molenda [Thu, 8 Apr 2021 08:44:13 +0000 (01:44 -0700)]
Reorg firmware corefile tests; add test for OS plugin loading
A little cleanup to how these firmware corefile tests are done; add
a test that loads a dSYM that loads an OS plugin, and confirm that
the OS plugin's threads are created.
Thomas Preud'homme [Sun, 4 Apr 2021 10:12:58 +0000 (11:12 +0100)]
[AMDGPU, test] Fix use of undef FileCheck var
Test CodeGen/AMDGPU/amdgpu.private-memory.ll and
CodeGen/AMDGPU/private-memory-r600.ll have a block of CHECK directives
whose prefix is inconsistent: R600-CHECK Vs R600. This leads to a
R600-NOT directive using an undefined CHAN variable due to R600-CHECK
directives never being considered by FileCheck. Fixing the prefix leads
to the testcase failing. As per https://reviews.llvm.org/D99865#2675235
this commit removes the directives instead since it is not possible to
write a reliable check.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D99865
Tobias Gysi [Thu, 8 Apr 2021 08:15:14 +0000 (08:15 +0000)]
[mlir] add support for index type in vectors.
The patch enables the use of index type in vectors. It is a prerequisite to support vectorization for indexed Linalg operations. This refactoring became possible due to the newly introduced data layout infrastructure. The data layout of a module defines the bitwidth of the index type needed to verify bitcasts and similar vector operations.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D99948
serge-sans-paille [Thu, 1 Apr 2021 20:18:55 +0000 (22:18 +0200)]
[clang] Speedup line offset mapping computation
Clang spends a decent amount of time in the LineOffsetMapping::get(...)
function. This function used to be vectorized (through SSE2) then the
optimization got dropped because the sequential version was on-par performance
wise.
This provides an optimization of the sequential version that works on a word at
a time, using (documented) bithacks to provide a portable vectorization.
When preprocessing the sqlite amalgamation, this yields a sweet 3% speedup.
This is a recommit of
6951b72334bbe4c189c71751edc1e361d7b5632c with endianness
and unsigned long vs uint64_t issues fixed (hopefully).
Differential Revision: https://reviews.llvm.org/D99409
LemonBoy [Thu, 8 Apr 2021 07:57:50 +0000 (09:57 +0200)]
[AsmParser] Recognize more escaped characters between single quotes
The GNU AS manual states the following about single-character constants enclosed within single quotes:
> Some backslash escapes apply to characters, \b, \f, \n, \r, \t, and \" with the same meaning as for strings, plus \' for a single quote.
Add two more characters to the switch handling this case to match GAS behaviour, plus a test to make sure nothing regresses.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D99609
Serguei Katkov [Thu, 8 Apr 2021 07:38:38 +0000 (14:38 +0700)]
[GreedyRA ORE] Extract computeNumberOfSplillsReloads to use in different places. NFC.
Extract one basic block handling to introduce stat computation for method scope.
Reviewers: reames, MatzeB, anemet, thegameg
Reviewed By: reames, thegameg
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D100013
Serguei Katkov [Thu, 8 Apr 2021 07:27:37 +0000 (14:27 +0700)]
[GreedyRA ORE] Extract stats in RAGreedyStats struct. NFC.
Combine all collected stats into separate struct RAGreedyStats
with add and report methods.
The motivation is to extend the number of statistics to capture and instead of
adding new parameters, just combine all of them into one structure.
Additionally I plan to use report from different places in future to report data
for function as well.
Reviewers: reames, MatzeB, anemet, thegameg
Reviewed By: thegameg
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D100012
Serguei Katkov [Tue, 6 Apr 2021 14:32:02 +0000 (21:32 +0700)]
[GreedyRA ORE] Compute ORE stats if extra analysis is enabled
To save compile time, avoid computation of stats if ORE will not emit it.
The motivation is to add more stats and compute it only if it will dumped.
Reviewers: reames, MatzeB, anemet, thegameg
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D100010
Esme-Yi [Thu, 8 Apr 2021 07:20:22 +0000 (07:20 +0000)]
[Debug-Info] Use inlined strings in .dwinfo section by default for DBX.
Summary: Set the default DwarfInlinedStrings as inlined strings for DBX, due to DBX does not support .dwstr section for now.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D99933
Hsiangkai Wang [Thu, 8 Apr 2021 02:49:10 +0000 (10:49 +0800)]
[RISCV] Add scalable offset under very large stack size.
If the stack size is larger than 12 bits, we have to use a scratch
register to store the stack size. Before we introduce the scalable stack
offset, we could simplify
%0 = ADDI %stack.0, 0
=>
%scratch = ... # sequence of instructions to move the offset into
%%scratch
%0 = ADD %fp, %scratch
However, if the offset contains scalable part, we need to consider it.
%0 = ADDI %stack.0, 0
=>
%scratch = ... # sequence of instructions to move the offset into
%%scratch
%scratch = ADD %fp, %scratch
%scalable_offset = ... # sequence of instructions for vscaled-offset.
%0 = ADD/SUB %scratch, %scalable_offset
Differential Revision: https://reviews.llvm.org/D100035
Hsiangkai Wang [Thu, 8 Apr 2021 02:44:09 +0000 (10:44 +0800)]
[NFC][RISCV] Add test for scalable offset under large stack size.
This test case shows that we access wrong stack slots when the frame
object has scalable offset under large stack size.
Differential Revision: https://reviews.llvm.org/D100084
Juneyoung Lee [Thu, 8 Apr 2021 06:44:42 +0000 (15:44 +0900)]
[Constant] Remove unused variable
Juneyoung Lee [Thu, 8 Apr 2021 06:20:08 +0000 (15:20 +0900)]
[Constant] ConstantStruct/Array should not lower poison to undef
This is a (late) follow-up patch of
8871a4b4cab8a56fd6ff12fd024002c3c79128b3 and
c95f39891a282ebf36199c73b705d4a2c78a46ce to make ConstantStruct::get/ConstantArray::getImpl
correctly return PoisonValue if all elements are poison.
This was found while discussing about the elements of a vector-typed UndefValue (D99853)
Hongtao Yu [Wed, 7 Apr 2021 01:32:23 +0000 (18:32 -0700)]
[CSSPGO] Move pseudo probes to the beginning of a block to unblock SelectionDAG combine.
Pseudo probes, when scattered in a block, can be chained dependencies of other regular DAG nodes and block DAG combine optimizations. To fix this, scattered probes in a block are grouped and placed at the beginning of the block. This shouldn't affect the profile quality.
Test Plan:
Reviewed By: wenlei, wmi
Differential Revision: https://reviews.llvm.org/D100002
Mehdi Amini [Thu, 8 Apr 2021 03:46:56 +0000 (03:46 +0000)]
Change the default value for `preloadDialectsInContext` for MlirOptMain
This option has been deprecated for 6 months, change the default setting for now before
future removal.
While clients can set the option to true for now, they should start
updating their passes to define the right `dependentDialects` in
preparation of the removal of this option. See the FAQ for more info:
https://mlir.llvm.org/getting_started/Faq/
Reviewed By: rriddle, jpienaar
Differential Revision: https://reviews.llvm.org/D99025
Dan Liew [Thu, 8 Apr 2021 04:21:07 +0000 (21:21 -0700)]
Include `llvm-config` and `not` in AppleClang toolchains.
The motivation here is so that we can configure and run compiler-rt
tests from a standalone build against AppleClang.
rdar://
75975846
Differential Revision: https://reviews.llvm.org/D100086
Philip Reames [Thu, 8 Apr 2021 03:59:40 +0000 (20:59 -0700)]
[docs] Document our norms around reverts
This has come up a few times recently, and I was surprised to notice that we don't have anything in the docs.
This patch deliberately sticks to stuff that is uncontroversial in the community. Everything herein is thought to be widely agreed to by a large majority of the community. A few things were noted and removed in review which failed this standard, if you spot anything else, please point it out.
Differential Revision: https://reviews.llvm.org/D99305
Fangrui Song [Thu, 8 Apr 2021 04:01:10 +0000 (21:01 -0700)]
[Driver] Drop $DEFAULT_TRIPLE-$name as a fallback program name
D13340 introduced this behavior which is not needed even for mips.
This was raised on https://lists.llvm.org/pipermail/cfe-dev/2020-May/065437.html
but no action was taken.
This was raised again in https://lists.llvm.org/pipermail/cfe-dev/2021-April/067974.html
"The LLVM host/target TRIPLE padding drama on Debian"
as it caused confusion. This patch drops the behavior.
Differential Revision: https://reviews.llvm.org/D99996
Serge Pavlov [Thu, 18 Mar 2021 15:07:27 +0000 (22:07 +0700)]
[RISCV] DAG nodes and pseudo instructions for CSR access
New custom DAG nodes were added to represent operations on CSR. These
nodes are lowered to corresponding pseudo instruction. Using the pseudo
instructions allows to specify different scheduling information for
operations on different system registers. It also make possible to
specify dependencies of instructions on specific system registers.
Differential Revision: https://reviews.llvm.org/D98936
hsmahesha [Thu, 8 Apr 2021 02:41:42 +0000 (08:11 +0530)]
[AMDGPU] Only use ds_read/write_b128 for alignment >= 16
PS: Submitting on behalf of Jay.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D100008
hsmahesha [Thu, 8 Apr 2021 02:37:32 +0000 (08:07 +0530)]
[AMDGPU] Add some exhaustive ds read/write alignment tests
PS: Submitting on behalf of Jay.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D100007
Chen Zheng [Thu, 8 Apr 2021 01:46:25 +0000 (21:46 -0400)]
[PowerPC] fixup killed flags for ri + addi to ri transformation
Fixup killed flags if DefMI and MI are not in the same basic blocks.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D100023
Congzhe Cao [Thu, 8 Apr 2021 01:15:15 +0000 (21:15 -0400)]
Revert "[LoopInterchange] Fix transformation bugs in loop interchange"
This reverts commit
6ec68bd815d00c1eec2a6b9766452554f0e6cb61.
Tony Tye [Thu, 8 Apr 2021 00:58:02 +0000 (00:58 +0000)]
[NFC][AMDGPU] Correct indentation in AMDGPUUsage.rst
Correct indentation that results in rST syntax error.
CongzheUalberta [Thu, 8 Apr 2021 00:44:32 +0000 (20:44 -0400)]
[LoopInterchange] Fix transformation bugs in loop interchange
After loop interchange, the (old) outer loop header should not jump to
`LoopExit`. Note that the old outer loop becomes the new inner loop
after interchange. If we branched to `LoopExit` then after interchange
we would jump directly from the (new) inner loop header to `LoopExit`
without executing the rest of (new) outer loop.
This patch modifies adjustLoopBranches() such that the old outer
loop header (which becomes the new inner loop header) jumps to the
old inner loop latch which becomes the new outer loop latch after
interchange.
Reviewed By: bmahjour
Differential Revision: https://reviews.llvm.org/D98475
Craig Topper [Thu, 8 Apr 2021 00:33:20 +0000 (17:33 -0700)]
[RISCV] Use multiclass inheritance to simplify some of riscv_vector.td. NFCI
We don't need to instantiate single multiclasses inside of
other multiclasses. We can use inheritance and save writing 'defm ""'.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D100074
Jez Ng [Wed, 7 Apr 2021 23:55:45 +0000 (19:55 -0400)]
[lld-macho] Parallelize __LINKEDIT generation
Benchmarking chromium_framework on a 3.2 GHz 16-Core Intel Xeon W Mac Pro:
N Min Max Median Avg Stddev
x 20 4.33 4.42 4.37 4.37 0.
021026299
+ 20 4.12 4.23 4.18 4.175 0.
035318103
Difference at 95.0% confidence
-0.195 +/- 0.0186025
-4.46224% +/- 0.425686%
(Student's t, pooled s = 0.0290644)
Reviewed By: #lld-macho, gkm
Differential Revision: https://reviews.llvm.org/D99998
Stanislav Mekhanoshin [Wed, 7 Apr 2021 17:34:53 +0000 (10:34 -0700)]
Disable use of SCC bit from asm
Differential Revision: https://reviews.llvm.org/D100069
Tony Tye [Tue, 30 Mar 2021 22:38:19 +0000 (22:38 +0000)]
[AMDGPU] Update gfx90a memory model support
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D100070
Stanislav Mekhanoshin [Wed, 7 Apr 2021 19:45:13 +0000 (12:45 -0700)]
[AMDGPU] Split GCNRegBankReassign
Allow pass to work separately with SGPR, VGPR registers or both.
This is NFC now but will be needed to split RA for separate
SGPR and VGPR passes.
Differential Revision: https://reviews.llvm.org/D100063
Florian Hahn [Wed, 7 Apr 2021 21:26:01 +0000 (22:26 +0100)]
[BasicAA] Add another GEP modulo test with shl with odd op.