Bas Nieuwenhuizen [Fri, 31 May 2019 00:23:44 +0000 (02:23 +0200)]
radv: Implement radv_GetPipelineExecutableInternalRepresentationsKHR.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Thu, 30 May 2019 23:57:43 +0000 (01:57 +0200)]
radv: Implement radv_GetPipelineExecutablePropertiesKHR.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Thu, 30 May 2019 23:06:27 +0000 (01:06 +0200)]
radv: Keep shader info when needed.
This allows enabling the shader info keeping on a per shader basis.
Also disables the cache on a per shader basis.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 1 Jun 2019 19:45:39 +0000 (21:45 +0200)]
radv: Add VK_KHR_pipeline_executable_properties in disabled state.
So we can add the functions.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 1 Jun 2019 18:54:35 +0000 (20:54 +0200)]
radv: Use string for nir dumping.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Allows us to easily dump all nir shaders for combined variants in
vega and simplifies ownership.
Bas Nieuwenhuizen [Sat, 1 Jun 2019 18:25:47 +0000 (20:25 +0200)]
radv: Get max workgroup size without nir.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 1 Jun 2019 16:46:21 +0000 (18:46 +0200)]
radv: Add utility function to calculate max waves.
Not AC because a lot of it is data extraction out of radv structs.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Francisco Jerez [Sat, 10 Aug 2019 19:45:46 +0000 (12:45 -0700)]
iris/gen9: Optimize slice and subslice load balancing behavior.
See "i965/gen9: Optimize slice and subslice load balancing behavior."
for the rationale.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Thu, 18 Jul 2019 01:30:45 +0000 (18:30 -0700)]
intel/genxml: Add GT_MODE hashing defs for Gen9.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Wed, 17 Jul 2019 21:56:18 +0000 (14:56 -0700)]
i965/gen9: Optimize slice and subslice load balancing behavior.
The default pixel hashing mode settings used for slice and subslice
load balancing are far from optimal under certain conditions (see the
comments below for the gory details). The top-of-the-line GT4 parts
suffer from a particularly severe performance problem currently due to
a subslice load balancing issue. Fixing this seems to improve
graphics performance across the board for most of the benchmarks in my
test set, up to ~20% in some cases, e.g. from SKL GT4:
unigine/valley: 3.44% ±0.11%
gfxbench/gl_manhattan31: 3.99% ±0.13%
gputest/pixmark_piano: 7.95% ±0.33%
synmark/OglTexFilterAniso: 15.22% ±0.07%
synmark/OglTexMem128: 22.26% ±0.06%
Lower-end platforms are also affected by some subslice load imbalance
to a lesser degree, especially during CCS resolve and fast clear
operations, which are handled specially here due to rasterization
ocurring in reduced CCS coordinates, which changes the semantics of
the pixel hashing mode settings.
No regressions seen during my tests on some SKL, KBL and BXT
configurations. Additional benchmark reports welcome on any Gen9
platforms (that includes anything with Skylake, Broxton, Kabylake,
Geminilake, Coffeelake, Whiskey Lake, Comet Lake or Amber Lake in your
renderer string).
P.S.: A similar problem is likely to be present on other non-Gen9
platforms, especially for CCS resolve and fast clear operations.
Will follow-up with additional patches fixing the hashing mode
for those once I have enough performance data to justify it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alyssa Rosenzweig [Tue, 6 Aug 2019 00:40:55 +0000 (17:40 -0700)]
pan/midgard: Handle 64-bit address in mir_mask_of_read_components
This is a bit of a hack, but it'll hold us over until we have 64-bit
support wired through.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 9 Aug 2019 17:40:23 +0000 (10:40 -0700)]
pan/midgard: Allocate separate spill indices for lowered moves
This helps RA be slightly more reasonable.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 9 Aug 2019 17:40:01 +0000 (10:40 -0700)]
pan/midgard: Extend liveness analysis to trinary ops
Fixes RA fails with multiple indirect SSBO writes.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 9 Aug 2019 15:56:44 +0000 (08:56 -0700)]
pan/midgard: Fix load/store pairing
This used a delicate hack to try to find indirect inputs and skip them
as candidates for pairing. Let's use a better criterion -- no sources --
and pair based on that.
We could do better, but that would require more complex data flow
analysis than we're interested in doing here.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 6 Aug 2019 21:07:10 +0000 (14:07 -0700)]
pan/midgard: Implement nir_intrinsic_load_num_work_groups
Just a sysval to route through.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 6 Aug 2019 20:47:17 +0000 (13:47 -0700)]
pan/midgard: Implement some compute builtins
We implement gl_WorkGroupID and gl_LocalInvocationID, which map to
ld_compute_id with special sources.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 6 Aug 2019 20:46:56 +0000 (13:46 -0700)]
pan/midgard: Rename ld_global_id -> ld_compute_id
It's used for more general loads within a compute shader.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 6 Aug 2019 01:17:27 +0000 (18:17 -0700)]
pan/midgard: Handle partial writes in liveness analysis
This allows liveness analysis within a loop to be more fine grained,
fixing RA failures with partial spilled movs within a loop, as well as
enabling a slight reduction of register pressure more generally:
total registers in shared programs: 350 -> 347 (-0.86%)
registers in affected programs: 12 -> 9 (-25.00%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 25.00% max: 25.00% x̄: 25.00% x̃: 25.00%
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 6 Aug 2019 01:09:36 +0000 (18:09 -0700)]
pan/midgard: Dump "no spill"?
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 6 Aug 2019 01:06:24 +0000 (18:06 -0700)]
pan/midgard: Absorb nonexistance sources
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 6 Aug 2019 00:59:53 +0000 (17:59 -0700)]
pan/midgard: Pretty-print destinations
They're not "sources" but they follow the same conventions.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 6 Aug 2019 00:58:52 +0000 (17:58 -0700)]
pan/midgard: Pretty-print units
Since we are seeing some use of MIR post-scheduling, let's get this
printed right.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 6 Aug 2019 00:52:56 +0000 (17:52 -0700)]
pan/midgard: Print mask in dumped MIR
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 5 Aug 2019 22:00:11 +0000 (15:00 -0700)]
pan/midgard: Add no_spill flag
Hint for the RA to avoid infinite spilling loops.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 5 Aug 2019 21:47:28 +0000 (14:47 -0700)]
pan/midgard: Generalize mir_mask_of_read_components
This now works for load/store and texture instructions as well as ALU.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 1 Aug 2019 17:03:02 +0000 (10:03 -0700)]
pan/midgard: Implement SSBO access
Just laying the groundwork. Reads and writes should be supported (both
direct and indirect, either int or float, vec1/2/3/4), but no bounds
checking is done at the moment.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 5 Aug 2019 16:19:39 +0000 (09:19 -0700)]
pan/midgard: Pipe uniform mask through when spilling
This is a corner case that happens a lot with SSBOs. Basically, if we
only read a few components of a uniform, we need to only spill a few
components or otherwise we try to spill what we spilled and RA hangs.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sat, 3 Aug 2019 00:10:18 +0000 (17:10 -0700)]
pan/midgard: Clamp sysval component count
We don't want to load a 128-bit sysval when 64-bits will do. Fixes RA
failures with SSBO indirect writes.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sat, 3 Aug 2019 00:09:54 +0000 (17:09 -0700)]
pan/midgard: Pass uploaded midgard_instruction through
We want to edit it after emission in some cases.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 2 Aug 2019 18:06:21 +0000 (11:06 -0700)]
pan/midgard: Allow sysval destination override
Sometimes a sysval is used to facilitate an instruction but is not the
instruction itself.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Fri, 9 Aug 2019 15:32:49 +0000 (08:32 -0700)]
panfrost: Force flush every compute job
This is of course suboptimal for performance, forcing each
glDispatchCompute call to be submitted separately to the kernel and
finish to completion. However, for the initial bring-up of compute jobs,
this simplifies quite a bit.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 1 Aug 2019 18:03:15 +0000 (11:03 -0700)]
panfrost: Add SSBO system value
For each SSBO index we get from Gallium/NIR, we need two pieces of
information in the shader:
1. The address of the SSBO in GPU memory. Within the shader, we'll be
accessing it with raw memory load/store, so we need the actual address,
not just an index.
2. The size of the SSBO. This is not strictly necessary, but at some
point, we may like to do bounds checking on SSBO accesses.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 8 Aug 2019 21:27:41 +0000 (14:27 -0700)]
gallium/util: Add u_stream_outputs_for_vertices helper
This u_prim.h helper determines the number of outputs for stream output,
given a particular primitive type and a vertex count. This is useful for
statically calculating sizes of stream output buffers (i.e. when there
is no geometry/tessellation shader in use).
This helper will be used in Panfrost's transform feedback
implementation, as you can probably guess since why else would I be
submitting it....
See also dEQP's getTransformFeedbackOutputCount routine.
v2: Simplify definition using new helpers, which also extends to non-ES2
primitive types (Eric).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Marek Olšák [Thu, 1 Aug 2019 19:49:39 +0000 (15:49 -0400)]
radeonsi: remove the always_nir option
tgsi_to_nir is no longer optional if NIR is enabled.
Marek Olšák [Thu, 1 Aug 2019 18:47:03 +0000 (14:47 -0400)]
radeonsi/nir: implement default tess level system values
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Marek Olšák [Thu, 1 Aug 2019 18:38:40 +0000 (14:38 -0400)]
compiler: add SYSTEM_VALUE_TESS_LEVEL_OUTER/INNER_DEFAULT
TCS system values for internal passthru TCS, needed by radeonsi NIR support
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Marek Olšák [Thu, 1 Aug 2019 18:21:41 +0000 (14:21 -0400)]
gallium: add TGSI_SEMANTIC_DEFAULT_OUTER/INNER_LEVEL
for radeonsi NIR support.
Marek Olšák [Thu, 1 Aug 2019 18:16:01 +0000 (14:16 -0400)]
tgsi_to_nir: handle tess level inner/outer varyings
for internal radeonsi shaders
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Marek Olšák [Thu, 1 Aug 2019 16:29:05 +0000 (12:29 -0400)]
tgsi_to_nir: add support for the stencil FS output
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Marek Olšák [Thu, 1 Aug 2019 16:25:12 +0000 (12:25 -0400)]
tgsi_to_nir: add support for TEX_LZ
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Marek Olšák [Thu, 1 Aug 2019 01:52:48 +0000 (21:52 -0400)]
compiler: add SYSTEM_VALUE_USER_DATA_AMD
for internal radeonsi shaders
Marek Olšák [Thu, 1 Aug 2019 01:33:37 +0000 (21:33 -0400)]
compiler: add shader_info.cs.user_data_components_amd
Marek Olšák [Thu, 1 Aug 2019 01:30:22 +0000 (21:30 -0400)]
tgsi_to_nir: add basic compute shader support
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Marek Olšák [Thu, 1 Aug 2019 01:17:47 +0000 (21:17 -0400)]
tgsi_to_nir: add support for LOAD & STORE with SSBOs and images
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Marek Olšák [Thu, 1 Aug 2019 01:17:05 +0000 (21:17 -0400)]
tgsi_to_nir: make setup_texture_info reusable
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Marek Olšák [Wed, 31 Jul 2019 21:31:52 +0000 (17:31 -0400)]
tgsi_to_nir: add support for TXF_LZ
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Marek Olšák [Wed, 31 Jul 2019 20:55:33 +0000 (16:55 -0400)]
compiler: add shader_info.vs.blit_sgprs_amd
for internal radeonsi shaders
Marek Olšák [Wed, 31 Jul 2019 21:16:23 +0000 (17:16 -0400)]
tgsi_to_nir: be careful about not losing any TGSI properties silently (v2)
v2: squash with Timur Kristof's commit
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Marek Olšák [Wed, 31 Jul 2019 21:15:18 +0000 (17:15 -0400)]
tgsi/scan: don't set GS_INVOCATIONS for all shader stages
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Marek Olšák [Thu, 1 Aug 2019 01:16:12 +0000 (21:16 -0400)]
compiler: add ACCESS_STREAM_CACHE_POLICY
radeonsi will use this.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Marek Olšák [Thu, 1 Aug 2019 01:28:40 +0000 (21:28 -0400)]
gallium: add AMD-specific compute TGSI enums
for tgsi_to_nir
Marek Olšák [Wed, 31 Jul 2019 20:45:21 +0000 (16:45 -0400)]
gallium: add TGSI_PROPERTY_VS_BLIT_SGPRS_AMD for tgsi_to_nir
needed by radeonsi NIR support
Marek Olšák [Fri, 2 Aug 2019 23:11:53 +0000 (19:11 -0400)]
st/mesa: don't allocate mipmapped texture for NEAREST_MIPMAP_LINEAR
Reviewed-by: Brian Paul <brianp@vmware.com>
Kenneth Graunke [Thu, 8 Aug 2019 08:44:52 +0000 (01:44 -0700)]
glsl: Optimize the SoftFP64 shader when first creating it.
By optimizing the shader before inlining, we avoid having to redo this
work for each inlined copy of a function. It should also reduce the
memory consumption a bit.
This cuts the KHR-GL46.arrays_of_arrays_gl.SubroutineFunctionCalls2
runtime by 25% on my Icelake. That test compiles many shaders, which
contain large types (dmat4) and division (expensive operations).
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Christian Gmeiner [Mon, 12 Aug 2019 09:09:47 +0000 (11:09 +0200)]
etnaviv: fix compile warnings in release build
[27/31] Compiling C object 'src/gallium/drivers/etnaviv/df32d18@@etnaviv@sta/etnaviv_compiler_nir.c.o'.
In file included from ../../src/gitlab_mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c:552:
../../src/gitlab_mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.h: In function 'ra_assign':
../../src/gitlab_mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.h:903:9: warning: unused variable 'ok' [-Wunused-variable]
bool ok = ra_allocate(g);
^~
../../src/gitlab_mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c: In function 'etna_compile_shader_nir':
../../src/gitlab_mesa/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c:663:9: warning: unused variable 'ok' [-Wunused-variable]
bool ok = emit_shader(c->nir, &options, &v->num_temps, &num_consts);
^~
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Bas Nieuwenhuizen [Sat, 10 Aug 2019 13:04:30 +0000 (15:04 +0200)]
radv: Do not setup attachments without a framebuffer.
Test that found this: dEQP-VK.geometry.layered.1d_array.secondary_cmd_buffer
Fixes:
49e6c2fb78c "radv: Store color/depth surface info in attachment info instead of framebuffer."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Mon, 12 Aug 2019 12:41:49 +0000 (07:41 -0500)]
anv: Implement VK_EXT_subgroup_size_control version 2
The version bump adds a proper features struct.
Fixes:
d10de253097 "anv: Implement VK_EXT_subgroup_size_control"
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Jason Ekstrand [Mon, 12 Aug 2019 12:37:54 +0000 (07:37 -0500)]
vulkan: Update the XML and headers to 1.1.119
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bas Nieuwenhuizen [Sat, 3 Aug 2019 23:34:19 +0000 (01:34 +0200)]
radv: Hash Wave32 settings in shader key.
Can result in different shaders.
Fixes:
8a86908e9a7 "radv/gfx10: add Wave32 support for vertex, tessellation and geometry shaders"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 3 Aug 2019 23:29:53 +0000 (01:29 +0200)]
radv: Properly use Wave64 for non-NGG GS and copy shader.
Fixes:
8a86908e9a7 "radv/gfx10: add Wave32 support for vertex, tessellation and geometry shaders"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 3 Aug 2019 22:48:05 +0000 (00:48 +0200)]
radv: Put wave size in shader options/info.
Instead of having the three values everywhere. This is also more
future proof if we want the driver to make those decisions eventually.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Fri, 2 Aug 2019 21:06:37 +0000 (23:06 +0200)]
relnotes: Make entries for radv more consistent.
Always use 'on' as for the rest of the drivers.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Fri, 2 Aug 2019 21:05:43 +0000 (23:05 +0200)]
relnotes: Add new exts on radv for 19.2.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tapani Pälli [Mon, 12 Aug 2019 07:44:41 +0000 (10:44 +0300)]
iris: reorder arguments as expected by the function
CID: 1452262
Fixes:
b4c54894bba "iris: Handle vertex shader with window space position"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Tapani Pälli [Mon, 12 Aug 2019 05:33:21 +0000 (08:33 +0300)]
iris/android: move iris_query.c to 'per gen' LIBIRIS_SRC_FILES
Fixes Iris build on Android.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Sun, 11 Aug 2019 14:46:03 +0000 (07:46 -0700)]
iris: Free query on error path
CID: 1452276
Kenneth Graunke [Sun, 11 Aug 2019 14:44:41 +0000 (07:44 -0700)]
iris: Add missing 'break'
We don't want to fall through to unreachable().
CID: 1452277
Caio Marcelo de Oliveira Filho [Thu, 8 Aug 2019 17:00:45 +0000 (10:00 -0700)]
spirv: Drop lower_workgroup_access_to_offsets
Intel drivers are not using this anymore, and turnip still don't have
Compute Shaders, so won't make a difference to stop using this option.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Rob Clark <robdclark@chromium.org>
Caio Marcelo de Oliveira Filho [Thu, 8 Aug 2019 17:55:50 +0000 (10:55 -0700)]
i965/spirv: Lower shared memory later
Instead of asking spirv_to_nir to lower the workgroup (shared memory)
to offsets, keep them as derefs longer, then lower it later on.
Because Workgroup memory doesn't have explicit offsets, we need to set
those using nir_lower_vars_to_explicit_types before calling the I/O
lowering pass.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Danylo Piliaiev [Wed, 17 Apr 2019 11:27:16 +0000 (14:27 +0300)]
i965: Use force_compat_profile driconf option
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Engestrom [Fri, 9 Aug 2019 22:41:53 +0000 (23:41 +0100)]
i965: fix mem leak in error path
Fixes:
8ae6667992ccca41d088 ("intel/perf: move query_object into perf")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Eric Engestrom [Fri, 9 Aug 2019 22:46:50 +0000 (23:46 +0100)]
gitlab-ci: simplify $CROSS option
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Sat, 10 Aug 2019 06:27:29 +0000 (23:27 -0700)]
iris: minor restyling
Mark Janes [Wed, 3 Jul 2019 23:27:22 +0000 (16:27 -0700)]
iris/query: enable amd performance monitors
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Mark Janes [Wed, 3 Jul 2019 23:13:26 +0000 (16:13 -0700)]
iris/perf: get monitor results
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Mark Janes [Wed, 3 Jul 2019 22:36:42 +0000 (15:36 -0700)]
iris/perf: add begin/end hooks
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Mark Janes [Wed, 3 Jul 2019 19:50:01 +0000 (12:50 -0700)]
iris/perf: add delete query
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Mark Janes [Wed, 3 Jul 2019 19:38:16 +0000 (12:38 -0700)]
iris/perf: implement iris_create_monitor_object
This is the first call that provides the iris context to the monitor
implementation. On the first call, use the iris context to initialize
the monitor context.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Mark Janes [Mon, 22 Apr 2019 18:43:12 +0000 (11:43 -0700)]
iris/perf: implement routines to return counter info
With this commit, Iris will report that AMD_performance_monitor is
supported, and will allow the caller to query the available metrics.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Engestrom [Fri, 9 Aug 2019 22:34:29 +0000 (23:34 +0100)]
anv: add missing `break`
Fixes:
f6e7de41d7b15185b746 ("anv: Implement VK_EXT_line_rasterization")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Fri, 9 Aug 2019 13:14:38 +0000 (16:14 +0300)]
util: drop final reference to p_compiler.h
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Lionel Landwerlin [Fri, 9 Aug 2019 13:05:56 +0000 (16:05 +0300)]
util: os_misc: drop p_compiler.h include
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Lionel Landwerlin [Fri, 9 Aug 2019 13:02:42 +0000 (16:02 +0300)]
util: u_math: drop p_compiler.h include
This file was moved from gallium so drop depending on gallium headers.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Lionel Landwerlin [Fri, 9 Aug 2019 13:52:30 +0000 (16:52 +0300)]
vc4: prepare for p_compiler.h dependency removal
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Lionel Landwerlin [Fri, 9 Aug 2019 13:01:04 +0000 (16:01 +0300)]
amd: prepare dropping include of p_compiler.h
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Lionel Landwerlin [Fri, 9 Aug 2019 13:00:30 +0000 (16:00 +0300)]
mesa: be consistent on GL_TRUE/GL_FALSE & TRUE/FALSE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Lionel Landwerlin [Fri, 9 Aug 2019 12:59:42 +0000 (15:59 +0300)]
mesa: drop some p_compiler.h types
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Lionel Landwerlin [Fri, 9 Aug 2019 12:59:10 +0000 (15:59 +0300)]
mesa: add stddef include in preparation for dropping p_compiler.h
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Lionel Landwerlin [Fri, 9 Aug 2019 13:39:58 +0000 (16:39 +0300)]
panfrost: prepare for p_compiler.h dependency removal
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Lionel Landwerlin [Fri, 9 Aug 2019 13:01:22 +0000 (16:01 +0300)]
i965: don't use p_compiler.h types
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Tue, 6 Aug 2019 10:28:31 +0000 (11:28 +0100)]
gitlab-ci: generate meson cross-files earlier
Suggested-by: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Alyssa Rosenzweig [Wed, 7 Aug 2019 16:49:07 +0000 (09:49 -0700)]
panfrost: Assign varying buffers dynamically
Rather than hardcoding certain varying buffer indices "by convention",
work it out at draw time. This added flexibility is needed for
futureproofing and will be enable streamout.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 7 Aug 2019 16:38:53 +0000 (09:38 -0700)]
panfrost: Assign indices at draw-time
This will allow us to shuffle buffers.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 7 Aug 2019 16:16:32 +0000 (09:16 -0700)]
panfrost: Break out pan_varyings.c
This code is fairly self-contained, so let's factor it out of the giant
pan_context.c monster.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 8 Aug 2019 16:21:27 +0000 (09:21 -0700)]
panfrost: Enable PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
Just as easy/hard as the rest of XFB.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 6 Aug 2019 23:43:28 +0000 (16:43 -0700)]
panfrost: Import streamout data structures
Pretty much copypasted from v3d to jumpstart us.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 8 Aug 2019 16:16:05 +0000 (09:16 -0700)]
pan/midgard: Account for swizzle/mask in st_vary
Register allocation for varying stores is a bit different, since the
instructions ignore the writemask (varyings are normalized
packed/vectorized..)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 8 Aug 2019 16:23:29 +0000 (09:23 -0700)]
pan/decode: Resolve crash with NULL attr/varyings
This case needs more investigation, but this was found with geometry
shaders.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Krzysztof Raszkowski [Fri, 9 Aug 2019 15:04:57 +0000 (17:04 +0200)]
gallium/swr: Fix glClear when it's used with glEnable/glDisable GL_SCISSOR_TEST
When GL_SCISSOR_TEST is enabled glClear is handled by state tracker
and there is no need to do this in gallium driver.
Reviewed-by: Alok Hota alok.hota@intel.com
Gurchetan Singh [Fri, 9 Aug 2019 01:39:17 +0000 (18:39 -0700)]
util: Revert "util: added missing headers in anon-file"
This reverts commit
c73988300f943e185a50aaba015f2f114ffcb262.
Reason: Made a fix for this, then saw @eric's change
("util/anon_file: add missing"), but some sequence of events
I don't really remember caused this to get merged. So revert ;-)
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>