Randy Dunlap [Thu, 16 Jul 2020 01:28:58 +0000 (18:28 -0700)]
bcm963xx_tag.h: fix duplicated word
Change doubled word "is" to "it is".
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: linux-mips@vger.kernel.org
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Chuanhong Guo [Tue, 13 Oct 2020 02:05:47 +0000 (10:05 +0800)]
mips: ralink: enable zboot support
Some of these ralink devices come with an ancient u-boot which can't
extract LZMA properly when image gets too big.
Enable zboot support to get a self-extracting kernel instead of relying
on broken u-boot support.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Mon, 12 Oct 2020 19:27:39 +0000 (21:27 +0200)]
MIPS: ingenic: Remove CPU_SUPPORTS_HUGEPAGES
While it is true that Ingenic SoCs support huge pages, we cannot use
them yet as PTEs don't have any single bit that is free. Right now,
having that symbol only causes build errors, so remove it until the
situation with PTEs is resolved.
Fixes:
f0f4a753079c ("MIPS: generic: Add support for Ingenic SoCs")
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Fri, 9 Oct 2020 12:26:48 +0000 (14:26 +0200)]
MIPS: cpu-probe: remove MIPS_CPU_BP_GHIST option bit
MIPS_CPU_BP_GHIST is only set two times and more or less immediately
used in cpu-probe.c itself. Remove this option to make room in options
word.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Thu, 8 Oct 2020 21:33:26 +0000 (23:33 +0200)]
MIPS: cpu-probe: introduce exclusive R3k CPU probe
Running a kernel on a R3k of machine definitly will never see one of
the newer CPU cores. And since R3k system usually are low on memory
we could save quite some kbytes:
text data bss dec hex filename
15070 88 32 15190 3b56 arch/mips/kernel/cpu-probe.o
844 4 16 864 360 arch/mips/kernel/cpu-r3k-probe.o
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Thu, 8 Oct 2020 21:33:25 +0000 (23:33 +0200)]
MIPS: cpu-probe: move fpu probing/handling into its own file
cpu-probe.c has grown when supporting more and more CPUs and there
are use cases where probing for all the CPUs isn't useful like
running on a R3k system. But still the fpu handling is nearly
the same. For sharing put the fpu code into it's own file.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Fri, 9 Oct 2020 12:14:46 +0000 (14:14 +0200)]
MIPS: replace add_memory_region with memblock
add_memory_region was the old interface for registering memory and
was already changed to used memblock internaly. Replace it by
directly calling memblock functions.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Tiezhu Yang [Sat, 10 Oct 2020 23:47:52 +0000 (07:47 +0800)]
MIPS: Loongson64: Clean up numa.c
(1) Replace nid_to_addroffset() with nid_to_addrbase() and then remove the
related useless code.
(2) Since end_pfn = start_pfn + node_psize, use "node_psize" instead of
"end_pfn - start_pfn" to avoid the redundant calculation.
(3) After commit
6fbde6b492df ("MIPS: Loongson64: Move files to the
top-level directory"), CONFIG_ZONE_DMA32 is always set for Loongson64
due to MACH_LOONGSON64 selects ZONE_DMA32, so no need to use ifdef any
more, just remove it.
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Tiezhu Yang [Sat, 10 Oct 2020 23:47:51 +0000 (07:47 +0800)]
MIPS: Loongson64: Select SMP in Kconfig to avoid build error
In the current code, CONFIG_SMP can be set as N by user on the Loongson
platform, then there exists the following build error under !CONFIG_SMP:
CC arch/mips/kernel/asm-offsets.s
In file included from ./include/linux/gfp.h:9:0,
from ./include/linux/xarray.h:14,
from ./include/linux/radix-tree.h:18,
from ./include/linux/fs.h:15,
from ./include/linux/compat.h:17,
from arch/mips/kernel/asm-offsets.c:12:
./include/linux/topology.h: In function 'numa_node_id':
./include/linux/topology.h:119:2: error: implicit declaration of function 'cpu_logical_map' [-Werror=implicit-function-declaration]
return cpu_to_node(raw_smp_processor_id());
^
cc1: some warnings being treated as errors
scripts/Makefile.build:117: recipe for target 'arch/mips/kernel/asm-offsets.s' failed
make[1]: *** [arch/mips/kernel/asm-offsets.s] Error 1
Select SMP in Kconfig to avoid the above build error and then remove
CONFIG_SMP=y in loongson3_defconfig.
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Mikhail Gusarov [Sat, 10 Oct 2020 10:08:58 +0000 (12:08 +0200)]
mips: octeon: Add Ubiquiti E200 and E220 boards
These boards are used in
- Ubiquiti EdgeRouter (E200),
- Ubiquiti EdgeRouter Pro (E200) and
- Ubiquiti Security Gateway Pro 4 (E220).
Signed-off-by: Mikhail Gusarov <dottedmag@dottedmag.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Wed, 7 Oct 2020 10:17:04 +0000 (12:17 +0200)]
MIPS: SGI-IP28: disable use of ll/sc in kernel
SGI-IP28 systems only use broken R10k rev 2.5 CPUs, which could lock
up, if ll/sc sequences are issued in certain order. Since those systems
are all non-SMP, we can disable ll/sc usage in kernel.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Tue, 6 Oct 2020 13:58:37 +0000 (15:58 +0200)]
MIPS: tx49xx: move tx4939_add_memory_regions into only user
tx4939_add_memory_regions() is only used in txx9/rbtx4939/prom.c.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 5 Oct 2020 11:28:46 +0000 (13:28 +0200)]
MIPS: pgtable: Remove used PAGE_USERIO define
There are no users of PAGE_USERIO.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 5 Oct 2020 11:28:45 +0000 (13:28 +0200)]
MIPS: alchemy: Share prom_init implementation
All boards have the same prom_init() function. Move it to common code and
delete the duplicates.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 5 Oct 2020 09:42:19 +0000 (11:42 +0200)]
MIPS: alchemy: Fix build breakage, if TOUCHSCREEN_WM97XX is disabled
Only include wm97xx touchscreen probing code, if driver is enabled.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Pujin Shi [Tue, 29 Sep 2020 09:30:47 +0000 (17:30 +0800)]
MIPS: process: include exec.h header in process.c
arch/mips/kernel/process.c:696:15: error: no previous prototype for 'arch_align_stack' [-Werror=missing-prototypes]
Signed-off-by: Pujin Shi <shipujin.t@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Pujin Shi [Tue, 29 Sep 2020 09:30:46 +0000 (17:30 +0800)]
MIPS: process: Add prototype for function arch_dup_task_struct
This commit adds a prototype to fix warning at W=1:
arch/mips/kernel/process.c:95:5: error: no previous prototype for 'arch_dup_task_struct' [-Werror=missing-prototypes]
Signed-off-by: Pujin Shi <shipujin.t@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Pujin Shi [Sun, 27 Sep 2020 09:22:05 +0000 (17:22 +0800)]
MIPS: idle: Add prototype for function check_wait
This commit adds a prototype to fix warning at W=1:
arch/mips/kernel/idle.c:126:13: error: no previous prototype for 'check_wait' [-Werror=missing-prototypes]
Signed-off-by: Pujin Shi <shipujin.t@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Thu, 17 Sep 2020 13:35:28 +0000 (15:35 +0200)]
MIPS: Increase range of CONFIG_FORCE_MAX_ZONEORDER
There is nothing that prevents us from using lower maximum values.
It's something that we actually want, when using bigger page sizes on
devices with low RAM.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
周琰杰 (Zhou Yanjie) [Tue, 22 Sep 2020 01:24:44 +0000 (09:24 +0800)]
MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.
1.Fix bugs when detecting ways value of JZ4775's L2 cache.
2.Fix bugs when detecting sets value and ways value of X1000E's L2 cache.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
周琰杰 (Zhou Yanjie) [Tue, 22 Sep 2020 01:24:43 +0000 (09:24 +0800)]
MIPS: Ingenic: Add system type for new Ingenic SoCs.
Add JZ4775, X1000E, X2000, and X2000E system type for cat /proc/cpuinfo
to give out JZ4775, X1000E, X2000 and X2000E.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
周琰杰 (Zhou Yanjie) [Tue, 22 Sep 2020 01:24:42 +0000 (09:24 +0800)]
dt-bindings: MIPS: Add X2000E based CU2000-Neo.
Add bindings for Ingenic X2000E based board, prepare for later dts.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Wed, 23 Sep 2020 07:26:44 +0000 (09:26 +0200)]
Revert "MIPS: OCTEON: use devm_platform_ioremap_resource"
This reverts commit
0ee69c589ec8659560910815f32c13af8587a779.
Resource is still needed later in the code, so using
devm_platform_ioremap_resource is no win at all.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Youling Tang [Sat, 19 Sep 2020 01:55:46 +0000 (09:55 +0800)]
MIPS: kexec: Add crashkernel=YM handling
When the kernel crashkernel parameter is specified with just a size,
we are supposed to allocate a region from RAM to store the crashkernel.
However, MIPS merely reserves physical address zero with no checking
that there is even RAM there.
Fix this by lifting similar code from x86, importing it to MIPS with the
MIPS specific parameters added. In the absence of any platform specific
information, we allocate the crashkernel region from the first 512MB of
physical memory (limited to CKSEG0 or KSEG0 address range).
When X is not specified, crash_base defaults to 0 (crashkernel=YM@XM).
E.g. without this patch:
The environment as follows:
[ 0.000000] MIPS: machine is loongson,loongson64c-4core-ls7a
...
[ 0.000000] Kernel command line: root=/dev/sda2 crashkernel=96M ...
The warning as follows:
[ 0.000000] Invalid memory region reserved for crash kernel
And the iomem as follows:
00200000-
0effffff : System RAM
00200000-
00b47f87 : Kernel code
00b47f88-
00dfffff : Kernel data
00e60000-
01f73c7f : Kernel bss
1a000000-
1bffffff : pci@
1a000000
...
With this patch:
After increasing crash_base <= 0 handling.
And the iomem as follows:
00200000-
0effffff : System RAM
00200000-
00b47f87 : Kernel code
00b47f88-
00dfffff : Kernel data
00e60000-
01f73c7f : Kernel bss
04000000-
09ffffff : Crash kernel
1a000000-
1bffffff : pci@
1a000000
...
Signed-off-by: Youling Tang <tangyouling@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Tiezhu Yang [Thu, 17 Sep 2020 12:39:01 +0000 (20:39 +0800)]
MIPS: Loongson64: Add UART node for LS7A PCH
When I update the latest kernel on the Loongson platform used with
LS7A bridge chip, the serial console has no output, this is because
the machine uses LS7A UART0 instead of CPU UART0, add UART node for
LS7A PCH to enhance the compatibility.
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
周琰杰 (Zhou Yanjie) [Sat, 19 Sep 2020 11:38:59 +0000 (19:38 +0800)]
MIPS: Ingenic: Add CPU nodes for Ingenic SoCs.
Add 'cpus' node to the jz4725b.dtsi, jz4740.dtsi, jz4770.dtsi,
jz4780.dtsi, x1000.dtsi, and x1830.dtsi files.
Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Tested-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Sun, 20 Sep 2020 21:13:42 +0000 (23:13 +0200)]
MIPS: malta: remove mach-malta/malta-dtshim.h header file
To clean up mach-* directories move external declaration of malta_dt_shim()
to mips-boards/malta.h and remove malta-dtshim.h.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Sun, 20 Sep 2020 21:08:34 +0000 (23:08 +0200)]
MIPS: malta: remove unused header file
Remove unused heasder file asm/mach-malta/malta-pm.h.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Sun, 20 Sep 2020 21:03:47 +0000 (23:03 +0200)]
MIPS: alchemy: remove unused ALCHEMY_GPIOINT_AU1000
Remove unused config option ALCHEMY_GPIOINT_AU1000.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Sun, 20 Sep 2020 21:03:46 +0000 (23:03 +0200)]
MIPS: alchemy: remove unused ALCHEMY_GPIOINT_AU1300
Remove unused config option ALCHEMY_GPIOINT_AU1300 and related code.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Sun, 20 Sep 2020 20:51:50 +0000 (22:51 +0200)]
MIPS: SGI-IP30: Move irq bits to better header files
Move HEART specific parts of mach-ip30/irq.h to asm/sgi/heart.h and IP30
specific parts to sgi-ip30/ip30-common.h.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Huacai Chen [Mon, 21 Sep 2020 09:12:28 +0000 (17:12 +0800)]
MIPS: Loongson-3: Calculate ra properly when unwinding the stack
Loongson-3 has 16-bytes load/store instructions: gslq and gssq. This
patch calculate ra properly when unwinding the stack, if ra is saved
by gssq and restored by gslq.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Huacai Chen [Mon, 21 Sep 2020 09:12:27 +0000 (17:12 +0800)]
MIPS: Loongson-3: Enable COP2 usage in kernel
Loongson-3's COP2 is Multi-Media coprocessor, it is disabled in kernel
mode by default. However, gslq/gssq (16-bytes load/store instructions)
overrides the instruction format of lwc2/swc2. If we wan't to use gslq/
gssq for optimization in kernel, we should enable COP2 usage in kernel.
Please pay attention that in this patch we only enable COP2 in kernel,
which means it will lose ST0_CU2 when a process go to user space (try
to use COP2 in user space will trigger an exception and then grab COP2,
which is similar to FPU). And as a result, we need to modify the context
switching code because the new scheduled process doesn't contain ST0_CU2
in its THERAD_STATUS probably.
For zboot, we disable gslq/gssq be generated by toolchain.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Huacai Chen [Mon, 21 Sep 2020 09:12:26 +0000 (17:12 +0800)]
MIPS: context switch: Use save/restore instead of set/clear for Status.CU2
Some processors (such as Loongson-3) need to enable CU2 in kernel mode,
current set/clear method will lose Status.CU2 during context switching,
so use save/restore method instead.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Pujin Shi [Mon, 21 Sep 2020 16:18:21 +0000 (00:18 +0800)]
MIPS: kernel: include probes-common.h header in branch.c
arch/mips/kernel/branch.c:876:5: error: no previous prototype for '__insn_is_compact_branch' [-Werror=missing-prototypes]
Signed-off-by: Pujin Shi <shipujin.t@gmail.com>
Signed-off-by: Pujin Shi <shipj@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Jason Yan [Fri, 11 Sep 2020 02:01:32 +0000 (10:01 +0800)]
MIPS: Make setup_elfcorehdr and setup_elfcorehdr_size static
This addresses the following sparse warning:
arch/mips/kernel/setup.c:446:33: warning: symbol 'setup_elfcorehdr_size'
was not declared. Should it be static?
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:35 +0000 (21:29 +0200)]
MAINTAINERS: Update paths to Ingenic platform code
Support for Ingenic chips has been moved to the generic MIPS platform.
Update the paths accordingly.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:34 +0000 (21:29 +0200)]
MIPS: configs: Regenerate configs of Ingenic boards
For each board the MACH_INGENIC_SOC option was selected instead of
MACH_INGENIC. Nothing else was changed in the menuconfig.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:33 +0000 (21:29 +0200)]
MIPS: jz4740: Rename jz4740 folders to ingenic
Now that all the jz4740 platform code has been removed, and we're left
with only a Kconfig and the cpu-feature-overrides.h file, finalize the
cleanup process by renaming the jz4740 and include/mach-jz4740 folders
to ingenic and include/mach-ingenic.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:32 +0000 (21:29 +0200)]
MIPS: jz4740: Drop all obsolete files
Support for Ingenic SoCs is now provided by the arch/mips/generic/ code,
so all files in the arch/mips/jz4740/ folder can dropped, except for the
Kconfig, and the cpu-feature-overrides.h header file.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:31 +0000 (21:29 +0200)]
MIPS: generic: Add support for Ingenic SoCs
Add support for Ingenic SoCs in arch/mips/generic/.
The Kconfig changes are here to ensure that it is possible to compile
either a generic kernel that supports Ingenic SoCs, or a Ingenic-only
kernel, both using the same code base, to avoid duplicated code.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:30 +0000 (21:29 +0200)]
MIPS: generic: Increase NR_IRQS to 256
128 IRQs is not enough to support Ingenic SoCs.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:29 +0000 (21:29 +0200)]
MIPS: generic: Add support for zboot
There is no reason we can't create compressed kernels here, so select
the option SYS_SUPPORTS_ZBOOT.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:28 +0000 (21:29 +0200)]
MIPS: generic: Support booting with built-in or appended DTB
The plat_get_fdt() checked that the kernel was booted using UHI before
reading the 'fw_passed_dtb' variable. However, this variable is also set
when the DT has been appended, or when it has been built into the kernel.
Support these usecases by removing the UHI check.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:27 +0000 (21:29 +0200)]
MIPS: generic: Init command line with fw_init_cmdline()
The function bootcmdline_init() in arch/mips/kernel/setup.c will
populate the boot_command_line string using the parameters hardcoded in
the kernel, and those provided in the devicetree file. Then, it would
append the content of the arcs_cmdline variable, which is filled by the
board's plat_mem_setup() function.
The plat_mem_setup() function for the generic MIPS board would just copy
the current boot_command_line to arcs_cmdline, which is nonsense for two
reasons:
- the result will be appended to the boot_command_line anyway, so all it
does is duplicate every single parameter on the command line;
- the code did not perform at all what it's supposed to, which is to
retrieve the parameters passed by the bootloader.
Fix this by calling fw_init_cmdline() in plat_mem_setup(), which will
properly initialize arcs_cmdline to the parameters passed by the
bootloader.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:26 +0000 (21:29 +0200)]
MIPS: generic: Allow boards to set system type
Check for the system_type variable in the get_system_type() function. If
non-NULL, return it as the system type.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:25 +0000 (21:29 +0200)]
MIPS: Kconfig: add MIPS_GENERIC_KERNEL symbol
The MIPS_GENERIC symbol now won't select any other configuration option.
The MIPS_GENERIC_KERNEL will select all the options that the previous
MIPS_GENERIC option did select, and will select MIPS_GENERIC as well.
The whole point of this, is that it now becomes possible to compile a
kernel for a SoC supported by the arch/mips/generic/ code, without
making that kernel generic itself.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:24 +0000 (21:29 +0200)]
MIPS: cpu-probe: ingenic: Fix broken BUG_ON
The previous code was doing:
BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
This only worked as the "cpu_has_counter" macro was overridden in
<cpu-feature-overrides.h>. The default "cpu_has_counter" macro is
non-constant, which triggered the BUG_ON() independently of the value
returned by the macro.
What we want to check here, is that *if* the macro was overridden to a
compile-time constant, then must be defined to zero, otherwise it's a
bug.
So the correct check is:
BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter);
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:23 +0000 (21:29 +0200)]
MIPS: cpu-probe: Mark XBurst CPU as having vtagged caches
XBurst CPUs present in Ingenic SoCs have virtually tagged caches,
according to the <cpu-features-override.h> header.
Add that information to cpu_probe_ingenic().
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:22 +0000 (21:29 +0200)]
MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WA
Previously, in cpu_probe_ingenic(), c->writecombine was set to
_CACHE_UNCACHED_ACCELERATED, but this macro was defined differently when
CONFIG_MACH_INGENIC was set. This made it impossible to support multiple
CPUs.
Address this issue by setting c->writecombine to _CACHE_CACHABLE_WA
directly and removing the dependency on CONFIG_MACH_INGENIC.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Sun, 6 Sep 2020 19:29:21 +0000 (21:29 +0200)]
MIPS: configs: lb60: Fix defconfig not selecting correct board
Since INGENIC_GENERIC_BOARD was introduced, the JZ4740_QI_LB60 option
is no longer the default, so the symbol has to be selected by the
defconfig, otherwise the kernel built will be for a generic Ingenic
board and won't have the Device Tree blob built-in.
Cc: stable@vger.kernel.org # v5.7
Fixes:
62249209a772 ("MIPS: ingenic: Default to a generic board")
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Huacai Chen [Fri, 11 Sep 2020 10:26:17 +0000 (18:26 +0800)]
MIPS: Loongson64: Increase NR_IRQS to 320
Modernized Loongson64 uses a hierarchical organization for interrupt
controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ
numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256)
is not enough to represent all interrupts, so let's increase NR_IRQS to
320 (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256).
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Youling Tang [Sat, 12 Sep 2020 01:54:39 +0000 (09:54 +0800)]
MIPS: netlogic: Remove unused code
Remove some unused code.
Signed-off-by: Youling Tang <tangyouling@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Qinglang Miao [Wed, 16 Sep 2020 06:21:27 +0000 (14:21 +0800)]
MIPS: OCTEON: use devm_platform_ioremap_resource
Note that error handling on the result of a call to platform_get_resource()
is unneeded when the value is passed to devm_ioremap_resource(), so remove
it. Then use the helper function that wraps the calls to
platform_get_resource() and devm_ioremap_resource() together.
Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Zhang Qilong [Thu, 17 Sep 2020 07:46:22 +0000 (15:46 +0800)]
MIPS: pci: use devm_platform_ioremap_resource_byname
Use the devm_platform_ioremap_resource_byname() helper instead of
calling platform_get_resource_byname() and devm_ioremap_resource()
separately.
Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Wei Li [Fri, 18 Sep 2020 01:41:11 +0000 (09:41 +0800)]
MIPS: Correct the header guard of r4k-timer.h
Rename the header guard of r4k-timer.h from __ASM_R4K_TYPES_H to
__ASM_R4K_TIMER_H what corresponding with the file name.
Signed-off-by: Wei Li <liwei391@huawei.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 24 Aug 2020 16:32:54 +0000 (18:32 +0200)]
MIPS: Remove mach-*/war.h
After conversion of all WAR defines we can now remove all mach-*/war.h
files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 24 Aug 2020 16:32:53 +0000 (18:32 +0200)]
MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WAR
CAVIUM_OCTEON_DCACHE_PREFETCH_WAR is a check for Octeon model CN6XXXX.
By using the version check we can remove the define.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 24 Aug 2020 16:32:52 +0000 (18:32 +0200)]
MIPS: Get rid of BCM1250_M3_WAR
BCM1250_M3_WAR is depending on CONFIG_CONFIG_SB1_PASS_2_WORKAROUNDS.
So using this option directly lets and remove define.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 24 Aug 2020 16:32:51 +0000 (18:32 +0200)]
MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS
SB1250 uart bug is related to PASS 2 workarounds. Use config
CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 24 Aug 2020 16:32:50 +0000 (18:32 +0200)]
MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option
Use a new config option to enable MIPS 34K ITLB workaround and remove
define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 24 Aug 2020 16:32:49 +0000 (18:32 +0200)]
MIPS: Convert R10000_LLSC_WAR info a config option
Use a new config option to enabel R1000_LLSC workaound and remove
define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 24 Aug 2020 16:32:48 +0000 (18:32 +0200)]
MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config option
Use a new config option to enable I-cache refill workaround and remove
define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 24 Aug 2020 16:32:47 +0000 (18:32 +0200)]
MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option
Use a new config option to enable TX49XX I-cache index invalidate
workaround and remove define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 24 Aug 2020 16:32:46 +0000 (18:32 +0200)]
MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR
Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented,
so removing defines for it won't change anything.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 24 Aug 2020 16:32:45 +0000 (18:32 +0200)]
MIPS: Convert R4600_V2_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V2 cacheop hit workaround
and remove define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 24 Aug 2020 16:32:44 +0000 (18:32 +0200)]
MIPS: Convert R4600_V1_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V1 cacheop hit workaround
and remove define from the different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Mon, 24 Aug 2020 16:32:43 +0000 (18:32 +0200)]
MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option
Use a new config option to enable R4600 V1 index I-cacheop workaround
and remove define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Fri, 4 Sep 2020 12:36:47 +0000 (14:36 +0200)]
MIPS: dts/ingenic: Cleanup qi_lb60.dts
Cleanup a bit the Device Tree file:
1. Respect the number of cells in GPIO descriptors and keyboard matrix;
2. Use 'ecc-engine' instead of deprecated 'ingenic,bch-controller'
property;
3. The NAND's rb-gpios is actually active high;
3. The FRE/FWE pins must be configured in the proper mode for the NAND
to work if it was not already done by the bootloader.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Jinyang He [Fri, 4 Sep 2020 10:29:51 +0000 (18:29 +0800)]
MIPS: Loongson64: Remove unused loongson_reboot.
Commit
1bdb7b76705a ("MIPS: Loongson64: Cleanup unused code")
left the loongson_reboot unused, delete it.
Signed-off-by: Jinyang He <hejinyang@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Jinyang He [Fri, 28 Aug 2020 01:53:03 +0000 (09:53 +0800)]
MIPS: p5600: Discard UCA config selection
Commit
2a5984360b01 ("MIPS: Drop CPU_SUPPORTS_UNCACHED_ACCELERATED")
removed UCA config, but left the selection unused, delete it.
Signed-off-by: Jinyang He <hejinyang@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Davidlohr Bueso [Mon, 31 Aug 2020 20:14:02 +0000 (13:14 -0700)]
MIPS: Use rcu to lookup a task in mipsmt_sys_sched_setaffinity()
The call simply looks up the corresponding task (without iterating
the tasklist), which is safe under rcu instead of the tasklist_lock.
In addition, the setaffinity counter part already does this.
Signed-off-by: Davidlohr Bueso <dbueso@suse.de>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Tue, 1 Sep 2020 14:26:51 +0000 (16:26 +0200)]
MIPS: Add support for ZSTD-compressed kernels
Add support for self-extracting kernels with a ZSTD compression.
Tested on a kernel for the GCW-Zero, it allows to reduce the size of the
kernel file from 4.1 MiB with gzip to 3.5 MiB with ZSTD, and boots just
as fast.
Compressed kernels are now also compiled with -D__DISABLE_EXPORTS in
order to disable the EXPORT_SYMBOL() macros inside of
lib/zstd/decompress.c.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Paul Cercueil [Tue, 1 Sep 2020 14:26:50 +0000 (16:26 +0200)]
lib: decompress_unzstd: Limit output size
The zstd decompression code, as it is right now, will most likely fail
on 32-bit systems, as the default output buffer size causes the buffer's
end address to overflow.
Address this issue by setting a sane default to the default output size,
with a value that won't overflow the buffer's end address.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Nick Terrell <terrelln@fb.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Tue, 25 Aug 2020 09:09:07 +0000 (11:09 +0200)]
MIPS: SGI-IP32: No need to include mc14818*.h
Nothing needs the includes in ip32-setup.c.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Tue, 25 Aug 2020 09:09:06 +0000 (11:09 +0200)]
MIPS: Remove unused header file m48t37.h
No users -> remove it.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Tue, 25 Aug 2020 09:09:05 +0000 (11:09 +0200)]
MIPS: Loongson2ef: Remove specific mc146818rtc.h
Loonson2ef's mc146818rtc.h is the same as the generic one -> remove it.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Acked-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Tue, 25 Aug 2020 09:09:04 +0000 (11:09 +0200)]
MIPS: SGI-IP27: No need for kmalloc.h
SGI-IP27 is always cache coherent so we can use generic kmalloc.h and
remove the ip27 specific one.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Sat, 22 Aug 2020 08:04:27 +0000 (10:04 +0200)]
MIPS: Remove PNX833x alias NXP_STB22x
Remove another unused MIPS platform.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Thomas Bogendoerfer [Sat, 22 Aug 2020 08:02:51 +0000 (10:02 +0200)]
MIPS: Paravirt: remove remaining pieces of paravirt
Commit
35546aeede8e ("MIPS: Retire kvm paravirt") removed
kvm paravirt support, but missed arch/mips/include/mach-paravirt.
Remove it as well.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Florian Fainelli [Sun, 26 Jul 2020 04:15:21 +0000 (21:15 -0700)]
MIPS: BCM47xx: Include bcm47xx_sprom.h
Now that bcm47xx_sprom.h contains a prototype for bcm47xx_fill_sprom,
include that header file directly from bcm47xx.h.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Florian Fainelli [Sun, 26 Jul 2020 04:15:20 +0000 (21:15 -0700)]
firmware: bcm47xx_sprom: Fix -Wmissing-prototypes warnings
bcm47xx_sprom.h did not include a prototype for bcm47xx_fill_sprom()
therefore add one, and make sure we do include that header to fix
-Wmissing-prototypes warnings.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Álvaro Fernández Rojas [Wed, 12 Aug 2020 07:52:35 +0000 (09:52 +0200)]
MIPS: BCM63xx: switch to SPDX license identifier
Use SPDX license indentifier instead of local reference to COPYING.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Álvaro Fernández Rojas [Wed, 12 Aug 2020 07:52:34 +0000 (09:52 +0200)]
MIPS: BCM63xx: refactor board declarations
Current board declarations are a mess. Let's put some order and make them
follow the same structure.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Álvaro Fernández Rojas [Wed, 12 Aug 2020 07:52:33 +0000 (09:52 +0200)]
MIPS: BCM63xx: enable EHCI for DWV-S0 board
BCM6358 SoCs have OHCI and EHCI controllers that share the same USB ports.
Therefore, the board should also have EHCI enabled.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Álvaro Fernández Rojas [Wed, 12 Aug 2020 07:52:32 +0000 (09:52 +0200)]
MIPS: BCM63xx: remove EHCI from BCM6348 boards
There's no EHCI controller on BCM6348.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Álvaro Fernández Rojas [Wed, 12 Aug 2020 07:52:31 +0000 (09:52 +0200)]
MIPS: BCM63xx: remove duplicated new lines
There are 3 duplicated new lines, let's remove them.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Aleksander Jan Bajkowski [Mon, 10 Aug 2020 18:09:46 +0000 (20:09 +0200)]
MIPS: lantiq: add missing GPHY clock aliases for ar10 and grx390
Add missing GPHY clock aliases for ar10 (xrx300) and grx390 (xrx330).
PMU in ar10 and grx390 differs from vr9. Ar10 has 3 and grx390 has 4
built-in GPHY compared to vr9 which has 2.
Corespondings PMU bit:
GPHY0 -> bit 29
GPHY1 -> bit 30
GPHY2 -> bit 31
GPHY3 -> bit 26
Tested on D-Link DWR-966 with OpenWRT.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Cc: linux-mips@vger.kernel.org
Cc: john@phrozen.org
Cc: hauke@hauke-m.de
Cc: tsbogend@alpha.franken.de
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Tiezhu Yang [Fri, 14 Aug 2020 10:31:30 +0000 (18:31 +0800)]
MIPS: Loongson: Use default CONFIG_FRAME_WARN as 2048 for Loongson64 to fix build warnings
After commit
70b838292bef ("MIPS: Update default config file for
Loongson-3"), CONFIG_VHOST_SCSI and CONFIG_VHOST are set when use
loongson3_defconfig, and then there exists the following two build
warnings related with these two configs:
CC [M] drivers/vhost/scsi.o
drivers/vhost/scsi.c: In function ‘vhost_scsi_flush’:
drivers/vhost/scsi.c:1374:1: warning: the frame size of 1040 bytes is larger than 1024 bytes [-Wframe-larger-than=]
}
^
LD [M] drivers/vhost/vhost_scsi.o
CC [M] drivers/vhost/vsock.o
LD [M] drivers/vhost/vhost_vsock.o
CC [M] drivers/vhost/vhost.o
drivers/vhost/vhost.c: In function ‘log_used’:
drivers/vhost/vhost.c:1896:1: warning: the frame size of 1040 bytes is larger than 1024 bytes [-Wframe-larger-than=]
}
^
CONFIG_FRAME_WARN=2048 can fix it, since the default CONFIG_FRAME_WARN
for 64BIT is 2048, just delete the CONFIG_FRAME_WARN line in defconfig.
config FRAME_WARN
int "Warn for stack frames larger than"
range 0 8192
default 2048 if GCC_PLUGIN_LATENT_ENTROPY
default 1280 if (!64BIT && PARISC)
default 1024 if (!64BIT && !PARISC)
default 2048 if 64BIT
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Zejiang Tang [Fri, 14 Aug 2020 02:40:24 +0000 (10:40 +0800)]
MIPS: ftrace: Remove redundant #ifdef CONFIG_DYNAMIC_FTRACE
There exists redundant #ifdef CONFIG_DYNAMIC_FTRACE in ftrace.c, remove it.
Signed-off-by: Zejiang Tang <tangzejiang@loongson.cn>
Reviewed-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Linus Torvalds [Sun, 16 Aug 2020 20:04:57 +0000 (13:04 -0700)]
Linux 5.9-rc1
Linus Torvalds [Sun, 16 Aug 2020 17:55:12 +0000 (10:55 -0700)]
Merge tag 'io_uring-5.9-2020-08-15' of git://git.kernel.dk/linux-block
Pull io_uring fixes from Jens Axboe:
"A few differerent things in here.
Seems like syzbot got some more io_uring bits wired up, and we got a
handful of reports and the associated fixes are in here.
General fixes too, and a lot of them marked for stable.
Lastly, a bit of fallout from the async buffered reads, where we now
more easily trigger short reads. Some applications don't really like
that, so the io_read() code now handles short reads internally, and
got a cleanup along the way so that it's now easier to read (and
documented). We're now passing tests that failed before"
* tag 'io_uring-5.9-2020-08-15' of git://git.kernel.dk/linux-block:
io_uring: short circuit -EAGAIN for blocking read attempt
io_uring: sanitize double poll handling
io_uring: internally retry short reads
io_uring: retain iov_iter state over io_read/io_write calls
task_work: only grab task signal lock when needed
io_uring: enable lookup of links holding inflight files
io_uring: fail poll arm on queue proc failure
io_uring: hold 'ctx' reference around task_work queue + execute
fs: RWF_NOWAIT should imply IOCB_NOIO
io_uring: defer file table grabbing request cleanup for locked requests
io_uring: add missing REQ_F_COMP_LOCKED for nested requests
io_uring: fix recursive completion locking on oveflow flush
io_uring: use TWA_SIGNAL for task_work uncondtionally
io_uring: account locked memory before potential error case
io_uring: set ctx sq/cq entry count earlier
io_uring: Fix NULL pointer dereference in loop_rw_iter()
io_uring: add comments on how the async buffered read retry works
io_uring: io_async_buf_func() need not test page bit
Mike Rapoport [Sun, 16 Aug 2020 14:24:03 +0000 (17:24 +0300)]
parisc: fix PMD pages allocation by restoring pmd_alloc_one()
Commit
1355c31eeb7e ("asm-generic: pgalloc: provide generic pmd_alloc_one()
and pmd_free_one()") converted parisc to use generic version of
pmd_alloc_one() but it missed the fact that parisc uses order-1 pages for
PMD.
Restore the original version of pmd_alloc_one() for parisc, just use
GFP_PGTABLE_KERNEL that implies __GFP_ZERO instead of GFP_KERNEL and
memset.
Fixes:
1355c31eeb7e ("asm-generic: pgalloc: provide generic pmd_alloc_one() and pmd_free_one()")
Reported-by: Meelis Roos <mroos@linux.ee>
Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
Tested-by: Meelis Roos <mroos@linux.ee>
Reviewed-by: Matthew Wilcox (Oracle) <willy@infradead.org>
Link: https://lkml.kernel.org/r/9f2b5ebd-e4a4-0fa1-6cd3-4b9f6892d1ad@linux.ee
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Sun, 16 Aug 2020 03:36:42 +0000 (20:36 -0700)]
Merge tag 'block-5.9-2020-08-14' of git://git.kernel.dk/linux-block
Pull block fixes from Jens Axboe:
"A few fixes on the block side of things:
- Discard granularity fix (Coly)
- rnbd cleanups (Guoqing)
- md error handling fix (Dan)
- md sysfs fix (Junxiao)
- Fix flush request accounting, which caused an IO slowdown for some
configurations (Ming)
- Properly propagate loop flag for partition scanning (Lennart)"
* tag 'block-5.9-2020-08-14' of git://git.kernel.dk/linux-block:
block: fix double account of flush request's driver tag
loop: unset GENHD_FL_NO_PART_SCAN on LOOP_CONFIGURE
rnbd: no need to set bi_end_io in rnbd_bio_map_kern
rnbd: remove rnbd_dev_submit_io
md-cluster: Fix potential error pointer dereference in resize_bitmaps()
block: check queue's limits.discard_granularity in __blkdev_issue_discard()
md: get sysfs entry after redundancy attr group create
Linus Torvalds [Sun, 16 Aug 2020 01:54:42 +0000 (18:54 -0700)]
Merge tag 'riscv-for-linus-5.9-mw1' of git://git./linux/kernel/git/riscv/linux
Pull RISC-V fix from Palmer Dabbelt:
"I collected a single fix during the merge window: we managed to break
the early trap setup on !MMU, this fixes it"
* tag 'riscv-for-linus-5.9-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Setup exception vector for nommu platform
Linus Torvalds [Sun, 16 Aug 2020 01:50:32 +0000 (18:50 -0700)]
Merge tag 'sh-for-5.9' of git://git.libc.org/linux-sh
Pull arch/sh updates from Rich Felker:
"Cleanup, SECCOMP_FILTER support, message printing fixes, and other
changes to arch/sh"
* tag 'sh-for-5.9' of git://git.libc.org/linux-sh: (34 commits)
sh: landisk: Add missing initialization of sh_io_port_base
sh: bring syscall_set_return_value in line with other architectures
sh: Add SECCOMP_FILTER
sh: Rearrange blocks in entry-common.S
sh: switch to copy_thread_tls()
sh: use the generic dma coherent remap allocator
sh: don't allow non-coherent DMA for NOMMU
dma-mapping: consolidate the NO_DMA definition in kernel/dma/Kconfig
sh: unexport register_trapped_io and match_trapped_io_handler
sh: don't include <asm/io_trapped.h> in <asm/io.h>
sh: move the ioremap implementation out of line
sh: move ioremap_fixed details out of <asm/io.h>
sh: remove __KERNEL__ ifdefs from non-UAPI headers
sh: sort the selects for SUPERH alphabetically
sh: remove -Werror from Makefiles
sh: Replace HTTP links with HTTPS ones
arch/sh/configs: remove obsolete CONFIG_SOC_CAMERA*
sh: stacktrace: Remove stacktrace_ops.stack()
sh: machvec: Modernize printing of kernel messages
sh: pci: Modernize printing of kernel messages
...
Jens Axboe [Sat, 15 Aug 2020 22:58:42 +0000 (15:58 -0700)]
io_uring: short circuit -EAGAIN for blocking read attempt
One case was missed in the short IO retry handling, and that's hitting
-EAGAIN on a blocking attempt read (eg from io-wq context). This is a
problem on sockets that are marked as non-blocking when created, they
don't carry any REQ_F_NOWAIT information to help us terminate them
instead of perpetually retrying.
Fixes:
227c0c9673d8 ("io_uring: internally retry short reads")
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Jens Axboe [Sat, 15 Aug 2020 18:44:50 +0000 (11:44 -0700)]
io_uring: sanitize double poll handling
There's a bit of confusion on the matching pairs of poll vs double poll,
depending on if the request is a pure poll (IORING_OP_POLL_ADD) or
poll driven retry.
Add io_poll_get_double() that returns the double poll waitqueue, if any,
and io_poll_get_single() that returns the original poll waitqueue. With
that, remove the argument to io_poll_remove_double().
Finally ensure that wait->private is cleared once the double poll handler
has run, so that remove knows it's already been seen.
Cc: stable@vger.kernel.org # v5.8
Reported-by: syzbot+7f617d4a9369028b8a2c@syzkaller.appspotmail.com
Fixes:
18bceab101ad ("io_uring: allow POLL_ADD with double poll_wait() users")
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Linus Torvalds [Sat, 15 Aug 2020 18:17:15 +0000 (11:17 -0700)]
Merge tag 'perf-tools-2020-08-14' of git://git./linux/kernel/git/acme/linux
Pull more perf tools updates from Arnaldo Carvalho de Melo:
"Fixes:
- Fixes for 'perf bench numa'.
- Always memset source before memcpy in 'perf bench mem'.
- Quote CC and CXX for their arguments to fix build in environments
using those variables to pass more than just the compiler names.
- Fix module symbol processing, addressing regression detected via
"perf test".
- Allow multiple probes in record+script_probe_vfs_getname.sh 'perf
test' entry.
Improvements:
- Add script to autogenerate socket family name id->string table from
copy of kernel header, used so far in 'perf trace'.
- 'perf ftrace' improvements to provide similar options for this
utility so that one can go from 'perf record', 'perf trace', etc to
'perf ftrace' just by changing the name of the subcommand.
- Prefer new "sched:sched_waking" trace event when it exists in 'perf
sched' post processing.
- Update POWER9 metrics to utilize other metrics.
- Fall back to querying debuginfod if debuginfo not found locally.
Miscellaneous:
- Sync various kvm headers with kernel sources"
* tag 'perf-tools-2020-08-14' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: (40 commits)
perf ftrace: Make option description initials all capital letters
perf build-ids: Fall back to debuginfod query if debuginfo not found
perf bench numa: Remove dead code in parse_nodes_opt()
perf stat: Update POWER9 metrics to utilize other metrics
perf ftrace: Add change log
perf: ftrace: Add set_tracing_options() to set all trace options
perf ftrace: Add option --tid to filter by thread id
perf ftrace: Add option -D/--delay to delay tracing
perf: ftrace: Allow set graph depth by '--graph-opts'
perf ftrace: Add support for trace option tracing_thresh
perf ftrace: Add option 'verbose' to show more info for graph tracer
perf ftrace: Add support for tracing option 'irq-info'
perf ftrace: Add support for trace option funcgraph-irqs
perf ftrace: Add support for trace option sleep-time
perf ftrace: Add support for tracing option 'func_stack_trace'
perf tools: Add general function to parse sublevel options
perf ftrace: Add option '--inherit' to trace children processes
perf ftrace: Show trace column header
perf ftrace: Add option '-m/--buffer-size' to set per-cpu buffer size
perf ftrace: Factor out function write_tracing_file_int()
...
Linus Torvalds [Sat, 15 Aug 2020 17:38:03 +0000 (10:38 -0700)]
Merge tag 'x86-urgent-2020-08-15' of git://git./linux/kernel/git/tip/tip
Pull x86 fixes from Ingo Molnar:
"Misc fixes and small updates all around the place:
- Fix mitigation state sysfs output
- Fix an FPU xstate/sxave code assumption bug triggered by
Architectural LBR support
- Fix Lightning Mountain SoC TSC frequency enumeration bug
- Fix kexec debug output
- Fix kexec memory range assumption bug
- Fix a boundary condition in the crash kernel code
- Optimize porgatory.ro generation a bit
- Enable ACRN guests to use X2APIC mode
- Reduce a __text_poke() IRQs-off critical section for the benefit of
PREEMPT_RT"
* tag 'x86-urgent-2020-08-15' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/alternatives: Acquire pte lock with interrupts enabled
x86/bugs/multihit: Fix mitigation reporting when VMX is not in use
x86/fpu/xstate: Fix an xstate size check warning with architectural LBRs
x86/purgatory: Don't generate debug info for purgatory.ro
x86/tsr: Fix tsc frequency enumeration bug on Lightning Mountain SoC
kexec_file: Correctly output debugging information for the PT_LOAD ELF header
kexec: Improve & fix crash_exclude_mem_range() to handle overlapping ranges
x86/crash: Correct the address boundary of function parameters
x86/acrn: Remove redundant chars from ACRN signature
x86/acrn: Allow ACRN guest to use X2APIC mode