lavapipe: EXT_image_sliced_view_of_3d

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21514>

vulkan/runtime: store parameters of VK_EXT_sliced_view_of_3d

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21514>

radv/sqtt: Use code buffer from radv_shader directly instead of copying.

The reference-counted radv_shader always outlives the pipeline, so we can
use this buffer directly when dumping code objects to the trace.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21513>

radv: Keep shader code ptr in a separately allocated buffer.

RGP traces need a dump of shader code in order to display ISA and
instruction trace. Previously, this was read back from GPU at trace
creation time. However, for future changes that implements upload shader
to invisible VRAM, the upload destination will be a temporary staging
buffer and will be only accessible during shader creation.

To allow dumping in such cases, copy the shader code to a separate buffer
at creation time, if thread tracing is enabled.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21513>

zink: allow direct memory mapping for any COHERENT+CACHED buffer

some drivers may provide this in heaps that get used by non-staging resources,
so avoid extra copies in that case

unlike the previous attempt at this optimization, this utilizes the screen-based
context for thread-safe transfers, which should avoid races/crashes

fix #8171

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21452>

zink: add locking for zink_screen::copy_context and defer creation

the copy context isn't always used, so this allows its creation to
be deferred and potentially save a bunch of memory

also add locking for multi-context thread safety

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21452>

zink: avoid adding ubo/ssbo bindings multiple times for different bitsizes

these are valid variables, but the descriptor binding needs to be unique

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21522>

zink: simplify/rework image typing in ntv

the array approach was broken if a shader contained both bindless
and non-bindless resources, whereas a hash table is simpler and can
handle both images and samplers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21522>

zink: delete unused emit_image param in ntv

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21522>

zink: fix bindless texture barrier generation

whenever I redid barriers I forgot to handle bindless textures,
which meant they weren't getting barriers added

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21522>

zink: rework descriptor unbind params to use is_compute directly

much simpler

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21522>

zink: fix shader read access removal for barrier generation

barrier access is based on total binds per gfx/compute, not per stage

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21522>

zink: delete dead uniform variables

this just obfuscate nir, so delete them now

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21522>

agx: Lower sampler LOD bias

G13 does not support sampler descriptor LOD biasing, so this needs to be lowered
to shader code for APIs that require this functionality. Add an option to do
this lowering while doing our other backend texture lowerings. This generates
lod_bias_agx texture instructions which the driver is expected to lower
according to its binding model.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21276>

asahi: Lower lod_bias_agx to uniform registers

Track the LOD bias of samplers and upload them at draw time to uniform
registers. This could be optimized in the future.

Vulkan will probably want to pull from a descriptor set instead.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21276>

nir: Add nir_texop_lod_bias_agx

Add a new texture opcode that returns the LOD bias of the sampler. This will be
used on AGX to lower sampler LOD bias to txb and friends. This needs to be a
texture op (and not a new intrinsic) to handle both bindless and bindful
samplers across GL and Vulkan in a uniform way.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21276>

ac/llvm,radeonsi: lower fbfetch in abi

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21436>

radeonsi: add num_component param to load_internal_binding

Prepare for different component number, ie. 8 when image desc.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21436>

ac/llvm,radeonsi: lower nir_load_barycentric_at_sample in abi

RADV already did this in radv_lower_fs_intrinsics().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21436>

nir: lower to fragment_mask_fetch/load_amd with EQAA correctly

Fixes: 194add2c232 ("nir: lower image add lower_to_fragment_mask_load_amd option")
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21436>

nir/lower_blend: Consume dual stores

Now that we're working on lowered I/O, passing in the dual source blend colour
via a sideband doesn't make any sense. The primary source blend colours are
implicitly passed in as the sources of store_output intrinsics; likewise, we
should get dual source blend colours from their respective stores. And since
dual colours are only needed by blending, we can delete the stores as we go.
That means nir_lower_blend now provides an all-in-one software lowering of dual
source blending with no driver support needed! It even works for 8 dual-src
render targets, but I don't have a use case for that.

The only tricky bit here is making sure we are robust against different orders
of store_output within the exit block. In particular, if we naively lower

   x = ...
   primary color = x
   y = ...
   dual color = y

we end up emitting uses of y before it has been defined, something like

   x = ...
   primary color = blend(x, y)
   y = ...

Instead, we remove dual stores and sink blend stores to the bottom of the block,
so we end up with the correct

   x = ...
   y = ...
   primary color = blend(x, y)

lower_io_to_temporaries ensures that the stores will be in the same (exit)
block, so we don't need to sink further than that ourselves.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21426>

panfrost: Use proper locations in blend shaders

Rather than always blending to FRAG_RESULT_DATA0. This removes silly special
cases in the compiler.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21426>

intel/rt: Fix L3 bank performance bottlenecks due to SW stack stride alignment.

Power-of-two SW stack sizes are prone to causing collisions in the
hashing function used by the L3 to map memory addresses to banks,
which can cause stack accesses from most DSSes to bottleneck on a
single L3 bank.  Fix it by padding the SW stack stride by a single
cacheline if it was a power of two.  This has been reported by Felix
DeGrood to improve Quake2 RTX performance by ~30% on DG2-512 in
combination with other RT patches Lionel Landwerlin has been working
on.

Many thanks to Felix DeGrood for doing much of the legwork and
providing several iterations of Q2RTX performance counter dumps which
eventually prompted me to consider the hash collision theory and
motivated this patch, and for providing additional performance counter
dumps confirming that there is no longer an appreciable imbalance in
traffic across L3 banks after this change.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21461>

docs: Fix formatting for RMV tracing docs

Fixes: e1cbff22 ("docs: Add short documentation about RMV tracing variables")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21502>

meson: print c_cpp_args

Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21539>

radv/rt: Pre shift cull_mask

This removes the need for masking the instance mask.

Totals from 14 (14.43% of 97) affected shaders:
CodeSize: 378696 -> 378308 (-0.10%); split: -0.12%, +0.02%
Instrs: 70854 -> 70855 (+0.00%); split: -0.02%, +0.02%
Latency: 1651235 -> 1651215 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 336290 -> 336285 (-0.00%); split: -0.00%, +0.00%
Copies: 9915 -> 9923 (+0.08%); split: -0.03%, +0.11%
PreSGPRs: 890 -> 896 (+0.67%)

 PERCENTAGE DELTAS Shaders  CodeSize   Instrs   Latency  InvThroughput   Copies   PreSGPRs
 q2rtx-pipe        48        -0.02%    -0.02%    -0.00%      -0.00%      -0.03%      .
 q2rtx_1           49        -0.10%    +0.02%    +0.00%      +0.00%      +0.14%    +0.31%
 -------------------------------------------------------------------------------------------
 All affected      14        -0.10%    +0.00%    -0.00%      -0.00%      +0.08%    +0.67%
 -------------------------------------------------------------------------------------------
 Total             97        -0.06%    +0.00%    -0.00%      -0.00%      +0.06%    +0.16%

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21530>

pvr: remove duplicate define

The same define appears a few lines above.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21495>

pvr: stop restricting the compiler to the Sascha Willems triangle demo

Do this by removing the compatibility table and only using hard coded shaders
when present. The hard coded shaders, along with the hard coding framework
itself, can be dropped once the compiler is capable of compiling the hard coded
shaders. In the meantime we don't want to risk regressing things that we know
work because we temporarily can't test them.

This restriction is being dropped now as the new compiler framework has been
merged and we want to make use of it so it can be developed further.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21495>

d3d12: Track up to 16 active context resource states locally in d3d12_bo

After 16 entries, we fall back to the previous logic that used a hash
map to link the resource's state per context.

Preventing hash map churn by cheaply tracking up to 16 context's worth
of states per resource significantly reduces CPU cost in
find_or_create_state_entry

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21528>

d3d12: Assign up to 16 simultaneously active contexts unique IDs

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21528>

d3d12: Move d3d12_context_state_table_entry to d3d12_resource_state.h

Also renamed desired_resource_state to d3d12_desired_resource_state,
since it's also in the header now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21528>

tu/kgsl: Propagate tu_physical_device_init() errors

Should fix dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail.basic

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>

tu+meson: Re-work KMD selection

Now that turnip can support multiple kernel-mode drivers in a single
build, re-work the meson option to have a single list of KMDs, rather
than special options to enable kgsl for turnip or virtio for gallium.

It is temporarily a bit awkward as gallium does not yet support kgsl
and turnip does not yet support virtio.  But both of those are planned
or in-progress, so long term a single list is the most sensible option.

TODO freedreno/drm support to build with only virtio support.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>

turnip: Refactor device loading

1) Allow the two different entrypoints for drm vs non-drm (kgsl) to
   coexist.
2) Split the generic drm related device initialization from the msm
   specifics.  This will simplify adding support for additional drm
   based kernel mode drivers (ie. virtgpu)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>

turnip: Handle kgsl vs drm specifics at runtime

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>

turnip: Move QueueWaitIdle entrypoint to kgsl

Handle in the same way as other kgsl specific entrypoints.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>

turnip: Allow knl backend specific entrypoints

Because kgsl sync primitives are not drm_syncobj, the kgsl kernel
support needs the ability to patch in it's own entrypoints related
to fences, etc.  The current entrypoint table magic using weak syms
won't work if we are building both kgsl and drm support into one
binary, so switch to runtime patching in the kgsl specific entry-
points.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>

turnip: Split out vfuncs for kernel interface

To allow support for multiple KMD's to coexist, split out vfuncs.  This
doesn't quite *yet* let us have kgsl and msm coexist, because of the
different vk entrypoints needed by the kgsl backend.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>

turnip: drm code-motion

Move a few functions around in prep for next commit.  Only code-motion.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>

turnip: Move things to prep for multi-kernel support

The end goal is a single build that supports kgsl (non-drm) as well
as msm and virtgpu (both drm).  First lets move around some files to
accomodate that.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>

vk/runtime: Allow enumerate and try_create_for_drm to coexist

For drivers that can support both drm and non-drm kernel mode drivers it
is useful to be able to provide both entrypoints.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>

ci/freedreno: add flaking KHR-GL45.buffer_storage.map_persistent_dispatch

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21531>

docs: update link to intel optimization reference manual

Seems this document has moved since last we updated this link. But
instead of chasing the exact CDN link, let's link to the document on
Intel's website. There's both a download-link there, as well as the
ability to read the document online.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21448>

ci: correct typo in name of linkcheck job

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21448>

intel: use c_see2_arg instead of explicit -msse2

This allows us to also inherit `-mfpmath=sse` added in previous commit.

Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21371>

intel: enable -mfpmath=sse on x86

It's not enabled by default until `-msse2` and -ffast-math is passed.
We pass only the `-msse2`. Let's align it with main `meson.build`.

See: https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html (-mfpmath).

Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21371>

r600/sfn: Fix minimum required registers

Don't count the local registers, just the arrays, because local
registers might be renamed during register allocation.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8100

Fixes: 9fd9f3cd10cf58549f850aeca9103d8cca5a5f81
   r600/sfn: Set minimum required registers based on array allocation

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21523>

radv/rt: Merge cull_mask and flags

Since cull_mask is only one byte, we can trivially store it in the same
register as the flags. This leaves us with a 2% performance gain in
Quake II RTX:

Totals from 7 (14.00% of 50) affected shaders:
VGPRs: 720 -> 688 (-4.44%)
CodeSize: 213052 -> 212980 (-0.03%); split: -0.05%, +0.02%
MaxWaves: 67 -> 70 (+4.48%)
Instrs: 39429 -> 39394 (-0.09%); split: -0.15%, +0.06%
Latency: 1096258 -> 1096943 (+0.06%); split: -0.05%, +0.11%
InvThroughput: 230661 -> 222963 (-3.34%); split: -3.42%, +0.08%
VClause: 1208 -> 1206 (-0.17%); split: -0.25%, +0.08%
Copies: 5321 -> 5269 (-0.98%); split: -1.22%, +0.24%
Branches: 1903 -> 1902 (-0.05%)
PreVGPRs: 650 -> 645 (-0.77%)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21470>

nir: Add cull_mask_and_flags_amd intrinsic

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21470>

anv: remove assert typed write support when using NULL surface

A number of apps hit this assert in debug mode.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21382>

ci: uprev virglrenderer

Update virglrenderer to bring in venus protocol fixes described in
https://gitlab.freedesktop.org/olv/venus-protocol/-/issues/4.

Signed-off-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21496>

zink: fix build with -Dvulkan-beta=true

Fix a build error with -Dvulkan-beta=true:

  ../src/gallium/drivers/zink/zink_screen.c: In function ‘zink_internal_create_screen’:
  ../src/gallium/drivers/zink/zink_screen.c:2764:20: error: ‘struct zink_device_info’ has no member named ‘have_KHR_portability_subset’
   2764 |    if (screen->info.have_KHR_portability_subset) {
        |                    ^
  ../src/gallium/drivers/zink/zink_screen.c:2765:60: error: ‘struct zink_device_info’ has no member named ‘portability_subset_feats’
   2765 |       screen->have_triangle_fans = (VK_TRUE == screen->info.portability_subset_feats.triangleFans);
        |                                                            ^

Fixes: e02cdb397e62 ("zink: prefer vulkan_core.h over vulkan.h")
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21491>

zink: fix slab allocator sizing

now that the mem type is passed directly to pb, there have to be enough
slabs to allocate all the mem types (not heaps), so create memoryTypeCount
slabs to allow this

fixes #8369

Fixes: f6d3a5755f6 ("zink: zink_heap isn't 1-to-1 with memoryTypeIndex"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21526>

vbo/save: fix possible crash related to fixup_vertex()

Indeed, buffer_in_ram could be reallocated by fixup_vertex()
which triggers this issue.

For instance, with "piglit/gl-1.0-dlist-materials -auto -fbo":
==28392==ERROR: AddressSanitizer: heap-use-after-free on address 0x607000010024 at pc 0x7f3f416fcf18 bp 0x7f3f33d12800 sp 0x7f3f33d127f8
WRITE of size 4 at 0x607000010024 thread T6
    #0 0x7f3f416fcf17 in _save_Materialfv ../src/mesa/vbo/vbo_save_api.c:1405
    #1 0x7f3f418199de in _mesa_unmarshal_Materialfv src/mapi/glapi/gen/marshal_generated0.c:5006
    #2 0x7f3f413c6863 in glthread_unmarshal_batch ../src/mesa/main/glthread.c:65
    #3 0x7f3f4124d368 in util_queue_thread_func ../src/util/u_queue.c:309
    #4 0x7f3f41391eba in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #5 0x7f3f4c619c6b in start_thread glibc-2.35/nptl/pthread_create.c:442
    #6 0x7f3f4c69e1fb in __clone3 (/lib64/libc.so.6+0x10c1fb)

0x607000010024 is located 20 bytes inside of 80-byte region [0x607000010010,0x607000010060)
freed by thread T6 here:
    #0 0x7f3f4f093b48 in __interceptor_realloc (/usr/lib64/libasan.so.6+0xb1b48)
    #1 0x7f3f416e5b0c in grow_vertex_storage ../src/mesa/vbo/vbo_save_api.c:417
    #2 0x7f3f416e69bc in fixup_vertex ../src/mesa/vbo/vbo_save_api.c:1266
    #3 0x7f3f416fb13e in _save_Materialfv ../src/mesa/vbo/vbo_save_api.c:1405
    #4 0x7f3f418199de in _mesa_unmarshal_Materialfv src/mapi/glapi/gen/marshal_generated0.c:5006
    #5 0x7f3f413c6863 in glthread_unmarshal_batch ../src/mesa/main/glthread.c:65
    #6 0x7f3f4124d368 in util_queue_thread_func ../src/util/u_queue.c:309
    #7 0x7f3f41391eba in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #8 0x7f3f4c619c6b in start_thread glibc-2.35/nptl/pthread_create.c:442

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21419>

anv: stop tracking color blend state in the pipeline

Now that all color blend bits are dynamic, emit_cb_state() is doing
almost nothing and half of that is wrong.

In the case that color write enable is dynamic, at the time the pipeline
state is emitted, it sees all the color attachments as having write
disabled and stores the WriteDisabled bit for each channel.
When all dynamic state is flushed, we have the right values already but
the values recorded into the command buffer get ORed with the ones
stored in the pipeline, and so WriteDisabled tag along when they
shouldn't.

Since all disabled color attachments are handled already when dynamic
state is flushed, there's no point in doing so at pipeline creation
time too. And since the only other thing done by emit_cb_state() is
writing three hardcoded values, they might as well be taken care of in
the same place as everything else.

Fixes CTS from the future:
dEQP-VK.pipeline.*.extended_dynamic_state.*.color_blend_equation_*dynamic*
dEQP-VK.pipeline.*.extended_dynamic_state.*.color_blend_all_*

Fixes: fc3fd7c69e8 (anv: dynamic color write mask)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21509>

anv: fix testing for dynamic color blend bits

Fixes: fc3fd7c69e8 (anv: dynamic color write mask)
Fixes: 9dc6bed9a10 (anv: dynamic state for logic op enable)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21509>

vulkan: track the right value on CmdSetColorWriteMasks

Fixes: 092be5a3290 ("vulkan: Add more dynamic color blend states")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21509>

nir,amd: add and use nir_intrinsic_load_esgs_vertex_stride_amd

This will emulate VGT_ESGS_RING_ITEMSIZE, which does the multiplication
for us. It's beneficial to stop setting VGT_ESGS_RING_ITEMSIZE to reduce
context rolls, and also the register will be removed in the future.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd/gpu_info: add a workaround for SI_FORCE_FAMILY=gfx1100

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd: implement conformant TRUNC_COORD behavior for gfx11

For testing, the conformant behavior can be enabled by setting
conformant_trunc_coord to true manually and running this to enable
the conformant behavior in hw:
    umr -w *.*.regTA_CNTL2 0x40000

The layer index rounding and TRUNC_COORD resetting workarounds can disabled
in the shader compiler.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi/gfx11: change the default of COMPUTE_DISPATCH_INTERLEAVE to 256

This is an internal recommendation.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: don't set PACKET_TO_ONE_PA for line stippling

A hw guy told me this.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: reorganize si_init_depth_surface for better readability

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: reorganize si_initialize_color_surface for better readability

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: reorganize emit_db_render_state and simplify VRS code

for better readability

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd/registers: only define SPI and COMPUTE registers in the 0xB000 range

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: don't clamp z_samples to fix Unreal Tournament 99

Fixes: a29218b5 - radeonsi/gfx11: always set MSAA_NUM_SAMPLES=0 for DCC_DECOMPRESS
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8261

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd: query the per-SIMD VGPR counts from the kernel, don't hardcode them

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: rename esgs_itemsize -> esgs_vertex_stride

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: correct and clean up obsolete vs_state_bits comments

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: always add 1 to lshs_vertex_stride now that LS_OUT_PATCH_SIZE is gone

LS_OUT_PATCH_SIZE limited the maximum value.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: remove unused VS_STATE_LS_OUT_PATCH_SIZE

This became unused when we switched to nir_lower_hs_inputs_to_mem.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: remove a gfx11 check in si_shader_gs (legacy GS)

Gfx11 doesn't support legacy GS.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: reformat emit_cb_render_state, create_blend_state, create_rs_state

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: remove returns from si_emit_global_shader_pointers

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd: replace SI_BIG_ENDIAN with UTIL_ARCH_BIG_ENDIAN

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd/registers: unify VRS combiner definition names between gfx103 and gfx11

use gfx11 names

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd,radeonsi: remove unused LLVM functions

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: disable Smart Access Memory because CPU access has large overhead

It will be remove completely in the next commit.

Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8176

Cc: mesa-stable
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: replace si_screen::has_out_of_order_rast with the radeon_info field

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi/gfx11: ignore alpha_is_on_msb because the hw ignores it

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: set PA_SU_VTX_CNTL consecutively with PA_CL_GB_VERT_CLIP_ADJ

because they are all next to each other.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: use SPI_SHADER_USER_DATA_HS_0 definition instead of LS_0

The value is the same, but LS_0 is for gfx9 only, and HS_0 is for everything
except gfx9.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: remove no-op setting of THDS_PER_SUBGRP

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: change si_shader::ctx_reg to a nameless union for better readability

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: move a few DB_SHADER_CONTROL states into si_shader_ps

They can be set si_shader_ps.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi/gfx11: set CB_COLORi_INFO.MAX_COMP_FRAG on GFX1103_R2

Fixes: caa09f66ae4 - amd: add chip identification for gfx1100-1103

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi/gfx11: don't set non-existent VGT_STRMOUT_BUFFER_CONFIG

Fixes: 9fecac091f3 - radeonsi/gfx11: scattered register deltas

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi/gfx11: fix the CU_EN clear mask for RSRC4_GS

Fixes: 9fecac091f3 - radeonsi/gfx11: scattered register deltas

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd: bump AMD_MAX_SE and change the CU mask type to 16 bits

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd: add missing gfx11 register definitions

Fixes: caa09f66ae4 - amd: add chip identification for gfx1100-1103

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

amd: fix LOD_BIAS on gfx6-9 and adjust the lod bias CAP

Fixes: e673bb4ae44 - amd,util: fix how lod bias is converted to fixed-point

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

radeonsi: fix COMPAT_MODE on gfx8-9

It was set in the wrong dword.

Fixes: e673bb4ae44 ("amd,util: fix how lod bias is converted to fixed-point")

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

Revert "radeonsi/ci: Update stoney test expectations"

This reverts commit 53cc5092885d5d8dd01a66302e2f762f5b00e045.

This MR fixes it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>

spirv: Always emit deref_buffer_array_length intrinsics

All the drivers have been converted to setting this option now except
imagination and they don't support SSBOs yet.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3993
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>

v3dv: Set spirv_options::use_deref_buffer_array_length

It'll get lowered to get_ssbo_size by nir_lower_explicit_io() so the
driver should never notice this change.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>

lavapipe: Set spirv_options::use_deref_buffer_array_length

It'll get lowered to get_ssbo_size by nir_lower_explicit_io() so the
driver should never notice this change.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>

turnip: Set spirv_options::use_deref_buffer_array_length

It'll get lowered to get_ssbo_size by nir_lower_explicit_io() so the
driver should never notice this change.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>

panvk: Drop our manual SSBO size handling

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>

hasvk: Drop our manual SSBO size handling

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>