Kai Nacke [Wed, 8 Jan 2020 19:26:12 +0000 (14:26 -0500)]
[SystemZ] Add implementation for the intrinsic llvm.read_register
This change implements the llvm intrinsic llvm.read_register for
the SystemZ platform which returns the value of the specified
register
(http://llvm.org/docs/LangRef.html#llvm-read-register-and-llvm-write-register-intrinsics).
This implementation returns the value of the stack register, and
can be extended to return the value of other registers. The
implementation for this intrinsic exists on various other platforms
including Power, x86, ARM, etc. but missing on SystemZ.
Reviewers: uweigand
Differential Revision: https://reviews.llvm.org/D73378
Hans Wennborg [Mon, 10 Feb 2020 13:07:41 +0000 (14:07 +0100)]
Fix an unused variable warning
Georgii Rymar [Wed, 5 Feb 2020 13:53:27 +0000 (16:53 +0300)]
[llvm-readobj] - Change the error to warning when a section name is unknown.
We reported the error in this case.
But it was asked (https://reviews.llvm.org/D73193#inline-665595) to convert it
to a warning. This patch does it.
Differential revision: https://reviews.llvm.org/D74047
Mikael Holmen [Mon, 10 Feb 2020 12:32:44 +0000 (13:32 +0100)]
Fix compiler warning when compiling without asserts [NFC]
Louis Dionne [Mon, 10 Feb 2020 12:47:27 +0000 (13:47 +0100)]
[libc++][span] Add failing tests for span::first and span::last
Both methods have compile time constraints that we should test against.
Patch by Michael Schellenberger Costa
Differential Revision: https://reviews.llvm.org/D71999
Kadir Cetinkaya [Mon, 10 Feb 2020 12:38:58 +0000 (13:38 +0100)]
[OpenMP] Fix unused variable
Nico Weber [Mon, 10 Feb 2020 12:42:27 +0000 (07:42 -0500)]
[gn build] make 'clang' target depend on libcxx/include on mac
On macOS, libc++ headers are distributed with the compiler, not
the sysroot. Without this, compiling a file that includes something
like <string> won't compile with gn-built clang without manual tweaks.
I used to do the manual tweaks, but now that other people are starting
to use this on mac, let's make it Just Work.
(This is marginally nicer than the cmake build now in that you can
just build 'clang' and it'll do the right thing.)
Differential Revision: https://reviews.llvm.org/D74247
Louis Dionne [Mon, 10 Feb 2020 12:38:04 +0000 (13:38 +0100)]
[libc++] Protect <span> against min/max macro
Patch by Corentin Jabot
Differential Revision: https://reviews.llvm.org/D73855
Florian Hahn [Mon, 10 Feb 2020 12:37:22 +0000 (12:37 +0000)]
[DSE,MSSA] Move more passing test cases from todo to simple.ll.
Kerry McLaughlin [Mon, 10 Feb 2020 11:33:06 +0000 (11:33 +0000)]
[AArch64][SVE] SVE2 intrinsics for complex integer arithmetic
Summary:
Adds the following SVE2 intrinsics:
- cadd & sqcadd
- cmla & sqrdcmlah
- saddlbt, ssublbt & ssubltb
Reviewers: sdesmalen, dancgr, efriedma, cameron.mcinally, c-rhodes, rengolin
Reviewed By: sdesmalen
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73636
Simon Pilgrim [Mon, 10 Feb 2020 11:58:05 +0000 (11:58 +0000)]
Revert rGe82e17d4d4cac8b2df00094e80d5e1cb22795664 - [X86] Add lowerShuffleAsBitRotate (PR44379)
As noted on PR44379, we didn't attempt to lower vector shuffles using bit rotations on XOP/AVX512F targets.
This patch lowers to uniform ISD:ROTL nodes - ROTR isn't supported by XOP and they are interchangeable for constant values anyway.
There might be cases where targets without ISD:ROTL support would benefit from this (expanding to SRL+SHL+OR), which I'll investigate in a future patch.
Also, non-AVX512BW targets fail to concatenate 256-bit rotations back to 512-bits (split during shuffle lowering as they don't have v32i16/v64i8 types).
---
Internal shuffle tests indicate theres a bug somewhere that I haven't been able to track down yet.
Raphael Isemann [Mon, 10 Feb 2020 11:45:19 +0000 (12:45 +0100)]
[lldb][NFC] Don't hide a bool in LibCxxOptional's OptionalFrontend::m_size
m_size can only be 1 or 0 and indicates if the optional has a value. Calling
it 'm_size', giving it a size_t data type and then also comparing indices against
'size' is very confusing. Let's just make this a bool.
Florian Hahn [Mon, 10 Feb 2020 10:44:37 +0000 (10:44 +0000)]
[DSE] Add first version of MemorySSA-backed DSE (Bottom up walk).
This patch adds a first version of a MemorySSA based DSE. It is missing
a lot of features, which will get added as follow-ups, to help to keep
the review manageable.
The patch uses the following general approach: given a MemoryDef, walk
upwards to find clobbering MemoryDefs that may be killed by the
starting def. Then check that there are no uses that may read the
location of the original MemoryDef in between both MemoryDefs. A bit
more concretely:
For all MemoryDefs StartDef:
1. Get the next dominating clobbering MemoryDef (DomAccess) by walking upwards.
2. Check that there no reads between DomAccess and the StartDef by checking
all uses starting at DomAccess and walking until we see StartDef.
3. For each found DomDef, check that:
1. There are no barrier instructions between DomDef and StartDef (like
throws or stores with ordering constraints).
2. StartDef is executed whenever DomDef is executed.
3. StartDef completely overwrites DomDef.
4. Erase DomDef from the function and MemorySSA.
The patch uses a very simple approach to guarantee that no throwing
instructions are between 2 stores: We only allow accesses to stack
objects, access that are in the same basic block if the block does not
contain any throwing instructions or accesses in functions that do
not contain any throwing instructions. This will get lifted later.
Besides adding support for the missing cases, there is plenty of additional
potential for improvements as follow-up work, e.g. the way we visit stores
(could be just a traversal of the MemorySSA, rather than collecting them
up-front), using the alias information discovered during walking to optimize
the MemorySSA.
This is loosely based on D40480 by Dave Green.
Reviewers: dmgreen, rnk, efriedma, bryant, asbirlea, Tyker
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D72700
Raphael Isemann [Mon, 10 Feb 2020 11:39:42 +0000 (12:39 +0100)]
[lldb][NFC] Don't call call formatv for no reason in LibCxxOptional
Raphael Isemann [Mon, 10 Feb 2020 11:37:44 +0000 (12:37 +0100)]
[lldb][NFC] Fix code style of LibcxxVariantIndexValidity
Enum cases aren't all uppercase.
Raphael Isemann [Mon, 10 Feb 2020 11:23:01 +0000 (12:23 +0100)]
[lldb][NFC] Don't construct a ConstString twice in LibCxxVariant
Kerry McLaughlin [Mon, 10 Feb 2020 11:08:00 +0000 (11:08 +0000)]
[AArch64][SVE] SVE2 intrinsics for character match & histogram generation
Summary:
Implements the following intrinsics:
- @llvm.aarch64.sve.histcnt
- @llvm.aarch64.sve.histseg
- @llvm.aarch64.sve.match
- @llvm.aarch64.sve.nmatch
Reviewers: c-rhodes, sdesmalen, dancgr, efriedma, rengolin
Reviewed By: c-rhodes
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74117
Kirill Bobyrev [Mon, 10 Feb 2020 10:53:17 +0000 (11:53 +0100)]
[clangd] Support renaming designated initializers
Summary:
Clangd does not find references of designated iniitializers yet and, as a
result, is unable to rename such references. This patch addresses this issue.
Resolves: https://github.com/clangd/clangd/issues/247
Reviewers: sammccall
Reviewed By: sammccall
Subscribers: merge_guards_bot, ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D72867
Kerry McLaughlin [Mon, 10 Feb 2020 10:30:12 +0000 (10:30 +0000)]
[AArch64][SVE] Add SVE2 intrinsics for widening DSP operations
Summary:
Implements the following intrinsics:
- @llvm.aarch64.sve.[s|u]abalb
- @llvm.aarch64.sve.[s|u]abalt
- @llvm.aarch64.sve.[s|u]addlb
- @llvm.aarch64.sve.[s|u]addlt
- @llvm.aarch64.sve.[s|u]sublb
- @llvm.aarch64.sve.[s|u]sublt
- @llvm.aarch64.sve.[s|u]abdlb
- @llvm.aarch64.sve.[s|u]abdlt
- @llvm.aarch64.sve.sqdmullb
- @llvm.aarch64.sve.sqdmullt
- @llvm.aarch64.sve.[s|u]mullb
- @llvm.aarch64.sve.[s|u]mullt
Reviewers: sdesmalen, dancgr, efriedma, cameron.mcinally, rengolin
Reviewed By: sdesmalen
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73719
Florian Hahn [Fri, 6 Dec 2019 14:55:07 +0000 (14:55 +0000)]
[DSE] Add tests for MemorySSA based DSE.
This copies the DSE tests into a MSSA subdirectory to test the MemorySSA
backed DSE implementation, without disturbing the original tests.
Differential Revision: https://reviews.llvm.org/D72145
Frank Laub [Mon, 10 Feb 2020 09:17:28 +0000 (01:17 -0800)]
[MLIR][Affine] NFC: Move AffineValueMap and MutableAffineMap
Summary:
The `AffineValueMap` is moved into `Dialect/AffineOps` to prevent a cyclic
dependency between `Analysis` and `Dialect/AffineOps`.
Reviewers: bondhugula, herhut, nicolasvasilache, rriddle, mehdi_amini
Reviewed By: rriddle, mehdi_amini
Subscribers: mgorny, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, Joonsoo, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74277
Richard Smith [Mon, 10 Feb 2020 10:17:43 +0000 (02:17 -0800)]
Fix handling of destructor names that name typedefs.
1) Fix a regression in llvmorg-11-init-2485-g0e3a4877840 that would
reject some cases where a class name is shadowed by a typedef-name
causing a destructor declaration to be rejected. Prefer a tag type over
a typedef in destructor name lookup.
2) Convert the "type in destructor declaration is a typedef" error to an
error-by-default ExtWarn to allow codebases to turn it off. GCC and MSVC
do not enforce this rule.
Djordje Todorovic [Mon, 10 Feb 2020 09:43:41 +0000 (10:43 +0100)]
[CSInfo] Fix the assertions regarding updating the CSInfo
The call site info was not updated correctly when deleting
corresponding call instructions.
Differential Revision: https://reviews.llvm.org/D73700
Simon Moll [Mon, 10 Feb 2020 09:34:58 +0000 (10:34 +0100)]
[Doc] Proposal for vector predication
Summary:
Proposal and roadmap towards vector predication in LLVM.
This patch documents that
a) It is recognized that current LLVM is ill-equipped for vector predication.
b) The community is working on a solution.
c) A concrete prototype exists in the VP extension (D57504).
Reviewers: rkruppe, rengolin, cameron.mcinally, SjoerdMeijer, andrew.w.kaylor, craig.topper, sdesmalen, k-ishizaka, lattner, fhahn
Reviewed By: andrew.w.kaylor
Subscribers: rogfer01, merge_guards_bot, simoncook, s.egerton, llvm-commits, efocht
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73889
Jan Kratochvil [Mon, 10 Feb 2020 09:29:26 +0000 (10:29 +0100)]
[lldb] Fix+re-enable Assert StackFrame Recognizer on Linux
D73303 was failing on Fedora Linux and so it was disabled by Skip the
AssertFrameRecognizer test for Linux.
I find no easy way how to find out if it gets recognized as
`__assert_fail` or `__GI___assert_fail` as during `Process` ctor
libc.so.6 is not yet loaded by the debuggee.
DWARF symbol `__GI___assert_fail` overrides the ELF symbol `__assert_fail`.
While external debug info (=DWARF) gets disabled for testsuite (D55859)
that sure does not apply for real world usage.
Differential Revision: https://reviews.llvm.org/D74252
Martin Storsjö [Mon, 10 Feb 2020 09:17:48 +0000 (11:17 +0200)]
[LLDB] Fix GCC warnings about extra semicolons. NFC.
Kai Nacke [Wed, 5 Feb 2020 20:08:19 +0000 (15:08 -0500)]
[SytemZ] Disable vector ABI when using option -march=arch[8|9|10]
When specifying -march=arch[8|9|10], those CPU types do NOT support
the vector extension. In this case the vector ABI must be disabled.
The generated data layout should NOT contain 64-v128.
Reviewers: uweigand
Differential Revision: https://reviews.llvm.org/D74146
Djordje Todorovic [Mon, 10 Feb 2020 08:49:14 +0000 (09:49 +0100)]
[CSInfo] Use isCandidateForCallSiteEntry() when updating the CSInfo
Use the isCandidateForCallSiteEntry().
This should mostly be an NFC, but there are some parts ensuring
the moveCallSiteInfo() and copyCallSiteInfo() operate with call site
entry candidates (both Src and Dest should be the call site entry
candidates).
Differential Revision: https://reviews.llvm.org/D74122
Jan Kratochvil [Mon, 10 Feb 2020 08:50:37 +0000 (09:50 +0100)]
[lldb] [doc] Change sample commands prefix from > to $
Remove all beginning > from the sample commands as my accidental
copy-paste (multiple times...) will discard ./bin/llvm-lit which is
difficult to rebuild (I have to rm -rf and cmake it all again).
Differential Revision: https://reviews.llvm.org/D74296
Raphael Isemann [Thu, 6 Feb 2020 14:11:06 +0000 (15:11 +0100)]
[lldb] Refactored TestCallOverriddenMethod.py to general virtual function test
This actually tests all the different situations in which we can call virtual
functions. This removes also all skipIfs as the first skipIf for Linux is
apparently fixed and the second skipIf was just failing due to the constructor
call (which should be its own test and not be tested here).
Sebastian Neubauer [Wed, 29 Jan 2020 09:04:36 +0000 (10:04 +0100)]
[AMDGPU] Add a16 feature to gfx10
Based on D72931
This adds a new feature called A16 which is enabled for gfx10.
gfx9 keeps the R128A16 feature so it can share all the instruction encodings
with gfx7/8.
Differential Revision: https://reviews.llvm.org/D73956
Johannes Doerfert [Mon, 10 Feb 2020 07:31:20 +0000 (01:31 -0600)]
[Attributor][FIX] Make check lines explicit
There is a bug in `update_test_checks.py` that combines check lines it
should not. For now we unbreak the bots by making all possibilities
explicit.
Johannes Doerfert [Sun, 26 Jan 2020 02:21:41 +0000 (20:21 -0600)]
[Attributor] Simple casts preserve no-alias property
This is a minimal but important advancement over the existing code. A
cast with an operand that is only used in the cast retains the no-alias
property of the operand.
Johannes Doerfert [Mon, 10 Feb 2020 01:08:19 +0000 (19:08 -0600)]
[Attributor][Tests] Run the CGSCC versions on the range.ll test
Djordje Todorovic [Fri, 7 Feb 2020 17:15:04 +0000 (18:15 +0100)]
[llvm-dwarfdump][Stats] Fix the License header
Fix the added License.
Differential Revision: https://reviews.llvm.org/D74207
Amara Emerson [Sun, 9 Feb 2020 18:09:51 +0000 (10:09 -0800)]
[GlobalISel][CallLowering] Tighten constantexpr check for callee.
I'm not sure there's a test case for this, but it's better to be safe.
Johannes Doerfert [Mon, 10 Feb 2020 02:14:35 +0000 (20:14 -0600)]
[Attributor] Allow PHI nodes in AAValueConstantRangeFloating
Traversing PHI nodes is natural with the genericValueTraversal but also
a bit tricky. The problem is similar to the ones we have seen in AAAlign
and AADereferenceable, namely that we continue to increase the range in
each iteration. We use a pessimistic approach here to stop the
iterations. Nevertheless, optimistic information can now be propagated
through a PHI node.
Johannes Doerfert [Mon, 10 Feb 2020 02:21:56 +0000 (20:21 -0600)]
[Attributor][FIX] Remove FIXME that seems outdated
The change is performed as stated by the FIXME and the tests are
adjusted. All changes look fine to me and values can be inferred as
undef without it being an error.
Johannes Doerfert [Mon, 10 Feb 2020 01:08:04 +0000 (19:08 -0600)]
[Attributor] Allow SelectInst in AAValueConstantRangeFloating
The genericValueTraversal will already handle SelectInst properly and we
just needed to allow them in the initialize method.
Johannes Doerfert [Mon, 10 Feb 2020 01:07:30 +0000 (19:07 -0600)]
[Attributor] Look through (some) casts in AAValueConstantRangeFloating
Casts can be handled natively by the ConstantRange class. We do limit it
to extends for now as we assume an integer type in different locations.
A TODO and a test case with a FIXME was added to remove that restriction
in the future.
Johannes Doerfert [Mon, 10 Feb 2020 01:05:15 +0000 (19:05 -0600)]
[Attributor][FIX] Call right base method in AAValueConstantRangeFloating
We now call the base class method as we should.
Craig Topper [Mon, 10 Feb 2020 06:31:30 +0000 (22:31 -0800)]
[X86] Autogenerate complete checks. NFC
Johannes Doerfert [Mon, 10 Feb 2020 01:06:09 +0000 (19:06 -0600)]
[Attributor][Tests][NFC] Add more range tests
Inspired by https://llvm.discourse.group/t/impossible-condition-optimization/461
Johannes Doerfert [Sun, 26 Jan 2020 02:16:31 +0000 (20:16 -0600)]
[Attributor][NFC] Use existing constant instead of magic one
Craig Topper [Mon, 10 Feb 2020 05:48:00 +0000 (21:48 -0800)]
[X86] Make (insert_vector_elt (v8i16 zerovec), i16 %x, 0) generate the same code as (v8i16 (build_vector %x, 0, 0, 0, 0, 0, 0, 0)).
Instead of using a insrw to element 0, use movzx and movd.
Same for v16i8.
Michael Liao [Mon, 10 Feb 2020 05:41:46 +0000 (00:41 -0500)]
Fix `-Wparentheses` warning. NFC.
Michael Liao [Sun, 9 Feb 2020 18:09:19 +0000 (13:09 -0500)]
[clang][codegen] Fix another lifetime emission on alloca on non-default address space.
- Lifetime intrinsics expect the pointer directly from alloca. Need
extra handling for targets with alloca on non-default (or non-zero)
address space.
Craig Topper [Mon, 10 Feb 2020 04:31:56 +0000 (20:31 -0800)]
[X86] Autogenerate complete checks. NFC
Craig Topper [Mon, 10 Feb 2020 02:35:57 +0000 (18:35 -0800)]
[X86] Use MOVZX instead of MOVSX in f16_to_fp isel patterns.
Using sign extend forces the adjacent element to either all zeros
or all ones. But all ones is a NAN. So that doesn't seem like a
great idea.
Trying to work on supporting this with strict FP where NAN would
definitely be bad.
Shiva Chen [Mon, 3 Feb 2020 05:52:13 +0000 (13:52 +0800)]
[RISCV] Fix incorrect FP base CFI offset for variable argument functions
When the FP exists, the FP base CFI directive offset should take the size of variable arguments into account.
Differential Revision: https://reviews.llvm.org/D73862
Fangrui Song [Mon, 10 Feb 2020 01:28:20 +0000 (17:28 -0800)]
[DebugInfo] Add a DWARFDataExtractor constructor that takes ArrayRef<uint8_t>
Similar to D67797 (DataExtractor).
Matt Arsenault [Fri, 7 Feb 2020 17:24:15 +0000 (12:24 -0500)]
GlobalISel: Fix narrowScalar for G_{CTLZ|CTTZ}_ZERO_UNDEF
Narrow these for 64-bit VALU for AMDGPU.
Matt Arsenault [Sun, 26 Jan 2020 02:10:17 +0000 (21:10 -0500)]
AMDGPU/GlobalISel: Split 64-bit G_CTPOP in RegBankSelect
Matt Arsenault [Fri, 7 Feb 2020 16:55:39 +0000 (11:55 -0500)]
GlobalISel: Fix narrowing of G_CTLZ/G_CTTZ
The result type is separate from the source type.
Matt Arsenault [Thu, 6 Feb 2020 22:18:17 +0000 (17:18 -0500)]
AMDGPU/GlobalISel: Don't mis-select vector index on a constant
Vector indexing with a constant index should be folded out in the
legalizer, but this was accidentally falling through. This would
produce the indexing operation with $noreg. Handle this case as a
dynamic index just in case a bug like this happens again in the
future.
Matt Arsenault [Thu, 6 Feb 2020 21:52:04 +0000 (16:52 -0500)]
AMDGPU/GlobalISel: Look through casts when legalizing vector indexing
We were failing to find constants that were casted. I feel like the
artifact combiner should have folded the constant in the trunc before
the custom lowering, but that doesn't happen.
Matt Arsenault [Mon, 6 Jan 2020 20:57:51 +0000 (15:57 -0500)]
AMDGPU: Remove dead kill handling
At one point a custom node was used for kill handling, but now the
intrinsic is directly selected. Remove leftover pattern machinery.
Matt Arsenault [Fri, 27 Dec 2019 18:11:06 +0000 (13:11 -0500)]
AMDGPU: Fix SI_IF lowering when the save exec reg has terminator uses
Reverts part of
6524a7a2b9ca072bd7f7b4355d1230e70c679d2f. Since that
commit, the expansion was ignoring the actual save exec register
produced by the instruction, and looking at other instructions. I do
not understand why it was looking at other instructions, but relying
on this scan was wrong.
Fixes verifier errors after SI_IF is tail duplicated, which should be
correct to do. The results were fed into a phi, which was lowered to
the S_MOV_B64_term instructions.
Simon Pilgrim [Sun, 9 Feb 2020 21:49:37 +0000 (21:49 +0000)]
[X86] combineConcatVectorOps - combine VROTLI/VROTRI ops
Fix issue mentioned on rGe82e17d4d4ca - non-AVX512BW targets failed to concatenate 256-bit rotations back to 512-bits (split during shuffle lowering as they don't have v32i16/v64i8 types).
Craig Topper [Sun, 9 Feb 2020 21:08:25 +0000 (13:08 -0800)]
[X86] Use custom isel for (X86sbb_flag 0, 0) so we can use 32-bit SBB for i8/i16.
We were using MOV32r0 and an extract_subreg as an input. By using
custom isel we can move the extract_subreg to after the SBB instead
of on the input.
Craig Topper [Sun, 9 Feb 2020 20:31:21 +0000 (12:31 -0800)]
[X86] Add flag result VT to a MOV32r0 created in X86DAGToDAGISel::Select
The flag isn't used, but I believe this matches the MOV32r0 that
would be created by the table emitter. This should allow this node
to be CSEed with any others created by the table.
Simon Pilgrim [Sun, 9 Feb 2020 21:15:03 +0000 (21:15 +0000)]
[X86] Add lowerShuffleAsBitRotate (PR44379)
As noted on PR44379, we didn't attempt to lower vector shuffles using bit rotations on XOP/AVX512F targets.
This patch lowers to uniform ISD:ROTL nodes - ROTR isn't supported by XOP and they are interchangeable for constant values anyway.
There might be cases where targets without ISD:ROTL support would benefit from this (expanding to SRL+SHL+OR), which I'll investigate in a future patch.
Also, non-AVX512BW targets fail to concatenate 256-bit rotations back to 512-bits (split during shuffle lowering as they don't have v32i16/v64i8 types).
Craig Topper [Sun, 9 Feb 2020 19:57:22 +0000 (11:57 -0800)]
[X86] Use MVT::i32 for the type of a MOV32r0 created in X86DAGToDAGISel::Select.
Not sure if this really matters. The VT isn't really used after
this point. At best it might affect CSE.
Craig Topper [Sun, 9 Feb 2020 05:35:21 +0000 (21:35 -0800)]
[X86] Remove isel patterns that include a vselect/X86selects and a strict FP node.
A vselect+strictfp node is not equivalent to a masked operation.
The exceptions of the strictfp node are not masked by a vselect
after it so we can't match it to a masked operation.
We already had a hack in IsLegalToFold to prevent these patterns from
matching. This patch removes that hack and removes the patterns.
Jan Vesely [Wed, 5 Feb 2020 01:14:04 +0000 (20:14 -0500)]
libclc/r600: Use target specific builtins to implement rsqrt and native_rsqrt
Fixes OCL CTS rsqrt and half_rsqrt (1 thread, scalaer) tests on AMD Turks.
Reviewer: awatry
Differential Revision: https://reviews.llvm.org/D74016
Jan Vesely [Wed, 5 Feb 2020 01:09:12 +0000 (20:09 -0500)]
libclc: Move rsqrt implementation to a .cl file
Reviewer: awatry
Differential Revision: https://reviews.llvm.org/D74013
Simon Pilgrim [Sun, 9 Feb 2020 18:35:02 +0000 (18:35 +0000)]
[X86][XOP] Add XOP target to vXi16/vXi8 shuffle tests
Helps with bit rotation test coverage for PR44379
Simon Pilgrim [Sun, 9 Feb 2020 17:51:53 +0000 (17:51 +0000)]
[X86][SSE] Add more tests showing failure to lower shuffles as bit rotations
Simon Pilgrim [Sun, 9 Feb 2020 14:23:19 +0000 (14:23 +0000)]
[X86] Rename matchShuffleAsRotate - matchShuffleAsByteRotate. NFCI.
A matchShuffleAsBitRotate variant will be added soon and we need to make the difference more obvious.
Jan Kratochvil [Sun, 9 Feb 2020 17:13:04 +0000 (18:13 +0100)]
[lldb] [doc] Status: Linux: Update the paragraph
Kamil Rytarowski [Sun, 9 Feb 2020 17:02:07 +0000 (18:02 +0100)]
[LLDB] [doc] Document NetBSD status and sort OSs alphabetically
LLVM GN Syncbot [Sun, 9 Feb 2020 15:41:05 +0000 (15:41 +0000)]
[gn build] Port
a17f03bd939
Sanjay Patel [Sun, 9 Feb 2020 15:04:41 +0000 (10:04 -0500)]
[VectorCombine] new IR transform pass for partial vector ops
We have several bug reports that could be characterized as "reducing scalarization",
and this topic was also raised on llvm-dev recently:
http://lists.llvm.org/pipermail/llvm-dev/2020-January/138157.html
...so I'm proposing that we deal with these patterns in a new, lightweight IR vector
pass that runs before/after other vectorization passes.
There are 4 alternate options that I can think of to deal with this kind of problem
(and we've seen various attempts at all of these), but they all have flaws:
InstCombine - can't happen without TTI, but we don't want target-specific
folds there.
SDAG - too late to assist other vectorization passes; TLI is not equipped
for these kind of cost queries; limited to a single basic block.
CGP - too late to assist other vectorization passes; would need to re-implement
basic cleanups like CSE/instcombine.
SLP - doesn't fit with existing transforms; limited to a single basic block.
This initial patch/transform is based on existing code in AggressiveInstCombine:
we walk backwards through the function looking for a pattern match. But we diverge
from that cost-independent IR canonicalization pass by using TTI to decide if the
vector alternative is profitable.
We probably have at least 10 similar bug reports/patterns (binops, constants,
inserts, cheap shuffles, etc) that would fit in this pass as follow-up enhancements.
It's possible that we could iterate on a worklist to fix-point like InstCombine does,
but it's safer to start with a most basic case and evolve from there, so I didn't
try to do anything fancy with this initial implementation.
Differential Revision: https://reviews.llvm.org/D73480
Jan Kratochvil [Sun, 9 Feb 2020 14:22:36 +0000 (15:22 +0100)]
[lldb] [doc] Status: Debugserver (remote debugging) is OK now
Jan Kratochvil [Sun, 9 Feb 2020 14:11:38 +0000 (15:11 +0100)]
[lldb] [doc] Testing: Fix typos
Kamil Rytarowski [Sun, 9 Feb 2020 13:59:04 +0000 (14:59 +0100)]
[LLDB] [doc] Remove note about libpanel(3) and NetBSD
libpanel(3) is now supported in all supported versions of NetBSD.
Kamil Rytarowski [Sun, 9 Feb 2020 13:57:09 +0000 (14:57 +0100)]
[LLDB] [doc] Update the current status of pkgsrc (NetBSD) building
Jan Kratochvil [Sun, 9 Feb 2020 13:49:38 +0000 (14:49 +0100)]
[lldb] [testsuite] TestGdbRemoteLibrariesSvr4Support: Fix symlinked builddir
When I have symlinked builddir on Fedora 31 x86_64 I get:
FAIL: test_libraries_svr4_libs_present (TestGdbRemoteLibrariesSvr4Support.TestGdbRemoteLibrariesSvr4Support)
----------------------------------------------------------------------
...
File "lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries-svr4/TestGdbRemoteLibrariesSvr4Support.py", line 106, in
libraries_svr4_libs_present
self.assertIn(self.getBuildDir() + "/" + lib, libraries_svr4_names)
AssertionError:
'/home/jkratoch/redhat/llvm-monorepo-clangassertsymlink/lldb-test-build.noindex/tools/lldb-server/libraries-svr4/TestGdbRemoteLibrariesSvr4Support.test_libraries_svr4_libs_present/libsvr4lib_a.so' not found in ['/home/jkratoch/redhat/llvm-monorepo/lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries-svr4/linux-vdso.so.1', '/quad/home/jkratoch/redhat/llvm-monorepo-clangassertsymlink/lldb-test-build.noindex/tools/lldb-server/libraries-svr4/TestGdbRemoteLibrariesSvr4Support.test_libraries_svr4_libs_present/libsvr4lib_a.so', '/quad/home/jkratoch/redhat/llvm-monorepo-clangassertsymlink/lldb-test-build.noindex/tools/lldb-server/libraries-svr4/TestGdbRemoteLibrariesSvr4Support.test_libraries_svr4_libs_present/libsvr4lib_b".so', '/usr/lib64/libdl-2.30.so', '/usr/lib64/libstdc++.so.6.0.27', '/usr/lib64/libm-2.30.so', '/usr/lib64/libgcc_s-9-
20190827.so.1', '/usr/lib64/libc-2.30.so', '/usr/lib64/ld-2.30.so']
Config=x86_64-/quad/home/jkratoch/redhat/llvm-monorepo-clangassertsymlink/bin/clang-11
----------------------------------------------------------------------
Differential Revision: https://reviews.llvm.org/D74295
Simon Pilgrim [Sun, 9 Feb 2020 13:35:03 +0000 (13:35 +0000)]
Fix signed/unsigned warning.
Simon Pilgrim [Sun, 9 Feb 2020 12:25:19 +0000 (12:25 +0000)]
[X86] Recognise ROTLI/ROTRI rotations as faux shuffles
Allows us to combine rotations with shuffles.
One of many things necessary to fix PR44379 (lowering shuffles to rotations)
Ehud Katz [Sun, 9 Feb 2020 10:25:21 +0000 (12:25 +0200)]
[LoopExtractor] Convert LoopExtractor from LoopPass to ModulePass
The LoopExtractor created new functions (by definition), which violates
the restrictions of a LoopPass.
The correct implementation of this pass should be as a ModulePass.
Includes reverting rL82990 implications on the LoopExtractor.
Fixes PR3082 and PR8929.
Differential Revision: https://reviews.llvm.org/D69069
Ayman Musa [Tue, 28 Jan 2020 14:31:44 +0000 (16:31 +0200)]
[AggressiveInstCombine] Add test with baseline CHECKs for aggressive inst combine for SELECT.
serge_sans_paille [Mon, 9 Sep 2019 14:59:34 +0000 (16:59 +0200)]
Support -fstack-clash-protection for x86
Implement protection against the stack clash attack [0] through inline stack
probing.
Probe stack allocation every PAGE_SIZE during frame lowering or dynamic
allocation to make sure the page guard, if any, is touched when touching the
stack, in a similar manner to GCC[1].
This extends the existing `probe-stack' mechanism with a special value `inline-asm'.
Technically the former uses function call before stack allocation while this
patch provides inlined stack probes and chunk allocation.
Only implemented for x86.
[0] https://www.qualys.com/2017/06/19/stack-clash/stack-clash.txt
[1] https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00556.html
This a recommit of
39f50da2a357a8f685b3540246c5d762734e035f with proper LiveIn
declaration, better option handling and more portable testing.
Differential Revision: https://reviews.llvm.org/D68720
serge-sans-paille [Sun, 9 Feb 2020 09:06:31 +0000 (10:06 +0100)]
Revert "Support -fstack-clash-protection for x86"
This reverts commit
0fd51a4554f5f4f90342f40afd35b077f6d88213.
Failures:
http://lab.llvm.org:8011/builders/llvm-clang-win-x-armv7l/builds/4354
serge_sans_paille [Mon, 9 Sep 2019 14:59:34 +0000 (16:59 +0200)]
Support -fstack-clash-protection for x86
Implement protection against the stack clash attack [0] through inline stack
probing.
Probe stack allocation every PAGE_SIZE during frame lowering or dynamic
allocation to make sure the page guard, if any, is touched when touching the
stack, in a similar manner to GCC[1].
This extends the existing `probe-stack' mechanism with a special value `inline-asm'.
Technically the former uses function call before stack allocation while this
patch provides inlined stack probes and chunk allocation.
Only implemented for x86.
[0] https://www.qualys.com/2017/06/19/stack-clash/stack-clash.txt
[1] https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00556.html
This a recommit of
39f50da2a357a8f685b3540246c5d762734e035f with proper LiveIn
declaration, better option handling and more portable testing.
Differential Revision: https://reviews.llvm.org/D68720
Fangrui Song [Sun, 9 Feb 2020 06:39:09 +0000 (22:39 -0800)]
[ELF][test] Use llvm-readelf -l instead of llvm-readobj -l for some memory region tests
MaheshRavishankar [Sun, 9 Feb 2020 02:23:09 +0000 (18:23 -0800)]
[mlir][GPUToSPIRV] Modify the lowering of gpu.block_dim to be consistent with Vulkan SPEC
The existing lowering of gpu.block_dim added a global variable with
the WorkGroupSize decoration. This raises an error within
Vulkan/SPIR-V validation since Vulkan requires this to have a constant
initializer. This is not yet supported in SPIR-V dialect. Changing the
lowering to return the workgroup size as a constant value instead,
obtained from spv.entry_point_abi attribute gets around the issue for
now. The validation goes through since the workgroup size is specified
using spv.execution_mode operation.
Craig Topper [Sun, 9 Feb 2020 02:56:17 +0000 (18:56 -0800)]
[X86] Add more scalar intrinsic instructions to isNonFoldablePartialRegisterLoad.
I think this covers most if not all of the scalar intrinsic
instructions.
Johannes Doerfert [Wed, 27 Nov 2019 06:30:12 +0000 (00:30 -0600)]
[Attributor] Add an Attributor CGSCC pass and run it
In addition to the module pass, this patch introduces a CGSCC pass that
runs the Attributor on a strongly connected component of the call graph
(both old and new PM). The Attributor was always design to be used on a
subset of functions which makes this patch mostly mechanical.
The one change is that we give up `norecurse` deduction in the module
pass in favor of doing it during the CGSCC pass. This makes the
interfaces simpler but can be revisited if needed.
Reviewed By: hfinkel
Differential Revision: https://reviews.llvm.org/D70767
Fangrui Song [Sun, 9 Feb 2020 03:01:17 +0000 (19:01 -0800)]
Fix -Wunused-lambda-capture for -DLLVM_ENABLE_ASSERTIONS=off builds after
6556c615f3c3aae8af876806777065961ae20024
Johannes Doerfert [Sun, 9 Feb 2020 02:14:01 +0000 (20:14 -0600)]
[FIX] Ordering problem accidentally introduced with D72304
Craig Topper [Sun, 9 Feb 2020 01:46:59 +0000 (17:46 -0800)]
[X86] Add the recently added (V)CVTSS2SI/CVTSD2SI instructions used for LRINT/LLRINT to the load folding tables.
Johannes Doerfert [Sun, 9 Feb 2020 00:58:16 +0000 (18:58 -0600)]
[FIX] Fix warning in LazyCallGraphTest caused by D70927
fady [Sun, 9 Feb 2020 00:54:08 +0000 (18:54 -0600)]
[OpenMP][OMPIRBuilder] Add Directives (master and critical) to OMPBuilder.
Add support for Master and Critical directive in the OMPIRBuilder. Both make use of a new common interface for emitting inlined OMP regions called `emitInlinedRegion` which was added in this patch as well.
Also this patch modifies clang to use the new directives when `-fopenmp-enable-irbuilder` commandline option is passed.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D72304
Johannes Doerfert [Sun, 9 Feb 2020 00:42:24 +0000 (18:42 -0600)]
[OpenMP][Opt] Delete terminating and read-only parallel regions
Parallel regions known to be read-only, e.g., after we removed all dead
write accesses, and terminating (`willreturn`) can be removed.
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D69954
Johannes Doerfert [Sun, 9 Feb 2020 00:03:40 +0000 (18:03 -0600)]
[OpenMP][Opt] Annotate known runtime functions and deduplicate more
This adds ~27 more runtime calls to the OpenMPKinds.def file, all with
attributes. We deduplicate 16 of those automatically in function =
thread scope. And we annotate all of them automatically during the
OpenMPOpt discovery step. A test with all omp_XXXX runtime calls to
track annotation coverage is included.
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D69984
Nico Weber [Sat, 8 Feb 2020 23:50:51 +0000 (18:50 -0500)]
[gn build] (manually) port
72277ecd62e and the LLVMBuild bit of
9548b74a83
Craig Topper [Sat, 8 Feb 2020 23:52:57 +0000 (15:52 -0800)]
[X86] Use any_fadd/sub/mul/div/sqrt with the AVX512 scalar_*_patterns.
Making sure not to use them with patterns for masked instructions.
Also fix FMA patterns that were matching strict_fma+x86selects to
masked instructions.
River Riddle [Sat, 8 Feb 2020 23:46:02 +0000 (15:46 -0800)]
[mlir][DeclarativeParser] Move several missed parsers over to the declarative form.
Differential Revision: https://reviews.llvm.org/D74283
River Riddle [Sat, 8 Feb 2020 18:01:17 +0000 (10:01 -0800)]
[mlir][DeclarativeParser] Add support for attributes with buildable types.
This revision adds support in the declarative assembly form for printing attributes with buildable types without the type, and moves several more parsers over to the declarative form.
Differential Revision: https://reviews.llvm.org/D74276