Fraser Cormack [Fri, 19 Nov 2021 20:21:47 +0000 (20:21 +0000)]
[VP] Propagate align parameter attr on VP load/store to ISel
This patch fixes a case where the 'align' parameter attribute on the
pointer operands to llvm.vp.load and llvm.vp.store was being dropped
during the conversion to the SelectionDAG. The default alignment
equal to the ABI type alignment of the vector type was kept. It also
updates the documentation to reflect the fact that the parameter
attribute is now properly supported.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D114422
Jaroslav Sevcik [Sat, 4 Dec 2021 20:32:09 +0000 (21:32 +0100)]
[lldb] Fix windows path guessing for root paths
Fix recognizing "<letter>:\" as a windows path.
Differential Revision: https://reviews.llvm.org/D115104
Ties Stuij [Tue, 7 Dec 2021 10:13:17 +0000 (10:13 +0000)]
[ARM] Implement PAC return address signing mechanism for PACBTI-M
This patch implements PAC return address signing for armv8-m. This patch roughly
accomplishes the following things:
- PAC and AUT instructions are generated.
- They're part of the stack frame setup, so that shrink-wrapping can move them
inwards to cover only part of a function
- The auth code generated by PAC is saved across subroutine calls so that AUT
can find it again to check
- PAC is emitted before stacking registers (so that the SP it signs is the one
on function entry).
- The new pseudo-register ra_auth_code is mentioned in the DWARF frame data
- With CMSE also in use: PAC is emitted before stacking FPCXTNS, and AUT
validates the corresponding value of SP
- Emit correct unwind information when PAC is replaced by PACBTI
- Handle tail calls correctly
Some notes:
We make the assembler accept the `.save {ra_auth_code}` directive that is
emitted by the compiler when it saves a register that contains a
return address authentication code.
For EHABI we need to have the `FrameSetup` flag on the instruction and
handle the `t2PACBTI` opcode (identically to `t2PAC`), so we can emit
`.save {ra_auth_code}`, instead of `.save {r12}`.
For PACBTI-M, the instruction which computes return address PAC should use SP
value before adjustment for the argument registers save are (used for variadic
functions and when a parameter is is split between stack and register), but at
the same it should be after the instruction that saves FPCXT when compiling a
CMSE entry function.
This patch moves the varargs SP adjustment after the FPCXT save (they are never
enabled at the same time), so in a following patch handling of the `PAC`
instruction can be placed between them.
Epilogue emission code adjusted in a similar manner.
PACBTI-M code generation should not emit any instructions for architectures
v6-m, v8-m.base, and for A- and R-class cores. Diagnostic message for such cases
is handled separately by a future ticket.
note on tail calls:
If the called function has four arguments that occupy registers `r0`-`r3`, the
only option for holding the function pointer itself is `r12`, but this register
is used to keep the PAC during function/prologue epilogue and clobbers the
function pointer.
When we do the tail call we need the five registers (`r0`-`r3` and `r12`) to
keep six values - the four function arguments, the function pointer and the PAC,
which is obviously impossible.
One option would be to authenticate the return address before all callee-saved
registers are restored, so we have a scratch register to temporarily keep the
value of `r12`. The issue with this approach is that it violates a fundamental
invariant that PAC is computed using CFA as a modifier. It would also mean using
separate instructions to pop `lr` and the rest of the callee-saved registers,
which would offset the advantages of doing a tail call.
Instead, this patch disables indirect tail calls when the called function take
four or more arguments and the return address sign and authentication is enabled
for the caller function, conservatively assuming the caller function would spill
LR.
This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:
https://developer.arm.com/documentation/ddi0553/latest
The following people contributed to this patch:
- Momchil Velikov
- Ties Stuij
Reviewed By: danielkiss
Differential Revision: https://reviews.llvm.org/D112429
David Spickett [Tue, 7 Dec 2021 10:02:44 +0000 (10:02 +0000)]
[llvm][X86] Add x86 triple to fentry test
When run on AArch64 hardware llc would default to native
arch.
Jay Foad [Tue, 7 Dec 2021 09:53:40 +0000 (09:53 +0000)]
[AMDGPU] Remove redundant mayLoad = 0, mayStore = 0. NFC.
Almost everything in this file is mayLoad = 0, mayStore = 0 by
default anyway.
Cullen Rhodes [Tue, 7 Dec 2021 09:20:42 +0000 (09:20 +0000)]
[IR] Remove unbounded as possible value for vscale_range minimum
The default for min is changed to 1. The behaviour of -mvscale-{min,max}
in Clang is also changed such that 16 is the max vscale when targeting
SVE and no max is specified.
Reviewed By: sdesmalen, paulwalker-arm
Differential Revision: https://reviews.llvm.org/D113294
Gabor Marton [Wed, 1 Dec 2021 20:10:42 +0000 (21:10 +0100)]
[Analyzer] SValBuilder: Simlify a SymExpr to the absolute simplest form
Move the SymExpr simplification fixpoint logic into SValBuilder.
Differential Revision: https://reviews.llvm.org/D114938
Vitaly Buka [Tue, 7 Dec 2021 08:16:28 +0000 (00:16 -0800)]
[sanitizer] Don't lock for StackStore::Allocated()
Vitaly Buka [Tue, 7 Dec 2021 08:10:25 +0000 (00:10 -0800)]
[sanitizer] Fix CompressStackStore VPrint message
LLVM GN Syncbot [Tue, 7 Dec 2021 08:10:43 +0000 (08:10 +0000)]
[gn build] Port
ae53d02f557c
Petr Hosek [Tue, 7 Dec 2021 08:08:51 +0000 (00:08 -0800)]
Revert "Microsoft's floating-point to_chars powered by Ryu and Ryu Printf"
This reverts commit
a8025e06fc0f2fe1bbee9e1a6f15c336bfbdcb05 since
it triggers PR52584 with debug info enabled.
LLVM GN Syncbot [Tue, 7 Dec 2021 06:41:50 +0000 (06:41 +0000)]
[gn build] Port
0fe61ecc2cef
Vitaly Buka [Tue, 7 Dec 2021 06:35:55 +0000 (22:35 -0800)]
[NFC][sanitizer] Non-copyable ScopedBlockSignals
Sameer Sahasrabuddhe [Tue, 7 Dec 2021 06:31:22 +0000 (12:01 +0530)]
CycleInfo: Introduce cycles as a generalization of loops
LLVM loops cannot represent irreducible structures in the CFG. This
change introduce the concept of cycles as a generalization of loops,
along with a CycleInfo analysis that discovers a nested
hierarchy of such cycles. This is based on Havlak (1997), Nesting of
Reducible and Irreducible Loops.
The cycle analysis is implemented as a generic template and then
instatiated for LLVM IR and Machine IR. The template relies on a new
GenericSSAContext template which must be specialized when used for
each IR.
This review is a restart of an older review request:
https://reviews.llvm.org/D83094
Original implementation by Nicolai Hähnle <nicolai.haehnle@amd.com>,
with recent refactoring by Sameer Sahasrabuddhe <sameer.sahasrabuddhe@amd.com>
Differential Revision: https://reviews.llvm.org/D112696
Vitaly Buka [Tue, 7 Dec 2021 06:22:04 +0000 (22:22 -0800)]
[NFC][lsan] Refactor LockThreadRegistry/LockAllocator calls
Vitaly Buka [Tue, 7 Dec 2021 05:17:32 +0000 (21:17 -0800)]
[NFC][sanitizer] Fix typo in comment
Prashant Kumar [Sun, 5 Dec 2021 15:40:41 +0000 (21:10 +0530)]
[MLIR] Simplify division extraction unit testing.
The new `getLocalReprs` function also outputs `dividends` and
`denominators` and hence the CheckDivisionRepresentation fn is
modified to take the newer getLocalReprs function into account.
Signed-off-by: Prashant Kumar <pk5561@gmail.com>
Reviewed By: Groverkss
Differential Revision: https://reviews.llvm.org/D115146
LLVM GN Syncbot [Tue, 7 Dec 2021 05:54:10 +0000 (05:54 +0000)]
[gn build] Port
d9941f74549a
Shraiysh Vaishay [Tue, 7 Dec 2021 04:57:40 +0000 (10:27 +0530)]
[mlir][OpenMP] Added omp.atomic.read lowering
This patch adds lowering from omp.atomic.read to LLVM IR along with the
memory ordering clause. Tests for the same are also added.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D115134
wren romano [Tue, 7 Dec 2021 01:28:33 +0000 (17:28 -0800)]
[mlir][sparse] Requiring emitCInterface parameter to be explicit
Depends On D115004
Cleans up code legibility by requiring the `emitCInterface` parameter to be explicit at all call-sites, and defining boolean aliases for that parameter.
Reviewed By: aartbik, rriddle
Differential Revision: https://reviews.llvm.org/D115005
Joao Moreira [Tue, 7 Dec 2021 02:34:37 +0000 (10:34 +0800)]
[X86] Fix fentry handling in X86IndirectBranchTracking.cpp
When compiling with indirect branch tracking and fentry (-fcf-protection=branch -mfentry -pg) the X86IndirectBranchTrackingPass will attempt to place endbr in basic blocks, checking for Calls/IsCallReturnTwice. For calling the function IsCallReturnTwice(), the pass attempts to retrieve the first operand of the respective machine instruction. Since FENTRY_CALL is considered a call, and it does not have any argument, the condition inside the pass will attempt to call IsCallReturnTwice on the machine instruction, but since it does not have operands, it will lead into a crash.
Kudos to Alyssa Milburn for helping in the issue triage. The diff brings a test, but to reproduce the problem, follow the steps below.
```
echo "int main() {};" > repro.c
clang repro.c -fcf-protection=branch -mfentry -pg
```
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D111108
Mircea Trofin [Tue, 7 Dec 2021 01:33:13 +0000 (17:33 -0800)]
[NFC][MachineInstr] Pass-by-value DebugLoc in CreateMachineInstr
DebugLoc is cheap to move, passing it by-val rather than const ref to
take advantage of the fact that it is consumed that way by the
MachineInstr ctor, which creates some optimization oportunities.
Differential Revision: https://reviews.llvm.org/D115208
Lang Hames [Tue, 7 Dec 2021 01:22:30 +0000 (12:22 +1100)]
[ORC] Pad section start to account for alignment offset in MachO GDB JIT plugin.
In order to present a well-formed MachO debug object for debugger registration
the first block in each section must have a zero alignment offset (since there
is no way to represent a non-zero offset in a MachO section load command). This
patch updates the MachODebugObjectSynthesizer class to introduce a padding
padding block at the start of the section if necessary to guarantee a zero
alignment offset.
Igor Kudrin [Tue, 7 Dec 2021 03:10:24 +0000 (10:10 +0700)]
[ELF] Do not report undefined weak references in shared libraries
This fixes an issue introduced in D101996.
A weak reference in a shared library could be incorrectly reported if
there is another library that has a strong reference to the same symbol.
Differential Revision: https://reviews.llvm.org/D115041
Kai Luo [Tue, 7 Dec 2021 02:09:18 +0000 (02:09 +0000)]
[MachineVerifier] Make TiedOpsRewritten computable in MIRParser
This patch is to address post-commit comment https://reviews.llvm.org/D80538#anchor-inline-1091625, which make the constraint stronger based on what https://reviews.llvm.org/D80538 does, i.e., "TiedOpsRewritten is set iff leave-ssa and all tied operands share the same register".
Reviewed By: MatzeB
Differential Revision: https://reviews.llvm.org/D114573
Med Ismail Bennani [Tue, 7 Dec 2021 01:55:19 +0000 (17:55 -0800)]
[lldb/test] Fix InvalidScriptedThread windows test failure
This patch should fix a Windows test failure for the
InvalidScriptedThread test:
https://lab.llvm.org/buildbot/#/builders/83/builds/12571
This refactors the test to stop using python `tempfile` since it's not
supported on Windows and creates a logfile at runtime in the test folder.
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Luís Ferreira [Tue, 7 Dec 2021 00:52:38 +0000 (00:52 +0000)]
[Demangle] Add support for D function-local parent symbols
Internally `__Sddd` function-local parent symbols are used to solve ambiguities on symbols in
the same scope with the same mangled name.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D114309
Luís Ferreira [Tue, 7 Dec 2021 00:52:37 +0000 (00:52 +0000)]
[Demangle] Add support for D special identifiers
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D114308
not-jenni [Tue, 7 Dec 2021 01:13:51 +0000 (17:13 -0800)]
[mlir][tosa] Add tosa.depthwise_conv2d as tosa.mul canonicalization
For a 1x1 weight and stride of 1, the input/weight can be reshaped and
multiplied elementwise then reshaped back
Reviewed By: rsuderman, KoolJBlack
Differential Revision: https://reviews.llvm.org/D115207
Noah Shutty [Mon, 6 Dec 2021 18:28:07 +0000 (18:28 +0000)]
[Support] [Debuginfod] Move HTTPClient to Debuginfod library.
Following the discussion in D112753, this moves the HTTPClient from Support to Debuginfod library so that tools depending on Support do not automatically depend on Curl as well. This also removes `HTTPClient::initialize()` and `HTTPClient::cleanup()` from `InitLLVM` so these steps should be implemented by user tools instead.
Reviewed By: phosek
Differential Revision: https://reviews.llvm.org/D115131
Mircea Trofin [Tue, 7 Dec 2021 01:17:55 +0000 (17:17 -0800)]
[NFC][MachineInstr] Rename some vars to conform to coding style
Evandro Menezes [Fri, 2 Apr 2021 18:55:19 +0000 (13:55 -0500)]
[RISCV] Add scheduling resources for Vector pseudo instructions.
Add the scheduling resources for the V extension pseudo instructions.
Authored-by: Evandro Menezes <evandro.menezes@sifive.com>
Differential Revision: https://reviews.llvm.org/D113353
Chen Zheng [Tue, 16 Nov 2021 07:50:37 +0000 (07:50 +0000)]
[PowerPC][NFC] add cases for D114062
Matthias Springer [Mon, 6 Dec 2021 10:36:48 +0000 (19:36 +0900)]
[mlir][linalg][bufferize][NFC] Clean up BufferizationState
Make fields private and clean up the interface. In particular, BufferizableOpInterface::bufferize no longer has access to `aliasInfo`. This was potentially dangerous because some of the ops registered in BufferizationAliasInfo may have been deleted.
Differential Revision: https://reviews.llvm.org/D114931
Nico Weber [Mon, 6 Dec 2021 14:33:20 +0000 (09:33 -0500)]
[tsan] Move tsan/rtl build rules into tsan/rtl/CMakeLists.txt
That way, the build rules are closer to the source files they describe.
No intended behavior change.
Differential Revision: https://reviews.llvm.org/D115155
Nico Weber [Tue, 7 Dec 2021 00:12:58 +0000 (19:12 -0500)]
Tweak diagnostic text from
e4eb6216c2e
Ye Luo [Tue, 7 Dec 2021 00:19:08 +0000 (18:19 -0600)]
[OpenMP][libomptarget] amdgpu plugin adds runpath for dependencies
amdgpu plugin depends on libhsa-runtime64 library. Add runpath in case it is not on the LD_LIBRARY_PATH.
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D115198
Med Ismail Bennani [Thu, 2 Dec 2021 02:56:29 +0000 (18:56 -0800)]
[lldb/plugins] Add arm64(e) support to ScriptedProcess
This patch adds support for arm64(e) targets to ScriptedProcess, by
providing the `DynamicRegisterInfo` to the base `lldb.ScriptedThread` class.
This allows create and debugging ScriptedProcess on Apple Silicon
hardware as well as Apple mobile devices.
It also replace the C++ asserts on `ScriptedThread::GetDynamicRegisterInfo`
by some error logging, re-enables `TestScriptedProcess` for arm64
Darwin platforms and adds a new invalid Scripted Thread test.
rdar://
85892451
Differential Revision: https://reviews.llvm.org/D114923
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Nico Weber [Tue, 7 Dec 2021 00:08:59 +0000 (19:08 -0500)]
[gn build] Port
3678326d2839
Nico Weber [Tue, 7 Dec 2021 00:08:20 +0000 (19:08 -0500)]
Revert "ext-tsp basic block layout"
This reverts commit
c68f71eb37c2b6ffcf29e865d443a910e73083bd.
Breaks tests on arm hosts, see comments on https://reviews.llvm.org/D113424
Nico Weber [Mon, 6 Dec 2021 23:41:37 +0000 (18:41 -0500)]
Fix incorrect fallthrough in
e4eb6216c2e
Rob Suderman [Mon, 6 Dec 2021 23:33:03 +0000 (15:33 -0800)]
[mlir][tosa] Resubmit add tosa.conv2d as tosa.fully_connected canonicalization
Fixed the tosa.conv2d to tosa.fully_connected canonicalization for incorrect
output channels. Included uptes to tests to include checks for the result
shapes during canonicalization.
This allows conv2d to transform to the simpler fully_connected operation.
Reviewed By: mravishankar
Differential Revision: https://reviews.llvm.org/D115170
Dave Lee [Mon, 6 Dec 2021 21:04:27 +0000 (13:04 -0800)]
[lldb] Remove some trivial scoped timers
While profiling lldb (from swift/llvm-project), these timers were noticed to be short lived and high firing, and so they add noise more than value.
The data points I recorded are:
`FindTypes_Impl`: 49,646 calls, 812ns avg, 40.33ms total
`AppendSymbolIndexesWithName`: 36,229 calls, 913ns avg, 33.09ms total
`FindAllSymbolsWithNameAndType`: 36,229 calls, 1.93µs avg, 70.05ms total
`FindSymbolsWithNameAndType`: 23,263 calls, 3.09µs avg, 71.88ms total
Differential Revision: https://reviews.llvm.org/D115182
Chris Davis [Mon, 6 Dec 2021 23:11:34 +0000 (18:11 -0500)]
Enable pdbpagesize to allow support for PDB file sizes > 4GB
Enable the pdbpagesize flag to allow linking of PDB files > 4GB.
Also includes a couple small fixes to change to uint64_t to support the
larger file sizes. I updated the max file size check in MSFBuilder.cpp
to take into account the page size.
Differential Revision: https://reviews.llvm.org/D115051
LLVM GN Syncbot [Mon, 6 Dec 2021 23:16:18 +0000 (23:16 +0000)]
[gn build] Port
cc3bb8558018
Nico Weber [Mon, 6 Dec 2021 23:15:20 +0000 (18:15 -0500)]
Reland "[gn build] (manually) port
4a16fe1369f3ab (debuginfod)"
This reverts commit
4b63562ebcfa2bc194a778018e212dc3b99528f7.
The debuginfod change relanded in
0e0f1b28fce8
Kirill Stoimenov [Mon, 6 Dec 2021 23:07:21 +0000 (23:07 +0000)]
Revert "[ASan] Added asan_shadow_defines.h, which contatins shadow offset for various platforms."
This reverts commit
2f3bb59f512f8904fb2f0d7cd7bead3172fbc5d1.
Reviewed By: kstoimenov
Differential Revision: https://reviews.llvm.org/D115193
Daniele Castagna [Mon, 6 Dec 2021 23:06:29 +0000 (15:06 -0800)]
[CUDA][SPIRV] Use OpenCLKernel CC for CUDA -> SPIRV
Select the OpenCLKernel calling convention for kernels when compiling
CUDA targeting SPIR-V.
In this way the generated LLVM IR will have a spir_kernel calling
convention that will be translated to an OpEntryPoint when converting
to SPIRV.
Reviewed By: jlebar, tra
Differential Revision: https://reviews.llvm.org/D114407
James Nagurne [Fri, 22 Oct 2021 22:08:16 +0000 (17:08 -0500)]
[llvm][Hexagon] Generalize VLIWResourceModel, VLIWMachineScheduler, and ConvergingVLIWScheduler
The Pre-RA VLIWMachineScheduler used by Hexagon is a relatively generic
implementation that would make sense to use on other VLIW targets.
This commit lifts those classes into their own header/source file with the
root VLIWMachineScheduler. I chose this path rather than adding the
strategy et al. into MachineScheduler to avoid bloating the file with other
implementations.
Target-specific behaviors have been captured and replicated through
function overloads.
- Added an overloadable DFAPacketizer creation member function. This is
mainly done for our downstream, which has the capability to override
the DFAPacketizer with custom implementations. This is an upstreamable
TODO on our end. Currently, it always returns the result of
TargetInstrInfo::CreateTargetScheduleState
- Added an extra helper which returns the number of instructions in the
current packet. This is used in our downstream, and may be useful
elsewhere.
- Placed the priority heuristic values into the ConvergingVLIWscheduler
class instead of defining them as local statics in the implementation
- Added a overridable helper in ConvergingVLIWScheduler so that targets
can create their own VLIWResourceModel
Differential Revision: https://reviews.llvm.org/D113150
wren romano [Fri, 3 Dec 2021 23:58:03 +0000 (15:58 -0800)]
[mlir][sparse] Code cleanup for SparseTensorConversion
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D115004
Noah Shutty [Mon, 6 Dec 2021 21:46:22 +0000 (21:46 +0000)]
[llvm] [Debuginfo] Debuginfod client library.
This adds a Debuginfod client library which queries servers specified by the `DEBUGINFOD_URLS` environment variable for the debuginfo, executable, or a specified source file associated with a given build id.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D112758
Kirill Stoimenov [Fri, 3 Dec 2021 22:24:10 +0000 (22:24 +0000)]
[ASan] Added asan_shadow_defines.h, which contatins shadow offset for various platforms.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D115075
Yaxun (Sam) Liu [Thu, 2 Dec 2021 22:49:36 +0000 (17:49 -0500)]
[HIP] Fix -fgpu-rdc for Windows
This patch fixes issues for -fgpu-rdc for Windows MSVC
toolchain:
Fix COFF specific section flags and remove section types
in llvm-mc input file for Windows.
Escape fatbin path in llvm-mc input file.
Add -triple option to llvm-mc.
Put __hip_gpubin_handle in comdat when it has linkonce_odr
linkage.
Reviewed by: Artem Belevich
Differential Revision: https://reviews.llvm.org/D115039
Danil Stefaniuc [Mon, 6 Dec 2021 20:48:48 +0000 (12:48 -0800)]
[formatters] Add a pointer and reference tests for a list and forward_list formatters for libstdcpp and libcxx
This adds extra tests for libstdcpp and libcxx list and forward_list formatters to check whether formatter behaves correctly when applied on pointer and reference values.
Reviewed By: wallace
Differential Revision: https://reviews.llvm.org/D115137
Walter Erquinigo [Fri, 3 Dec 2021 01:46:15 +0000 (17:46 -0800)]
[formatters] Add a deque formatter for libstdcpp and fix the libcxx one
This adds the formatters for libstdcpp's deque as a python
implementation. It adds comprehensive tests for the two different
storage strategies deque uses. Besides that, this fixes a couple of bugs
in the libcxx implementation. Finally, both implementation run against
the same tests.
This is a minor improvement on top of Danil Stefaniuc's formatter.
Eugene Zhulenev [Mon, 6 Dec 2021 19:23:53 +0000 (11:23 -0800)]
[mlir] Improve async parallel for tests + fix typos
Do load and store to verify that we process each element of the iteration space once.
Reviewed By: cota
Differential Revision: https://reviews.llvm.org/D115152
David Blaikie [Mon, 6 Dec 2021 20:18:02 +0000 (12:18 -0800)]
Bazel: add new llvm-c/Deprecated.h header
Michael Kruse [Mon, 6 Dec 2021 20:08:07 +0000 (14:08 -0600)]
[OpenMPIRBuilder] Implicitly defined control blocks. NFC.
Do not explicitly store the BasicBlocks for Preheader, Body and After inside CanonicalLoopInfo, but look the up when needed using their position relative to the other loop control blocks. By definition, instructions inside these are not managed by CanonicalLoopInfo (except terminator for Preheader) hence it makes sense to think of them as connections to the CanonicalLoopInfo instead of part of the CanonicalLoopInfo itself.
In particular for Preheader, it makes using SplitBasicBlock easier since inserting control flow at an InsertPoint may otherwise require updating the CanonicalLoopInfo's Preheader because the branch that jumps to the header is moved to another BasicBlock.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D114368
Rob Suderman [Mon, 6 Dec 2021 19:54:09 +0000 (11:54 -0800)]
[mlir] Add CtPop to MathOps with lowering to LLVM
math.ctpop maths to the llvm.ctpop intrinsic.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D114998
Arnold Schwaighofer [Mon, 6 Dec 2021 19:01:13 +0000 (11:01 -0800)]
[coro async] Don't use lifetime.start based alloca localization for ABI.Async/ABI.Retcon
Infinite loops can lead to an IR representation where the lifetime.end
intrinsice is missing. The code to do lifetime based optimization then
fails to see that an address escapes (is life) accross a supspend.
Eventually, we could detect such situations and disable it under more narrow
circumstances. For now, do the correct thing.
rdar://
83635953
Differential Revision: https://reviews.llvm.org/D110949
Simon Pilgrim [Mon, 6 Dec 2021 19:45:40 +0000 (19:45 +0000)]
[X86] LowerRotate - fix assertion. NFC.
v32i16 rotation lowering is only lowered on non-BWI targets.
Balázs Kéri [Mon, 6 Dec 2021 17:16:02 +0000 (18:16 +0100)]
[clang][ASTImporter] Update lookup table correctly at deduction guides.
Declaration context of template parameters of a FunctionTemplateDecl
may be different for each one parameter if the template is a
deduction guide. This case is handled correctly after this change.
Reviewed By: martong
Differential Revision: https://reviews.llvm.org/D114418
Nick Desaulniers [Mon, 6 Dec 2021 19:11:19 +0000 (11:11 -0800)]
[clang][ARM] only check -mtp=cp15 for non-asm sources
This diagnostic is really to highlight lack of support for hard thread
pointers in post-RA instruction scheduling for non-armv6k+ targets;
something that isn't run for assembler sources.
Fixes: https://github.com/ClangBuiltLinux/linux/issues/1502
Link: https://lore.kernel.org/all/814585495.6773.1636629846970@jenkins.jenkins/
Reviewed By: ardb
Differential Revision: https://reviews.llvm.org/D114124
Nico Weber [Mon, 6 Dec 2021 19:24:01 +0000 (14:24 -0500)]
Revert "[gn build] (manually) port
4a16fe1369f3ab (debuginfod)"
This reverts commit
f0cda7155cdc3672a715eb84f03ea3461042e48f.
4a16fe1369f3ab got reverted in
f45c9c56c59f.
Noah Shutty [Mon, 6 Dec 2021 19:19:14 +0000 (19:19 +0000)]
Revert "[llvm] [Debuginfo] Debuginfod client library."
This reverts commit
4a16fe1369f3ab0e98261d4bd133034425d0523c because it
caused failures on Windows builds.
Aaron Ballman [Mon, 6 Dec 2021 19:12:54 +0000 (14:12 -0500)]
Fixing this test which failed due to different warnings
Arnold Schwaighofer [Mon, 6 Dec 2021 17:23:50 +0000 (09:23 -0800)]
[coro async] Disable lifetime.start sinking for ABI::Async and ABI::Retcon
It does not handle loops correctly i.e it moves the lifetime.start
intrinsic into a loop rendering the stack object as not alive for part
of the loop.
```
entry:
%obj = alloca i8
lifetime.start(%obj)
br loop
loop:
coro.suspend()
escape(%obj)
cond_br %cond, label %exit, label loop
br loop
exit:
lifetime.end(%obj
```
After sinking:
```
entry:
%obj = alloca i8
br loop
loop:
coro.suspend()
lifetime.start(%obj)
escape(%obj)
cond_br %cond, label %exit, label loop
br loop
exit:
lifetime.end(%obj
```
rdar://
83411917
Differential Revision: https://reviews.llvm.org/D110953
Aaron Ballman [Mon, 6 Dec 2021 18:51:26 +0000 (13:51 -0500)]
Fix a failing test case after
6c75ab5f66b403f7ca67e86aeed3a58abe10570b
The test is the same whether it's testing _BitInt or _ExtInt, so use
the type which is not deprecated.
Louis Dionne [Mon, 22 Nov 2021 21:44:50 +0000 (16:44 -0500)]
[libc++] Fix the return value of max_size()
I assume nobody ever uses std::string_view::max_size() outside of
testing. However, we should still return a value that is based on
something with a reasonable rationale. Previously, we would forget
to take into account the size of the character type stored in the
string, and this patch takes that into account.
Thanks to @mclow.lists for pointing out this issue.
Differential Revision: https://reviews.llvm.org/D114395
Alexey Bataev [Mon, 6 Dec 2021 16:32:15 +0000 (08:32 -0800)]
[SLP]Fix compiler crash when calculating extract cost for undefs.
Need to add an extra check for potential undef values in
computeExtractCost function to avoid compiler crash on casting to
instructon.
Differential Revision: https://reviews.llvm.org/D115162
Louis Dionne [Mon, 6 Dec 2021 18:44:15 +0000 (13:44 -0500)]
[libc++][NFC] Fix release note indentation
Florian Hahn [Mon, 6 Dec 2021 18:32:35 +0000 (18:32 +0000)]
[LV] Check VPValue operand instead of Cost::isUniformAfterVec (NFC).
ILV::scalarizeInstruction still uses the original IR operands to check
if an input value is uniform after vectorization.
There is no need to go back to the cost model to figure that out, as the
information is already explicit in the VPlan. Just check directly
whether the VPValue is defined outside the plan or is a uniform
VPReplicateRecipe.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D114253
Aaron Ballman [Mon, 6 Dec 2021 18:29:17 +0000 (13:29 -0500)]
Speculatively fix the LLDB build bots from
6c75ab5f66b403f7ca67e86aeed3a58abe10570b
It looks like some renames got missed.
Nico Weber [Mon, 6 Dec 2021 18:17:06 +0000 (13:17 -0500)]
[gn build] (manually) port
4a16fe1369f3ab (debuginfod)
Aaron Ballman [Mon, 6 Dec 2021 18:13:13 +0000 (13:13 -0500)]
Update the status of N2412 in C (we do not implement large parts of it)
Jonas Paulsson [Thu, 14 Oct 2021 18:10:47 +0000 (20:10 +0200)]
[SystemZ] Improve codegen for memset.
Memset with a constant length was implemented with a single store followed by
a series of MVC:s. This patch changes this so that one store of the byte is
emitted for each MVC, which avoids data dependencies between the MVCs. An
MVI/STC + MVC(len-1) is done for each block.
In addition, memset with a variable length is now also handled without a
libcall. Since the byte is first stored and then MVC is used from that
address, a length of two must now be subtracted instead of one for the loop
and EXRL. This requires an extra check for the one-byte case, which is
handled in a special block with just a single MVI/STC (like GCC).
Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D112004
Martin Probst [Fri, 3 Dec 2021 10:20:56 +0000 (11:20 +0100)]
clang-format: [JS] test case for numeric separators.
ES2021 allows numeric literals using `_` as a separator. This already
works, but had no test.
Differential Revision: https://reviews.llvm.org/D115147
Noah Shutty [Mon, 6 Dec 2021 17:35:48 +0000 (17:35 +0000)]
[llvm] [Debuginfo] Debuginfod client library.
This adds a Debuginfod client library which queries servers specified by the `DEBUGINFOD_URLS` environment variable for the debuginfo, executable, or a specified source file associated with a given build id.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D112758
Aaron Ballman [Mon, 6 Dec 2021 17:46:54 +0000 (12:46 -0500)]
Introduce _BitInt, deprecate _ExtInt
WG14 adopted the _ExtInt feature from Clang for C23, but renamed the
type to be _BitInt. This patch does the vast majority of the work to
rename _ExtInt to _BitInt, which accounts for most of its size. The new
type is exposed in older C modes and all C++ modes as a conforming
extension. However, there are functional changes worth calling out:
* Deprecates _ExtInt with a fix-it to help users migrate to _BitInt.
* Updates the mangling for the type.
* Updates the documentation and adds a release note to warn users what
is going on.
* Adds new diagnostics for use of _BitInt to call out when it's used as
a Clang extension or as a pre-C23 compatibility concern.
* Adds new tests for the new diagnostic behaviors.
I want to call out the ABI break specifically. We do not believe that
this break will cause a significant imposition for early adopters of
the feature, and so this is being done as a full break. If it turns out
there are critical uses where recompilation is not an option for some
reason, we can consider using ABI tags to ease the transition.
Balazs Benics [Mon, 6 Dec 2021 17:38:58 +0000 (18:38 +0100)]
[analyzer][solver] Fix assertion on (NonLoc, Op, Loc) expressions
Previously, the `SValBuilder` could not encounter expressions of the
following kind:
NonLoc OP Loc
Loc OP NonLoc
Where the `Op` is other than `BO_Add`.
As of now, due to the smarter simplification and the fixedpoint
iteration, it turns out we can.
It can happen if the `Loc` was perfectly constrained to a concrete
value (`nonloc::ConcreteInt`), thus the simplifier can do
constant-folding in these cases as well.
Unfortunately, this could cause assertion failures, since we assumed
that the operator must be `BO_Add`, causing a crash.
---
In the patch, I decided to preserve the original behavior (aka. swap the
operands (if the operator is commutative), but if the `RHS` was a
`loc::ConcreteInt` call `evalBinOpNN()`.
I think this interpretation of the arithmetic expression is closer to
reality.
I also tried naively introducing a separate handler for
`loc::ConcreteInt` RHS, before doing handling the more generic `Loc` RHS
case. However, it broke the `zoo1backwards()` test in the `nullptr.cpp`
file. This highlighted for me the importance to preserve the original
behavior for the `BO_Add` at least.
PS: Sorry for introducing yet another branch into this `evalBinOpXX`
madness. I've got a couple of ideas about refactoring these.
We'll see if I can get to it.
The test file demonstrates the issue and makes sure nothing similar
happens. The `no-crash` annotated lines show, where we crashed before
applying this patch.
Reviewed By: martong
Differential Revision: https://reviews.llvm.org/D115149
James Farrell [Mon, 6 Dec 2021 17:35:26 +0000 (17:35 +0000)]
Revert "Use VersionTuple for parsing versions in Triple, fixing issues that caused the original change to be reverted. This makes it possible to distinguish between "16" and "16.0" after parsing, which previously was not possible."
This reverts commit
50324670342d9391f62671685f4d6b4880a4ea9a.
Jonas Devlieghere [Mon, 6 Dec 2021 17:30:01 +0000 (09:30 -0800)]
Revert "[clang][DebugInfo] Allow function-local statics and types to be scoped within a lexical block"
This reverts commit
e403f4fdc88322201040f2bee7b328e8a78e2f7f because it
breaks TestSetData.py on GreenDragon:
https://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/39089/
Craig Topper [Mon, 6 Dec 2021 17:06:48 +0000 (09:06 -0800)]
[RISCV] Loosen some restrictions on lowering constant BUILD_VECTORs using vid.v.
The immediate size check on StepNumerator did not take into account
that vmul.vi does not exist. It also did not account for power of 2
constants that can be done with vshl.vi.
This patch fixes this by moving the conversion from mul to shift
further up. Then we can consider the immediates separately for MUL
vs SHL. For MUL I've allowed simm12 which requires a single addi
before a vmul.vx. For SHL I've allowed any uimm5 which works with
vshl.vi. We could relax these further in the future. This is a
starting point that allows us to emit the same number of instructions
we were already using for smaller numerators.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D115081
Joseph Huber [Mon, 6 Dec 2021 16:14:54 +0000 (11:14 -0500)]
[OpenMP] Make reduction functions SPMD compatible
Reduction functions were guarded before which was wrong, these are SPMD
compatible.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D115159
Joseph Huber [Mon, 6 Dec 2021 15:58:02 +0000 (10:58 -0500)]
[OpenMP][FIX] Invalidate the SPMDCompatibilityTracker explicitly
Before SPMDzation it was sufficient to add an incompatible instruction
to the SPMDCompatibilityTracker. However, now adding instructions means
they need guarding. As calls cannot be guarded in general we need to
explicitly prevent SPMD mode.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D115158
Evgeny Mandrikov [Mon, 6 Dec 2021 17:06:51 +0000 (18:06 +0100)]
Fix compilation of Google Test in C++20 mode
Without this patch when using CMAKE_CXX_STANDARD=20
and MSVC 19.30.30705.0 compilation of unit tests
fails with
llvm\utils\unittest\googlemock\include\gmock/gmock-actions.h(828): error C2039: 'result_of': is not a member of 'std'
Patch is taken from Google Test:
https://github.com/google/googletest/commit/
61f010d703b32de9bfb20ab90ece38ab2f25977f
Do not use std::result_of as it was removed in C++20.
Differential Revision: https://reviews.llvm.org/D115163
LLVM GN Syncbot [Mon, 6 Dec 2021 17:02:44 +0000 (17:02 +0000)]
[gn build] Port
c68f71eb37c2
spupyrev [Mon, 8 Nov 2021 15:02:33 +0000 (07:02 -0800)]
ext-tsp basic block layout
A new basic block ordering improving existing MachineBlockPlacement.
The algorithm tries to find a layout of nodes (basic blocks) of a given CFG
optimizing jump locality and thus processor I-cache utilization. This is
achieved via increasing the number of fall-through jumps and co-locating
frequently executed nodes together. The name follows the underlying
optimization problem, Extended-TSP, which is a generalization of classical
(maximum) Traveling Salesmen Problem.
The algorithm is a greedy heuristic that works with chains (ordered lists)
of basic blocks. Initially all chains are isolated basic blocks. On every
iteration, we pick a pair of chains whose merging yields the biggest increase
in the ExtTSP value, which models how i-cache "friendly" a specific chain is.
A pair of chains giving the maximum gain is merged into a new chain. The
procedure stops when there is only one chain left, or when merging does not
increase ExtTSP. In the latter case, the remaining chains are sorted by
density in decreasing order.
An important aspect is the way two chains are merged. Unlike earlier
algorithms (e.g., based on the approach of Pettis-Hansen), two
chains, X and Y, are first split into three, X1, X2, and Y. Then we
consider all possible ways of gluing the three chains (e.g., X1YX2, X1X2Y,
X2X1Y, X2YX1, YX1X2, YX2X1) and choose the one producing the largest score.
This improves the quality of the final result (the search space is larger)
while keeping the implementation sufficiently fast.
Differential Revision: https://reviews.llvm.org/D113424
Jon Chesterfield [Mon, 6 Dec 2021 16:56:13 +0000 (16:56 +0000)]
[openmp] Default to new rtl for amdgpu
Reverts D114965 as the compiler backend appears to be working again
Reviewed By: jhuber6
Differential Revision: https://reviews.llvm.org/D115157
Peter Waller [Mon, 6 Dec 2021 15:11:45 +0000 (15:11 +0000)]
[AArch64][SVE] Fix ICE extracting fixedvec from scalable load
f526c600c043 had a concern raised because of an invalid typesize request
on a scalable vector, which this patch addresses.
Prevent shouldReduceLoadWidth from attempting to query the bit size, and
add a regression test in sve-extract-fixed-vector.ll.
Differential Revision: https://reviews.llvm.org/D115156
Kazu Hirata [Mon, 6 Dec 2021 16:49:10 +0000 (08:49 -0800)]
[CodeGen] Use range-based for loops (NFC)
Jon Chesterfield [Mon, 6 Dec 2021 16:42:25 +0000 (16:42 +0000)]
[libomptarget] Add cmake variables to disable building the amdgpu or cuda plugins
Analogous to the controls on building device runtimes
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D115148
Jon Chesterfield [Mon, 6 Dec 2021 16:41:22 +0000 (16:41 +0000)]
[openmp] Run tests on both runtimes, independent of the default
Minor fix to the lit.cfg. Currently, nvptx runs the tests twice on the new runtime.
Soon, amdgpu will run them on the new runtime as well as the old.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D115150
Bardia Mahjour [Mon, 6 Dec 2021 16:22:25 +0000 (11:22 -0500)]
[VP] getVPMemoryOpCost interface
Added TTI queries for the cost of a VP Memory operation, and added Opcode,
DataType and Alignment to the hasActiveVectorLength() interface.
Reviewed By: Roland Froese
Differential Revision: https://reviews.llvm.org/D109416
Arthur O'Dwyer [Sun, 5 Dec 2021 15:08:05 +0000 (10:08 -0500)]
[libc++] Work around a Clang bug in transform_view, and regression-test.
Clang trunk rejects the new test case, but this is a Clang bug
(PR47414, 47509, 50864, 44833).
```
In module 'std' imported from /Users/aodwyer/llvm-project/libcxx/test/std/ranges/range.adaptors/range.transform/general.pass.cpp:17:
/Users/aodwyer/llvm-project/build2/include/c++/v1/__ranges/transform_view.h:85:44: error: constraints not satisfied for alias template 'range_reference_t' [with _Rp = const NonConstView]
regular_invocable<const _Fn&, range_reference_t<const _View>>
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/Users/aodwyer/llvm-project/build2/include/c++/v1/__ranges/transform_view.h:416:25: note: in instantiation of template class 'std::ranges::transform_view<NonConstView, (lambda at /Users/aodwyer/llvm-project/libcxx/test/std/ranges/range.adaptors/range.transform/general.pass.cpp:73:71)>' requested here
-> decltype( transform_view(_VSTD::forward<_Range>(__range), _VSTD::forward<_Fn>(__f)))
^
```
We can work around this by adding a layer of indirection: put the
problematic constraint into a named concept and Clang becomes more
amenable to SFINAE'ing instead of hard-erroring.
Drive-by simplify `range.transform/general.pass.cpp` to make it clearer
what it's actually testing in this area.
Differential Revision: https://reviews.llvm.org/D115116
Simon Moll [Mon, 6 Dec 2021 15:44:36 +0000 (16:44 +0100)]
Revert "[Clang] Ignore CLANG_DEFAULT_LINKER for custom-linker toolchains"
Reverted until all Toolchains are fixed for the new behavior.
This reverts commit
34a43f2115af79f896c889433c57f3b400e9f2c6.
Jon Chesterfield [Mon, 6 Dec 2021 15:26:17 +0000 (15:26 +0000)]
[openmp] Enable tests on new devicertl on amdgpu
Reviewed By: pdhaliwal
Differential Revision: https://reviews.llvm.org/D114891
Ties Stuij [Mon, 6 Dec 2021 15:03:14 +0000 (15:03 +0000)]
[ARM][clang] Add back branch protection tests
When committing the PACBTI-M frontend support
patch (https://reviews.llvm.org/D112421), the tests in
arm-invalid-branch-protection.c were failing on certain test setups, so it was
removed to make the llvm test suite pass. The fix is to require
arm-registered-target.
This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:
https://developer.arm.com/documentation/ddi0553/latest
Reviewed By: erichkeane
Differential Revision: https://reviews.llvm.org/D115141
Nikita Popov [Mon, 6 Dec 2021 14:59:28 +0000 (15:59 +0100)]
[llvm-c] Avoid use of deprecated APIs in unit tests
As pointed out in https://reviews.llvm.org/D114936#3173327,
unit tests were still using deprecated C APIs.
James Farrell [Wed, 1 Dec 2021 16:54:32 +0000 (16:54 +0000)]
Use VersionTuple for parsing versions in Triple, fixing issues that caused the original change to be reverted. This makes it possible to distinguish between "16" and "16.0" after parsing, which previously was not possible.
This reverts commit
40d5eeac6cd89a2360c3ba997cbaa816abca828c.
Differential Revision: https://reviews.llvm.org/D114885