nouveau: Delete the nouveau_compiler tool

It's TGSI only.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nouveau: Drop BuildUtil::Location

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nouveau: Drop BuildUtil::DataArray

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nouveau: Drop ConverterCommon::Subroutine

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nouveau: Drop tgsi support from nv50_ir_prog_info

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nouveau: Delete nv50_ir_from_tgsi.cpp

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nv50: Keep nir directly in nv50_program

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nvc0: Keep nir directly in nvc0_program

instead of under pipe_shader_state.

This makes it obvious that we never produce tgsi shaders since
c3cbe610 "nouveau: Delete the NV50_PROG_USE_TGSI env var."

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

zink: emit SpvCapabilitySampleMaskPostDepthCoverage with SpvExecutionModePostDepthCoverage

can't have one without the other

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24183>

zink: be even dumber about buffer refs when replacing storage

these extra checks can cause issues when multiple contexts and transfer
ops are involved

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24141>

nvc0: fix num_gprs for Volta+

Overallocating by 2 gprs for ugprs is a wild guess by me. It does make
sense though as each subgroup shares 64 ugprs and that's 2 per thread.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24261>

llvmpipe: enable system SVM

The API bits are already implemented in clover and rusticl and by
definition a CPU driver implements SVM.

This should allow anybody to work on proper SyCL/CHIP-SPV support for
rusticl running llvmpipe.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24092>

rusticl/mesa: make svm_migrate optional

It's just a hint and drivers might want to ignore implementing it for now.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24092>

intel/isl: Add a score for DG2_RC_CCS

This enables the DG2 render compression modifier in anv. When I tested
this against vkcube, I observed that the full resolve which happened at
the end of every frame was converted to a partial resolve, allowing the
framebuffer to retain compression.

According to Caleb Callaway's testing, enabling this modifier positively
impacts the FPS of the following game benchmarks:

 - Strange Brigade.vk-g6              +12.78%
 - Strange Brigade.dx12vk-g6          + 9.33%
 - Shadow of the Tomb Raider.vk-g6-lx + 2.37%
 - Dota 2 (replay Jul 2020).vk-g6     + 2.28%

Thanks to Felix Degrood for pointing out that Strange Brigade would
benefit from this optimization.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>

intel/isl: Move the Tile4 modifier score case down

Group modifiers by platform first, then the score. I find it easier to
read this way.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>

intel: Describe modifier compression with booleans

Replace the aux_usage field with two booleans: one for render
compression and one for media compression.

This more accurately describes how CCS_E is used on gfx12. On those
platforms, the FCV feature may be enabled or disabled, but ISL's
modifier table has been using the FCV aux-usage for every gfx12 render
compression modifier. Instead, set the newly-added render compression
boolean to true.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>

iris: Swap stencil and modifier aux assignment order

Makes the next patch clearer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>

hasvk: Delete modifier with aux code

Modifiers with compression are not supported.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>

crocus: Delete modifier with aux code

Modifiers with compression are not supported.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>

iris: Reduce accesses of mod_info->aux_usage

This field will be replaced in an upcoming patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>

anv: Reduce accesses of isl_mod_info->aux_usage

This field will be replaced in an upcoming patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>

anv: Handle explicit surface layout of DG2_RC_CCS

We're going to enable the DG2 modifier. Account for the reduced plane
count that exists with it.

Also add an assert to make it clearer that the aux in use is CCS.
Otherwise, it may not be obvious because of the generic compression
names being used here.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>

intel: Add and use isl_drm_modifier_get_plane_count

We're going to enable the DG2_RC_CCS modifier in anv. Add and use this
function to prepare for the new plane count that comes with that
modifier.

iris is left alone for now because it supports more modifiers than
isl_drm_modifier_get_score is aware of.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>

anv: Don't support ASTC images with modifiers

Before this change, anv_get_image_format_features2 reported support for
ASTC formats with any modifier (even those not supported by anv). But,
we didn't intend to support that compressed image format with modifiers.

With this change, the format feature function reports no support for
modifiers on ASTC-formatted images.

This prevents the next patch from causing assertion failures due to
unsupported modifiers.

Fixes: 355f3188438 ("anv: Allow transfer-only linear ASTC images")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>

iris: Remap DRM_FORMAT_MOD_INVALID more often during import

We'd eventually like to use an ISL helper that doesn't support
DRM_FORMAT_MOD_INVALID. Prepare for this by replacing the invalid value
with the modifier associated with the BO's tiling in more cases.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>

anv: use the correct GFX_VERx10 macro for WA

Fixes: 60b0d2c2cbea ("add required invalidate/flush for Wa_14014427904")
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23937>

anv: use the WA infrastructure where possible when generating state

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23937>

radeonsi: fix a CDNA regression breaking compute

reported internally

Fixes: 315231b5a519bdc14 - radeonsi: eliminate redundant compute SH register changes

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24169>

nir/print: print instr pass_flags

From time to time it can be helpful to "see" the pass_flags.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24234>

turnip: flush cache for dstBuffer in vkCmdCopyQueryPoolResults

There can be other writes to the dstBuffer gated by proper barriers
beforehand.

TEST=dEQP-VK.pipeline.*.timestamp.* with Venus on Turnip

Fixes: 487aa807bd1b ("tu: Rewrite flushing to use barriers")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24245>

ir2: Switch to nir_legacy

Addresses a2xx portion of #9051.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24118>

asahi: Advertise Z16_UNORM

This works (on the downstream kernel, anyway).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Execute preambles for background programs

This will be useful when spilling render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Offset clear colour uniform by 4

Frees up u0_u1 for a bindless base address which will make render target
spilling easier to implement.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Ignore spilled render targets for background load

Nothing to reload.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Permit meta shaders to use preambles

Preambles are occassionally useful with background programs.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Lower multisample image stores

These will be used for spilling multisampled render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Lower tilebuffer access for spilled RTs

Conceptually similar, we just don't have the tilebuffer available this time.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Extract some tilebuffer lowering code

In prep for spilling. No functional change.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Ignore spilled render targets with partial renders

Partial renders exist to the spill the tilebuffer to memory, there's nothing to
do if it's already spilled (and would just waste memory bandwidth and create a
feedback loop).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Ignore spilled render targets in EOT shaders

Regardless whether we implement Apple-style eMRT or something simpler, the EOT
shader isn't involved here.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Do not support masking with spilled RTs

Extra complexity for this interaction, not worth it until we have an actual use
case IMHO.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Add agx_tilebuffer_spills query

We can skip various work in the driver if we're not spilling render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Introduce concept of spilled render targets

To accommodate framebuffers which exceed tilebuffer limits, we'll need to spill
render targets to main memory. In effect, we need to emulate an immediate-mode
renderer for some render targets. This decision is made on a per-render target
basis. In our tilebuffer layout calculation, rather than asserting that all
render targets fit, introduce a notion of spilling.

This doesn't actually implement spilling -- it just pushes the assert failure
down to the users. But it's progress.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Extract sampler_view_for_surface

We'll reuse this logic for the spilled RT case.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Plumb in coverage mask

This is internally used by the hardware when writing to the tilebuffer. We need
to use it externally to spill multisample render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Require tag writes with side effects

Otherwise the fragment shader might be skipped entirely. (Possibly this is the
wrong approach to this though...)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Add simple image fencing pass

Minimum needed to pass CTS.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Implement fence_*_to_tex_agx intrinsics

We need these fencing intrinsics because our image caches aren't coherent with
memory. Furthermore, we need some sync intrinsics for imageblocks (which are
spicy images). These are a stub of what the final fragment shader interlock
implementation will look like, or what a real Metal-grade imageblock
implementation needs, but this is good enough for handling the sync requirements
with spilled render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Don't emit silly barriers

Trust in the scoped_barrier.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Emit global memory barriers for images

This is part of image atomics, since those go through the regular memory path.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Implement image_load

Texture loads can be reordered freely but image loads can't be (since there
could be writes). Implement image_load natively to avoid subtle problems with
CSE and scheduling.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Extract texture write mask handling

image_load will share the logic.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Add image_load opcode

This is equivalent to texture_load but cannot be reordered, since it might be
writeable.

It also sets bit 43. This needs more investigation, but it fixes
KHR-GLES31.core.shader_image_load_store.basic-glsl-misc-fs. Some sort of cache
control bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi,agx: Fix txf sampler

Bizarrely, the clamps/wrap modes are respected so we need to set them
appropriately for correct out-of-bounds behaviour (returning all zero). That in
turn means we can't use whatever sampler is already there, instead we need to
allocate a dedicated sampler just for txf. Good news is we have an extra sampler
state register available for the purpose.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Lower buffer images

Similar to buffer reads, we need to implement buffer images as 2D images with
fixed width and some lowering code.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Lower image atomics

Lower image atomics to texel address loads, and lower texel address loads to
arithmetic and descriptor reads. This implements image atomics.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Extract texture_descriptor_ptr_for_* helpers

For implementing image_texel_address, when there's no point in creating an
internal texture instruction just to lower immediately.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Extract coords_for_buffer_texture helper

The mapping of 1D -> 2D coordinates for indexing into buffer textures (lowered
to fixed-width 2D images) will be shared between both texture load and image
store code paths, so pull it out.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Add interleave opcode

We'll use it for texture atomics.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Handle early_fragment_tests

Simply doing nothing fixes
dEQP-GLES31.functional.image_load_store.early_fragment_tests.*. However, we need
to actually insert the sample_mask instruction to make sure the shader runs at
all (I think), doing that fixes:

   KHR-GLES31.core.shader_image_load_store.basic-glsl-earlyFragTests

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Implement image barriers

Or cache flushes or whatever these actually are. Probably could be optimized
once we understand what the 4 individual instructions are actually doing. Fixes
dEQP-GLES31.functional.image_load_store.2d.qualifiers.*.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Wait for outstanding stores before barriers

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Handle frag side effects without render targets

We still need to insert our lowering code, though this case could probably be
optimized somehow. Fixes a massive number of KHR-GLES3 and KHR-GLES31 tests,
including
KHR-GLES31.core.shader_atomic_counters.advanced-usage-many-draw-calls2 and lots
of PBO tests.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Translate image_store from NIR

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Translate texture bindless handles

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Pack bindless textures

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Handle bindless properly for txs lowering

When I wrote this pass I mostly guessed what our bindless handles would look
like. Now that we know we can do it right.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Model texture bindless base

Extra source we need to implement bindless.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Add image write instruction

Model and pack what's in the hardware for this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Generalize texture/PBE packing

For the generic image write instruction we'll want the full forms of these
fields.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Lower image size to txs

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Legalize image LODs to be 16-bit

Required by the hardware. Do it in NIR so we can optimize the conversion.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Use nir_lower_robust_access

This makes images robust as required by the OpenGL ES spec.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Extend PBE packing for image support

We need to support arrayed images and sRGB images, which are hardware. For
atomics, we need to pack the augmented software data structure. Finally, we need
to support buffer images. Like their texture counterparts, these get lowered to
2D images.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Augment PBE descriptor for software access

For implementing image atomics (and multisample image writes), we need
information about the image layout in the shader. It's a lot nicer to determine
the image layouts on the CPU (where we have ail) and stash the results in the
PBE descriptor, where we have a convenient hole to do so, rather than trying to
do all the layout calculations on the GPU on the fly. Add a data structure that
the driver will fill out and the image atomic lowering will consider as part of
the hardware.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Add a shared library interface for decode

Add a simple API so that decode can be used as a shared library by the
Python hypervisor. Note that this is not thread-safe. If we ever want to
use this in other contexts with thread safety, it will need a refactor
(along with the core decode code anyway).

Signed-off-by: Asahi Lina <lina@asahilina.net>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: decode: Add a function to construct decode_params from a chip_id

Should be useful on macOS later to properly support detecting the right
GPU, but for now just hardcode T8103/G13G.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: decode: Refactor to always copy GPU mem to local buffers

We want to plug this library into the hypervisor, but there we don't
have all GPU memory already mapped in our address space. Refactor the
GPU mem read function to always allocate local buffers and copy in the
data there.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: wrap: Handle freeing shmems

Needed for some Metal demos that end up creating multiple queues.

This is still definitely broken/not fully correct, but it at least
gets things working for those.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Add extra CDM header block for G14X

Looks like we finally found our first properly divergent codepath.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: decode: Add a params argument to pass through

Sooner or later we were going to need divergent codepaths in decode, and
it looks like now is the time. Add a `params` typedef and pass it
through all the decoder callbacks. This is an alias for
drm_asahi_params_global, but use a typedef so we can change that later
without changing dozens of instances.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Fix bogus assert

Dolphin uses all the uniforms.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Reduce un/packs with mem access lowering

Often not needed and makes the NIR harder to read.

shader-db is noise.

total instructions in shared programs: 1752712 -> 1752688 (<.01%)
instructions in affected programs: 8338 -> 8314 (-0.29%)
helped: 21
HURT: 8
Inconclusive result (%-change mean confidence interval includes 0).

total bytes in shared programs: 11943572 -> 11943434 (<.01%)
bytes in affected programs: 56716 -> 56578 (-0.24%)
helped: 21
HURT: 8
Inconclusive result (%-change mean confidence interval includes 0).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Vectorize 16-bit parallel copies

If we have two 16-bit copies to/from adjacent 16-bit registers, we can instead
use a single 32-bit copy from the 32-bit register pair. Since 32-bit integer
arithmetic is (almost) as efficient as 16-bit on AGX, this (almost) doubles
performance of affected parallel copies.

total instructions in shared programs: 1788606 -> 1788301 (-0.02%)
instructions in affected programs: 17057 -> 16752 (-1.79%)
helped: 150
HURT: 0
Instructions are helped.

total bytes in shared programs: 12196492 -> 12194662 (-0.02%)
bytes in affected programs: 122894 -> 121064 (-1.49%)
helped: 150
HURT: 0
Bytes are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Try to allocate phi sources with loop phis

total instructions in shared programs: 1788666 -> 1788606 (<.01%)
instructions in affected programs: 7953 -> 7893 (-0.75%)
helped: 29
HURT: 0
Instructions are helped.

total bytes in shared programs: 12196852 -> 12196492 (<.01%)
bytes in affected programs: 53908 -> 53548 (-0.67%)
helped: 29
HURT: 0
Bytes are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Try to allocate phi sources with phis

Not meaningfully using more registers since this is just about how we assign
registers after fixing the maximum # of registers used (note that thread count
is unaffected).

total instructions in shared programs: 1790901 -> 1788666 (-0.12%)
instructions in affected programs: 230680 -> 228445 (-0.97%)
helped: 681
HURT: 2
Instructions are helped.

total bytes in shared programs: 12210266 -> 12196852 (-0.11%)
bytes in affected programs: 1634100 -> 1620686 (-0.82%)
helped: 682
HURT: 2
Bytes are helped.

total halfregs in shared programs: 532130 -> 532218 (0.02%)
halfregs in affected programs: 848 -> 936 (10.38%)
helped: 3
HURT: 13
Halfregs are HURT.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Try to allocate phis compatibly with sources

All shaders affected for thread count are in pubg... by chance the allocation
before used fewer registers than the calculated register demand (I guess because
we're conservative with our vector handling) and so got lucky and got higher
thread count. That shader is also helped massively for instructions.

The halfreg change doesn't matter -- we're not actually increasing register
demand, we're just being more choosy about our registers.

total instructions in shared programs: 1799738 -> 1790901 (-0.49%)
instructions in affected programs: 306081 -> 297244 (-2.89%)
helped: 889
HURT: 14
Instructions are helped.

total bytes in shared programs: 12263290 -> 12210266 (-0.43%)
bytes in affected programs: 2150966 -> 2097942 (-2.47%)
helped: 889
HURT: 14
Bytes are helped.

total halfregs in shared programs: 531981 -> 532130 (0.03%)
halfregs in affected programs: 1925 -> 2074 (7.74%)
helped: 0
HURT: 26
Halfregs are HURT.

total threads in shared programs: 18885184 -> 18884224 (<.01%)
threads in affected programs: 13440 -> 12480 (-7.14%)
helped: 0
HURT: 15

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

agx: Add try_coalesce_with helper

Common logic the next few patches will use to try to assign something to the
same register as something else. "If it's already been assigned a register and
that register is free now, use it, otherwise bail."

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Forbid 2D Linear with images

There's no known use case, so forbidding this reduces the combinatorics required
in the texture atomic lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Don't restrict sampler views

We now emulate an infinitely large binding table with bindless, so the sky is
the limit for this CAP. Note we still have the limit for samplers, so this
probably doesn't do anything for OpenGL.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Make clear the non-sRGBness of EOT images

For sRGB render targets, we encode sRGB when writing pixels into the tilebuffer
(in the fragment shader), not when writing out the image. When we actually write
out the tilebuffer to the image, we don't use the PBE's sRGB conversion, we just
bind it as a UNORM 8 image and blit the pre-transformed pixels.

We're about to add real sRGB support for the PBE, so make this linearization
explicit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Upload image descriptors

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Upload at most the max texture state registers

The rest are bindless now.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Add texture/image indexing lowering pass

Both textures and images share a unified indexing scheme in AGX. When binding
tables are used, they can be mapped to texture state registers. Otherwise, there
is bindless access available.

It would be nice to map OpenGL's binding table based textures and images to AGX
texture state registers 1:1. The problem is that OpenGL allows more combined
textures and images than we necessarily have texture state registers. So, we use
as many texture state registers as we can, and then we fallback on an internal
bindless scheme mapping an extended binding table.

Add and use a lowering pass to map all of the API-level texture/image indices to
either texture state registers or bindless handles as required.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Add agx_batch_track_image helper

Adapted from Panfrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Reallocate to set the writeable image flag

...If needed, for array images.

But avoid doing so for non-array images.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi: Mark writeable images as such

ail needs this information to select the appropriate layout.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

ail: Page-align layers for writable images

This appears to be necessary for PBE writes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

asahi,agx: Set coherency bit for clustered targets

We need to set a particular bit on atomics for them to be coherent across
clusters. Fixes atomics on G13X.

Setting this bit on the single-cluster G13G, on the other hand, wedges the GPU.
So best be careful ;-)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>