Yonggang Luo [Wed, 28 Jun 2023 04:37:46 +0000 (12:37 +0800)]
util: Remove redundant #if !defined(XF86_LIBC_H) in u_string.h
This is added in
3b5ee3d6de2c08faf69c701bf05d8f33ccd01502 but then dropped
in
fe14868d96d4820dba73c3a507d191b8a73c6870
So this is not needed anymore
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23897>
Yonggang Luo [Wed, 28 Jun 2023 04:35:14 +0000 (12:35 +0800)]
util: Remove redundant defined(_WIN32) in u_string.h
This defined(_WIN32) is nested in an "#ifdef _WIN32",
so it's duplicated
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23897>
Dave Airlie [Fri, 9 Jun 2023 06:19:05 +0000 (16:19 +1000)]
lavapipe: check sampler pointer before deref
This fixes the vulkan samples deferred demo from crashing in here.
Cc: mesa-stable
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23542>
Mike Blumenkrantz [Thu, 22 Jun 2023 15:16:10 +0000 (11:16 -0400)]
zink: get new bda when rebinding invalidated buffers
this otherwise yields a broken descriptor
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23803>
Mike Blumenkrantz [Wed, 21 Jun 2023 19:45:37 +0000 (15:45 -0400)]
zink: fix unbinding generated gs on real gs bind
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23803>
Mike Blumenkrantz [Wed, 21 Jun 2023 19:16:28 +0000 (15:16 -0400)]
zink: fix assert for inline uniform invalidation with generated gs bound
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23803>
Paulo Zanoni [Fri, 21 Apr 2023 23:26:37 +0000 (16:26 -0700)]
intel/isl: tile 64 calculations work with 1D surfaces
Depth/stencil surfaces cannot be linear but they can be 1D, so they
end up being tile64 when sparse (as we force every sparse resource to
be either tile64 or linear).
According to the "1D surfaces" page from BSpec, our driver treats 1D
surfaces as 2D surfaces with a height of 1 texel, since we don't
enable the corresponding bit from HAS_SLICE_CHICKEN7. And since we
support 2D surfaces, we should also support 1D.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22974>
Paulo Zanoni [Wed, 3 May 2023 21:54:55 +0000 (14:54 -0700)]
iris: also avoid isl_memcpy_linear_to_tiled for Tile64
Just like we avoid it for Tile4, avoid it for Tile64.
We can't easily notice this problem since Tile4 is preferred over
Tile64, but if we patch isl_surf_choose_tiling() to choose Tile64 over
Tile4, then we start getting more than 1600 failures in CI.
These are the two most common error messages:
../src/gallium/drivers/iris/iris_resource.c:2168: get_image_offset_el: Assertion `z0_el == 0 && a0_el == 0' failed.
../src/intel/isl/isl_tiled_memcpy.c:857: linear_to_tiled: Assertion `!"" "unsupported tiling"' failed.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22974>
Alyssa Rosenzweig [Tue, 27 Jun 2023 21:00:55 +0000 (17:00 -0400)]
broadcom/compiler: Use nir_steal_tex_src
It's great for passes like these. Noticed while in the area.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23895>
Alyssa Rosenzweig [Tue, 27 Jun 2023 21:02:50 +0000 (17:02 -0400)]
broadcom/compiler: Remove unused #define
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23895>
Alyssa Rosenzweig [Tue, 27 Jun 2023 21:21:56 +0000 (17:21 -0400)]
broadcom/compiler: Remove v3d_nir_lower_robust_access
Now unused.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23895>
Alyssa Rosenzweig [Tue, 27 Jun 2023 21:21:20 +0000 (17:21 -0400)]
broadcom/compiler: Use nir_lower_robust_access
The common code version, instead of the vendor version.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23895>
Alyssa Rosenzweig [Tue, 27 Jun 2023 20:29:55 +0000 (16:29 -0400)]
nir: Add nir_lower_robust_access pass
Add a pass for bounds checking UBOs, SSBOs, and images to implement robustness.
This pass is based on v3d_nir_lower_robust_access.c, with significant
modifications to be appropriate for common code. Notably:
* v3d-isms are removed.
* Stop generating invalid imageSize() instructions for cube maps, this
blows up nir_validate with asahi's lowerings.
* Logic to wrap an intrinsic in an if-statement is extracted in anticipation of
future robustness2 support that will reuse that code path for buffers.
* Misc cleanups to follow modern NIR best practice. This pass is noticeably
shorter than the original v3d version.
For future support of robustness2, I envision the booleans turning into tristate
enums.
There's a few more knobs added for Asahi's benefit. Apple hardware can do
imageLoad and imageStore to non-buffer images (only). There is no support for
image atomics. To handle, Asahi implements software lowering for buffer images
and for image atomics. While the hardware is robust, the software paths are not.
So we would like to use this pass to lower robustness for the software paths but
not the hardware paths.
Or maybe we want a filter callback?
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23895>
Iván Briano [Mon, 12 Jun 2023 23:38:31 +0000 (16:38 -0700)]
anv: flush data cache before emitting availability
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23814>
Kenneth Graunke [Thu, 15 Jun 2023 21:24:00 +0000 (14:24 -0700)]
intel/genxml: Update RENDER_SURFACE_STATE Fields
I went through the RENDER_SURFACE_STATE docs today and found a number
of fields that are simply gone, marked as "must be zero", or had their
enum meanings change. Update those here.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23684>
Kenneth Graunke [Wed, 28 Jun 2023 19:22:54 +0000 (12:22 -0700)]
intel/genxml: Fix gen_sort_tags.py to handle mbz/mbo
mbz and mbo are base types and not a structure to find as a dependency.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23684>
Kenneth Graunke [Thu, 15 Jun 2023 21:25:22 +0000 (14:25 -0700)]
isl: Don't set "Enable Unorm Path in Color Pipe" on Alchemist
This bit no longer exists and is marked MBZ. I assume that the
optimization is just permanently enabled; this was always a basically
a chicken bit.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23684>
Yonggang Luo [Thu, 29 Jun 2023 03:32:05 +0000 (11:32 +0800)]
broadcom: replace redefined ALIGN() macro with common util functions
`cl_aligned_packet_length()` expand literals, so use ALIGN_POT to compute it
at compile time.
`v3dv_AllocateMemory()` uses a 64-bit `allocationSize`, so use `align64()`.
`v3d_lower_nir()` uses a 32-bit `shared_size`, so use `align()`.
Extracted out of https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23932
for easier review.
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23938>
Eric Engestrom [Thu, 22 Jun 2023 16:46:28 +0000 (17:46 +0100)]
ci: split valve farm in two
There are two physical locations, so it makes sense to manage them
separately.
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23908>
Helen Koike [Thu, 29 Jun 2023 15:38:07 +0000 (12:38 -0300)]
ci: remove unused tag DEBIAN_X86_64_TEST_IMAGE_PATH
DEBIAN_X86_64_TEST_IMAGE_PATH is unused and
DEBIAN_X86_TEST_IMAGE_GL_PATH doesn't even exist, so remove it to avoid
confusion.
Signed-off-by: Helen Koike <helen.koike@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23939>
Christian Gmeiner [Thu, 29 Jun 2023 14:22:02 +0000 (16:22 +0200)]
etnaviv: make use nir_shader_clear_pass_flags(..)
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23931>
Christian Gmeiner [Wed, 21 Jun 2023 12:04:16 +0000 (14:04 +0200)]
nir/lower_amul: make use nir_shader_clear_pass_flags(..)
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23931>
Christian Gmeiner [Wed, 21 Jun 2023 12:02:57 +0000 (14:02 +0200)]
nir: add helper to clear all pass_flags
Will be used in different places so lets move it to a common place.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23931>
Eric Engestrom [Thu, 29 Jun 2023 17:06:31 +0000 (18:06 +0100)]
amd/ci: add another dEQP-VK.dynamic_rendering.primary_cmd_buff.basic.* flake
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
44643768
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23935>
Juston Li [Wed, 28 Jun 2023 20:25:57 +0000 (13:25 -0700)]
radv: fix incorrect size for primitives generated query
Primitives generated queries write 1 integer, the primitives-generated
count that is incremented every time a primitive emitted to that stream
reaches the transform feedback stage.
Fixes:
1ebf463a5a6 ("radv: implement VK_EXT_primitives_generated_query")
Signed-off-by: Juston Li <justonli@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23915>
Rohan Garg [Thu, 29 Jun 2023 13:02:59 +0000 (15:02 +0200)]
anv: move WA
1607854226 to use the WA infrastructure
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23929>
Mike Blumenkrantz [Wed, 28 Jun 2023 17:41:26 +0000 (13:41 -0400)]
lavapipe: handle multiview queries
the availability info has to be available for N bits of multiview when active
Reviewed-by: Juston Li <justonli@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23913>
Alyssa Rosenzweig [Tue, 27 Jun 2023 18:01:58 +0000 (14:01 -0400)]
nir/validate: Assert txf(_ms) matches dimension
We can't txf_ms on non-MS images and we can't txf on MS images. This would have
caught a regression on Asahi.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23892>
Georg Lehmann [Mon, 29 May 2023 11:52:12 +0000 (13:52 +0200)]
aco/optimizer: delete s_bitcmp optimization
This is now done in NIR.
No Foz-DB changes.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23298>
Georg Lehmann [Sat, 27 May 2023 13:31:07 +0000 (15:31 +0200)]
radv: set has_bit_test for aco
Foz-DB Navi21:
Totals from 15285 (11.52% of 132657) affected shaders:
VGPRs: 1019136 -> 1019000 (-0.01%); split: -0.02%, +0.01%
SpillSGPRs: 10889 -> 10909 (+0.18%)
SpillVGPRs: 901 -> 914 (+1.44%); split: -0.89%, +2.33%
CodeSize:
103578640 ->
103523220 (-0.05%); split: -0.08%, +0.03%
MaxWaves: 259782 -> 259820 (+0.01%)
Instrs:
19247383 ->
19223764 (-0.12%); split: -0.15%, +0.02%
Latency:
323877613 ->
323684655 (-0.06%); split: -0.10%, +0.04%
InvThroughput:
62505295 ->
62386541 (-0.19%); split: -0.21%, +0.02%
VClause: 366162 -> 366136 (-0.01%); split: -0.03%, +0.02%
SClause: 786505 -> 785527 (-0.12%); split: -0.22%, +0.10%
Copies: 1348920 -> 1349209 (+0.02%); split: -0.26%, +0.29%
Branches: 456331 -> 456324 (-0.00%); split: -0.01%, +0.00%
PreSGPRs: 849542 -> 849402 (-0.02%); split: -0.02%, +0.01%
PreVGPRs: 925300 -> 924678 (-0.07%)
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23298>
Georg Lehmann [Sat, 27 May 2023 13:28:10 +0000 (15:28 +0200)]
nir/opt_algebraic: combine bitz/bitnz
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23298>
Georg Lehmann [Sat, 27 May 2023 12:37:57 +0000 (14:37 +0200)]
aco: implement nir_op_bitz/bitnz
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23298>
Georg Lehmann [Sat, 27 May 2023 10:04:37 +0000 (12:04 +0200)]
nir/lower_bit_size: mask bitz/bitnz src1 like shifts
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23298>
Georg Lehmann [Sat, 27 May 2023 09:27:12 +0000 (11:27 +0200)]
nir: add single bit test opcodes
These directly map to amd's SALU s_bitcmp0/1.
For VALU we can use v_cmp_class_f32 if the second source is constant.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23298>
Patrick Lerda [Thu, 29 Jun 2023 10:52:04 +0000 (12:52 +0200)]
util/blitter: revert util_blitter_clear_buffer()
The previous change was creating a regression.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9252
Fixes:
23c003b88c54 ("util/blitter: fix util_blitter_clear_buffer() refcnt imbalance")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23923>
Daniel Stone [Thu, 29 Jun 2023 11:16:26 +0000 (12:16 +0100)]
ci/fdno: Pause a660 testing
The a660 machines are having a bunch of fastboot issues today. Pause it
until we can fix it.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23922>
Yonggang Luo [Wed, 28 Jun 2023 11:40:56 +0000 (19:40 +0800)]
intel/compiler: Switch to use nir_foreach_function_impl
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23920>
Yonggang Luo [Wed, 28 Jun 2023 11:22:35 +0000 (19:22 +0800)]
crocus: Switch to use nir_foreach_function_impl
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23920>
Yonggang Luo [Wed, 28 Jun 2023 14:12:38 +0000 (22:12 +0800)]
glsl: Remove the extra scope in gl_nir_link_uniforms.c
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23920>
Yonggang Luo [Wed, 28 Jun 2023 11:00:27 +0000 (19:00 +0800)]
glsl: Switch to use nir_foreach_function_impl from nir_foreach_function
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23920>
Yonggang Luo [Wed, 28 Jun 2023 11:22:21 +0000 (19:22 +0800)]
d3d12: Switch to use nir_foreach_function_impl
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23920>
Yonggang Luo [Wed, 28 Jun 2023 10:41:27 +0000 (18:41 +0800)]
asahi: Use nir_foreach_function_impl instead nir_foreach_function in function agx_nir_lower_zs_emit
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23920>
Yonggang Luo [Wed, 28 Jun 2023 11:09:24 +0000 (19:09 +0800)]
gallium/auxiliary: Switch to use nir_foreach_function_impl
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23920>
Corentin Noël [Tue, 27 Jun 2023 14:28:41 +0000 (16:28 +0200)]
nir/split_64bit_vec3_and_vec4: Use the right number of components
Always make sure to correctly deref and store a 64bits variable
from the right number of components.
This fixes the `spec@arb_enhanced_layouts@matching_fp64_types_`
piglit tests for virgl.
Corrects this validation issue:
```
decl_var INTERP_MODE_FLAT dvec2[] var_7@2
decl_var INTERP_MODE_FLAT dvec2[] var_7@3
...
vec1 32 ssa_302 = deref_var &var_7@2 (function_temp dvec2[])
vec1 32 ssa_303 = deref_var &var_7@3 (function_temp dvec2[])
vec1 32 ssa_304 = deref_array &(*ssa_302)[ssa_301] (function_temp dvec2) /* &var_7@2[ssa_301] */
vec1 32 ssa_305 = deref_array &(*ssa_303)[ssa_301] (function_temp dvec2) /* &var_7@3[ssa_301] */
vec1 64 ssa_306 = mov ssa_110.z
intrinsic store_deref (ssa_305, ssa_306) (wrmask=x, access=0)
error: instr->num_components == glsl_get_vector_elements(dst->type) (../src/compiler/nir/nir_validate.c:632)
vec4 64 ssa_111 = vec4 ssa_14, ssa_13, ssa_12, ssa_109
vec1 32 ssa_307 = load_const (0x00000000 = 0.000000)
vec1 32 ssa_308 = iadd ssa_307, ssa_61
vec1 32 ssa_309 = deref_var &var_7@2 (function_temp dvec2[])
vec1 32 ssa_310 = deref_var &var_7@3 (function_temp dvec2[])
vec1 32 ssa_311 = deref_array &(*ssa_309)[ssa_308] (function_temp dvec2) /* &var_7@2[ssa_308] */
vec1 32 ssa_312 = deref_array &(*ssa_310)[ssa_308] (function_temp dvec2) /* &var_7@3[ssa_308] */
vec1 64 ssa_313 = mov ssa_111.w
intrinsic store_deref (ssa_312, ssa_313) (wrmask=, access=0)
error: (nir_intrinsic_write_mask(instr) & ~component_mask) == 0 (../src/compiler/nir/nir_validate.c:803)
```
Fixes:
496fd59d711b9a0744878918caeeaafb961e3deb (add pass to split 64 bit vec3/4 variable access)
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23880>
Lionel Landwerlin [Sun, 25 Jun 2023 16:02:57 +0000 (19:02 +0300)]
Revert "isl: Set Depth to array len for 3D storage images"
This reverts commit
7e1b62ea5b35d7bd0245d10c8667184a7a6a4882.
This is now following the PRMs, RENDER_SURFACE_STATE Depth should be
programmed to the base level depth value.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23868>
Lionel Landwerlin [Sun, 25 Jun 2023 15:59:13 +0000 (18:59 +0300)]
anv: implement storage image depth query using descriptor buffer read
The HW not returning the depth value we would like for
VK_EXT_sliced_view_of_3d, we can pull that value by reading the
RENDER_SURFACE_STATE struct directly.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23868>
Iago Toral Quiroga [Thu, 29 Jun 2023 08:09:33 +0000 (10:09 +0200)]
v3dv: fix blit path for compressed image to buffer copies
Here we were aliasing the full compressed image with an uncompressed
format that we would then use for sampling during the blit copy. This
had 2 issues:
1. Uncompressed image views would have smaller dimensions than the
compressed image, and thus, would also have less mip levels.
2. When sampling from smaller mip levels, the hw internally computes
the size of the mip level from the size of level 0, which then uses
to interpret the texture coordinates, but for some texture sizes
this size would not be an exact match for compressed and uncompressed
views.
To fix this, we modify the aliasing technique to only alias the
miplevel selected in the copy as a level 0 image and we ensure the
slice 0 for that image matches exactly the slice description of the
aliased mip level in the original image.
Fixes all test failures in
dEQP-VK.api.copy_and_blit.core.image_to_buffer.*
for compressed formats when we forcefully disable the TLB path.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23919>
Iago Toral Quiroga [Thu, 29 Jun 2023 08:07:45 +0000 (10:07 +0200)]
v3dv: use div_round_up for division by block size
We always want to round up when we divide by the block size.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23919>
Lionel Landwerlin [Tue, 27 Jun 2023 13:54:04 +0000 (16:54 +0300)]
anv: look into batch bo reloc list looking for BOs to decode
On DG2 I ran into a case where the surface state was not being decoded
with INTEL_DEBUG=bat. This is because the surface states are not part
of a state pool there anymore. Instead BO are allocate manually and
placed in vma heap.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
96c33fb027 ("anv: enable direct descriptors on platforms with extended bindless offset")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23891>
Yonggang Luo [Wed, 28 Jun 2023 08:19:47 +0000 (16:19 +0800)]
clang-format: Add nir_foreach_function_impl into src/.clang-format
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23903>
Yonggang Luo [Wed, 28 Jun 2023 10:21:31 +0000 (18:21 +0800)]
treewide: Switch to use nir_foreach_function_with_impl when possible
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23903>
Yonggang Luo [Wed, 28 Jun 2023 13:28:00 +0000 (21:28 +0800)]
clang-format: Add nir_foreach_function_with_impl into src/.clang-format
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23903>
Yonggang Luo [Wed, 28 Jun 2023 10:20:40 +0000 (18:20 +0800)]
nir: Split macro nir_foreach_function_with_impl out of nir_foreach_function_impl
This macro nir_foreach_function_with_impl can be used when func and func->impl are both accessed in
foreach loop
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23903>
Erik Faye-Lund [Fri, 16 Jun 2023 17:43:30 +0000 (19:43 +0200)]
nir: use imm-helpers
We have to use 1ull instead of 1u because MSVC is stupid...
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 17:43:19 +0000 (19:43 +0200)]
gallium: use imm-helpers
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 17:43:06 +0000 (19:43 +0200)]
etnaviv: use imm-helpers
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 17:40:57 +0000 (19:40 +0200)]
amd: use imm-helpers
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 13:54:36 +0000 (15:54 +0200)]
mesa/st: use imm-helpers
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 13:48:48 +0000 (15:48 +0200)]
hasvk: use imm-helpers
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 13:45:17 +0000 (15:45 +0200)]
anv: use imm-helpers
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 13:38:39 +0000 (15:38 +0200)]
intel: use imm-helpers
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 13:28:17 +0000 (15:28 +0200)]
vc4: use imm-helpers
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 13:23:33 +0000 (15:23 +0200)]
radeonsi: use imm-helpers
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 13:08:45 +0000 (15:08 +0200)]
d3d12: use imm-helpers
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 13:21:45 +0000 (15:21 +0200)]
r600/sfn: use imm-helpers
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 12:35:12 +0000 (14:35 +0200)]
freedreno: use imm-helpers
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Thu, 15 Jun 2023 18:20:41 +0000 (20:20 +0200)]
pan: use imm-helpers
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Thu, 15 Jun 2023 14:26:12 +0000 (16:26 +0200)]
v3dv: use imm-helpers
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Thu, 15 Jun 2023 14:16:33 +0000 (16:16 +0200)]
broadcom/compiler: use imm-helpers
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 10:51:36 +0000 (12:51 +0200)]
vulkan: avoid needless constant-folding
While we're at it, also switch to the nir_f{add,mul}_imm helpers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Fri, 16 Jun 2023 13:51:26 +0000 (15:51 +0200)]
mesa/st: use nir_ineg
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Erik Faye-Lund [Thu, 15 Jun 2023 19:34:07 +0000 (21:34 +0200)]
microsoft/compiler: use nir_imm_zero
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
Yonggang Luo [Sun, 25 Jun 2023 02:06:37 +0000 (10:06 +0800)]
mapi: Remove dead struct _glapi_function in glapi/glapi_getproc.c
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23879>
Yonggang Luo [Sun, 25 Jun 2023 02:04:42 +0000 (10:04 +0800)]
mapi: Merge get_static_proc_address into _glapi_get_proc_address
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23879>
Yonggang Luo [Fri, 23 Jun 2023 04:50:35 +0000 (12:50 +0800)]
mapi: Style fixes in glapi/glapi_getproc.c
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23879>
Yonggang Luo [Mon, 19 Jun 2023 19:36:31 +0000 (03:36 +0800)]
util: sizeof bucket are always 32bit width, use align instead align64
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23732>
Yonggang Luo [Mon, 19 Jun 2023 19:37:04 +0000 (03:37 +0800)]
util: Do not use align64 over unsigned int in register_allocate.c
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23732>
Yonggang Luo [Mon, 19 Jun 2023 19:12:51 +0000 (03:12 +0800)]
util: Replace the usage of redundant u_align_u32 with align and remove u_align_u32
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23732>
Yonggang Luo [Mon, 19 Jun 2023 19:11:40 +0000 (03:11 +0800)]
util: Getting align and align64 consistence with ALIGN
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23732>
Yonggang Luo [Tue, 20 Jun 2023 01:49:10 +0000 (09:49 +0800)]
util: use uint32_t instead of unsigned in bitscan.h
uint32_t is more exact than unsigned for these functions
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23732>
Yonggang Luo [Tue, 20 Jun 2023 01:48:26 +0000 (09:48 +0800)]
util: Add function util_is_power_of_two_nonzero64 in bitscan.h
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23732>
Donald Robson [Fri, 12 May 2023 08:35:12 +0000 (09:35 +0100)]
pvr: Rename rogue_fw.xml -> rogue_kmd_stream.xml.
The UMD does not care if firmware is used, and the current name isn't
very informative either.
Signed-off-by: Donald Robson <donald.robson@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23872>
Matt Coster [Thu, 18 Aug 2022 15:21:38 +0000 (16:21 +0100)]
pvr: Rename transfer 3D heap to transfer frag heap
This better matches the naming throughout the rest of the driver.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23872>
Sarah Walker [Fri, 14 Oct 2022 13:06:15 +0000 (14:06 +0100)]
pvr: Merge main and extension command streams
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23872>
Sarah Walker [Tue, 18 Oct 2022 13:20:52 +0000 (14:20 +0100)]
pvr: Rename heap reserved area to static data carveout
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23872>
Sarah Walker [Tue, 30 Aug 2022 14:23:47 +0000 (15:23 +0100)]
pvr: use pvr_csb_pack() to setup CR_FB_CDC_ZLS
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23872>
Sarah Walker [Tue, 23 Aug 2022 09:50:37 +0000 (10:50 +0100)]
pvr: Fragment register fb_cdc_zls is feature dependent
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23872>
Prodea Alexandru-Liviu [Tue, 27 Jun 2023 17:32:57 +0000 (17:32 +0000)]
microsoft/clc: Don't build compiler test if build-tests is false
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8161
Cc: mesa-stable
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23890>
Sil Vilerino [Wed, 28 Jun 2023 15:22:11 +0000 (11:22 -0400)]
d3d12: Fix usage of D3D12_VIDEO_ENCODER_RATE_CONTROL_FLAG, was using D3D12_VIDEO_ENCODER_SUPPORT_FLAG wrongly instead
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23904>
Sil Vilerino [Wed, 28 Jun 2023 14:14:11 +0000 (10:14 -0400)]
d3d12: Only set reduced_tx_set when supported by D3D12 caps (no libva caps for reduced_tx_set to map to)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23904>
Sil Vilerino [Wed, 28 Jun 2023 13:48:18 +0000 (09:48 -0400)]
d3d12: Correct tx_mode_support reporting as specified in libva spec
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23904>
Yonggang Luo [Fri, 23 Jun 2023 12:31:00 +0000 (20:31 +0800)]
compiler: set alignment=1 by default for handling empty struct/interface in glsl_types.cpp
When there is no elements in struct/interface, the alignment of it should be 1 instead of 0.
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23841>
Joshua Ashton [Tue, 27 Jun 2023 16:02:09 +0000 (17:02 +0100)]
radv: Do not enable robustness for push constants with robustBufferAccess2
There is no spec text requiring this behaviour, it is only for buffers.
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23885>
Caio Oliveira [Wed, 21 Jun 2023 23:58:00 +0000 (16:58 -0700)]
nir/print: Print more representations in load_const
In addition to the hexadecimal and float (when applicable), print the
signed and unsigned representations. Representations may be omitted based
on information about the value:
- If gather types has unambiguous information, we use it;
- Float is omitted for 8 bit values;
- Signed decimal is omitted for positive values;
- Unsigned decimal is omitted for small values (representation is same as hex);
Note for now the "terse form" that appear in SSA uses is unchaged.
Based on a patch by Mike Blumenkrantz.
Examples:
```
// Just used as float. Omitted decimals.
vec4 32 ssa_81 = load_const (0x3f800000, 0x3f800000, 0x3e4ccccd, 0x3f800000) = (1.000000, 1.000000, 0.200000, 1.000000)
vec1 32 ssa_28 = load_const (0x3e4ccccd = 0.200000)
// Just a small integer. Omitted float and decimal.
vec1 32 ssa_45 = load_const (0x00000001)
// Larger positive integers. Omitted float.
vec1 32 ssa_39 = load_const (0x00002000 = 8192)
vec1 32 ssa_30 = load_const (0x000000ff = 255)
vec1 32 ssa_28 = load_const (0x00000010 = 16)
// Integers with negative values.
load_const (0xff = -1 = 255)
load_const (0xff80 = -128 = 65408)
load_const (0xffff = -1 = 65535)
// Same value, in the first case we know is used as an integer.
load_const (0xffffffe0 = -32 =
4294967264)
load_const (0xffffffe0 = -nan = -32 =
4294967264)
```
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
Caio Oliveira [Tue, 13 Jun 2023 04:59:34 +0000 (21:59 -0700)]
nir/print: Use src_type when printing consts in SSA uses
If the src_type is not available, untie by looking at the results from
nir_gather_ssa_types(). If that is ambiguous, just pick uint.
Now in print_const_from_load() when the type is invalid, print the full
constant form (with both padded hex and float); when the passed type
is valid, print the terse form based on it.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
Caio Oliveira [Tue, 13 Jun 2023 04:58:19 +0000 (21:58 -0700)]
nir: Extract logic to get dest and srcs types from intrinsic
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
Caio Oliveira [Tue, 13 Jun 2023 04:58:43 +0000 (21:58 -0700)]
nir: Make a const-friendly way to get the offset_src and arrayed_io_src from intrinsic
The existing helper returns a `nir_src *` so expects a non-const instr.
We plan to use this function in queries that don't modify the shader, so
create (and use internally) a variant that returns the index instead.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
Caio Oliveira [Sat, 10 Jun 2023 02:55:49 +0000 (19:55 -0700)]
nir/print: Make NIR_DEBUG=print_consts behavior the default
Now there's a NIR_DEBUG=print_no_inline_consts to omit them.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
Caio Oliveira [Sat, 10 Jun 2023 00:40:58 +0000 (17:40 -0700)]
nir/print: Improve NIR_PRINT=print_consts by using nir_gather_ssa_types()
The two representations are *always* used for `load_const`, but when
inlining the value as SSA source, use just a single terse
representation.
The choice between integer or float is based on the result of
nir_gather_ssa_types(), with a bias for integer when in doubt.
Also remove extra comment `/* */` syntax since the value is already
enclosed by parenthesis.
---
For illustration, here's some instructions from crucible test
func.shader.averageRounded.uint64_t with NIR_DEBUG=print_consts:
BEFORE:
```
vec1 32 con ssa_23 = load_const (0xfffffffc = -nan)
vec1 32 div ssa_24 = iand ssa_13, ssa_23 /*(0xfffffffc = -nan)*/
vec1 32 con ssa_25 = load_const (0x00000024 = 0.000000)
vec1 32 con ssa_26 = intrinsic load_ubo (ssa_1 /*(0x00000002 = 0.000000)*/, ssa_25 /*(0x00000024 = 0.000000)*/) (access=0, align_mul=
1073741824, align_offset=36, range_base=0, range=-1)
vec1 32 con ssa_27 = load_const (0x00000008 = 0.000000)
vec1 32 con ssa_28 = load_const (0x00000007 = 0.000000)
vec1 32 con ssa_29 = iand ssa_4.y, ssa_1 /*(0x00000002 = 0.000000)*/
vec1 32 con ssa_30 = ishl ssa_29, ssa_28 /*(0x00000007 = 0.000000)*/
vec1 32 con ssa_31 = load_const (0x7b000808 =
664776890994587263929995856502063104.000000)
vec1 32 con ssa_32 = ior ssa_31 /*(0x7b000808 =
664776890994587263929995856502063104.000000)*/, ssa_30
```
AFTER:
```
vec1 32 con ssa_23 = load_const (0xfffffffc = -nan)
vec1 32 div ssa_24 = iand ssa_13, ssa_23 (0xfffffffc)
vec1 32 con ssa_25 = load_const (0x00000024 = 0.000000)
vec1 32 con ssa_26 = intrinsic load_ubo (ssa_1 (0x2), ssa_25 (0x24)) (access=0, align_mul=
1073741824, align_offset=36, range_base=0, range=-1)
vec1 32 con ssa_27 = load_const (0x00000008 = 0.000000)
vec1 32 con ssa_28 = load_const (0x00000007 = 0.000000)
vec1 32 con ssa_29 = iand ssa_4.y, ssa_1 (0x2)
vec1 32 con ssa_30 = ishl ssa_29, ssa_28 (0x7)
vec1 32 con ssa_31 = load_const (0x7b000808 =
664776890994587263929995856502063104.000000)
vec1 32 con ssa_32 = ior ssa_31 (0x7b000808), ssa_30
```
and some instructions from crucible test func.gs.basic with NIR_DEBUG=print_consts,
now showing float representation being selected:
BEFORE:
```
vec4 32 ssa_10 = load_const (0x3e4ccccd, 0x3e4ccccd, 0x00000000, 0x00000000) = (0.200000, 0.200000, 0.000000, 0.000000)
vec4 32 ssa_9 = intrinsic load_deref (ssa_42) (access=0)
vec4 32 ssa_11 = fadd ssa_9, ssa_10 /*(0x3e4ccccd, 0x3e4ccccd, 0x00000000, 0x00000000) = (0.200000, 0.200000, 0.000000, 0.000000)*/
```
AFTER:
```
vec4 32 ssa_10 = load_const (0x3e4ccccd, 0x3e4ccccd, 0x00000000, 0x00000000) = (0.200000, 0.200000, 0.000000, 0.000000)
vec4 32 ssa_9 = intrinsic load_deref (ssa_42) (access=0)
vec4 32 ssa_11 = fadd ssa_9, ssa_10 (0.200000, 0.200000, 0.000000, 0.000000)
```
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>
Caio Oliveira [Sat, 10 Jun 2023 02:18:03 +0000 (19:18 -0700)]
nir: Allow nir_gather_ssa_types() to ignore regs instead of assert
If we infer a type for a reg, just ignore and keep going. This will allow
to use this pass even when registers are present.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23562>