Yang Xiwen [Sat, 1 Apr 2023 11:17:36 +0000 (19:17 +0800)]
arm: histb: hi3798mv200: add initial support for Hi3798MV200 HC2910-2AGHD05 board
A board with Hi3798MV200 SoC and various peripherals. Details are in the
board README.md.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Yang Xiwen [Sat, 1 Apr 2023 11:17:35 +0000 (19:17 +0800)]
dt-binding: histb-clock: add clocks definition for Hi3798MV200
These clocks are found on Hi3798MV200
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Yang Xiwen [Sat, 1 Apr 2023 11:17:34 +0000 (19:17 +0800)]
mmc: hi6220_dw_mmc: add compatible for HC2910 support
It adds compatible "hisilicon,hi3798mv200-dw-mshc" for HC2910 SoC
Hi3798MV200 to probe this mmc driver.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Yang Xiwen [Sat, 1 Apr 2023 11:17:33 +0000 (19:17 +0800)]
arm: add support for Hisilicon HiSTB family SoCs
First supported chip is hi3798mv200 (which is similar to Hi3798cv200
used by poplar).
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Tom Rini [Tue, 4 Apr 2023 15:47:25 +0000 (11:47 -0400)]
arm: Remove omap5_uevm board
This platform is unsupported by TI and was never widely distributed. As
this is untested for a long while and missing some DM conversions,
remove it and related device tree files.
Signed-off-by: Tom Rini <trini@konsulko.com>
Nitin Yadav [Thu, 6 Apr 2023 07:59:36 +0000 (13:29 +0530)]
arm: mach-k3: Workaround errata ID i2331
Errata doc: https://www.ti.com/lit/pdf/sprz457
Errata ID i2331 CPSW: Device lockup when reading CPSW registers
Details: A device lockup can occur during the second read of any CPSW
subsystem register after any MAIN domain power on reset (POR). A MAIN
domain POR occurs using the hardware MCU_PORz signal, or via software
using CTRLMMR_RST_CTRL.SW_MAIN_POR or CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR.
After these resets, the processor and internal bus structures may get
into a state which is only recoverable with full device reset using
MCU_PORz.
Due to this errata, Ethernet boot should not be used on this device.
Workaround(s): To avoid the lockup, a warm reset should be issued after
a MAIN domain POR and before any access to the CPSW registers. The warm
reset realigns internal clocks and prevents the lockup from happening.
Workaround above errata by calling do_reset() in case of cold boot in
order to trigger warm reset. This needs enabling SYSRESET driver in R5
SPL to enable TI SCI reset driver.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Kishon Vijay Abraham I [Mon, 10 Apr 2023 06:10:15 +0000 (11:40 +0530)]
board: ti: j721s2: Add support to detect daughtercards
Add support to detect daughtercards (GESI Ethernet card) in-order
to set the MAC address of the main CPSW2G interface.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Kishon Vijay Abraham I [Tue, 11 Apr 2023 09:48:37 +0000 (15:18 +0530)]
configs: j7200_evm_a72: Enhance bootcmd to configure ethernet PHY
Update the default BOOTCOMMAND to provide an automatic and easier way
to configure ethernet PHY before loading the firmware.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Frank Wunderlich [Tue, 11 Apr 2023 15:19:47 +0000 (17:19 +0200)]
configs: change bpi-r3 to board specific dts and change prompt
Use own devicetree for the board and change the prompt.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Daniel Golle [Tue, 11 Apr 2023 15:19:46 +0000 (17:19 +0200)]
board: mediatek: add Bananapi-R3 devicetree
Add board specific devicetree for Bananapi R3 SBC.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Daniel Golle [Wed, 12 Apr 2023 20:36:43 +0000 (21:36 +0100)]
pinctrl: mediatek: set R1/R0 in case pullen/pullsel succeeded
Commit
dafe0fbfb0f3 ("pinctrl: mediatek: rewrite mtk_pinconf_set and
related functions") changed the logic deciding to set R0 and R1
registers for V1 devices.
Before:
/* Also set PUPD/R0/R1 if the pin has them */
err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup);
if (err != -EINVAL) {
mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0);
mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1);
}
After:
/* try pupd_r1_r0 if pullen_pullsel return error */
err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup,
val);
if (err)
return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable,
pullup, val);
Tracing mtk_pinconf_bias_set_pullen_pullsel shows that the function
always either returns 0 in case of success or -EINVAL in case any error
has occurred. Hence the logic responsible of the decision to program R0
and R1 has been inverted.
This leads to problems on BananaPi R2 (MT7623N) when booting from
SDMMC, it turns out accessing eMMC no longer works since
U-Boot 2022.07:
MT7623> mmc dev 0
Card did not respond to voltage select! : -110
The problem wasn't detected for a long time as both eMMC and SDMMC work
fine if they are used to boot from, and hence R0 and R1 were already
setup by the bootrom and/or preloader.
Fix the logic to restore the originally intended and correct behavior
and also change the descriptive comment accordingly.
Fixes:
dafe0fbfb0f3 ("pinctrl: mediatek: rewrite mtk_pinconf_set and related functions")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Tested-By: Frank Wunderlich <frank-w@public-files.de>
Aradhya Bhatia [Fri, 14 Apr 2023 07:27:25 +0000 (12:57 +0530)]
arm: mach-k3: am62a7: Enable QoS for DSS
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to 8.
The C7x and VPAC have been overwhelming the DSS's access to the DDR
(when it was accessing via the Non Real-Time (NRT) Queue), primarily
because their functional frequencies, and hence DDR accesses, were
significantly higher than that of DSS. This led the display to flicker
when certain edgeAI models were being run.
With the DSS traffic serviced from the RT queue, the flickering issue
has been found to be mitigated.
The am62a qos files are auto generated from the k3 resource partitioning
tool.
Section-3.1.12, "QoS Programming Guide", in the AM62A TRM[1], provides
more information about the QoS, and section-14.1, "System Interconnect
Registers", provides the register descriptions.
[1] AM62A Tech Ref Manual: https://www.ti.com/lit/pdf/spruj16
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Manorit Chawdhry [Mon, 17 Apr 2023 06:34:09 +0000 (12:04 +0530)]
arm: mach-k3: j7200: Fix firewall warnings at boot time
J721E and J7200 have same file j721e_init.c which had the firewall
configs for J721E being applied on J7200 causing the warnings. Split the
firewalls for both the boards to remove those warnings.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Bhupesh Sharma [Thu, 20 Apr 2023 11:28:48 +0000 (16:58 +0530)]
board: Fix documentation for Snapdragon based Samsung and Qualcomm boards
The current documentation for Snapdragon based Samsung
and Qualcomm boards is vague in the sense that at one place
it mentions that u-boot can be used as a replacement for ABL
bootloader and at another it mentions that u-boot is loaded
as an Android boot image through ABL.
Fix the same.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Bhupesh Sharma [Thu, 20 Apr 2023 11:28:47 +0000 (16:58 +0530)]
board: Fix board file path for sdm845.c for Samsung and Qualcomm boards
Currently a few 'board/qualcomm/../Makefile' point to incorrect
path of sdm845 board file.
Fix the same.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Manorit Chawdhry [Thu, 20 Apr 2023 11:46:24 +0000 (17:16 +0530)]
arm: mach-k3: common: don't reconfigure background firewalls
K3 devices have some firewalls set up by ROM that we usually remove so
that the development is easy in HS devices.
While removing the firewalls disabling a background region before
disabling the foreground regions keeps the firewall in a state where all
the transactions will be blacklisted until all the regions are disabled.
This causes a race for some other entity trying to access that memory
region before all the firewalls are disabled and causes an exception.
Since the background regions configured by ROM are in such a manner
that they allow all transactions, don't touch the background regions at
all.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Vignesh Raghavendra [Thu, 20 Apr 2023 16:12:21 +0000 (21:42 +0530)]
arm: mach-k3: common: Default to non fitImage boot on HS-FS
Allow non fitImage bootflow on Field Securable (HS-FS) devices in
addition to GP, force fitImage boot only on Security enforced (HS-SE)
devices where signed images are necessary to maintain chain of trust.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Vladimir Zapolskiy [Fri, 21 Apr 2023 17:50:41 +0000 (20:50 +0300)]
arm: dts: msm: add GENI SE QUP device tree node
On modern Qualcomm platforms including SDM845 a GENI SE QUP IP
description is supposed to be found in board device tree nodes,
the version of the IP is used by the GENI UART driver to properly
set an oversampling divider value, which impacts UART baudrate.
The change touches dragonboard845c and starqltechn board device
tree source files, a device tree node label to "debug" UART is
renamed to 'uart9' according to the naming found in Linux.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Vladimir Zapolskiy [Fri, 21 Apr 2023 17:50:40 +0000 (20:50 +0300)]
serial: msm-geni: correct oversampling value based on QUP hardware revision
Starting from QUP v2.5 the value of oversampling is changed from 32
to 16, keeping the old value on newer platforms results on wrong set
UART IP clock divider, thus the asked baudrate does not correspond to
the actually set with all the consequencies for a user.
The change links the driver to a new Qualcomm GENI SE QUP driver
to get its hardware version and update the oversampling value.
Deliberately the code under CONFIG_DEBUG_UART_MSM_GENI is not touched,
since a wanted baudrate can be controlled by setting a modified
CONFIG_DEBUG_UART_CLOCK build time variable.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Konrad Dybcio [Fri, 21 Apr 2023 17:50:39 +0000 (20:50 +0300)]
serial: msm-geni: Use upstream Linux bindings
The name "se" is used in upstream Linux device trees and has been for
ages, long before this U-Boot-ism was introduced. Same goes for the
existing compatible. Get rid of that.
[vzapolskiy: removed a ready change in the driver]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Vladimir Zapolskiy [Fri, 21 Apr 2023 17:50:38 +0000 (20:50 +0300)]
serial: msm-geni: fix a compile time warning from msm_serial_setbrg()
A compiler warns about a missing function prototype, which is valid
and fixed by converting the function into static one, also fix
interleaved local variable declarations and assignments.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Fixes:
324df15a292e ("serial: qcom: add support for GENI serial driver")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Vladimir Zapolskiy [Fri, 21 Apr 2023 17:50:37 +0000 (20:50 +0300)]
serial: msm-geni: fix code indentation
This a cosmetic change, which corrects code indentation in a few places.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Vladimir Zapolskiy [Fri, 21 Apr 2023 17:50:36 +0000 (20:50 +0300)]
serial: msm-geni: remove invalid se-clk clock name
There is only one clock supplier to the serial IP, thus getting it by
name is not needed, also note that "clock-names" property is not listed
under doc/device-tree-bindings/serial/msm-geni-serial.txt, and finally
"se-clk" clock name is invalid, if added, it shall get "se" value like
it's already described in Linux device tree documentation.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad Dybcio [Fri, 21 Apr 2023 17:50:35 +0000 (20:50 +0300)]
serial: msm-geni: Always bind before relocation
In preparation for supporting upstream Linux device trees on Qualcomm
platforms, make this the default behavior.
[vzapolskiy: extracted the driver change from a combination with dts changes]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Vladimir Zapolskiy [Fri, 21 Apr 2023 17:50:34 +0000 (20:50 +0300)]
serial: msm-geni: remove redundant includes
For whatever reason, likely a driver stub was copied from another
driver, the driver contains a bunch of unnecessary and confusing
includes like watchdog.h etc., the change reduces the list.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Vladimir Zapolskiy [Fri, 21 Apr 2023 17:50:33 +0000 (20:50 +0300)]
misc: add Qualcomm GENI SE QUP device driver
This change adds a Qualcomm GENI SE QUP device driver as a wrapper for
actually enabled and used serial devices found on a board.
At the moment the driver is pretty simple, its intention is to populate
childred devices and provide I/O mem read interface to them as clients,
this is needed for GENI UART driver to set up a proper clock divider
and provide the actually asked baud rate.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Linus Walleij [Mon, 24 Apr 2023 07:38:30 +0000 (09:38 +0200)]
board: Add new Broadcom Northstar board
This adds a simple Northstar "BRCMNS" board to be used with
the BCM4708x and BCM5301x chips.
The main intention is to use this with the D-Link DIR-890L
and DIR-885L routers for loading the kernel into RAM from
NAND memory using the BCH-1 ECC and using the separately
submitted SEAMA load command, so we are currently not adding
support for things such as networking.
The DTS file is a multiplatform NorthStar board, designed to
be usable with several NorthStar designs by avoiding any
particulars not related to the operation of U-Boot.
If other board need other ECC for example, they need to
create a separate DTS file and augment the code, but I don't
know if any other users will turn up.
Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 24 Apr 2023 07:38:29 +0000 (09:38 +0200)]
arm: Add support for the Broadcom Northstar SoCs
The original Northstar is an ARM SoC series that comprise
BCM4709x and BCM5301x and uses a dual-core Cortex A9, the
global timer and a few other things.
This series should not be confused with North Star Plus
(NSP) which is partly supported by U-Boot already.
The SoC is well supported by the Linux kernel and OpenWrt
as it is used in many routers.
Since we currently don't need any chip-specific quirks
and can get the system up from just the device tree, a
mach-* directory doesn't even need to be added, just
some small Kconfig fragments.
Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 24 Apr 2023 07:38:28 +0000 (09:38 +0200)]
arm: dts: Import device tree for Broadcom Northstar
This brings in the main SoC device tree used by the
Broadcom Northstar chipset, i.e. BCM4709x and BCM5301x.
This is taken from the v6.3 Linux kernel.
Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Svyatoslav Ryhel [Tue, 25 Apr 2023 07:57:22 +0000 (10:57 +0300)]
extcon: add MAX14526 MUIC support
MAX14526 is a powerful extcon chip which allows detection of various
plugs like usb, mhl, uart, headset etc. This version of driver
implements support of AP-usb and CP-usb/uart paths.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # LG P880 T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Svyatoslav Ryhel [Tue, 25 Apr 2023 07:57:21 +0000 (10:57 +0300)]
test: Add tests for the extcon
Provide tests to the simple extcon device.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Svyatoslav Ryhel [Tue, 25 Apr 2023 07:57:20 +0000 (10:57 +0300)]
dm: extcon: add an uclass for extcon
Add a new simple uclass for extcon. Currently all setup is done
in the probe. Uclass struct and ops are empty for now.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 2 May 2023 16:52:40 +0000 (12:52 -0400)]
Merge tag 'tpm-master-
02052023' of https://source.denx.de/u-boot/custodians/u-boot-tpm
adjust maintainers
Tom Rini [Tue, 2 May 2023 16:50:42 +0000 (12:50 -0400)]
Merge branch '2023-05-01-assorted-powerpc-updates'
- A number of PCI fixes, and one Kconfig cleanup for PowerPC platforms
Pali Rohár [Thu, 20 Apr 2023 19:44:25 +0000 (21:44 +0200)]
pci: auto: Remove PCI_CLASS_PROCESSOR_POWERPC autoconfig case
PCI autoconfig case for PCI_CLASS_PROCESSOR_POWERPC just prints debug
message and then calls autoconfig setup code like for any other standard
endpoint device. We do not need special debug message for it, so remove
this case and handle PCI_CLASS_PROCESSOR_POWERPC via default code path.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Heinrich Schuchardt [Sun, 2 Apr 2023 04:51:01 +0000 (06:51 +0200)]
MAINTAINERS: assign include/tpm*, cmd/tpm*
The files include/tpm* are an integral part of the TPM drivers.
The tpm* commands are used to access TPM devices.
Both should be managed by the TPM DRIVERS maintainer.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Heinrich Schuchardt [Sun, 2 Apr 2023 04:51:54 +0000 (06:51 +0200)]
cmd: missing break in test_write_limit()
In test_write_limit() an unintended fall-through occurs.
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Pali Rohár [Thu, 20 Apr 2023 19:44:23 +0000 (21:44 +0200)]
pci: mpc85xx: Do not access PCI BARs registers of BDF address 00:00.0
At BDF address 00:00.0 is fictional device which PCI configuration header
is for configuring mpc85xx PCI controller itself. PCI config space of this
device has ATMU inbound registers on position of PCI BARs. Trying to do PCI
auto configuration of this device cause rewriting ATMU inbound registers.
To avoid it, do not allow overwriting registers at BARs positions. And
because this device does not have any PCI memory, return zeros when trying
to read PCI BARs config space registers. It signals to auto configuration
tool to not allocate any PCI memory for this device.
This information is taken from MPC8544E Reference Manual, sections
17.3.1.3, 17.3.1.1.1, 17.3.2 and 17.3.2.11. Available at NXP website:
https://www.nxp.com/docs/en/reference-manual/MPC8544ERM.pdf
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Pali Rohár [Thu, 13 Apr 2023 20:41:46 +0000 (22:41 +0200)]
pci: mpc85xx: Do not try to access extended PCIe registers
Driver pci_mpc85xx.c is PCI controller driver for old PCI Local Bus,
which does not support access to extended PCIe registers (above 0xff),
as opposite of the PCIe driver pcie_fsl.c for the same platform.
So do not try to access extended PCIe registers as it cannot work.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Pali Rohár [Thu, 13 Apr 2023 20:41:45 +0000 (22:41 +0200)]
pci: mpc85xx: Allow 8/16-bit access to PCI config space
This Freescale mpc85xx PCI controller should support 8-bit and 16-bit read
and write access to PCI config space as described in more Freescale
reference manuals.
This change fixes issue that 8-bit and 16-bit write to PCI config space
caused to clear adjacent bits of 32-bit PCI register.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Pali Rohár [Thu, 13 Apr 2023 20:41:44 +0000 (22:41 +0200)]
pci: mpc85xx: Add missing sync() after writing to PCI config space
On PowerPC we should use barrier after store operation to HW register.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Christophe Leroy [Fri, 27 Jan 2023 13:51:06 +0000 (14:51 +0100)]
mpc83xx: Don't allow W and G bits in IBATs
The "Programming Environments Manual for 32-Bit Implementations of the
PowerPC™ Architecture" says "W and G bits are not defined for IBAT
registers. Attempting to write to these bits causes boundedly-undefined
results"
The "e300 Power Architecture™ Core Family Reference Manual" says the
same: "Neither the W or G bits of the IBAT registers should be set.
Attempting to write to these bits causes boundedly-undefined results."
Remove the possibility to set those bytes.
Fixes:
30915ab95d9 ("mpc83xx: Migrate BATS config to Kconfig")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Mario Six <mario.six@gdsys.cc>
Tom Rini [Mon, 1 May 2023 17:29:52 +0000 (13:29 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi
- cadence-quadspi fixes (Apurva Nandan, Dhruva Gole)
- CHIP_ERASE optimization (Marek Vasut)
- fixups for s25fs512s (Takahiro Kuwano)
Tom Rini [Mon, 1 May 2023 16:02:02 +0000 (12:02 -0400)]
Prepare v2023.07-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 1 May 2023 15:50:26 +0000 (11:50 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 1 May 2023 01:29:50 +0000 (21:29 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
Please pull the second part of the sunxi pull request for this cycle.
Another bunch of patches that replace old-school U-Boot hacks with
proper DM based code, this time for the raw NAND flash driver, and the
USB PHY VBUS detection code. Plus two smaller patches that were sitting
in my inbox for a while.
Gitlab CI passed. In lack of some supported board with NAND flash I
couldn't really test this part, but apparently this was tested by the
reviewer. I briefly ran the branch on some boards with USB-OTG, and
this still worked.
Tom Rini [Sat, 29 Apr 2023 13:29:41 +0000 (09:29 -0400)]
Merge branch 'for-2023.07' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx
This pull request adds support for the last CPU board from
CS GROUP France (previously CSSI).
That CPU board called CMPCPRO has a mpc8321E CPU (Family PQII PRO hence
its name) and can be plugged in place of the CMPC885 board.
In order to support that new board, the following changes are included
in this series:
- Make the mpc8xx watchdog driver more generic for reusing it
with mpc83xx
- Fix various small problems on mpc83xx platform
- Add a GPIO Driver for QE GPIOs
- Add support for mpc832x into mpc83xx SPI driver
- Refactor existing board code that will be shared with new board
- Add the new board
Tom Rini [Fri, 28 Apr 2023 23:00:01 +0000 (19:00 -0400)]
Merge tag 'dm-pull-28apr23' of https://source.denx.de/u-boot/custodians/u-boot-dm
sandbox and fdt bug fixes / tweaks
various other minor fixes
Simon Glass [Tue, 25 Apr 2023 16:27:21 +0000 (10:27 -0600)]
fdt: Indicate that people should use the ofnode API
Add a note to the comment at the top of this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Hugo Villeneuve [Mon, 24 Apr 2023 20:51:50 +0000 (16:51 -0400)]
fdt_support: fix comments syntax error
Fix comments syntax error in fdt_node_offset_by_compat_reg()
description:
compatiable -> compatible
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Johan Jonker [Sun, 23 Apr 2023 09:19:41 +0000 (11:19 +0200)]
core: fdtaddr: use map_sysmem() as cast for the return
For the devfdt_get_addr_index_ptr() and devfdt_get_addr_size_index_ptr()
function use map_sysmem() function as cast for the return for use in
sandbox. Also fix sandbox test.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Drop second hunk:
Signed-off-by: Simon Glass <sjg@chromium.org>
Jan Kiszka [Sat, 22 Apr 2023 14:42:48 +0000 (16:42 +0200)]
tools: Fall back to importlib_resources on Python 3.6
importlib.resources became part of 3.7 only. Allow using distros with
3.6 and the importlib_resources backport.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Sat, 22 Apr 2023 12:59:58 +0000 (14:59 +0200)]
test: fdt: Fix copyright message
Drop the map_to_sysmem() copy paste error. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Thu, 20 Apr 2023 18:07:29 +0000 (20:07 +0200)]
patman: fix class TestFunctional
Variable orig_dir cannot be used in the finally block if it has not be
assigned outside of the try block.
tools/patman/func_test.py:523:21:
E0601: Using variable 'orig_dir' before assignment
(used-before-assignment)
tools/patman/func_test.py:691:21:
E0601: Using variable 'orig_dir' before assignment
(used-before-assignment)
Fixes:
fd70986a62af ("patman: Add a test that uses gitpython")
Fixes:
be051c0c7741 ("patman: Detect missing upstream in CountCommitsToBranch")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 19 Apr 2023 21:21:14 +0000 (15:21 -0600)]
binman: Use expanduser instead of HOME
There may not be a HOME environment variable, so use the os.expanduser()
function instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rasmus Villemoes [Thu, 13 Apr 2023 15:17:03 +0000 (17:17 +0200)]
dm: core: introduce uclass_get_device_by_of_path()
There's quite a few instances of board-specific code doing
off = fdt_path_offset(gd->fdt_blob, ...);
...
ret = uclass_get_device_by_of_offset(..., off, &dev);
looking for an eeprom or a pmic via some alias. Such code can be
simplified a little if we have a helper for directly getting a device
via device tree path (including being given as an alias).
Implement it in terms of ofnode rather than raw offsets so that this
will work whether live tree is enabled or not.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Rasmus Villemoes [Thu, 13 Apr 2023 15:16:11 +0000 (17:16 +0200)]
uclass: add uclass_find_device_by_phandle_id() helper
The functions uclass_find_device_by_phandle() and
uclass_get_device_by_phandle_id() both loop over a given uclass
looking for a device with a given phandle. Factor that out to a common
helper.
For now, there are no (known potential) users of the new helper
outside uclass.c, so make it static.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fix warning on sandbox_spl; fix code style:
Signed-off-by: Simon Glass <sjg@chromium.org>
Pavel Skripkin [Wed, 12 Apr 2023 18:55:44 +0000 (21:55 +0300)]
sandbox: disable tracing before unmapping RAM
Currently doing 'reset' command in sandbox with tracing enabled causes
SIGSEV
```
Hit any key to stop autoboot: 0
=>
=>
=> reset
resetting ...
Segmentation fault (core dumped)
```
Tracing callback uses RAM buffer for storing tracing reports, but
state_uninit() function unmaps whole RAM, which causes SIGSEV on umapped
memory inside tracing subsystem.
Fix it by disabling tracing before unmapping memory
Signed-off-by: Pavel Skripkin <paskripkin@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add missing check for CONFIG_TRACE:
Signed-off-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Mon, 17 Apr 2023 07:08:56 +0000 (09:08 +0200)]
sandbox: correct posix_types.h define
arch/arm/include/asm/posix_types.h and
arch/sandbox/include/asm/posix_types.h should use different defines.
Add SPDX header.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 6 Apr 2023 14:03:33 +0000 (10:03 -0400)]
bootflow: Rework do_bootflow_menu() slightly
When building this with clang, we get a warning such as:
cmd/bootflow.c:412:27: warning: variable 'bflow' is uninitialized when used here [-Wuninitialized]
printf("Selected: %s\n", bflow->os_name ? bflow->os_name : bflow->name);
^~~~~
And a suggestion to just initialize bflow to NULL. This would however
would be ensuring a bad dereference. Instead, looking at the function we
rework things so that when CONFIG_EXPO is not enabled (and so, no UI) we
error early and would never reach this point in the code. Simplify the
rest slightly as well while at this.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 5 Apr 2023 14:37:55 +0000 (22:37 +0800)]
dm: core: Make aliases_lookup static
aliases_lookup is only referenced in of_access.c
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jorge Ramirez-Ortiz [Sat, 8 Apr 2023 15:35:31 +0000 (17:35 +0200)]
drivers: tee: sandbox: Fix SCP03 control emulator
Fix and document the Secure Channel Protocol03 emulator.
Fixes:
5a8783c80c39 ("drivers: tee: sandbox: SCP03 control emulator")
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Heinrich Schuchardt [Wed, 5 Apr 2023 09:34:15 +0000 (11:34 +0200)]
sandbox: fix return type of os_filesize()
Given a file ../img of size
4294967296 with GPT partition table and
partitions:
=> host bind 0 ../img
=> part list host 0
Disk host-0.blk not ready
The cause is os_filesize() returning int. File sizes must use off_t.
Correct all uses of os_filesize() too.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Wed, 5 Apr 2023 09:26:38 +0000 (11:26 +0200)]
MAINTAINERS: assign include/os.h
os.h is only used by the sandbox.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andrew Davis [Tue, 4 Apr 2023 18:45:41 +0000 (13:45 -0500)]
binman: Use unsigned long over typedef ulong
The header binman_sym.h depends on ulong typedef but does not include
types.h. This means the header must be included after including types.h
or a header that includes it.
We could include types.h but instead let's just switch from ulong
to directly using unsigned long. This removes the need for typedef'ing
it in some of the tests, so also remove those.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Mon, 3 Apr 2023 18:46:50 +0000 (20:46 +0200)]
common: static fdt_simplefb_enable_existing_node()
Function fdt_simplefb_enable_existing_node() should be static as it is not
used outside common/fdt_simplefb.c.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 3 Apr 2023 03:40:26 +0000 (11:40 +0800)]
boot: vbe_simple: Fix vbe_simple_read_bootflow() dependency
vbe_simple_read_bootflow() calls vbe_simple_read_bootflow_fw()
which is only available when BOOTMETH_VBE_SIMPLE_FW is on.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Sat, 1 Apr 2023 07:54:25 +0000 (09:54 +0200)]
sandbox: mark sandbox_exit() as no return.
Fix a -Wimplicit-fallthrough warning in sandbox_sysreset_request().
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Sat, 1 Apr 2023 07:38:05 +0000 (09:38 +0200)]
sandbox: spi: sandbox_sf_process_cmd() missing fallthrough
Add a missing fallthrough macro to avoid a -Wimplicit-fallthrough warning.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Sat, 1 Apr 2023 06:57:33 +0000 (08:57 +0200)]
sandbox: fix sandbox_hub_submit_control_msg()
Avoid incorrect fall through:
A USB_RT_HUB request should not be treated as USB_RT_PORT.
Simplify the coding:
Avoid duplicate debug() statements.
This fixes all -Wimplicit-fallthrough warnings.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Sat, 1 Apr 2023 06:24:52 +0000 (08:24 +0200)]
sandbox: fix fall through in sandbox_flash_bulk()
Handling of SANDBOX_FLASH_EP_OUT should never fall through to
SANDBOX_FLASH_EP_IN.
This addresses a warning shown when compiling with
-Wimplicit-fallthrough.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Christophe Leroy [Tue, 4 Apr 2023 11:09:36 +0000 (13:09 +0200)]
board: cssi: Add CPU board CMPCPRO
CSSI has another CPU board, similar to the CMPC885 board
that get plugged on the two base boards MCR3000_2G and MIAE.
That CPU board is called CMPCPRO because it has a MPC8321E CPU,
also known as Power QUICC II PRO.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Christophe Leroy [Wed, 5 Apr 2023 16:50:23 +0000 (18:50 +0200)]
board: cssi: Move all mother board code into common.c
All the code used to manage the mother boards will be
common to soon to come CPU board.
Move all that code into common.c
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Christophe Leroy [Wed, 5 Apr 2023 14:05:36 +0000 (16:05 +0200)]
board: cssi: Refactor EEPROM read
On cmpc885 board, the ethernet addresses are stored in an
EEPROM that is accessed through SPI.
A 3 bytes command is sent to the chip then the content
gets read. At the time being a single block access is
performed, ignoring the first 3 bytes read.
Reword the SPI transfer to first send 3 bytes then
receive the content of the EEPROM so that there don't be
3 dummy bytes at the beginning of the buffer.
And move the function into common.c so that it can be
reused by the board that will be added in a future patch.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Christophe Leroy [Tue, 4 Apr 2023 10:42:15 +0000 (12:42 +0200)]
board: cssi: Create dedicated file for common sources
In preparation of the new cssi board called cmpcpro which
we be introduce in a future patch, move common
functions into a dedicated file in a common directory.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Christophe Leroy [Fri, 28 Apr 2023 15:42:33 +0000 (17:42 +0200)]
board: cssi: Migrate to hashed password
Use a hashed password instead of clear text in order to
improve board security.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Samuel Holland [Sun, 22 Jan 2023 17:23:51 +0000 (11:23 -0600)]
Kconfig: Remove an impossible condition
ARCH_SUNXI selects BINMAN, so the condition "!BINMAN && ARCH_SUNXI"
is impossible to satisfy.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Fri, 15 Jul 2022 03:34:53 +0000 (22:34 -0500)]
phy: sun4i-usb: Do not drive VBUS with external VBUS present
It is possible to use host-side USB with externally-provided VBUS. For
example, some USB OTG cables have an extra power input which powers
both the board and the USB peripheral.
To support this setup, skip enabling the VBUS switch/regulator if VBUS
voltage is already present. This behavior matches the Linux PHY driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 23:46:22 +0000 (17:46 -0600)]
gpio: axp/sunxi: Remove virtual VBUS detection GPIO
Now that this functionality is modeled using the device tree and
regulator uclass, the named GPIO is not referenced anywhere. Remove it.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 23:46:21 +0000 (17:46 -0600)]
sunxi: Switch to PMIC USB power supply VBUS detection
Update boards to use the USB power supply driver, as referenced in the
device tree, instead of a virtual GPIO. This removes the need for some
DM-incompatible special cases in the GPIO driver.
The following five boards used AXP0-VBUS-DETECT in their config, but are
missing the "usb0_vbus_power-supply" property in their device tree:
- Ainol_AW1_defconfig / sun7i-a20-ainol-aw1
- Cubieboard4_defconfig / sun9i-a80-cubieboard4
- Merrii_A80_Optimus_defconfig / sun9i-a80-optimus
- Yones_Toptech_BD1078_defconfig / sun7i-a20-yones-toptech-bd1078
- Yones_Toptech_BS1078_V2_defconfig /
sun6i-a31s-yones-toptech-bs1078-v2
None of those five boards have the MUSB controller (USB OTG) enabled in
their device trees, so this change should not break anything for them.
Additionally, the following board intentionally omits the property
because VBUS is always enabled:
- Nintendo_NES_Classic_Edition_defconfig /
sun8i-r16-nintendo-nes-classic
The PHY driver already assumes VBUS is enabled when no detection method
is available, so again this will not cause any problems.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 23:46:20 +0000 (17:46 -0600)]
power: regulator: Add a driver for the AXP USB power supply
This driver reports the presence/absence of voltage on the PMIC's USB
VBUS pin. This information is used by the USB PHY driver. The
corresponding Linux driver uses the power supply class, which does not
exist in U-Boot. UCLASS_REGULATOR seems to be the closest match.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 22:06:36 +0000 (16:06 -0600)]
mtd: nand: sunxi: Pass the device to the init function
This more closely matches the U-Boot driver to the Linux version.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Michael Trimarchi <micahel@amarulasolutions.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 22:06:35 +0000 (16:06 -0600)]
mtd: nand: sunxi: Convert to the driver model
Clocks, resets, and pinmuxes are now handled by the driver model, so the
only thing the "board" code needs to do is load the driver. This matches
the pattern used by other DM raw NAND drivers (there is no NAND uclass).
The actual board code is now only needed in SPL.
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 22:06:34 +0000 (16:06 -0600)]
mtd: nand: sunxi: Convert from fdtdec to ofnode
As a first step toward converting this driver to the driver model, use
the ofnode abstraction to replace direct references to the FDT blob.
Using ofnode_read_u32_index removes an extra pair of loops and makes the
allwinner,rb property optional, matching the devicetree binding.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 22:06:33 +0000 (16:06 -0600)]
mtd: nand: sunxi: Remove an unnecessary check
Each chip is required to have a unique CS number ("reg" property) in the
range 0-7, so there is no need to separately count the number of chips.
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 22:06:32 +0000 (16:06 -0600)]
pinctrl: sunxi: Add NAND pinmuxes
NAND is always at function 2 on port C.
Pin lists and mux values were taken from the Linux drivers.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sun, 22 Jan 2023 22:06:31 +0000 (16:06 -0600)]
clk: sunxi: Add NAND clocks and resets
Currently NAND clock setup is done in board code, both in SPL and in
U-Boot proper. Add the NAND clocks/resets here so they can be used by
the "full" NAND driver once it is converted to the driver model.
The bit locations are copied from the Linux CCU drivers.
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sat, 21 Jan 2023 23:25:17 +0000 (17:25 -0600)]
sunxi: binman: Fix U-Boot offset when SPL is not 32 KiB
On sunxi boards, SPL looks for U-Boot at a 32 KiB offset, unless SPL is
larger than 32 KiB, in which case U-Boot immediately follows SPL. See
the logic in spl_mmc_get_uboot_raw_sector() and spl_spi_load_image().
In two cases, the existing binman description mismatches the SPL code.
For 64-bit boards, binman would place U-Boot immediately following SPL,
even if SPL is smaller than 32 KiB. This can happen when SPL MMC support
is disabled (i.e. when booting from SPI flash).
In contrast, for 32-bit boards, binman would place U-Boot at 32 KiB,
even if SPL is larger than that. This happens because the 'offset'
property does not consider the size of previous entries.
Fix both issues by setting a minimum size for the SPL entry, which
exactly matches the logic in the SPL code. Unfortunately, this size must
be provided as a magic number, since none of the relevant config symbols
(SPL_PAD_TO, SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, and SYS_SPI_U_BOOT_OFFS)
are guaranteed to be defined in all cases.
Fixes:
cfa3db602caf ("sunxi: Convert 64-bit boards to use binman")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tom Rini [Thu, 27 Apr 2023 23:22:38 +0000 (19:22 -0400)]
Merge branch '2023-04-27-introduce-nvm-xip-block-storage-emulation'
To quote the author:
Adding block storage emulation for NVM XIP flash devices.
Some paltforms such as Corstone-1000 need to see NVM XIP raw flash
as a block storage device with read only capability.
Here NVM flash devices are devices with addressable
memory (e.g: QSPI NOR flash).
The NVM XIP block storage emulation provides the following features:
- Emulate NVM XIP raw flash as a block storage device with read only capability
- Being generic by design and can be used by any platform
- Device tree node
- Platforms can use multiple NVM XIP devices at the same time by defining a
DT node for each one of them
- A generic NVMXIP block driver allowing to read from the XIP flash
- A generic NVMXIP Uclass driver for binding the block device
- A generic NVMXIP QSPI driver
- Implemented on top of memory-mapped IO (using readq macro)
- Enabling NVMXIP in sandbox64
- A sandbox test case
- Enabling NVMXIP in Corstone1000 platform as a use case
For more details please refer to doc/develop/driver-model/nvmxip.rst
Abdellatif El Khlifi [Mon, 17 Apr 2023 09:11:58 +0000 (10:11 +0100)]
sandbox64: add a test case for UCLASS_NVMXIP
provide a test for NVM XIP devices
The test case allows to make sure of the following:
- The NVM XIP QSPI devices are probed
- The DT entries are read correctly
- the data read from the flash by the NVMXIP block driver is correct
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Abdellatif El Khlifi [Mon, 17 Apr 2023 09:11:57 +0000 (10:11 +0100)]
corstone1000: enable NVM XIP QSPI flash
add the QSPI flash device with block storage capability
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Abdellatif El Khlifi [Mon, 17 Apr 2023 09:11:56 +0000 (10:11 +0100)]
corstone1000: add NVM XIP QSPI device tree node
add QSPI flash device node for block storage access
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Abdellatif El Khlifi [Mon, 17 Apr 2023 09:11:55 +0000 (10:11 +0100)]
sandbox64: add support for NVMXIP QSPI
enable NVMXIP QSPI for sandbox 64-bit
Adding two NVM XIP QSPI storage devices.
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Abdellatif El Khlifi [Mon, 17 Apr 2023 09:11:54 +0000 (10:11 +0100)]
sandbox64: fix: return unsigned long in readq()
make readq return unsigned long
readq should return 64-bit data
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Abdellatif El Khlifi [Mon, 17 Apr 2023 09:11:53 +0000 (10:11 +0100)]
drivers/mtd/nvmxip: introduce QSPI XIP driver
add nvmxip_qspi driver under UCLASS_NVMXIP
The device associated with this driver is the parent of the blk#<id> device
nvmxip_qspi can be reused by other platforms. If the platform
has custom settings to apply before using the flash, then the platform
can provide its own parent driver belonging to UCLASS_NVMXIP and reuse
nvmxip-blk driver. The custom driver can be implemented like nvmxip_qspi in
addition to the platform custom settings.
Platforms can use multiple NVM XIP devices at the same time by defining a
DT node for each one of them.
For more details please refer to doc/develop/driver-model/nvmxip_qspi.rst
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Abdellatif El Khlifi [Mon, 17 Apr 2023 09:11:52 +0000 (10:11 +0100)]
drivers/mtd/nvmxip: introduce NVM XIP block storage emulation
add block storage emulation for NVM XIP flash devices
Some paltforms such as Corstone-1000 need to see NVM XIP raw flash
as a block storage device with read only capability.
Here NVM flash devices are devices with addressable
memory (e.g: QSPI NOR flash).
The implementation is generic and can be used by different platforms.
Two drivers are provided as follows.
nvmxip-blk :
a generic block driver allowing to read from the XIP flash
nvmxip Uclass driver :
When a device is described in the DT and associated with
UCLASS_NVMXIP, the Uclass creates a block device and binds it with
the nvmxip-blk.
Platforms can use multiple NVM XIP devices at the same time by defining a
DT node for each one of them.
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Tom Rini [Thu, 27 Apr 2023 20:33:58 +0000 (16:33 -0400)]
Merge branch '2023-04-27-IDE-code-cleanups'
To quote the author:
This code was converted to driver model a long time again but it was a
pretty rough conversion. It introduced a few minor bugs, e.g. the device
capacity is incorrect and some flags are lost (such as lba48).
This series tidies up the code and fixes these bugs. This involves quite
a bit of refactoring, so it is done one patch at a time for easier
review.
Simon Glass [Tue, 25 Apr 2023 16:54:55 +0000 (10:54 -0600)]
ide: Make use of U-Boot types
Use standard U-Boot types in the file to make the code less verbose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 25 Apr 2023 16:54:54 +0000 (10:54 -0600)]
ide: Simplify expressions and hex values
The code has quite a few unnecessary brackets and comparisons to zero,
etc. Fix these up as well as some upper-case hex values and use of 0x in
printf() strings.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 25 Apr 2023 16:54:53 +0000 (10:54 -0600)]
ide: Convert to use log_debug()
Avoid the use of the function name in a few of the debug() calls, since
this causes a checkpatch warning. Convert all other calls too.
Use lower-case hex consistently.
Signed-off-by: Simon Glass <sjg@chromium.org>