Dmitry Preobrazhensky [Mon, 2 Apr 2018 13:52:23 +0000 (13:52 +0000)]
[AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructions
See bug 36837: https://bugs.llvm.org/show_bug.cgi?id=36837
Differential Revision: https://reviews.llvm.org/D45085
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 328975
Nico Weber [Mon, 2 Apr 2018 13:49:35 +0000 (13:49 +0000)]
Attempt to heal bots after r328970.
llvm-svn: 328974
Lama Saba [Mon, 2 Apr 2018 13:48:28 +0000 (13:48 +0000)]
[X86] Reduce Store Forward Block issues in HW - Recommit after fixing Bug 36346
If a load follows a store and reloads data that the store has written to memory, Intel microarchitectures can in many cases forward the data directly from the store to the load, This "store forwarding" saves cycles by enabling the load to directly obtain the data instead of accessing the data from cache or memory.
A "store forward block" occurs in cases that a store cannot be forwarded to the load. The most typical case of store forward block on Intel Core microarchiticutre that a small store cannot be forwarded to a large load.
The estimated penalty for a store forward block is ~13 cycles.
This pass tries to recognize and handle cases where "store forward block" is created by the compiler when lowering memcpy calls to a sequence
of a load and a store.
The pass currently only handles cases where memcpy is lowered to XMM/YMM registers, it tries to break the memcpy into smaller copies.
breaking the memcpy should be possible since there is no atomicity guarantee for loads and stores to XMM/YMM.
Differential revision: https://reviews.llvm.org/D41330
Change-Id: Ib48836ccdf6005989f7d4466fa2035b7b04415d9
llvm-svn: 328973
Andrea Di Biagio [Mon, 2 Apr 2018 13:46:49 +0000 (13:46 +0000)]
[llvm-mca] Do not assume that implicit reads cannot be associated with ReadAdvance entries.
Before, the instruction builder incorrectly assumed that only explicit reads
could have been associated with ReadAdvance entries.
This patch fixes the issue and adds a test to verify it.
llvm-svn: 328972
Nico Weber [Mon, 2 Apr 2018 13:45:39 +0000 (13:45 +0000)]
Attempt to fix papertrail-warnings.test on Windows bots.
llvm-svn: 328971
Nico Weber [Mon, 2 Apr 2018 13:22:26 +0000 (13:22 +0000)]
Assume existence of inttypes.h and stdint.h in DataTypes.h.
These should exist in all toolchains LLVM supports nowadays.
Enables making DataTypes.h a regular header instead of a .h.cmake file and
allows deleting a bunch of cmake goop (which should also speed up cmake
configure time a bit).
All the code this removes is 9+ years old.
https://reviews.llvm.org/D45155
llvm-svn: 328970
Hiroshi Inoue [Mon, 2 Apr 2018 12:18:21 +0000 (12:18 +0000)]
[PowerPC] fix assertion failure due to missing instruction in P9InstrResources.td
This patch adds L(D|W|H|B)XTLS instructions introduced by https://reviews.llvm.org/rL327635 in P9InstrResources.td.
llvm-svn: 328969
Andrea Di Biagio [Mon, 2 Apr 2018 12:04:37 +0000 (12:04 +0000)]
Fix unused variable warning introduced at revision 328910.
llvm-svn: 328968
George Rimar [Mon, 2 Apr 2018 11:28:44 +0000 (11:28 +0000)]
[ELF] - cref.s: check that we print symbols from archives. NFCI.
This is consistent with bfd and we already supported it,
though test did not contain the explicit check.
llvm-svn: 328967
Jonas Devlieghere [Mon, 2 Apr 2018 10:44:36 +0000 (10:44 +0000)]
[test] Exit lldb-dotest in a more Pythonic way.
As suggested by Keith Smiley in:
https://github.com/apple/swift-lldb/pull/486
llvm-svn: 328966
Jonas Devlieghere [Mon, 2 Apr 2018 10:40:43 +0000 (10:40 +0000)]
[dsymutil] Upstream emitting of papertrail warnings.
When running dsymutil as part of your build system, it can be desirable
for warnings to be part of the end product, rather than just being
emitted to the output stream. This patch upstreams that functionality.
Differential revision: https://reviews.llvm.org/D44639
llvm-svn: 328965
Simon Pilgrim [Mon, 2 Apr 2018 10:34:39 +0000 (10:34 +0000)]
Wdocumentation fix. NFCI.
llvm-svn: 328964
Simon Pilgrim [Mon, 2 Apr 2018 10:21:51 +0000 (10:21 +0000)]
Wdocumentation fixes. NFCI.
llvm-svn: 328963
Craig Topper [Mon, 2 Apr 2018 06:34:16 +0000 (06:34 +0000)]
[X86][Silvermont] Use correct latency and throughput information for divide and square root in the scheduler model.
Data taken from Table 16-17 in the Intel Optimization Manual.
llvm-svn: 328962
Craig Topper [Mon, 2 Apr 2018 05:54:34 +0000 (05:54 +0000)]
[X86][SkylakeServer] Correct throughput for 512-bit sqrt and divide.
Data taken from the AVX512_SKX_PortAssign spreadsheet at http://instlatx64.atw.hu/
llvm-svn: 328961
Craig Topper [Mon, 2 Apr 2018 05:33:28 +0000 (05:33 +0000)]
[X86] Correct the throughput for divide instructions in Sandy Bridge/Haswell/Broadwell/Skylake scheduler models.
Fixes most of PR36898. Still need to fix the 512-bit instructions, but Agner's tables don't have those.
llvm-svn: 328960
Craig Topper [Mon, 2 Apr 2018 03:15:02 +0000 (03:15 +0000)]
[X86] Fix the SchedRW for AVX512 shift instructions.
It was being inadvertently defaulted to an FADD scheduler class.
llvm-svn: 328959
Craig Topper [Mon, 2 Apr 2018 02:44:55 +0000 (02:44 +0000)]
[X86] Give the AVX512 VEXTRACT instructions the same SchedRWs as the SSE/AVX versions.
llvm-svn: 328958
Nico Weber [Mon, 2 Apr 2018 01:46:08 +0000 (01:46 +0000)]
Remove a few unreferenced config.h defines.
Found by looking through the output of
for f in $(grep -o '\bHAVE_[A-Z0-9_]*\b' llvm/cmake/config-ix.cmake); do
echo $f $(git grep $f '*' | wc -l);
done
in the monorepo.
llvm-svn: 328957
Craig Topper [Mon, 2 Apr 2018 01:12:34 +0000 (01:12 +0000)]
[X86] Add an itinerary to BTR64rr.
llvm-svn: 328956
Craig Topper [Mon, 2 Apr 2018 01:12:32 +0000 (01:12 +0000)]
[X86] Make sure all the classes declare in the Haswell scheduler model are prefixed with HW.
The tablegen files all share a namespace so we shouldn't use a generic names in a specific scheduler model.
llvm-svn: 328955
Craig Topper [Mon, 2 Apr 2018 00:48:11 +0000 (00:48 +0000)]
[X86] Give VINSERTPS the same intinerary as INSERTPS.
llvm-svn: 328954
Harlan Haskins [Mon, 2 Apr 2018 00:17:40 +0000 (00:17 +0000)]
Add C API bindings for DIBuilder 'Type' APIs
This patch adds a set of unstable C API bindings to the DIBuilder interface for
creating structure, function, and aggregate types.
This patch also removes the existing implementations of these functions from
the Go bindings and updates the Go API to fit the new C APIs.
llvm-svn: 328953
Craig Topper [Sun, 1 Apr 2018 23:58:50 +0000 (23:58 +0000)]
[X86] Cleanup ADCX/ADOX instruction definitions.
Give them both the same itineraries. Add hasSideEffects = 0 to ADOX since they don't have patterns. Rename source operands to $src1 and $src2 instead of $src0 and $src. Add ReadAfterLd to the memory form SchedRW.
llvm-svn: 328952
Brian Gesiak [Sun, 1 Apr 2018 23:55:21 +0000 (23:55 +0000)]
[Coroutines] Schedule coro-split before asan
Summary:
The docs for the LLVM coroutines intrinsic `@llvm.coro.id` state that
"The second argument, if not null, designates a particular alloca instruction
to be a coroutine promise."
However, if the address sanitizer pass is run before the `@llvm.coro.id`
intrinsic is lowered, the `alloca` instruction passed to the intrinsic as its
second argument is converted, as per the
https://github.com/google/sanitizers/wiki/AddressSanitizerAlgorithm docs, to
an `inttoptr` instruction that accesses the address of the promise.
On optimization levels `-O1` and above, the `-asan` pass is run after
`-coro-early`, `-coro-split`, and `-coro-elide`, and before
`-coro-cleanup`, and so there is no issue. At `-O0`, however, `-asan`
is run in between `-coro-early` and `-coro-split`, which causes an
assertion to be hit when the `inttoptr` instruction is forcibly cast to
an `alloca`.
Rearrange the passes such that the coroutine passes are registered
before the sanitizer passes.
Test Plan:
Compile a simple C++ program that uses coroutines in `-O0` with
`-fsanitize-address`, and confirm no assertion is hit:
`clang++ coro-example.cpp -fcoroutines-ts -g -fsanitize=address -fno-omit-frame-pointer`.
Reviewers: GorNishanov, lewissbaker, EricWF
Reviewed By: GorNishanov
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D43927
llvm-svn: 328951
Petr Hosek [Sun, 1 Apr 2018 23:44:04 +0000 (23:44 +0000)]
[AArch64] Reserve x18 register on Fuchsia
This register is reserved as a platform register on Fuchsia.
Differential Revision: https://reviews.llvm.org/D45105
llvm-svn: 328950
Brian Gesiak [Sun, 1 Apr 2018 22:59:22 +0000 (22:59 +0000)]
[Coroutines] Find custom allocators in class scope
Summary:
https://reviews.llvm.org/rL325291 implemented Coroutines TS N4723
section [dcl.fct.def.coroutine]/7, but it performed lookup of allocator
functions within both the global and class scope, whereas the specified
behavior is to perform lookup for custom allocators within just the
class scope.
To fix, add parameters to the `Sema::FindAllocationFunctions` function
such that it can be used to lookup allocators in global scope,
class scope, or both (instead of just being able to look up in just global
scope or in both global and class scope). Then, use those parameters
from within the coroutine Sema.
This incorrect behavior had the unfortunate side-effect of causing the
bug https://bugs.llvm.org/show_bug.cgi?id=36578 (or at least the reports
of that bug in C++ programs). That bug would occur for any C++ user with
a coroutine frame that took a single pointer argument, since it would
then find the global placement form `operator new`, described in the
C++ standard 18.6.1.3.1. This patch prevents Clang from generating code
that triggers the LLVM assert described in that bug report.
Test Plan: `check-clang`
Reviewers: GorNishanov, eric_niebler, lewissbaker
Reviewed By: GorNishanov
Subscribers: EricWF, cfe-commits
Differential Revision: https://reviews.llvm.org/D44552
llvm-svn: 328949
Craig Topper [Sun, 1 Apr 2018 22:16:52 +0000 (22:16 +0000)]
[DebugCounter] Make -debug-counter cl::Hidden.
llvm-svn: 328948
Craig Topper [Sun, 1 Apr 2018 21:54:26 +0000 (21:54 +0000)]
[LegacyPassManager] Make 'print-module-scope' cl::Hidden like the rest of the printing options.
llvm-svn: 328947
Craig Topper [Sun, 1 Apr 2018 21:54:24 +0000 (21:54 +0000)]
[X86] Give ADC8/16/32/64mi the same scheduling information as ADC8/16/32/64mr and SBB8/16/32/64mi.
It doesn't make a lot of sense that it would be different.
llvm-svn: 328946
Chandler Carruth [Sun, 1 Apr 2018 21:53:18 +0000 (21:53 +0000)]
[x86] Correct the operand structure of the ADOX instruction.
This also moves to define it in the same way as ADCX which seems to use
constraints a bit better.
This is pulled out of the review for reducing the use of popf for
restoring EFLAGS, but is independent. There are still more problems with
our definitions for these instructions that Craig is going to look at
but this is at least less broken and he can start from this to improve
them more fully.
Thanks to Craig for the review here.
llvm-svn: 328945
Chandler Carruth [Sun, 1 Apr 2018 21:47:55 +0000 (21:47 +0000)]
[x86] Expose more of the condition conversion routines in the public API
for X86's instruction information. I've now got a second patch under
review that needs these same APIs. This bit is nicely orthogonal and
obvious, so landing it. NFC.
llvm-svn: 328944
Mandeep Singh Grang [Sun, 1 Apr 2018 21:24:53 +0000 (21:24 +0000)]
[tools] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: JDevlieghere, zturner, echristo, dberris, friss
Reviewed By: echristo
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D45141
llvm-svn: 328943
John McCall [Sun, 1 Apr 2018 21:04:30 +0000 (21:04 +0000)]
Fix a major swiftcall ABI bug with trivial C++ class types.
The problem with the previous logic was that there might not be any
explicit copy/move constructor declarations, e.g. if the type is
trivial and we've never type-checked a copy of it. Relying on Sema's
computation seems much more reliable.
Also, I believe Richard's recommendation is exactly the rule we use
now on the Itanium ABI, modulo the trivial_abi attribute (which this
change of course fixes our handling of in Swift).
This does mean that we have a less portable rule for deciding
indirectness for swiftcall. I would prefer it if we just applied the
Itanium rule universally under swiftcall, but in the meantime, I need
to fix this bug.
This only arises when defining functions with class-type arguments
in C++, as we do in the Swift runtime. It doesn't affect normal Swift
operation because we don't import code as C++.
llvm-svn: 328942
Mandeep Singh Grang [Sun, 1 Apr 2018 18:39:50 +0000 (18:39 +0000)]
[include] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: echristo, zturner, mzolotukhin, lhames
Reviewed By: echristo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45135
llvm-svn: 328940
Nicolai Haehnle [Sun, 1 Apr 2018 17:09:14 +0000 (17:09 +0000)]
AMDGPU: Make isIntrinsicSourceOfDivergence table-driven
Summary:
This is in preparation for the new dimension-aware image intrinsics,
which I'd rather not have to list here by hand.
Change-Id: Iaa16e3a635a11283918ce0d9e1e618591b0bf6fa
Reviewers: arsenm, rampitec, b-sumner
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D44938
llvm-svn: 328939
Nicolai Haehnle [Sun, 1 Apr 2018 17:09:07 +0000 (17:09 +0000)]
AMDGPU: Make getTgtMemIntrinsic table-driven for resource-based intrinsics
Summary:
Avoids having to list all intrinsics manually.
This is in preparation for the new dimension-aware image intrinsics,
which I'd rather not have to list here by hand.
Change-Id: If7ced04998397ef68c4cb8f7de66b5050fb767e5
Reviewers: arsenm, rampitec, b-sumner
Subscribers: kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D44937
llvm-svn: 328938
Nicolai Haehnle [Sun, 1 Apr 2018 17:08:58 +0000 (17:08 +0000)]
TableGen: Support Intrinsic values in SearchableTable
Summary:
We will use this in the AMDGPU backend in a subsequent patch
in the stack to lookup target-specific per-intrinsic information.
The generic CodeGenIntrinsic machinery is used to ensure that,
even though we don't calculate actual enum values here, we do
get the intrinsics in the right order for the binary search
index.
Change-Id: If61cd5587963a4c5a1cc53df1e59c5e4dec1f9dc
Reviewers: arsenm, rampitec, b-sumner
Subscribers: wdng, tpr, llvm-commits
Differential Revision: https://reviews.llvm.org/D44935
llvm-svn: 328937
Nicolai Haehnle [Sun, 1 Apr 2018 17:08:49 +0000 (17:08 +0000)]
TableGen: More helpful error messages
Summary: Change-Id: I3c23f6f6597912423762780cd8c5315870412bbe
Reviewers: arsenm, rampitec, b-sumner
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44936
Change-Id: Ie62614a3e2d7774f46e4034478b28f57100a2c92
llvm-svn: 328936
Mandeep Singh Grang [Sun, 1 Apr 2018 16:18:49 +0000 (16:18 +0000)]
[DebugInfo] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: echristo, zturner, samsonov
Reviewed By: echristo
Subscribers: JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D45134
llvm-svn: 328935
Teresa Johnson [Sun, 1 Apr 2018 15:54:40 +0000 (15:54 +0000)]
[ThinLTO] Add an import cutoff for debugging/triaging
Summary:
Adds -import-cutoff=N which will stop importing during the thin link
after N imports. Default is -1 (no limit).
Reviewers: wmi
Subscribers: inglorion, llvm-commits
Differential Revision: https://reviews.llvm.org/D45127
llvm-svn: 328934
David Green [Sun, 1 Apr 2018 12:48:24 +0000 (12:48 +0000)]
[LoopRotate] Rotate loops with loop exiting latches
If a loop has a loop exiting latch, it can be profitable
to rotate the loop if it leads to the simplification of
a phi node. Perform rotation in these cases even if loop
rotate itself didnt simplify the loop to get there.
Differential Revision: https://reviews.llvm.org/D44199
llvm-svn: 328933
Zinovy Nis [Sun, 1 Apr 2018 11:51:57 +0000 (11:51 +0000)]
[clang-tidy] Define __clang_analyzer__ macro for clang-tidy for compatibility with clang static analyzer
This macro is widely used in many well-known projects, ex. Chromium.
But it's not set for clang-tidy, so for ex. DCHECK in Chromium is not considered as [[no-return]], and a lot of false-positive warnings about nullptr dereferenced are emitted.
This patch fixes the issue by explicitly added macro definition.
Differential Revision: https://reviews.llvm.org/D44906
llvm-svn: 328932
Craig Topper [Sun, 1 Apr 2018 06:29:32 +0000 (06:29 +0000)]
[X86] Don't check for folding into a store when deciding if we can promote an i16 mul.
There's no RMW mul operation.
llvm-svn: 328931
Craig Topper [Sun, 1 Apr 2018 06:29:28 +0000 (06:29 +0000)]
[X86] Check if the load and store are to the same pointer before preventing i16 RMW shifts and subtracts from being promoted.
llvm-svn: 328930
Craig Topper [Sun, 1 Apr 2018 06:29:27 +0000 (06:29 +0000)]
[X86] Add test case to show failure to promote i16 subtract when the LHS is a load and the result is stored to a different address.
We mistakenly believe we might be able to fold this as a RMW operation, but that doesn't end up happening.
llvm-svn: 328929
Craig Topper [Sun, 1 Apr 2018 06:29:25 +0000 (06:29 +0000)]
[X86] Allow i16 subtracts to be promoted if the load is on the LHS and its not being stored.
llvm-svn: 328928
Craig Topper [Sun, 1 Apr 2018 06:29:23 +0000 (06:29 +0000)]
[X86] Add test case to show failure to promote i16 subtract because we mistakenly believe the load can be folded. NFC
The left hand side of the subtract is a load, but we cna't fold those unless we also have a store.
llvm-svn: 328927
Craig Topper [Sun, 1 Apr 2018 06:29:21 +0000 (06:29 +0000)]
[X86] Remove unneeded temporary variable. NFC
This Promote flag was alwasys set to true except in the default case. But in the default case we don't need to set PVT and can just return false.
llvm-svn: 328926
Mandeep Singh Grang [Sun, 1 Apr 2018 01:46:51 +0000 (01:46 +0000)]
[Analysis] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer D44363 for a list of all the required patches.
Reviewers: sanjoy, dexonsmith, hfinkel, RKSimon
Reviewed By: dexonsmith
Subscribers: david2050, llvm-commits
Differential Revision: https://reviews.llvm.org/D44944
llvm-svn: 328925
Eric Fiselier [Sun, 1 Apr 2018 00:33:51 +0000 (00:33 +0000)]
Add missing include to ContinuousRangeMap.h
llvm-svn: 328924
Eric Fiselier [Sun, 1 Apr 2018 00:31:14 +0000 (00:31 +0000)]
Add missing include to Visibility.h
llvm-svn: 328923
Nico Weber [Sat, 31 Mar 2018 18:26:25 +0000 (18:26 +0000)]
Revert r328845, it caused crbug.com/827810.
llvm-svn: 328922
Sanjay Patel [Sat, 31 Mar 2018 17:55:44 +0000 (17:55 +0000)]
[DAGCombine] (float)((int) f) --> ftrunc (PR36617)
fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC,
so replace a pair of casts with the equivalent node. We don't have to account for
special cases (NaN, INF) because out-of-range casts are undefined.
Differential Revision: https://reviews.llvm.org/D44909
llvm-svn: 328921
Lang Hames [Sat, 31 Mar 2018 16:01:01 +0000 (16:01 +0000)]
[llvm-rtdyld] Fix the InputFileList cl::opt description: it accepts multiple
input files.
llvm-svn: 328920
Henry Wong [Sat, 31 Mar 2018 12:46:46 +0000 (12:46 +0000)]
[analyzer] Unroll the loop when it has a unsigned counter.
Summary:
The original implementation in the `LoopUnrolling.cpp` didn't consider the case where the counter is unsigned. This case is only handled in `simpleCondition()`, but this is not enough, we also need to deal with the unsinged counter with the counter initialization.
Since `IntegerLiteral` is `signed`, there is a `ImplicitCastExpr<IntegralCast>` in `unsigned counter = IntergerLiteral`. This patch add the `ignoringParenImpCasts()` in the `IntegerLiteral` matcher.
Reviewers: szepet, a.sidorin, NoQ, george.karpenkov
Reviewed By: szepet, george.karpenkov
Subscribers: xazax.hun, rnkovacs, cfe-commits, MTC
Differential Revision: https://reviews.llvm.org/D45086
llvm-svn: 328919
Simon Pilgrim [Sat, 31 Mar 2018 09:15:54 +0000 (09:15 +0000)]
[X86][Btver2] Add MMX_PSHUFB to the JWritePSHUFB InstRW entries
llvm-svn: 328918
Simon Pilgrim [Sat, 31 Mar 2018 09:14:14 +0000 (09:14 +0000)]
Fix trailing whitespace. NFCI.
llvm-svn: 328917
Benjamin Kramer [Sat, 31 Mar 2018 07:41:25 +0000 (07:41 +0000)]
Unbreak the build of the go bindings after r328839.
llvm-svn: 328916
Puyan Lotfi [Sat, 31 Mar 2018 05:48:51 +0000 (05:48 +0000)]
[MIR-Canon] Adding support for local idempotent instruction hoisting.
llvm-svn: 328915
Craig Topper [Sat, 31 Mar 2018 04:54:32 +0000 (04:54 +0000)]
[X86] Add SchedRW for PMULLD
Summary:
It seems many CPUs don't implement this instruction as well as the other vector multiplies. Often using a multi uop flow. Silvermont in particular has a 7 uop flow with 11 cycle throughput. Sandy Bridge implements it as a single uop with 5 cycle latency and 1 cycle throughput. But Haswell and later use 2 uops with 10 cycle latency and 2 cycle throughput.
This patch adds a new X86SchedWritePair we can use to tag this instruction separately. I've provided correct information for Silvermont, Btver2, and Sandy Bridge. I've removed the InstRWs for SandyBridge. I've left Haswell/Broadwell/Skylake InstRWs in place because I wasn't sure how to account for the different load latency between 128 and 256 bits. I also left Znver1 InstRWs in place because the existing values don't match Agner's spreadsheet.
I also left a FIXME in the SandyBridge model because it being used for the "generic" model is too optimistic for the 256/512-bit versions since those are multiple uops on all known CPUs.
Reviewers: RKSimon, GGanesh, courbet
Reviewed By: RKSimon
Subscribers: gchatelet, gbedwell, andreadb, llvm-commits
Differential Revision: https://reviews.llvm.org/D44972
llvm-svn: 328914
George Karpenkov [Sat, 31 Mar 2018 02:17:15 +0000 (02:17 +0000)]
[analyzer] Hopefully fix the ARM buildbot.
llvm-svn: 328913
George Karpenkov [Sat, 31 Mar 2018 01:20:08 +0000 (01:20 +0000)]
[analyzer] Fix assertion crash in CStringChecker
An offset might be unknown.
rdar://
39054939
Differential Revision: https://reviews.llvm.org/D45115
llvm-svn: 328912
George Karpenkov [Sat, 31 Mar 2018 01:20:07 +0000 (01:20 +0000)]
[analyzer] Cache offset computation for MemRegion
Achieves almost a 200% speedup on the example where the performance of
visitors was problematic.
Performance on sqlite3 is unaffected.
rdar://
38818362
Differential Revision: https://reviews.llvm.org/D45113
llvm-svn: 328911
George Karpenkov [Sat, 31 Mar 2018 01:20:06 +0000 (01:20 +0000)]
[analyzer] Fix liveness calculation for C++17 structured bindings
C++ structured bindings for non-tuple-types are defined in a peculiar
way, where the resulting declaration is not a VarDecl, but a
BindingDecl.
That means a lot of existing machinery stops working.
rdar://
36912381
Differential Revision: https://reviews.llvm.org/D44956
llvm-svn: 328910
Teresa Johnson [Sat, 31 Mar 2018 00:18:08 +0000 (00:18 +0000)]
[ThinLTO] Add an option to force summary call edges cold for debugging
Summary:
Useful to selectively disable importing into specific modules for
debugging/triaging/workarounds.
Reviewers: eraman
Subscribers: inglorion, llvm-commits
Differential Revision: https://reviews.llvm.org/D45062
llvm-svn: 328909
Fangrui Song [Fri, 30 Mar 2018 23:13:00 +0000 (23:13 +0000)]
[ELF] Simplify read32. NFC
llvm-svn: 328908
Fangrui Song [Fri, 30 Mar 2018 22:22:31 +0000 (22:22 +0000)]
Fix a bunch of typoes. NFC
llvm-svn: 328907
Peter Szecsi [Fri, 30 Mar 2018 22:03:29 +0000 (22:03 +0000)]
[ASTImporter] Add test helper Fixture
Add a helper test Fixture, so we can add tests which can check internal
attributes of AST nodes like getPreviousDecl(), isVirtual(), etc.
This enables us to check if a redeclaration chain is correctly built during
import, if the virtual flag is preserved during import, etc. We cannot check
such attributes with the existing testImport.
Also, this fixture makes it possible to import from several "From" contexts.
We also added several test cases here, some of them are disabled.
We plan to pass the disabled tests in other patches.
Patch by Gabor Marton!
Differential Revision: https://reviews.llvm.org/D43967
llvm-svn: 328906
Peter Collingbourne [Fri, 30 Mar 2018 21:36:54 +0000 (21:36 +0000)]
ELF: Place ordered sections in the middle of the unordered section list on targets with limited-range branches.
It generally does not matter much where we place sections ordered
by --symbol-ordering-file relative to other sections. But if the
ordered sections are hot (which is the case already for some users
of --symbol-ordering-file, and is increasingly more likely to be
the case once profile-guided section layout lands) and the target
has limited-range branches, it is beneficial to place the ordered
sections in the middle of the output section in order to decrease
the likelihood that a range extension thunk will be required to call
a hot function from a cold function or vice versa.
That is what this patch does. After D44966 it reduces the size of
Chromium for Android's .text section by 60KB.
Differential Revision: https://reviews.llvm.org/D44969
llvm-svn: 328905
Ekaterina Romanova [Fri, 30 Mar 2018 21:35:42 +0000 (21:35 +0000)]
Prevent data races in concurrent ThinLTO processes.
Make sure ThinLTO with caching doesn't use non-atomic writes to the cache file (to prevent data races and cache files corruption).
1. Place temp file to the same place where the caching directory is (instead of creating it the directory pointed to by TMP/TEMP variable). This will help to prevent using non-atomic rename and falling back to non-atomic "direct" write to the cache file.
2. if rename failed do not write to the cache file directly (direct write to the file is non-atomic and could cause data race conditions).
3. if cache file doesn't exist (e.g., because 'rename' failed or because some other reasons), bypass using the cache altogether.
Differential Revision: https://reviews.llvm.org/D45076
llvm-svn: 328904
Artem Dergachev [Fri, 30 Mar 2018 21:22:35 +0000 (21:22 +0000)]
[analyzer] Fix test triple in missing-bind-temporary.cpp.
Otherwise the default triple for x86-windows-msvc2015 auto-inserts
__attribute__((thiscall)) to some calls.
Fixes the respective buildbot.
llvm-svn: 328903
Rumeet Dhindsa [Fri, 30 Mar 2018 20:49:34 +0000 (20:49 +0000)]
Initialize Elf Header to zero to ensure that bytes not assigned any value later on are initialized properly.
Differential Revision: https://reviews.llvm.org/D44986
llvm-svn: 328902
Jacob Gravelle [Fri, 30 Mar 2018 20:36:58 +0000 (20:36 +0000)]
[WebAssembly] Register wasm passes with the PassRegistry
Summary:
This exposes WebAssembly passes for use on the command line (as
arguments to -print-before and the like).
Reviewers: dschuff, sunfish
Subscribers: MatzeB, jfb, sbc100, llvm-commits, aheejin
Differential Revision: https://reviews.llvm.org/D45103
llvm-svn: 328901
Jonathan Peyton [Fri, 30 Mar 2018 19:55:11 +0000 (19:55 +0000)]
Minor cleanup in __kmp_atfork_child()
This change removes the unnecessary lock operation on __kmp_initz_lock inside
the __kmp_atfork_child() function for Linux; the lock variable is initialized
in the same function later.
Patch by Hansang Bae
Differential Revision: https://reviews.llvm.org/D44949
llvm-svn: 328900
Krzysztof Parzyszek [Fri, 30 Mar 2018 19:46:28 +0000 (19:46 +0000)]
[Hexagon] Fix testcase
llvm-svn: 328899
Krzysztof Parzyszek [Fri, 30 Mar 2018 19:30:28 +0000 (19:30 +0000)]
[Hexagon] Reduce excessive indentation in .s output
llvm-svn: 328898
Krzysztof Parzyszek [Fri, 30 Mar 2018 19:28:37 +0000 (19:28 +0000)]
[Hexagon] Avoid creating invalid offsets in packetizer
Two memory instructions with a dependency only on the address register
between the two (the first one of them being post-incrememnt) can be
packetized together after the offset on the second was updated to the
incremement value. Make sure that the new offset is valid for the
instruction.
llvm-svn: 328897
Artem Dergachev [Fri, 30 Mar 2018 19:27:42 +0000 (19:27 +0000)]
[analyzer] Track null or undef values through pointer arithmetic.
Pointer arithmetic on null or undefined pointers results in null or undefined
pointers. This is obvious for undefined pointers; for null pointers it follows
from our incorrect-but-somehow-working approach that declares that 0 (Loc)
doesn't necessarily represent a pointer of numeric address value 0, but instead
it represents any pointer that will cause a valid "null pointer dereference"
issue when dereferenced.
For now we've been seeing through pointer arithmetic at the original dereference
expression, i.e. in bugreporter::getDerefExpr(), but not during further
investigation of the value's origins in bugreporter::trackNullOrUndefValue().
The patch fixes it.
Differential Revision: https://reviews.llvm.org/D45071
llvm-svn: 328896
Artem Dergachev [Fri, 30 Mar 2018 19:25:39 +0000 (19:25 +0000)]
[CFG] [analyzer] Work around a disappearing CXXBindTemporaryExpr.
Sometimes template instantiation causes CXXBindTemporaryExpr to be missing in
its usual spot. In CFG, temporary destructors work by relying on
CXXBindTemporaryExprs, so they won't work in this case.
Avoid the crash and notify the clients that we've encountered an unsupported AST
by failing to provide the ill-formed construction context for the temporary.
Differential Revision: https://reviews.llvm.org/D44955
llvm-svn: 328895
Davide Italiano [Fri, 30 Mar 2018 19:24:08 +0000 (19:24 +0000)]
[lldb-dotest] Don't swallow error exit codes.
llvm-svn: 328894
Artem Dergachev [Fri, 30 Mar 2018 19:21:18 +0000 (19:21 +0000)]
[CFG] [analyzer] Avoid modeling C++17 constructors that aren't fully supported.
Not enough work has been done so far to ensure correctness of construction
contexts in the CFG when C++17 copy elision is in effect, so for now we
should drop construction contexts in the CFG and in the analyzer when
they seem different from what we support anyway.
This includes initializations with conditional operators and return values
across multiple stack frames.
Differential Revision: https://reviews.llvm.org/D44854
llvm-svn: 328893
Andrea Di Biagio [Fri, 30 Mar 2018 18:53:47 +0000 (18:53 +0000)]
[X86][BtVer2] Fixed the number of micro opcodes for AVX vector converts and
VSQRT instructions.
There were still a few AVX instructions with an incorrect number of opcodes.
These should be fixed now.
llvm-svn: 328892
Eli Friedman [Fri, 30 Mar 2018 18:39:28 +0000 (18:39 +0000)]
Remove unused CHECK lines leftover from r306928.
The RUN lines were removed, but the corresponding CHECK lines never
went away.
llvm-svn: 328891
Peter Collingbourne [Fri, 30 Mar 2018 18:37:55 +0000 (18:37 +0000)]
DataFlowSanitizer: wrappers of functions with local linkage should have the same linkage as the function being wrapped
This patch resolves link errors when the address of a static function is taken, and that function is uninstrumented by DFSan.
This change resolves bug 36314.
Patch by Sam Kerner!
Differential Revision: https://reviews.llvm.org/D44784
llvm-svn: 328890
Peter Collingbourne [Fri, 30 Mar 2018 18:32:24 +0000 (18:32 +0000)]
ELF: Try to create last thunk section at ThunkSectionSpacing bytes before the end.
Now that we have the ability to create short thunks, it is beneficial
for thunk sections to be surrounded by ThunkSectionSpacing bytes
of code on both sides in order to increase the likelihood that the
distance from the thunk to the target will be sufficiently small to
allow for the creation of a short thunk. This is currently the case
for most thunks that we create, except for the last one, which could,
depending on the size of the output section, potentially appear near
the end and therefore have a relatively small amount of code after it.
This patch moves the last thunk section to ThunkSectionSpacing bytes
before the end of the output section, as long as the section is larger
than 2*ThunkSectionSpacing bytes. It reduces the size of Chromium
for Android's .text section by 32KB.
Differential Revision: https://reviews.llvm.org/D44966
llvm-svn: 328889
Alexey Bataev [Fri, 30 Mar 2018 18:31:07 +0000 (18:31 +0000)]
[OPENMP] Added emission of offloading data sections for declare target
variables.
Added emission of the offloading data sections for the variables within
declare target regions + fixes emission of the declare target variables
marked as declare target not within the declare target region.
llvm-svn: 328888
Puyan Lotfi [Fri, 30 Mar 2018 18:15:54 +0000 (18:15 +0000)]
[MIR] Adding support for Named Virtual Registers in MIR.
llvm-svn: 328887
Andrea Di Biagio [Fri, 30 Mar 2018 18:15:30 +0000 (18:15 +0000)]
[X86][BtVer2] Fix the number of uOps for horizontal operations.
llvm-svn: 328886
Tim Shen [Fri, 30 Mar 2018 17:51:03 +0000 (17:51 +0000)]
[NVPTX] Enable StructuredCFG for NVPTX
Summary:
Make NVPTX require structured CFG. Added a temporary flag to
"roll back" the behavior for easy deployment.
Combined with D45008, this fixes several internal Nvidia GPU test
failures that we suspect to be ptxas miscompiles (PR27738).
Reviewers: jlebar
Subscribers: jholewinski, sanjoy, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D45070
llvm-svn: 328885
Tim Shen [Fri, 30 Mar 2018 17:51:00 +0000 (17:51 +0000)]
[BlockPlacement] Disable block placement tail duplciation in structured CFG.
Summary:
Tail duplication easily breaks the structure of CFG, e.g. duplicating on
a region entry. If the structure is intended to be preserved, then we
may want to configure tail duplication, or disable it for structured
CFG. From our benchmark results disabling it doesn't cause performance
regression.
Notice that this currently affects AMDGPU backend. In the next patch, I
also plan to turn on requiresStructuredCFG for NVPTX.
All unit tests still pass.
Reviewers: jlebar, arsenm
Subscribers: jholewinski, sanjoy, wdng, tpr, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D45008
llvm-svn: 328884
Robert Widmann [Fri, 30 Mar 2018 17:49:53 +0000 (17:49 +0000)]
[LLVM-C] Finish exception instruction bindings - Round 2
Summary:
Previous revision caused a leak in the echo test that got caught by the ASAN bots because of missing free of the handlers array and was reverted in r328759. Resubmitting the patch with that correction.
Add support for cleanupret, catchret, catchpad, cleanuppad and catchswitch and their associated accessors.
Test is modified from SimplifyCFG because it contains many diverse usages of these instructions.
Reviewers: whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits, vlad.tsyrklevich
Differential Revision: https://reviews.llvm.org/D45100
llvm-svn: 328883
Rui Ueyama [Fri, 30 Mar 2018 17:49:51 +0000 (17:49 +0000)]
Fix Windows buildbots.
llvm-svn: 328882
Zachary Turner [Fri, 30 Mar 2018 17:28:35 +0000 (17:28 +0000)]
Fix some signed / unsigned conversion problems.
llvm-svn: 328881
Rui Ueyama [Fri, 30 Mar 2018 17:22:44 +0000 (17:22 +0000)]
Improve error message for an unknown --plugin-opt.
Before:
$ ld.lld --plugin-opt=-foo
ld.lld: --Unknown command line argument '-abc'
After:
$ ld.lld --plugin-opt=-foo
ld.lld: --plugin-opt: ld.lld --Unknown command line argument '-abc'
Differential Revision: https://reviews.llvm.org/D45075
llvm-svn: 328880
Nico Weber [Fri, 30 Mar 2018 17:17:04 +0000 (17:17 +0000)]
[lld-link] Add comment explaining that /FIXED behavior is correct despite contradicting MSDN.
Also add a test for /FIXED.
https://reviews.llvm.org/D45087
llvm-svn: 328879
Zachary Turner [Fri, 30 Mar 2018 17:16:50 +0000 (17:16 +0000)]
[llvm-pdbutil] Dig deeper into the PDB and DBI streams when explaining.
This will show more detail when using `llvm-pdbutil explain` on an
offset in the DBI or PDB streams. Specifically, it will dig into
individual header fields and substreams to give a more precise
description of what the byte represents.
llvm-svn: 328878
Nico Weber [Fri, 30 Mar 2018 17:14:50 +0000 (17:14 +0000)]
[lld-link] Let /PROFILE imply /OPT:REF /OPT:NOICF /INCREMENTAL:NO /FIXED:NO
/FIXED:NO is always the default, so that part needs no work.
Also test the interaction of /ORDER: with /INCREMENTAL.
https://reviews.llvm.org/D45091
llvm-svn: 328877
Derek Schuff [Fri, 30 Mar 2018 17:02:50 +0000 (17:02 +0000)]
[WebAssembly] Refactor tablegen for store instructions (NFC)
Summary: Add patterns similar to loads.
Differential Revision: https://reviews.llvm.org/D45064
llvm-svn: 328876
Krzysztof Parzyszek [Fri, 30 Mar 2018 16:55:44 +0000 (16:55 +0000)]
Revert "peel loops with runtime small trip counts"
This reverts commit r328854, it breaks some Hexagon tests.
llvm-svn: 328875